Shunt Low Dropout Regulators

Abstract

A low dropout regulator includes a first stage that generates a first output voltage and a second stage that generates a second output voltage different from the first output voltage. The first stage and the second stage are coupled in parallel to a node, and the stages selectively control the corresponding first output signal and second output signal based on different conditions. One condition can be the operation of a load in one or more predetermined modes. Another condition can be a transition between modes. During a mode transition, the selective control of the first stage can reduce a voltage undershoot or a voltage overshoot in the load.

Description

Technical Field

[0001] Example embodiments disclosed herein generally relate to voltage regulation. Background Art

[0002] A low dropout (LDO) regulator generates a direct current (DC) output voltage from an input supply voltage. This type of regulator is used in many applications because it can linearly regulate the output voltage even when the supply voltage is very close to the output voltage. Also, LDOs tend to generate less noise, and LDOs can be smaller than other types of regulators. Summary of the invention

[0003] The following presents an overview of various exemplary embodiments. Some simplifications and omissions may be made in the following overview, which is intended to highlight and introduce some aspects of the various exemplary embodiments, but not to limit the scope of the present invention. In later chapters, exemplary embodiments sufficient to allow a person of ordinary skill in the art to obtain and use the inventive concept will be described in detail.

[0004] Various embodiments relate to a low dropout regulator, comprising: a first stage configured to generate a first output voltage; and a second stage configured to generate a second output voltage different from the first output voltage, wherein the first stage and the second stage are coupled in parallel to a node, the first stage is configured to be selectively controlled to generate the first output voltage based on a first condition, and the second stage is configured to be selectively controlled to generate the second output voltage based on a second condition different from the first condition, and wherein the second output voltage decreases during a mode transition so that the first output voltage is greater than the second output voltage.

[0005] Various embodiments are described wherein the first output voltage is within a range that reduces voltage overshoot in a signal output from the node.

[0006] Various embodiments are described wherein the first output voltage is within a range that reduces a voltage undershoot in a signal output from the node.

[0007] Various embodiments are described wherein: the first condition comprises a transition between a first mode and a second mode of a load coupled to the node, and the second condition comprises operation of the load during at least one of the first mode and the second mode.

[0008] Various embodiments are described wherein: the first stage is configured to be selectively controlled based on a first set of control signal values ​​to produce the first output voltage during the conversion period, and the second stage is configured to be selectively controlled based on a second set of control signal values ​​to produce the second output voltage during each of the first mode and the second mode.

[0009] Various embodiments are described wherein the first mode and the second mode correspond to different operating modes of the load.

[0010] Various embodiments are described wherein at least one of the first mode and the second mode is a power reduction mode.

[0011] Various embodiments are described in which: the first stage is configured to operate at a first speed and based on a first quiescent current, and the second stage is configured to operate at a second speed and based on a second quiescent current, the first speed being different from the second speed and the first quiescent current being different from the second quiescent current.

[0012] Various embodiments are described wherein: the first speed is greater than the second speed, and the first quiescent current is greater than the second quiescent current.

[0013] Various embodiments are described wherein the first stage includes a soft-off circuit configured to reduce a level of the first output voltage based on operation of the second stage.

[0014] Various other embodiments relate to a device for controlling a low dropout voltage (LDO) regulator comprising a first stage and a second stage, wherein the first stage and the second stage are coupled to an output node, the device comprising: a memory configured to store instructions; and a processor configured to execute the instructions to generate: one or more first control signals that cause the first stage to generate a first output voltage based on a first condition, one or more second control signals that cause the second stage to generate a second output voltage based on a second condition, wherein the second output voltage is different from the first output voltage, and wherein the second output voltage decreases during a mode transition so that the first output voltage is greater than the second output voltage.

[0015] Various embodiments are described wherein the first output voltage is within a range that reduces voltage overshoot in a signal output from the node.

[0016] Various embodiments are described wherein the first output voltage is within a range that reduces a voltage undershoot in a signal output from the node.

[0017] Various embodiments are described wherein: the first condition comprises a transition between a first mode and a second mode of a load coupled to the node, and the second condition comprises operation of the load during at least one of the first mode and the second mode.

[0018] Various embodiments are described wherein: the one or more first control signals control the first stage to produce the first output voltage during the conversion, and the one or more second control signals control the second stage to produce the second output voltage during each of the first mode and the second mode.

[0019] Various embodiments are described wherein the first mode and the second mode correspond to different operating modes of the load.

[0020] Various embodiments are described wherein at least one of the first mode and the second mode is a power reduction mode.

[0021] Various embodiments are described in which: the first stage is configured to operate at a first speed and based on a first quiescent current, and the second stage is configured to operate at a second speed and based on a second quiescent current, the first speed being different from the second speed and the first quiescent current being different from the second quiescent current.

[0022] Various embodiments are described wherein: the first speed is greater than the second speed, and the first quiescent current is greater than the second quiescent current.

[0023] Various embodiments are described wherein the processor is configured to generate a control signal for controlling a soft shutdown circuit of the first stage. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Additional objects and features of the present invention will become more apparent from the following detailed description and the appended claims when taken in conjunction with the accompanying drawings. Although several example embodiments are shown and described, like reference numerals identify like parts in each of the drawings, in which:

[0025] Figure 1 An embodiment of a low dropout regulator is shown;

[0026] Figure 2 An embodiment of a low dropout regulator is shown;

[0027] Figure 3A and 3B Examples of overshoot and / or undershoot conditions are shown;

[0028] Figure 4 An embodiment of a control signal for a low dropout regulator is shown;

[0029] Figure 5 shows examples of simulation results according to one or more embodiments;

[0030] Figure 6 shows examples of simulation results according to one or more embodiments; and

[0031] Figure 7 Examples of simulation results according to one or more embodiments are shown. DETAILED DESCRIPTION

[0032] It should be understood that the drawings are only schematic and are not drawn to scale. It should also be understood that the same reference numerals are used throughout the drawings to indicate the same or similar parts.

[0033] Description and drawings illustrate the principles of various example embodiments. It will therefore be appreciated that those skilled in the art will be able to design various arrangements, although the arrangements are not explicitly described or illustrated herein, the arrangements embody the principles of the present invention and are included within the scope of the present invention. In addition, all examples cited herein are primarily intended to be used for teaching purposes to help readers understand the principles of the present invention and the concepts provided by the inventors to deepen the art, and all examples should be considered as not limited to such specific cited examples and conditions. In addition, as used herein, unless otherwise indicated (e.g., "or in addition" or "or in an alternative"), the term "or" is a non-exclusive or (i.e., and / or). Moreover, the various embodiments described herein are not necessarily mutually exclusive, because some embodiments can be combined with one or more other embodiments to form new embodiments. For example, descriptors such as "first", "second", "third" are not intended to limit the order of the elements discussed, but are used to distinguish one element from the next element, and are generally interchangeable. Values ​​such as maximum or minimum values ​​can be predetermined, and can be set to different values ​​based on the application.

[0034] In one application, an LDO regulator is used to provide power for multiple operating modes of a host device. In these cases, the LDO regulator also needs to provide power during transitions between modes. Typically, the operating modes consume different levels of current. To meet these requirements, the LDO regulator must output a proportional load current. However, during transitions between modes, the load current value may change significantly, for example, from 1mA to 3mA or even a larger amount. Moreover, the change in load current value may occur very quickly, for example, within a few nS.

[0035] In an attempt to address the problems that occur during mode transitions, some LDO regulators are designed to have extremely low quiescent currents in order to limit the total current consumption of the host system. For example, LDOs have been designed in this way to support the requirements of host systems when operating in sleep states and other low-power states. During these states, the quiescent current of the LDO may need to be much lower than a few uA, because the total current consumption of the host system may need to be less than a few uA while the LDO is still on. Such low currents significantly limit the speed of the LDO regulator to a speed level below the required operation, which is sufficient to respond to the large and rapid changes in load current that occur during the host system mode transition, that is, from current mode to low current mode for low current mode to high current mode.

[0036] Currently used LDO regulators can also suffer from voltage overshoot or undershoot during mode transitions in the host system. This can severely impact system performance, for example by causing an accident or other destructive failure. In some cases, the voltage overshoot or undershoot can trigger an overvoltage / undervoltage detection, which in turn can trigger a system reset. In addition, the voltage overshoot can damage the host system.

[0037] Figure 1 An embodiment of a low dropout (LDO) regulator including a first LDO stage 20 and a second LDO stage 60 arranged in parallel is shown. The first LDO stage and the second LDO stage are selectively controlled to output output voltages of different levels to a common node N, from which an output voltage (V out_LDO In addition to different output voltage levels, the first LDO stage and the second LDO stage may have different quiescent currents. The LDO stages may be selectively enabled or otherwise controlled based on one or more control signals generated by the controller 80 to output respective voltages of the LDO stages during various operations, such as a load of a host system.

[0038] The LDO regulator and controller may be on the same chip or printed circuit board. In one embodiment, controller 80 may be within the same host system as the LDO regulator, but may be provided separately and communicatively coupled to the LDO regulator. Also, in other embodiments, one or more additional LDO stages may be connected in parallel with stages 20 and 60, for example, to provide additional levels of output voltage for one or more intended applications.

[0039] refer to Figure 1, the first LDO stage 20 operates at a first speed level and a first quiescent current. The second LDO stage 60 operates at a second speed level and a second quiescent current. The first speed level may be different from the second speed level. For example, the first speed level may be greater than the second speed level. Also, the first quiescent current may be different from the second quiescent current. For example, the first quiescent current may be greater than the second quiescent current. For example, the speed level and the current may correspond to predetermined values ​​that meet requirements of different operating modes of a load (e.g., a host system) that includes or is coupled to the LDO regulator.

[0040] The controller 80 may generate one or more first control signals for selectively enabling a first combination of the LDO stage 20 and the LDO stage 60. For example, the first combination of the LDO stages may be selectively enabled based on a first predetermined condition. The first predetermined condition may be based on an operating mode of the host system, a transition between two operating modes of the host system, and / or one or more other conditions related to the operation and / or requirements of an application executed by the host system. The first combination of the LDO stages may correspond to the operation of at least one of the stages.

[0041] In one embodiment, when the host system is operating in one or more modes, the controller 80 can generate a first control signal to disable the first LDO stage 20 and enable the second LDO stage 60. As previously indicated, the first LDO stage 20 can be a high-speed, high-quiescent current LDO stage, and the second LDO stage 60 can be a low-speed, low-quiescent current LDO stage. Configuring the LDO stages in this manner can meet the low power requirements of the host system during the first operating mode. The one or more first modes can include, for example, at least one of a normal operating mode of the host system or other type of load and a power reduction state (e.g., a sleep state, a hibernation state, or other low power state).

[0042] The controller 80 generates a set of second control signals for selectively enabling a second combination of the LDO stage 20 and the LDO stage 60. For example, the second combination of the LDO stages may be selectively enabled based on a second predetermined condition. The second predetermined condition may be based on, for example, a different one of the operating modes of the host system, a transition between two operating modes of the host system, and / or one or more other conditions related to the operating state and / or requirements of an application executed by the host system. The second combination of the LDO stages may correspond to the operation of at least one of the stages.

[0043] In one embodiment, the second predetermined condition includes a conversion of the host system from the first mode to the second mode. This may involve, for example, a conversion from a normal operating mode to a low power mode, from a low power mode to a normal operating mode, or a conversion between a low power mode or any two other modes of the host system. For example, the second control signal may be generated before a conversion between modes is about to occur, for example, when the controller 80 determines that a mode conversion is to be performed. The controller 80 may make this determination based on instructions from the host system and / or instructions stored in the non-transitory computer readable medium 85 and executed by the controller 80.

[0044] The controller 80 may generate a second control signal to enable at least the first LDO stage 60. In one embodiment, when a mode change occurs, the second control signal may enable both the first LDO stage 20 and the second LDO stage 60 during the transition period, but in one embodiment, the second LDO stage may be scaled down (or even shut down in some cases) during this transition period. Turning on the first LDO stage 20 or both LDO stages during the transition period between modes adjusts the response speed and output current level of the LDO regulator in a manner that reduces voltage undershoot and voltage overshoot (or prevents these conditions from occurring altogether) due to the mode transition.

[0045] In one embodiment, the response speed and output current level of the LDO regulator can be improved so that the output voltage (V out_LDO ) fall within a range sufficient to prevent voltage overshoot and voltage undershoot from occurring. Although enabling both LDO stages at the same time at this time (e.g., during a mode transition period) may temporarily increase power consumption, the benefits of preventing voltage overshoot and undershoot (which may adversely affect the performance of the host system, or even damage the host system) outweigh these considerations.

[0046] After the mode transition has been completed, the controller 80 may again generate a set of first control signals to disable the first LDO stage 20 and enable the second LDO stage 60, for example, to maintain low power consumption in normal or power reduction mode. In one embodiment, the generation of the second control signals in these situations may optionally be performed after a stabilization time after the mode transition period. Selectively enabling the first LDO stage 20 and the second LDO stage 60 (e.g., enabling and / or disabling a selected one of the first LDO stage and the second LDO stage) may be performed based on corresponding n and m control signals, where n≥1 and m≥1. The numbers m and n may be the same or different. Each of the set of first control signals and the set of second control signals may include one or more control signals.

[0047] The first LDO stage 20 may include a first current source 22, a second current source 24, a voltage regulator 26, and optional soft-off logic 28. In operation, the controller 80 generates one or more control signals for coupling the first current source to the second current source. The output of the second current source may be input to the voltage regulator, and the voltage regulator may then generate a first output voltage (V lout ). The optional soft shutdown logic can disable the output of the voltage regulator 26 based on one or more predetermined conditions, as discussed in detail below. Because the first LDO stage 20 generates the first output voltage when the second output voltage is not output (or has been scaled down), voltage overshoot and / or undershoot is reduced or prevented from occurring, and a stable output voltage is output from the LDO regulator during the mode transition period.

[0048] The second LDO stage 60 may include a voltage regulator 62 having an optional regulator 64 coupled to an output node of the LDO regulator. The voltage regulator 62 may be a closed-loop regulator or an open-loop regulator for generating a second output voltage at a desired level. The output voltage (V 2out ). The regulator 64 may adjust the second output voltage V before coupling to the output node. 2out The level of the second output voltage of the second LDO stage 60 is adjusted to one of the multiple desired voltages. For example, the regulator can be controlled based on at least one control signal from the host system, and the at least one control signal can set the level of the second output voltage of the second LDO stage 60 to one or more corresponding levels to power or drive one or more logic blocks, and the one or more logic blocks are used to support the operation of the host system in various modes. In one embodiment, the at least one control signal for setting the second output voltage level can be based on a user signal.

[0049] The controller 80 may control the second LDO stage 60 to generate a second output voltage V during one or more operating modes of the host system (or load). 2out , and the second LDO stage 60 can be controlled to temporarily block (or scale down) the second output voltage during the transition period between those modes. The second output voltage can be selectively generated in this manner even if, for example, in one embodiment, one or more enable signals are supplied to the second LDO stage 60 during the transition period, for example, for the purpose of performing the previously mentioned scaling down operation. In other embodiments, the second LDO stage 60 can be disabled during the transition period and / or based on the requirements of the host system.

[0050] Figure 22 shows an embodiment of a first LDO stage 220 and a second LDO stage 260 of an LDO regulator. The first LDO stage and the second LDO stage may be respectively connected to Figure 1 The controller 290 may generate signals for controlling the operating states of the LDO stages as described herein. The controller 290 may execute instructions stored in the memory 295 to generate control signals for selectively controlling the stages of the LDO regulators as described herein. The memory 295 may be a random access memory, a read-only memory, and / or various specific types of these non-transitory computer readable media. The controller 290 may be connected to, for example, Figure 1 The controller 80 may correspond to a different controller that generates one or more different control signals.

[0051] First, taking the second LDO stage 260 as an example, the second LDO stage 260 includes a voltage regulator 230 and a level adjuster 250. The voltage regulator includes a comparator 235 and a pass transistor 240. The comparator can be, for example, an operational amplifier having a non-inverting terminal coupled to receive a predetermined reference voltage (Vref) and an inverting terminal coupled to receive a feedback signal Vinn. The predetermined reference voltage Vref can correspond to a bandgap reference of a host system, for example. In one embodiment, the reference voltage Vref can serve as an accuracy reference with a first accuracy (e.g., 5%) without calibration and a second accuracy (e.g., 2%) with calibration. The feedback signal Vinn can correspond to the output of the level adjuster, for example. The pass transistor 240 can be an NMOS transistor that generates a second output voltage V by supplying a supply current from a voltage source Vdd. 2out To power the load in one or more operation modes. In another embodiment, the pass transistor may be a PMOS type transistor.

[0052] The comparator generates a voltage Vgate_2 that controls the gate of the transfer transistor 240. The voltage Vgate_2 can be fixed or can be controlled to one or more levels. In the latter case, the level adjuster can control the value of the input voltage Vinn. The level adjuster can include, for example, a voltage divider including a first resistor (R3) 241 and a second resistor (R4) 242. One of these resistors (e.g., the first resistor 241) can be a variable resistor having a value controlled, for example, based on a control signal from a host system and / or a user signal. By changing the value of this resistor, the second output voltage V 2out Adjusted to a level sufficient to meet the requirements of the intended application of the host system during one or more operating modes.

[0053] In this embodiment, the second LDO stage 260 has a closed-loop regulator topology formed by a comparator and a voltage divider, and uses a reference voltage Vref. In one embodiment, the second LDO stage 260 may have an open-loop topology provided, for example, this topology may meet the requirements of the host system. Based on Equation 1, the second output voltage V generated from the second LDO stage 260 may be generated 2out .

[0054] V 2out =V ref *[1+(R3 / R4)], (1)

[0055] Wherein R3 corresponds to a variable resistor, the resistance of which can be adjusted to change the level of the second output voltage. In one embodiment, the resistance value of R4 or the resistance values ​​of both R3 and R4 can be adjusted to change the level of the second output voltage.

[0056] The controller 290 can enable the second LDO stage 260 by asserting the control signal (en_1) 281, and can disable this stage by de-asserting (or inverting) this control signal. The controller 290 can assert the control signal (en_1) 281 during one or more operating modes. The operating mode can correspond to a normal mode or one or more low power modes (e.g., a sleep state, hibernation, etc.). One or more low power modes can correspond to situations where the host system is required to consume a small amount of current, and in some cases even as low as a few microamperes. In order to meet these performance requirements, the second LDO stage 260 may need to consume a quiescent current as low as a few microamperes or even lower.

[0057] The requirement for low quiescent current may limit the bandwidth (e.g., speed) of the second LDO stage. The second LDO stage 260 may not be fast enough to adequately respond to large and rapid changes in the required load current during mode transitions. For example, by Figure 3A This can be understood from the graph of FIG. 3, which shows two curves 310 and 320 showing that with only the second LDO stage turned on, when the load current switches from 1 mA to 3 mA within 3 nS, a large voltage undershoot is observed as low as 1.16 V. In this example, the voltage undershoot is about 35% lower than the typical output value of 1.8 V, which is low enough to trigger a host system reset. A voltage overshoot may also occur thereafter.

[0058] The additional effect of using only the second LDO stage during mode transitions is Figure 3B It is obvious. Figure 3BAs shown, when the load current switches from 3mA to 1mA in 3nS, a large voltage overshoot is observed up to 2.67V. This overshoot is about 48% higher than the typical output value of 1.8V of the first LDO stage. These conditions may also cause the host system (or other load) to crash or otherwise fail. When en_1 is deasserted, comparator 235 is disabled and its output Vgate_2 is pulled down to disable pass_FET_2240. When en_l_sd is asserted, R3241 is scaled to a higher value and V 2out to a lower value, and vice versa.

[0059] To compensate for these faults or the performance degradation that occurs therefrom, the controller 290 may enable the first LDO stage 220 during the mode transition. Because the first LDO stage 220 has a higher speed and a higher quiescent current than the second LDO stage 260, voltage overshoot and / or voltage undershoot may be reduced or prevented, thereby allowing improved performance during the transition period between operating modes of the host system. (In one embodiment, the operating mode may include any mode that does not involve a transition period between modes, and in this sense, any non-transition mode may be referred to as a normal mode.)

[0060] Reference again Figure 2 , the first LDO stage 220 includes a first current source 265, a second current source 270, and a voltage regulator 275. The first current source 265 may include, for example, a first transistor (MN1) 266 and a second transistor (MN2) 267 having gates coupled together at a node N1 to form a first current mirror circuit. The first transistor 266 is located in a first arm of the current mirror and receives an input current I bg , the input current I bg The mirror current I1 is mirrored in the second arm of the current mirror by the second transistor 267. The current mirror circuit 265 has a first current mirror ratio m, and thus the mirror current I1 output from the first current mirror circuit 265 is equal to m*I bg In one embodiment, if the host system supplies the current I1, the first current source 265 can be omitted.

[0061] The second current source 270 may include, for example, a first transistor (MP) having a gate l) 271 and a second transistor (MP2) 272, the gates of which are coupled together at a node N2 to form a second current mirror circuit. The first transistor 271 is located in the first arm of the second current mirror and receives the output current I1 from the first current mirror as its input current. The current I2 is mirrored in the second arm of the second current mirror by the second transistor 272. The current mirror circuit 270 has a second current mirror ratio n, and thus the mirror current I2 output from the second current mirror circuit 270 is proportional to n*I1. The current mirror ratios m and n can be predetermined values ​​that are the same or different from each other. The transistors of different conductivity types used in the first current mirror circuit and the second current mirror circuit partially allow the first LDO stage to operate in the following manner.

[0062] Current I bg By using the bandgap voltage V bg The division by resistor R results from the chip main bias and can be expressed, for example, by Equation 2.

[0063] I bg =V bg / R, (2)

[0064] Where V bg is a precise reference voltage, and R is a bandgap voltage generator that produces I bg The resistor R is required to be located on the same silicon substrate as R1277 so that R and R1 have the same process inflection point. Therefore, R1 / R is a constant number in the process, power supply voltage and temperature (PVT). The output current I1 from the first current source 265 and the output current I2 from the second current source 270 can be calculated based on equations 3 and 4, respectively.

[0065] I1=I bg *m=(V bg / R)*m (3)

[0066] I2=I1*n=(V bg / R)*m*n (4)

[0067] The voltage regulator 275 includes a matching transistor 276, a resistor (R1) 277, a transfer transistor 278, a capacitor 279, and a transistor 280. The matching transistor (matching FET) 276 is coupled to the transistor 272 at a node N3. In one embodiment, the matching transistor can be an NMOS transistor connected between the resistor 277 and the output of the second current source 270 in a diode-coupled state. When the current I2 has a sufficient magnitude to forward bias the matching transistor, the voltage of the node N3 is set based on the resistance value of the resistor 277 and the voltage drop of the diode-connected matching transistor 276. This voltage corresponding to Vgate_1 controls the gate signal entering the transfer transistor 278. Unstable changes in the gate signal Vgate_1 that may produce unstable performance can be suppressed (or otherwise controlled) by connecting the gate line in parallel with the capacitor (C2) 279. This capacitor can also be used to filter out stray (e.g., out-of-band) signals superimposed on the gate line.

[0068] Pass transistor 278 is controlled by the value of gate signal Vgate_1 output from matching transistor 276. In one embodiment, the pass transistor may have the same conductivity type as the matching transistor. Figure 2 In FIG. 2 , both transistors are shown as NMOS transistors, but in another embodiment, these transistors can be PMOS transistors. When the value of the gate signal Vgate_1 (based on I2) exceeds its threshold voltage, the pass transistor 278 is turned on to generate a current I derived from the voltage source Vdd. out Generates the first output voltage V of the first LDO stage lout The output voltage V can be generated based on Equation 5 lout :

[0069] V lout =I2*R1+V gs_match -V gs_pass

[0070] =(V bg *m*n)*(R1 / R)+V gs_match -V gs_pass , (5)

[0071] Where V gs_match is the gate-source voltage of matching transistor 276, and V gs_pass is the gate-source voltage of the pass transistor (pass FET_1) 2878.

[0072] In operation, the matched transistors enable the voltage V gs_match With voltage V gs_passIn this way, the voltage drop across the matching transistor and R1 effectively controls (or stabilizes) the level of the output voltage of the first LDO stage, for example, at one or more predetermined levels depending on the intended application or requirements of the host system. Due to this matching operation, the matching transistor and the pass transistor can have the same conductivity type and the same channel length. Moreover, in order to ensure that the voltage V gs_match With voltage V gs_pass Matching, the channel width ratio between the pass transistor and the matching transistor can be as close as possible to I out In this case, Equation 5 can be simplified to Equation 6:

[0073] V lout =I2*R1+V gs_match -V gs_pass

[0074] =I2*R1

[0075] =(V bg *m*n)*(R1 / R) (6)

[0076] Where R1 / R, m, and n are constant values ​​based on, for example, the design requirements of the host system. In this case, the output voltage V lout Can be V bg In some cases, there may be a mismatch in the first current mirror circuit and the second current mirror circuit, between R1 and R, and / or between the matching transistor and the pass transistor. Thus, in such a case, a calibration operation may be performed. For example, the calibration operation may involve changing one or more parameters of the first current mirror circuit 265 and / or the second current mirror circuit 270, and / or adjusting the resistance value R1 to improve accuracy.

[0077] In one embodiment, to ensure high speed, the value of current I2 can be increased (e.g., by controlling one or both current ratios of m or n) to limit the resistance value of R1. This resistance value can be limited to maintain the gate of pass transistor 278 as a low impedance node. Therefore, during the mode transition from low load current to high load current, the first output voltage V 1out can begin to drop, and the internal gate-source capacitance (Cgs) of the pass transistor can be charged fast enough to maintain a constant value of the gate voltage of the pass transistor 278. As a result, when the first output voltage V lout When decreased, the gate-source voltage of the pass transistor (Vgs_pass) 278 may be controlled (eg, increased).

[0078] In one embodiment, the load current I load(For example, from the second LDO stage to node N OUT The current output) can be determined based on Equation 7:

[0079] I load =(1 / 2)*μ n *C ox *(W / L)(V gs_pass -V thn )2*(1+λ*V ds_pass ), (7)

[0080] Among them, μ n Indicates the mobility of the transfer transistor, C ox is the gate oxide capacitance per unit area of ​​the pass transistor, V thn is the threshold voltage of the pass transistor (NMOS) 278, λ is the channel length modulation factor of the pass transistor, V gs_pass is the gate-to-source voltage of the pass transistor (i.e., V gate_1 -V lout ), and V ds_pass is the drain-to-source voltage of the pass transistor (i.e., Vdd-V lout ). It is obvious from equation 7 that as the current I load The first output voltage V lout decreases, then the voltage V gs_pass increases, which has the effect of suppressing the voltage V ds_pass further increase, thereby reducing or avoiding voltage undershoot.

[0081] On the other hand, during the mode transition from high load current to low load current, the opposite operation can be performed to avoid V lout The voltage overshoot at the point. It is obvious from equation 7 that as the current I load The first output voltage V lout increases, then the voltage V gs_pass decreases, which has the effect of suppressing the voltage V ds_pass further reduces, thereby reducing or avoiding voltage overshoot.

[0082] To maintain low impedance, the gate of pass transistor 278 is coupled to capacitor (C2) 279. The capacitance value of C2 may be selected, for example, based on limitations on the silicon area occupied by the pass transistor.

[0083] In addition to the foregoing features, the first LDO stage 220 may include a transistor (MN4) 285, a transistor 286 (MN6), and a transistor 287 (MP4). These transistors may be small switching devices having gates coupled to receive an enable signal for controlling aspects of the operation of the first LDO stage. For example, transistors 285 and 286 are controlled based on the complement of the enable signal enb_h, and transistor 287 is controlled based on the enable signal en_h. In the case where both transistors 285 and 286 are NMOS transistors and transistor 287 is a PMOS transistor, a logic zero value of the enable signal en_h will turn off the first current source 265 and the voltage regulator 275, and a logic one value of the complement of this enable signal will turn off the second current source 270. As a result, the first LDO stage will be disabled based on these logic values. Conversely, the first LDO stage will be enabled based on the opposite logic values ​​of en_h and enb_h. Therefore, transistors 285, 286, and 287 can be considered to be in the shutdown circuit of the first LDO stage.

[0084] In addition to the shutdown circuit, the first LDO stage 220 may include a soft shutdown circuit 68, which includes a capacitor (C1) 295, a transistor (MN3) 296, a resistor (R2) 297, and a transistor (MN5) 298. Transistor 296 is coupled between the gate line of the pass transistor and a reference potential through resistor R2. Transistor 298 is coupled between the gate line of transistor 296 and a ground reference potential, and capacitor 295 is coupled to receive a charging current I charg In operation, node N4 couples a portion of this charging current to the gate of transistor 296 and the drain of transistor 298 and couples another portion of the charging current for charging capacitor 295.

[0085] The soft-off circuit 68 can control the shutdown of the second LDO stage at a slower rate than the shutdown circuit. The rate can be based on the charging time of the capacitor (C1) 295, for example. For example, when the transistor 298 is turned on, the soft-off circuit 68 is disabled based on the first logic value of the enable signal en_h_s. When the transistor 298 is turned off based on the second logic value of the disable signal en_h_s, the charging current I current The capacitor 295 begins to be charged. When the capacitor 295 is charged, the gate voltage of the transistor 296 reaches its threshold voltage at a certain point in time. At this point in time, the transistor 296 is turned on and the current I3 flows through the resistor 297 to gradually reduce the gate voltage of the pass transistor, thereby slowly reducing or shutting off the first output voltage V of the first LDO stage. lout .

[0086] Figure 4 Shows the control Figure 21 is an embodiment of a timing diagram of a parallel stage of LDO regulators. The timing diagram is divided into time periods that sequentially include a first operating mode, a first mode transition, a second operating mode, a second mode transition, and a first operating mode. The first mode and the second mode can be, for example, modes of a host system or other loads. During each specified time period, the controller 290 controls (enables) the values ​​of various combinations of signals to selectively control the first and second stages of the LDO regulators. Reference numerals 410, 420, 430, and 440 are waveforms corresponding to respective signals in the control signal.

[0087] refer to Figure 4 , before the first mode, the LDO regulator operates in an initial mode, in which all control signals have a first logic value, which may be based on, for example, Figure 2 As described herein, the controller 290 changes the control signal from a first logic value to a complementary second logic value at a selected time. In another embodiment, the logic value of the control signal can be different, for example, based on implementing the LDO regulator using different transistor logic. The control signals may include a first control signal (en_1) for enabling the second LDO stage, a second control signal (en_h) for enabling the first LDO stage, a third control signal (en_h_s) for controlling a soft shutdown of the first LDO stage, and a fourth control signal (en_1_sd). These control signals are shown to Figure 2 The inputs of the various transistors.

[0088] In the first mode (first occurrence), the first control signal (en_1) is converted to a logic one value, and the remaining control signals have a logic zero value. As a result, the second LDO stage 260 is enabled and the first LDO stage is disabled, and the output voltage (Vout_LDO) of the LDO regulator is based on the output voltage Vout of the second LDO stage. 2out The first mode may be any operating mode of the host system. For illustrative purposes, the first mode is described as a normal mode, such as a normal power mode. In other embodiments, the normal mode may be considered to be, for example, a power reduction mode in a plurality of power reduction modes.

[0089] In the first mode conversion period (second occurrence), the second control signal (en_h) and the third control signal (en_h_s) are controlled to a logic one value together with the first control signal (en_1). At this time, the fourth control signal (en_l_sd) remains low. As a result, the second LDO stage remains turned on, and the first LDO stage 220 is enabled by the logic one value of the second control signal (en_h) and the logic one value of the third control signal (en_h_s), and the logic one value of the third control signal is used to disable the shutdown circuit 68 by coupling the gate of the transistor MN3296 to the ground. At this time, the first LDO stage generates its output V lout , the output together with the output of the second LDO stage V 2out Coupled to node N OUT Therefore, for a short period of time, the output voltage of the LDO regulator is based on any higher voltage, such as Vout_LDO = max(V 2out , V lout ).

[0090] Moreover, after the stabilization time t1 in the first mode conversion period, the fourth control signal (en_l_sd) is converted to a logic one value, for example, at this time all four control signals have a logic one value. The logic one value of the fourth control signal controls the second LDO stage to scale down its output voltage V by increasing the value of R3241 to a predetermined value. 2out .

[0091] The predetermined value is much lower than the output voltage V of the first LDO 220. 1out The value of 2240 is such that the output of the comparator 235 turns off the pass_FET_2240 and the first LDO takes over the power supply as described in the following paragraphs. The purpose of switching from the first mode to the second mode is that the first LDO takes over the power supply.

[0092] In one embodiment, the reference voltage Vref entering the comparator 235 may be represented by Equation 8 which may be derived from Equation 1.

[0093] V ref =V 2out *[1+(R3 / R4)] (8)

[0094] In this case, the feedback voltage Vinn can be based on Equation 9. Therefore, according to these equations, during the first mode transition, V inn >V ref , and V gate_2 will be pulled down to ground by the comparator. As a result, the pass transistor will be turned off. Then, the output voltage V lout Takes over to supply power to the host system.

[0095] Vinn =V lout *[1+(R3 / R4)] (9)

[0096] In one embodiment, depending on the requirements of the host system, another option is to de-assert the first control signal (en_1) to completely disable the second LDO stage, instead of asserting the fourth control signal (en_1_sd) to scale down the output voltage V of the second LDO stage from the pass transistor. 2out In this case, the second LDO stage can be re-enabled (by re-asserting en_1) after the host system switches back to the next or previous operating mode. 1out The parallel LDO stage takes over supplying power to the host system, so due to the high speed design of the first LDO stage, the parallel LDO stage has a sufficiently high speed to respond to the mode conversion. In other words, by controlling the logic value of the control signal in the aforementioned manner, the conversion to the second mode can be performed at a sufficient speed and power to prevent the voltage overshoot condition and the voltage undershoot condition from occurring.

[0097] In the second mode, the states of all four control signals may remain unchanged, for example, at a logic one value. By keeping all enable signals the same, the output voltage of the first LDO stage dominates the LDO regulator output. In the second mode, the output voltage of the first LDO must be designed to be higher than the scaled-down output voltage of the second LDO so that the first LDO dominates the LDO regulator output. As described above, the scaled-down V 2out Or turn off LDO260 to ensure that LDO 220 dominates the LDO regulator output so that V lout >V 2out .

[0098] In a second transition mode (e.g., returning from the second mode to the first mode), the fourth control signal (en_l_sd) transitions to a logic zero value. This turns off the scaling down of the output voltage of the second LDO stage. Then, after a period t2, the third control signal (en_h_s) transitions to a logic zero value, which has the effect of performing a soft shutdown of the first LDO stage. Then, after another period t3, the second control signal (en_h) transitions to a logic zero value, thereby turning off the first LDO stage. As a result, since the first control signal (en_1) remains at a logic one value and the scaling down circuit of the second LDO stage has been turned off, the output voltage V 2out The output voltage of the LDO regulator (Vout_LDO) is again controlled.

[0099] By controlling the transitions of the second, third, and fourth control signals in this stepwise manner, the controller can control the transition back to the first mode (or third mode) at sufficient speed and power to prevent voltage overshoot conditions and voltage undershoot conditions from occurring.

[0100] Instead of transferring from the second mode back to the first mode, in one embodiment, a transition may be performed from the second mode to a third mode, which may, for example, correspond to another operating mode of the host system, such as a power reduction mode or another type of mode.

[0101] The operation of the soft-off circuit 68 during mode transitions can be explained more fully as follows. Figure 4 As shown, during the transition from the second mode to the first mode and before the first LDO stage is disconnected by deasserting the control signal en_h, the output voltage V of the first LDO stage is performed. lout When both the en_h and en_h_s control signals have a logic one value, the gate voltage of transistor MN3 is pulled down due to the transistor MN5 being turned on. This causes transistor MN3 to be turned off, and the voltage stored in capacitor C1 is discharged to ground through transistor MN5. charge The derived current can also be connected to ground via MN5.

[0102] In addition, when the control signal en_h still has a logic one value and during this period the control signal en_h_s switches from logic high to low, the transistor MN5 is turned off and the current I charge C1 is charged. This causes the gate voltage of transistor MN3 to increase to a level sufficient to turn on transistor MN3. Raising the gate voltage of transistor MN3 causes the source voltage of transistor MN3 and current I3 to increase. Therefore, the current through resistor R2 increases, and the current through resistor R1 decreases. As a result, the gate voltage of the pass transistor decreases, which in turn causes the second LDO stage V lout The output voltage decreases.

[0103] Therefore, by controlling the current I charge The value of capacitor C1 and the voltage of the pass transistor V gate_1 This will control the output voltage V lout In addition, resistor R2 may be coupled to the source of transistor MN3, which may actually be a source negative feedback topology that uses transistor MN3 to prevent current I3 from increasing. In one embodiment, resistor R2 is coupled between node N3 and the drain of transistor MN3. In this case, a soft turn-off operation may be performed. Current I chargeIt may be generated locally, for example, from an internal current mirror of the LDO regulator, or may be provided from a host system. The first LDO stage has an open-loop topology. In another embodiment, the first LDO stage may have a closed-loop topology.

[0104] Figure 5 5 is a graph showing an example of simulation results of one or more of the foregoing embodiments. In this graph, as previously described, a graph showing the performance of an LDO regulator when a first mode transition (from a low load current to a high load current) occurs is shown. The voltage curve 510 shows the performance of the regulator output (Vout_LDO), and the current curve 520 shows the load current (I LOAD As shown in these curves, voltage overshoot and voltage undershoot are avoided during the mode transition period due to activation of the first LDO stage as described herein.

[0105] Figure 6 6 is a graph showing an example of additional simulation results for one or more of the foregoing embodiments. In this graph, as previously described, a graph showing the performance of an LDO regulator when a second mode transition occurs (from a high load current to a low load current) is shown. The voltage curve 610 shows the performance of the regulator output (Vout_LDO), and the current curve 620 shows the load current (I LOAD As shown in these curves, voltage overshoot and voltage undershoot are avoided during the mode transition period due to activation of the first LDO stage as described herein. Figure 5 and 6 In some cases, voltage changes may still occur during mode transitions. However, the changes are much smaller and within an acceptable range, such as within + / -10% of the typical value.

[0106] In some embodiments, after switching back from the second mode to the first mode, the first LDO stage can be completely disconnected to meet low power consumption requirements. Due to the low power and low speed design of the second LDO stage, a soft shutdown operation can be performed on the first LDO stage to provide sufficient time for the second LDO stage to take over the supply power during the first operation mode. As previously described, this can be achieved by first de-asserting the control signal en_h_s to allow the output voltage V lout The output voltage V 1out During the ramp-down period of , the pass transistor (pass FET_2) of the second LDO stage can be turned on, and the second LDO stage takes over supplying power to the host system (e.g., load). Then, the control signal en_h can be de-asserted to completely disconnect the first LDO stage.

[0107] Figure 77 is a graph showing an example of simulation results of the output voltage of the LDO regulator. In this graph, the curve 710 is plotted against the output voltage V out_LDO Correspondingly, curve 720 corresponds to control signal en_h, curve 730 corresponds to control signal en_h_s, and curve 740 corresponds to control signal en_l_sd. As can be seen, the changing values ​​of the control signals selectively activate the parallel connection of the LDO stages over a predetermined time sequence. As previously described, this selective activation prevents large voltage overshoot and large voltage undershoot conditions from occurring, even when the output voltage of the LDO regulator changes within a predetermined acceptable range.

[0108] According to one or more of the foregoing embodiments, an LDO regulator is provided with two LDO stages coupled in parallel, wherein each stage outputs a different voltage level and operates based on a different speed and quiescent current. The LDO stages are selectively controlled to reduce or prevent voltage undershoot and / or voltage overshoot that may occur during transitions between operating modes of a load, for example, the load may be a host system of the LDO regulator. Selective control of the LDO stages ensures smooth switching from one mode to another to prevent reset or other host circuit failures from occurring. The arrangement also ensures low power consumption during the operating modes.

[0109] The controllers, processors, voltage regulators, voltage regulators, comparators, current generators, and other signal generation and signal processing features of the embodiments disclosed herein may be implemented in logic that may include, for example, hardware, software, or both. When implemented at least in part in hardware, the controllers, processors, voltage regulators, voltage regulators, comparators, current generators, and other signal generation and signal processing features may be, for example, any of a variety of integrated circuits, including but not limited to an application specific integrated circuit, a field programmable gate array, a combination of logic gates, a system on a chip, a microprocessor, or another type of processing or control circuit. In addition, it is noted that R and R1 will be on the same chip so that R1 / R is constant over variations in process, voltage supply, and temperature (PVT).

[0110] When implemented at least in part in software, controllers, processors, voltage regulators, voltage regulators, comparators, current generators, and other signal generation and signal processing features may include, for example, a memory or other storage device for storing, for example, codes or instructions to be executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be one of those described herein or in addition to the elements described herein. Because the algorithms that form the basis of the method (or the operation of a computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operation of the method embodiments may transform the computer, processor, controller, or other signal processing device into a dedicated processor for performing the method described herein.

[0111] Benefits, advantages, solutions to problems, and any element that may make any benefit, advantage, or solution present or more significant are not to be construed as a critical, required, or essential feature or element of any or all the claims. The present invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.

[0112] Although various exemplary embodiments have been described in detail with particular reference to certain exemplary aspects of the various exemplary embodiments, it should be understood that the present invention allows for other exemplary embodiments, and the details of the present invention allow for modifications in various obvious aspects. As will be readily apparent to those skilled in the art, changes and modifications may be made while remaining within the spirit and scope of the present invention. The embodiments may be combined to form additional embodiments. Therefore, the foregoing disclosure, description, and drawings are for illustrative purposes only and do not limit the present invention in any way, the present invention being limited only by the claims.

Claims

1. A low voltage dropout regulator, characterized in that: include: a first stage configured to generate a first output voltage; as well as a second stage configured to generate a second output voltage different from the first output voltage, wherein the first stage and the second stage are coupled in parallel to a node, the first stage is configured to be selectively controlled to generate the first output voltage based on a first condition, and the second stage is configured to be selectively controlled to generate the second output voltage based on a second condition different from the first condition, and wherein the second output voltage decreases during a mode transition such that the first output voltage is greater than the second output voltage; The first stage is configured to operate at a first speed and based on a first quiescent current, and The second stage is configured to operate at a second speed and based on a second quiescent current, the first speed being different from the second speed and the first quiescent current being different from the second quiescent current.

2. The low voltage dropout regulator according to claim 1, characterized in that: The first output voltage is within a range that reduces voltage overshoot or undershoot in a signal output from the node.

3. The low voltage dropout regulator according to claim 1, characterized in that: The first condition includes a transition between a first mode and a second mode of a load coupled to the node, and The second condition includes operation of the load during at least one of the first mode and the second mode.

4. The low voltage dropout regulator according to claim 3, characterized in that: The first stage is configured to be selectively controlled based on a first set of control signal values ​​to produce the first output voltage during the conversion period, and The second stage is configured to be selectively controlled based on a second set of control signal values ​​to produce the second output voltage during each of the first mode and the second mode.

5. The low voltage dropout regulator according to claim 4, characterized in that: The first mode and the second mode correspond to different operation modes of a load.

6. The low voltage dropout regulator according to claim 5, characterized in that: At least one of the first mode and the second mode is a power reduction mode.

7. The low voltage dropout regulator according to claim 1, characterized in that: The first speed is greater than the second speed, and The first quiescent current is greater than the second quiescent current.

8. The low voltage dropout regulator according to claim 1, characterized in that: The first stage includes a soft-off circuit configured to reduce a level of the first output voltage based on operation of the second stage.

9. A device for controlling a low dropout voltage (LDO) regulator comprising a first stage and a second stage, characterized in that, The first stage and the second stage are coupled to an output node, the apparatus comprising: a memory configured to store instructions; and A processor configured to execute the instructions to produce: one or more first control signals that cause the first stage to generate a first output voltage based on a first condition, one or more second control signals that cause the second stage to generate a second output voltage based on a second condition, wherein the second output voltage is different from the first output voltage, and wherein the second output voltage decreases during a mode transition such that the first output voltage is greater than the second output voltage; The first stage is configured to operate at a first speed and based on a first quiescent current, and The second stage is configured to operate at a second speed and based on a second quiescent current, the first speed being different from the second speed and the first quiescent current being different from the second quiescent current.

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