Semiconductor device

Abstract

A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, a first bonding pad penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and a first metal pattern in the first insulating layer and in contact with the first bonding insulating layer and having an upper surface at a lower level than an upper surface of the first bonding pad. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and a second bonding pad penetrating the second bonding insulating layer and connected to the first bonding pad.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0052606, filed on April 29, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The exemplary embodiments of the present invention relate to semiconductor devices. Background Technology

[0004] It is desirable for semiconductor devices to have reduced size and the ability to process higher volumes of data. Therefore, there is a desire to increase the integration density of semiconductor elements included in semiconductor devices. Summary of the Invention

[0005] Some exemplary embodiments of the present invention provide a semiconductor device in which bonding pads forming a layer and a metal pattern used for wiring can be formed simultaneously, thereby reducing process and cost. Semiconductor devices employing methods of wafer bonding can be provided to improve the integration density of semiconductor devices.

[0006] According to some exemplary embodiments of the present invention, a semiconductor device includes: a first structure including a first bonding structure; and a second structure on the first structure, including a second bonding structure connected to the first bonding structure. The first bonding structure includes: a first insulating layer; a first bonding insulating layer on the first insulating layer; a first bonding pad penetrating at least a portion of the first insulating layer and the first bonding insulating layer; and a first metal pattern in the first insulating layer, the first metal pattern contacting the first bonding insulating layer, the first metal pattern having an upper surface that, in a vertical direction extending perpendicular to the lower surface of the first structure, is closer to the upper surface of the lower surface of the first structure than the upper surface of the first bonding pad. The second bonding structure includes: a second bonding insulating layer bonded to the first bonding insulating layer; a second insulating layer on the second bonding insulating layer; and a second bonding pad penetrating the second bonding insulating layer and connected to the first bonding pad.

[0007] According to some exemplary embodiments of the present invention, a semiconductor device includes: a first structure including a first bonding structure; and a second structure on the first structure, including a second bonding structure connected to the first bonding structure. The first bonding structure includes: a first insulating layer; a first bonding insulating layer on the first insulating layer; a first bonding pad penetrating the first insulating layer and at least a portion thereof; and a first metal pattern in the first insulating layer and in contact with the first bonding insulating layer. The first bonding insulating layer includes: a first region penetrated by the first bonding pad and a second region in contact with a portion of the first metal pattern.

[0008] According to some exemplary embodiments of the present invention, a semiconductor device includes: a first bonding structure having a first bonding surface; and a second bonding structure on the first bonding structure, having a second bonding surface in contact with the first bonding surface. The first bonding structure includes: a first insulating layer; a first bonding insulating layer on the first insulating layer and at least partially defining the first bonding surface; a first bonding pad penetrating the first insulating layer and at least a portion of the first bonding insulating layer, and at least partially defining the first bonding surface; and a first metal pattern in the first insulating layer, all having an upper surface lower than the first bonding surface. Detailed Implementation

[0009] The above and other aspects, features, and advantages of the present invention will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0010] Figure 1 This is a layout diagram illustrating the arrangement of semiconductor devices according to some exemplary embodiments of the concept of the present invention;

[0011] Figure 2A and Figure 2B This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention;

[0012] Figure 3 This is a cross-sectional view illustrating a portion of a semiconductor device according to some exemplary embodiments of the concept of the present invention;

[0013] Figure 4A , Figure 4B and Figure 4C This is a layout diagram illustrating a portion of the elements of a semiconductor device according to some exemplary embodiments of the concept of the present invention;

[0014] Figure 5A , Figure 5B and Figure 5CThis is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention;

[0015] Figure 6 , Figure 7 , Figure 8 , Figure 9A and Figure 9B This is a cross-sectional view illustrating a portion of a semiconductor device according to some exemplary embodiments of the concept of the present invention;

[0016] Figure 10 This is a cross-sectional view illustrating some exemplary embodiments of a semiconductor device according to the present invention;

[0017] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the present invention;

[0018] Figure 12A , Figure 12B , Figure 12C and Figure 12D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the present invention;

[0019] Figure 13A , Figure 13B and Figure 13C This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the present invention; and

[0020] Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 14F , Figure 14G , Figure 14H and Figure 14I This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the concept of the present invention. Attached Figure Description

[0021] In the following description, some exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings. In the following description, unless otherwise indicated, the terms "upper," "upper part," "upper surface," "lower," "lower part," "lower surface," "side surface," etc., may be used with reference to the accompanying drawings.

[0022] Figure 1 This is a layout diagram illustrating the arrangement of semiconductor devices according to some example embodiments.

[0023] refer to Figure 1 In some example embodiments, the semiconductor device 10 may include a first structure S1 and a second structure S2. The first structure S1 and the second structure S2 may be coupled and combined with each other.

[0024] The first structure S1 may include peripheral circuitry, and the second structure S2 may include a memory cell array region (MCA). Multiple memory cell arrays (MCAs) may be disposed within the second structure S2. In some example embodiments, the first structure S1 may be referred to as a logic chip structure, and the second structure S2 may be referred to as a memory chip structure.

[0025] Peripheral circuitry may include a row decoder (DEC), a page buffer (PB), and other PERI circuitry. PERI circuitry may include latch circuitry, cache circuitry, sense amplifiers, input and output buffers, electrostatic discharge (ED) devices, or data input and output circuitry. The row decoder (DEC), page buffer (PB), and PERI circuitry in the peripheral circuitry can be configured in various ways.

[0026] Figure 2A and Figure 2B This is a cross-sectional view of a semiconductor device according to some example embodiments.

[0027] Figure 3 This is a cross-sectional view showing a portion of a semiconductor device according to some example embodiments.

[0028] refer to Figures 2A to 3 The semiconductor device 10a may include a first structure S1 and a second structure S2 stacked on top of each other. Figure 2A The diagram shows the state before the first structure S1 and the second structure S2 are joined together, and Figure 2B The diagram shows the state in which the first structure S1 and the second structure S2 are joined together. Figure 3 It is shown Figure 2A Enlarged views of regions "A" and "B" as shown.

[0029] The first structure S1 may include a first substrate structure SS1 and a first bonding structure BS1 disposed on the first substrate structure SS1. The second structure S2 may include a second bonding structure BS2 and a second substrate structure SS2 disposed on the second bonding structure BS2. The second bonding structure BS2 may be connected to (e.g., in direct contact with) the first bonding structure BS1. As shown, the first bonding structure BS1 may have a first bonding surface BSS1, and the second bonding structure BS2 may have a second bonding surface BSS2 in contact with the first bonding surface BSS1. The first substrate structure SS1 may include a peripheral circuit region in which circuit devices are electrically connected to each other, and the second substrate structure SS2 may include a memory cell region.

[0030] It will be understood that an element described herein as being “on” another element can be directly on or indirectly on another element. An element being directly above another element will be understood as being in direct contact with the other element. An element being indirectly above another element will be understood as being in direct contact with each other through one or more intervening spaces and / or structures. Furthermore, it will be understood that an element described herein as being “on” another element can be “above” or “below” the other element.

[0031] The first bonding structure BS1 may include: a first insulating layer 195; a first bonding insulating layer 190 disposed (e.g., located) above the first insulating layer 195; and a first bonding pad 180 penetrating at least a portion of the first insulating layer 195 and the first bonding insulating layer 190. The second bonding structure BS2 may include: a second bonding insulating layer 290; a second insulating layer 295 disposed above the second bonding insulating layer 290; and a second bonding pad 280 penetrating at least a portion of the second insulating layer 295 and the second bonding insulating layer 290. The second bonding insulating layer 290 may be bonded (e.g., fixed, attached, etc.) to the first bonding insulating layer 190. The second bonding pad 280 may be connected to separate first bonding pads 180.

[0032] The first bonding pad 180 may have an upper surface 180S that, together with the upper surface 190S of the first bonding insulating layer 190 (which may include the upper surface of the conductive layer 180i of the first bonding pad 180 and the upper surface of the barrier metal layer BM), provides a bonding surface of the first structure S1 (e.g., the first bonding surface BSS1 of the first bonding structure BS1), and the lower surface of the second bonding pad 280 may, together with the upper surface of the second bonding insulating layer 290, provide a bonding surface of the second structure S2 (e.g., the second bonding surface BSS2). To reiterate, the first bonding insulating layer 190 and the first bonding pad 180 may jointly define the first bonding surface BSS1, and the second bonding insulating layer 290 and the second bonding pad 280 may jointly define the second bonding surface BSS2. The upper surfaces of the first bonding pad 180 and the second bonding pad 280 may be exposed at the bonding surfaces of the first structure S1 and the second structure S2. The first bonding pad 180, together with the second bonding pad 280, can serve as a bonding layer for bonding the first structure S1 and the second structure S2. Compared to other wiring structures, the first bonding pad 180 can have a relatively large planar area to provide bonding with the second structure S2 and the electrical connection path according to the bonding. The first bonding pad 180 can be disposed in a position corresponding to the second bonding pad 280, and each of the first bonding pads 180 can have dimensions that are substantially the same or similar to those of each of the second bonding pads 280. For example, the first bonding pad 180 can include a conductive material such as copper (Cu). The height of the lower surface of the first bonding pad 180 and the height of the lower surface of the first metal pattern 170 can be substantially the same (e.g., the lower surface of the first bonding pad 180 and the lower surface of the first metal pattern 170 can be the same height, or the distance from the lower surface S1b of the first structure S1 in the Z direction, which is a vertical direction perpendicular to the lower surface S1b), but some example embodiments are not limited to this.

[0033] It will be understood that the “height” of the surfaces, ends, etc., of the first structure S1 and / or the second structure S2 as described herein can refer to the distance of a given surface, end, etc., from the lower surface S1b of the first structure S1 in a vertical direction (e.g., the Z direction) perpendicular to the lower surface S1b, which can be as follows: Figure 2A The lower surface of the first substrate structure SS1 is shown. Therefore, a surface in the first structure S1 that has a “lower height” than another surface or end will be understood as being closer to the lower surface S1b in the Z direction than other surfaces or ends.

[0034] It will be understood that an element and / or its properties (e.g., structure, surface, orientation, etc.) can be described as "perpendicular", "parallel", "coplanar", etc., relative to other elements and / or its properties (e.g., structure, surface, orientation, etc.), and can be "perpendicular", "parallel", "coplanar", etc., respectively, or can be "substantially perpendicular", "substantially parallel", "substantially coplanar".

[0035] An element and / or its properties (e.g., structure, surface, orientation, etc.) being “substantially perpendicular” to other elements and / or its properties will be understood as being “perpendicular” to other elements and / or its properties within manufacturing and / or material tolerances, and / or having a deviation of equal to or less than 10% in size and / or angle from being “perpendicular” to other elements and / or its properties (e.g., ±10% tolerance).

[0036] An element and / or its properties (e.g., structure, surface, orientation, etc.) being “substantially parallel” relative to other elements and / or its properties will be understood as being “parallel” relative to other elements and / or its properties within manufacturing and / or material tolerances, and / or having a deviation of equal to or less than 10% in size and / or angle from the “parallelism” relative to other elements and / or its properties (e.g., ±10% tolerance).

[0037] An element and / or its properties (e.g., structure, surface, orientation, etc.) being "substantially coplanar" with respect to other elements and / or its properties will be understood as being "coplanar" with respect to other elements and / or its properties within manufacturing and / or material tolerances, and / or having a deviation of equal to or less than 10% in size and / or angle from the "coplanarity" with respect to other elements and / or its properties (e.g., ±10% tolerance).

[0038] It will be understood that elements and / or properties that may include means and / or operation may be described herein as “identical” or “equal” to other elements, and it will also be understood that describing elements and / or properties as “identical” or “equal” to other elements herein may mean “identical” or “equal” to other elements and / or properties, or “substantially identical” or “substantially equal” to other elements and / or properties. “Substantially identical” or “substantially equal” to other elements and / or properties will be understood to include elements and / or properties that are identical or equal to other elements and / or properties within manufacturing tolerances and / or material tolerances. “Identical or substantially identical” to other elements and / or properties may mean structurally identical or substantially identical, functionally identical or substantially identical, and / or compositionally identical or substantially identical.

[0039] It will be understood that elements and / or properties that may include the device and / or operation are described herein as “substantially” identical, including that the elements and / or properties are identical within manufacturing and / or material tolerances, and / or that the elements and / or properties have a relative difference of equal to or less than 10% in magnitude. Furthermore, regardless of whether the elements and / or properties are modified to “substantially”, it will be understood that these elements and / or properties should be taken into account, including the available manufacturing or operational tolerances (e.g., ±10%) of the described elements and / or properties (e.g., structure, properties of one or more elements, length, distance, parallel or perpendicular arrangement, etc.).

[0040] Furthermore, regardless of whether the elements and / or their properties (e.g., structure, surface, orientation, etc.) are "substantially" modified, it will be understood that these elements and / or their properties should be taken into account, including the manufacturing or operational tolerances (e.g., ±10%) of the described elements and / or their properties that are available.

[0041] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, it means that the associated numerical value includes a tolerance of ±10% around the stated value. When a range is specified, the range includes all values ​​within that range, such as an increment of 0.1%.

[0042] The first bonding insulating layer 190 and the second bonding insulating layer 290 may be formed of an insulating material to allow them to contact and bond with each other. For example, the first bonding insulating layer 190 and the second bonding insulating layer 290 may include at least one of SiCN, SiO, SiN, SiOC, SiON, or SiOCN. The first bonding insulating layer 190 and the second bonding insulating layer 290 may be formed of the same material, and when the first bonding insulating layer 190 and the second bonding insulating layer 290 are bonded to each other, an interface may be formed between the first bonding insulating layer 190 and the second bonding insulating layer 290 as a single layer. The interface between the first bonding insulating layer 190 and the second bonding insulating layer 290 may include SiO2.

[0043] The first structure S1 and the second structure S2 can be joined together by a bonding between the first bonding pad 180 and the second bonding pad 280, for example, a copper (Cu) to copper (Cu) bonding. Because each of the first bonding pad 180 and the second bonding pad 280 can have a relatively larger area than other elements of the wiring structure, the reliability of the electrical connection between the first structure S1 and the second structure S2 can be increased. In some example embodiments, the first structure S1 and the second structure S2 can be joined together by a copper (Cu) to copper (Cu) bonding between the first bonding pad 180 and the second bonding pad 280, and by a hybrid bonding of dielectric material to dielectric material bonding disposed between the first bonding insulating layer 190 and the second bonding insulating layer 290 surrounding the first bonding pad 180 and the second bonding pad 280.

[0044] The first bonding structure BS1 may further include a first metal pattern 170 disposed in the first insulating layer 195 and configured to contact (e.g., directly contact) the first bonding insulating layer 190 (e.g., located within a volume space defined by the outer surface of the first insulating layer 195, for example, at least as shown in the image). Figure 3 (As shown). Each first metal pattern 170 may have a width smaller than the width of each first bonding pad 180 in a first direction (e.g., the x-direction), but some example embodiments are not limited thereto. The first metal pattern 170 may be covered by a first bonding insulating layer 190 so that its upper surface 170S is not exposed (e.g., the upper surface 170S of each first metal pattern 170 may be below and in direct contact with the first bonding surface BSS1). The first metal pattern 170 may include a conductive material, such as copper (Cu), tungsten (W), aluminum (Al), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof. The first metal pattern 170 may be electrically connected to a peripheral circuit region disposed in the first substrate structure SS1 and may be used for input and output wiring, but some example embodiments are not limited thereto. At least as shown Figure 2A and Figure 3 As shown, the first metal pattern 170 may have an upper surface 170S, which is at a lower height than the upper surface 180S of the first bonding pad 180 (e.g., closer to the lower surface S1b of the first structure S1 in a direction perpendicular to the lower surface S1b of the first structure S1 (e.g., the Z direction)).

[0045] exist Figure 3In this embodiment, for the first metal pattern 170, the first bonding pad 180, and the second bonding pad 280, the maximum width d3 of each first metal pattern 170 can be configured to be smaller than the width d2 of each first bonding pad 180, but some example embodiments are not limited thereto. Each of the first metal pattern 170, the first bonding pad 180, and the second bonding pad 280 may include a conductive layer and a barrier metal layer BM that at least partially covers the conductive layer. The barrier metal layer BM can be configured to cover the lower and side surfaces of the first metal pattern 170 and the first bonding pad 180, and the upper and side surfaces of the second bonding pad 280. The barrier metal layer BM can prevent the conductive material (e.g., a conductive layer) forming the first metal pattern 170, the first bonding pad 180, and the second bonding pad 280 from diffusing to the peripheral insulating layer. The barrier metal layer BM can be formed from a material selected from Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof. At least as Figure 3 As shown, the first metal pattern 170 may include a conductive layer 170i and a barrier metal layer BM that partially covers the conductive layer 170i; the first bonding pad 180 includes a conductive layer 180i and a barrier metal layer BM that partially covers the conductive layer 180i; and the second bonding pad 280 may include a layer having a barrier metal layer BM that is similar to the first metal pattern 170i. Figure 3 The conductive layer and barrier metal layer have a similar structure to those shown for the first bonding pad 180. Therefore, each of the first metal pattern 170, the first bonding pad 180, and the second bonding pad 280 may include a conductive layer and a barrier metal layer that at least partially covers the conductive layer.

[0046] The first insulating layer 195 and the second insulating layer 295 may include insulating materials such as silicon oxide or silicon nitride, and may include insulating materials different from those of the first bonding insulating layer 190 and the second bonding insulating layer 290, but some example embodiments are not limited thereto. It will be understood that the first insulating layer 195 and the first bonding insulating layer 190 may include different materials (e.g., they may have different total material compositions), but the example embodiments are not limited thereto.

[0047] like Figure 3As shown, the first bonding insulating layer 190 may include a first region A penetrated by the first bonding pad 180 and a second region B in contact with the first metal pattern 170. To reiterate, the first bonding insulating layer 190 may include a first region A where the first bonding pad 180 is disposed and a second region B where the first metal pattern 170 is disposed. The first bonding insulating layer 190 in the first region A and the first bonding insulating layer 190 in the second region B may have different thicknesses (e.g., different sizes of thickness), and the thickness of the first bonding insulating layer 190 in the second region B may be greater than (e.g., larger in size) the thickness of the first bonding insulating layer 190 in the first region A. Therefore, in the first region A and the second region B, the upper surface 190S of the first bonding insulating layer 190 may be coplanar, and in the first region A and the second region B, the lower surface 190B of the first bonding insulating layer 190 may be disposed at different heights. Figure 3 As shown, the height of the first lowest surface 190B=190L1 of the first bonding insulating layer 190 in the first region A (e.g., the distance from the lower surface S1B in the Z direction) is different from the height of the second lowest surface 190B=190L2 of the first bonding insulating layer 190 in the second region B (e.g., the distance from the lower surface S1B in the Z direction). Figure 3 As shown, the first metal pattern 170 may be on the lower part (e.g., below) of the second lowest surface 190B=190L2 of the first bonding insulating layer 190.

[0048] In the first region A and the second region B, the upper surface 190S of the first bonding insulating layer 190 can be substantially coplanar with the upper surface 180S of the first bonding pad 180. Therefore, at least as Figure 2A and Figure 3 As shown, the first bonding pads 180 can all penetrate (e.g., completely penetrate) the first bonding insulating layer 190 in the first region A. The difference D1 between the thicknesses of the first bonding insulating layer 190 in the first region A and the second region B can be in the range of about 0.2 μm to about 0.3 μm. In the second region B, and as... Figure 2A and Figure 3 As shown, each of the first metal patterns 170 can contact (e.g., directly contact) the lower surface 190B of the first bonding insulating layer 190, and the upper surface 170S of the first metal pattern 170 can be covered by the first bonding insulating layer 190. Therefore, the upper surface 170S of the first metal pattern 170 may not be exposed at the upper part of the first bonding structure BS1. Figure 3As shown, the distance between the upper surface 170S of the first metal pattern 170 in the Z direction and the first bonding surface BSS1 can be greater than the thickness of the first region A of the first bonding insulating layer 190 in the Z direction. When the first metal pattern 170 is exposed at the upper part of the first structure S1, the non-bonding area may increase because the insulating material of the second bonding insulating layer 290 and the conductive material of the first metal pattern 170 cannot bond to each other, thereby potentially reducing the bonding strength between the first structure S1 and the second structure S2. However, in the first structure S1, when there is a difference in the thickness of the first bonding insulating layer 190 in the first region A and the second region B, the bonding strength between the first structure S1 and the second structure S2 can be further increased than in the example where the first metal pattern 170 is exposed, because the first metal pattern 170 for input and output wiring, etc., can be concealed at the bonding surface of the first bonding structure BS1. Therefore, the reliability of the electrical connection through this bonding can be increased.

[0049] In some example embodiments, the first bonding insulating layer 190 can be understood as being divided into a first region A and a second region B, wherein the first bonding insulating layer 190 includes: one or more first regions A (e.g., a single continuous first region A surrounding a plurality of second regions B) penetrated by the first bonding pad 180; and one or more second regions B (e.g., separate second regions B of the first bonding insulating layer 190 in contact with separate portions of the first metal pattern 170 of the first bonding structure BS1), each in contact with a portion (e.g., a limited portion) of the first metal pattern 170 in the first bonding structure BS1.

[0050] It will be understood that the “thickness” of layers, regions, etc., in the first structure S1 as described herein is the thickness in a vertical direction (e.g., the Z direction) perpendicular to the lower surface S1b, and the “thickness” of layers, regions, etc., in the second structure S2 as described herein is the thickness in a vertical direction (e.g., the Z direction) perpendicular to the lower surface S2b. The thickness of layers, regions, etc., in the first structure S1 or the second structure S2 may be the thickness in the same direction (e.g., the Z direction).

[0051] Figure 4A , Figure 4B and Figure 4C This is a layout diagram illustrating a portion of the elements of a semiconductor device according to some example embodiments.

[0052] Figures 4A to 4CThis is a plan view showing the bonding surface of the first bonding structure BS1 as viewed from above the first structure S1. The upper surface of the first bonding insulating layer 190 and the upper surface of the first bonding pad 180 may be exposed at the bonding surface of the first bonding structure BS1. The first metal pattern 170 may be covered by the first bonding insulating layer 190, so that its upper surface may not be exposed.

[0053] In the accompanying drawings, the first metal pattern 170 is shown extending in one direction, but some exemplary embodiments are not limited thereto. The first metal pattern 170 may be arranged in different directions depending on the arrangement of the external input and output contacts. For example, the first metal pattern 170 may extend in a first direction, and each first metal pattern 170 may include a bent portion configured to be bent to extend in a second direction perpendicular to the first direction. The number and arrangement of each of the first bonding pads 180 and the first metal patterns 170 may vary in some exemplary embodiments, and Figures 4A to 4C An example of the arrangement is shown.

[0054] Figure 4A A single first metal pattern 170 is shown to be disposed on the bonding surface between at least one first bonding pad 180 and other first bonding pads 180, and Figure 4B Two first metal patterns 170 are shown to be disposed on the bonding surface between at least one first bonding pad 180 and other first bonding pads 180. Figure 4C The mating surface is shown as a region divided into a region where a first bonding pad 180 is continuously disposed and a region where a first metal pattern 170 is continuously disposed.

[0055] like Figure 4A and Figure 4B As shown, one or two first metal patterns 170 may be disposed between at least one first bonding pad 180 and other first bonding pads 180. For example, the spacing d1 between the first bonding pads 180 and the first metal patterns 170 may be in the range of about 1.2 μm to 2.0 μm. Each first bonding pad 180 may have a square shape, a quadrilateral shape, or a circular shape, and the shape of the first bonding pad 180 is not limited thereto. For example, the width d2 of each first bonding pad 180 may be in the range of about 0.5 μm to 0.8 μm. The maximum width d3 of each first metal pattern 170 may be less than or greater than the width d2 of each first bonding pad, and may be, for example, about 0.2 μm or greater.

[0056] like Figure 4CAs shown, the area where the first bonding pad 180 is continuously disposed may be adjacent to the area where the first metal pattern 170 is continuously disposed, but some example embodiments are not limited thereto.

[0057] The above configuration can also be applied to the plane of the joint surface of the first joint structure BS1 viewed from the top of the first structure S1, and the plane of the joint surface of the second joint structure BS2 viewed from the bottom of the second structure S2.

[0058] Figure 5A , Figure 5B and Figure 5C This is a cross-sectional view of a semiconductor device according to some example embodiments. Figure 5A Showing with Figure 2B The corresponding cross-section.

[0059] refer to Figure 5A ,and Figure 2A and Figure 2B Unlike the semiconductor device 10a shown, the semiconductor device 10b may further include a second metal pattern 270 disposed in the second insulating layer 295 and in contact with the second bonding insulating layer 290 in the second bonding structure BS2. Each second metal pattern 270 may have a width in a first direction (e.g., the x-direction) smaller than the width of each second bonding pad 280, and the second metal pattern 270 may be covered by the second bonding insulating layer 290, thereby concealing its lower surface 270b. Therefore, at least as shown... Figure 5A As shown, the lower surface 270b of the second metal pattern 270 may be located at a higher height than the lower surface 280b of the second bonding pad 280 (e.g., farther away from the lower surface S1b in the Z direction). For example, the second bonding insulating layer 290 may include a conductive material, such as copper (Cu), tungsten (W), aluminum (Al), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof. The second metal pattern 270 may be electrically connected to the cell array region disposed in the second substrate structure SS2 and may be used for input and output wiring, but some example embodiments are not limited thereto.

[0060] like Figure 3As shown, the width d3 of each first metal pattern 170 can be smaller than the width d2 of each first bonding pad 180, making it difficult to align and set the first metal pattern 170 and the second metal pattern 270 when they are exposed at the bonding surfaces of the first structure S1 and the second structure S2. Furthermore, because the first metal pattern 170 and the second metal pattern 270 can extend further than the first bonding pad 180 and the second bonding pad 280, the non-bonded ratio on the bonding surfaces of the first structure S1 and the second structure S2 when they are exposed can be further increased than in the example where the first bonding pad 180 and the second bonding pad 280 are bonded only by copper (Cu) to copper (Cu) bonding. Therefore, the reliability of the electrical connection between the first structure S1 and the second structure S2 may be reduced. However, when the first bonding insulating layer 190 and the second bonding insulating layer 290 have different thicknesses in the first region A and the second region B of the first structure S1 and the second structure S2, respectively, the reliability of the electrical connection through the bonding between the first structure S1 and the second structure S2 can be increased because the first metal pattern 170 and the second metal pattern 270 for input and output wiring can be concealed at the bonding surface of the first structure S1 and the second structure S2.

[0061] Similar to the first metal pattern 170, the second metal pattern 270 may include a barrier metal layer BM. The barrier metal layer BM may be configured to cover the upper and side surfaces of each second metal pattern 270. The barrier metal layer BM prevents the diffusion of conductive material from the second metal pattern 270. The barrier metal layer BM may include one of Ta, TaN, Ti, or TiN, but some example embodiments are not limited thereto.

[0062] Whether to set the first metal pattern 170 and the second metal pattern 270 can vary in some example embodiments, for example, with Figure 2B and Figure 5A Unlike the examples in the previous examples, the first bonding structure BS1 may not include the first metal pattern 170, and the second bonding structure BS2 may include the second metal pattern 270.

[0063] refer to Figure 5B In the semiconductor device 10c, the arrangement relationship between the first bonding pad 180 and the first metal pattern 170 can be related to... Figure 2A and Figure 2B The arrangement of the semiconductor device 10a shown is different. For example, the first bonding structure BS1 of the semiconductor device 10c can be divided into an area where the first bonding pad 180 is continuously disposed and an area where the first metal pattern 170 is continuously disposed.

[0064] refer to Figure 5C ,and Figure 2B and Figure 3 The example shown is different; the width of each first metal pattern 170 can be greater than the width of each first bonding pad 180.

[0065] Figure 6 , Figure 7 , Figure 8 , Figure 9A and Figure 9B This is a cross-sectional view showing a portion of a semiconductor device according to some example embodiments. Figures 6 to 9B This shows the regions corresponding to regions "A" and "B". For example... Figure 6 , Figure 7 , Figure 8 , Figure 9A and Figure 9B As shown, the height of the first lowest surface 190B=190L1 of the first bonding insulating layer 190 in the first region A (e.g., the distance from the lower surface S1B in the Z direction) is the same as the height of the second lowest surface 190B=190L2 of the first bonding insulating layer 190 in the second region B (e.g., the distance from the lower surface S1B in the Z direction). Figure 6 , Figure 7 , Figure 8 , Figure 9A and Figure 9B As shown, the height of the upper surface 170S of the first metal pattern 170 (e.g., the distance from the lower surface S1B in the Z direction) is higher than the height of the first lowest surface and the second lowest surface 190B = 190L1 / 190L2 of the first bonding insulating layer 190 (e.g., the distance from the lower surface S1B in the Z direction).

[0066] refer to Figure 6The first bonding insulating layer 190 may have a first region A penetrated by the first bonding pad 180 and a second region B in contact with the first metal pattern 170. In the first region A and the second region B, the upper surfaces of the first bonding insulating layer 190 may be coplanar, and the lower surfaces of the first bonding insulating layer 190 may be disposed at different heights. The first bonding structure BS1 may further include an intermediate insulating layer 192 disposed between (e.g., directly therebetween) the first metal pattern 170 and at least one region (e.g., the second region B) of the first bonding insulating layer 190. For example, the intermediate insulating layer 192 may vertically overlap in the Z-direction, with the second region B of the first bonding insulating layer 190 instead of the first region A. The intermediate insulating layer 192 may be formed of an insulating material such as silicon oxide (e.g., may at least partially comprise it) and may be formed of a material different from the material of the first bonding insulating layer 190 (e.g., may have a different overall material composition than the first bonding insulating layer).

[0067] refer to Figure 7 The first bonding insulating layer 190 may have a first region A penetrated by the first bonding pad 180 and a second region B in contact with the first metal pattern 170. The spacing W1 between the first metal patterns 170 in the second region B may be narrower than the spacing between the first bonding pads 180 or the second spacing W2 between the first bonding pads 180 and other patterns including the first metal pattern 170 in the first region A, and as shown, the width d5 ​​of the first metal pattern 170 may be smaller than the width d4 of the first bonding pads 180, but some example embodiments are not limited thereto. The thickness of the first bonding insulating layer 190 in the first region A may be substantially the same as or similar to the thickness of the first bonding insulating layer 190 surrounding the first metal pattern 170 in the second region B, and the upper surface of the first metal pattern 170 with a smaller spacing between the first metal patterns 170 in the second region B may be positioned at a height higher than the lower surface of the first bonding insulating layer 190. In the second region B, the upper surface of the first metal pattern 170 may be positioned at a height higher than the lower surface 190B of the first bonding insulating layer 190 (for example, the upper surface 170S of the first metal pattern 170 may be farther from the lower surface S1b of the first structure S1 in the Z direction than the lowest surface 190L of the first bonding insulating layer 190, wherein the lowest surface 190L is the portion of the lower surface 190B closest to the lower surface S1b in the Z direction), but some exemplary embodiments are not limited to this.

[0068] refer to Figure 8The first bonding insulating layer 190 may have a first region A penetrated by the first bonding pad 180 and a second region B in contact with the first metal pattern 170. The width d7 of the first metal pattern may be wider than the width d6 of the first bonding pad 180. The thickness of the first bonding insulating layer 190 in the first region A may be substantially the same as or similar to the thickness of the first bonding insulating layer 190 surrounding the first metal pattern 170 in the second region B, and the upper surface of the first metal pattern 170 may be positioned at a higher height than the lower surface of the first bonding insulating layer 190.

[0069] refer to Figure 9A The first bonding insulating layer 190 may have a first region A penetrated by the first bonding pad 180 and a second region B in contact with the first metal pattern 170. For example... Figure 9A As shown, the first bonding pad 180 may include: a first conductive layer 180a; a first barrier metal layer BM1 covering the lower and side surfaces of the first conductive layer 180a; a second conductive layer 180b disposed above the first conductive layer 180a (e.g., directly above it); and a second barrier metal layer BM2 covering the lower and side surfaces of the second conductive layer 180b (e.g., at least partially directly between the first and second conductive layers 180a). Figure 9A As shown, the second barrier metal layer BM2 can cover at least a portion of the upper surface of the first conductive layer 180a. The second conductive layer 180b and the second barrier metal layer BM2 can be disposed within the first bonding insulating layer 190.

[0070] The first conductive layer 180a and the first metal pattern 170 (as well as conductive layers 180i and 170i) may comprise the same conductive material, and may include, for example, copper (Cu), tungsten (W), aluminum (Al), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof. The second conductive layer 180b may comprise the same or different conductive material as the first conductive layer 180a and the first metal pattern 170, and may include, for example, copper (Cu).

[0071] The thickness of the first bonding insulating layer 190 in the first region A and the second region B can be the same or similar to each other. In other words, the thickness of the first bonding insulating layer 190 in the first region A can be substantially the same or similar to the thickness of the first bonding insulating layer 190 surrounding the first metal pattern 170 in the second region B, and the upper surface of the first metal pattern 170 in the second region B can be disposed at a higher height than the lower surface of the first bonding insulating layer 190, but some exemplary embodiments are not limited to this.

[0072] refer to Figure 9BThe second width a2 of the first upper bonding pad may be smaller than the first width a1 of the first lower bonding pad, and the second barrier metal layer BM2 may cover a portion (e.g., a limited portion, so that the rest is exposed) of the upper surface of the first conductive layer 180a. In some example embodiments, the upper and lower widths of the first bonding pad 180 and the second bonding pad 280, as well as the first metal pattern 170 and the second metal pattern 270, may have the same form, but some example embodiments are not limited thereto. For example, the first bonding pad 180 may have a sloping side surface with a downwardly decreasing width.

[0073] Figure 10 This is a cross-sectional view of a semiconductor device according to some example embodiments.

[0074] refer to Figure 10 The semiconductor device may have a first structure S1 and a second structure S2 that are bonded to each other. The first structure S1 may include a first substrate structure SS1 and a first bonding structure BS1, and the second structure S2 may include a second substrate structure SS2 and a second bonding structure BS2.

[0075] The first substrate structure SS1 may include a first substrate 101, circuit devices 120 disposed on the first substrate 101, circuit contact plugs 140, and circuit wiring lines 160. In some example embodiments, the circuit contact plugs 140 and the circuit wiring lines 160 may be commonly referred to as wiring layers that electrically connect the first bonding pads 180 and the first metal pattern 170 to the plurality of circuit devices 120.

[0076] The first substrate 101 may have an upper surface extending in both the x and y directions. A device isolation layer may be formed in the first substrate 101 to define an active region. A source / drain region 105, including impurities, may be disposed within a portion of the active region. For example, the first substrate 101 may comprise a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the first substrate 101 may be configured as a single-crystal wafer.

[0077] Circuit device 120 may include planar transistors. Each circuit device 120 may include a circuit gate dielectric layer 122, a spacer layer 124, and a circuit gate electrode 125. Source / drain regions 105 may be disposed on both sides of the circuit gate electrode 125 in the first substrate 101.

[0078] A peripheral region insulating layer 195a may be disposed on the circuit device 120 on the first substrate 101 and may be formed as a first insulating layer 195 connected to the first bonding structure BS1. A circuit contact plug 140 may penetrate the peripheral region insulating layer 195a and may be connected to the source / drain region 105 (which may be electrically connected to at least one circuit device 120), and may include first to third circuit contact plugs 142, 144, and 146 sequentially disposed based on the first substrate 101. Electrical signals may be applied to the circuit device 120 through the circuit contact plug 140. In an area not shown in the figures, the circuit contact plug 140 may also be connected to the circuit gate electrode 125. Circuit wiring lines 160 (e.g., circuit wiring lines 162, 164, and 166) may be connected to the circuit contact plug 140 and may include first to third circuit contact plugs 142, 144, and 146 forming multiple layers (e.g., at least partially forming multiple wiring layers). The first bonding pad 180 or the first metal pattern 170 of the first bonding structure BS1 can be configured to connect to the third circuit contact plug 146.

[0079] The second substrate structure SS2 may include: a second substrate 201; gate electrodes 231, 232, 233, 234, 235, 236, 237, and 238 (230), also referred to herein as a plurality of gate electrode layers, stacked on the lower surface of the second substrate 201 and between the second substrate 201 and the second bonding structure BS2; an interlayer insulating layer 220, stacked alternately with the gate electrode 230; a channel CH, configured to penetrate the gate electrode 230; a cell region insulating layer 295a, covering the gate electrode 230; and a pad insulating layer 292, stacked on the upper surface of the second substrate 201 and disposed on the cell region insulating layer 295a. As shown, the gate electrodes 231 to 238 (230) may be isolated from direct contact with each other (e.g., in the Z direction). The cell region insulating layer 295a may be configured to connect to the second insulating layer 295 of the second bonding structure BS2. In some example embodiments, the second substrate structure SS2 may include NAND memory cells, but some example embodiments are not limited thereto. In some example embodiments, the second substrate structure SS2 may include: non-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), etc.; and various non-volatile memory devices.

[0080] The second substrate structure SS2 may further include a channel region 240, a gate dielectric layer 245, a channel insulating layer 250, and a channel pad 255 disposed in the channel CH. Some or all of the channel region 240, gate dielectric layer 245, channel insulating layer 250, and channel pad 255 and / or epitaxial layer 207 disposed in a given channel CH may be collectively referred to as a channel structure penetrating some or all of the gate electrode 231 to the gate electrode 238 (230). The second substrate structure SS2 may be configured as a wiring structure and may further include: a cell contact plug 260 for applying a signal to the gate electrode 230; a second substrate 201; a first conductive plug 262; bit lines 265 and 265a; and a second conductive plug 264.

[0081] The second substrate 201 may have a lower surface extending in both the x and y directions. For example, the second substrate 201 may include semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors. For example, group IV semiconductors may include silicon, germanium, or silicon-germanium. For example, the second substrate 201 may be configured as a polycrystalline layer or an epitaxial layer. The second substrate 201 may include doped regions containing impurities.

[0082] Gate electrodes 230 can be vertically stacked on the lower surface of the second substrate 201, spaced apart from each other, and can form a stacked structure with an interlayer insulating layer 220. Gate electrodes 230 may include a lower gate electrode 231, gate electrodes 232 to 236 forming a plurality of memory cells MC, and upper gate electrodes 237 and 238. The number of memory gate electrodes 232 to 236 included in the memory cells MC can be determined according to the capacity of the semiconductor device 10. In some example embodiments, the number of each of the upper and lower gate electrodes 231, 237, and 238 may be one or two, and each of the upper and lower gate electrodes 231, 237, and 238 may have a structure that is the same as or different from the structure of the gate electrode 230 of the memory cell MC. A portion of the memory cell MC, for example, the memory gate electrodes 232 and 236 adjacent to the upper and lower gate electrodes 231, 237, and 238, may be a dummy gate electrode.

[0083] The gate electrodes 230 can be vertically stacked on the lower surface of the second substrate 201 and can be spaced apart from each other, and can extend to different lengths in at least one direction, forming a stair-like portion. The gate electrodes 230 can form a stair-like portion in the x-direction, such as... Figure 10As shown, a ladder-shaped portion can also be formed in the y-direction. Through the ladder-shaped portion, a specific region of the gate electrode 230, including the end of the gate electrode 230, can be exposed. The gate electrode 230 can be connected to the cell contact plug 260 in the aforementioned region.

[0084] Gate electrode 230 can be divided in the y-direction by isolation regions (not shown in the figures) according to specific units. Gate electrode 230 can form a single memory block between a pair of isolation regions, but the range of examples of memory blocks is not limited thereto. A portion of gate electrode 230, such as memory gate electrodes 232 to 236, can form a single layer within a single memory block.

[0085] Interlayer insulating layers 220 may be disposed between gate electrodes 230. The interlayer insulating layers 220 may be spaced apart from each other in a direction perpendicular to the lower surface of the second substrate 201, and may extend in the x-direction similar to the gate electrodes 230. The interlayer insulating layers 220 may comprise an insulating material such as silicon oxide or silicon nitride.

[0086] The channel CH can be formed on the lower surface of the second substrate 201, forming rows and columns that can be spaced apart from each other. The channel CH can be configured to form a lattice pattern, or it can be configured in a zigzag pattern in one direction. The channel CH can have a cylindrical shape and can have sloping side surfaces with a width decreasing toward the second substrate 201 according to the aspect ratio. In some example embodiments, a portion of the channel CH can be configured as a pseudo-channel, and additional pseudo-channels can be provided on the outer side of the channel CH.

[0087] A channel region 240 may be disposed in a channel CH. The channel region 240 in the channel CH may be configured to have an annular shape surrounding a channel insulating layer 250 disposed therein, and in some example embodiments, the channel insulating layer 250 may also have a columnar shape, such as a cylindrical or prismatic shape. The channel region 240 may be connected to an epitaxial layer 207 on its upper portion. The channel region 240 may comprise a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material may be implemented as an undoped material or a material including p-type or n-type impurities.

[0088] The channel pad 255 can be disposed on the upper part of the channel region 240 in the channel CH. The channel pad 255 can be configured to cover the upper surface of the channel insulating layer 250 and be electrically connected to the channel region 240. The channel pad 255 may include, for example, doped polysilicon.

[0089] A gate dielectric layer 245 may be disposed between the gate electrode 230 and the channel region 240. Although not shown in detail in the figures, the gate dielectric layer 245 may include a tunneling layer, a charge storage layer, and a barrier layer sequentially stacked based on the channel region 240. The tunneling layer can tunnel charge to the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer may be configured as a charge trapping layer or a floating gate conductive layer. The barrier layer 166 may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. In some example embodiments, at least a portion of the gate dielectric layer 245 may extend horizontally along the gate electrode 230.

[0090] The epitaxial layer 207 can be disposed on the upper end of the channel CH on the lower surface of the second substrate 201, and can also be disposed on the side surface of at least one gate electrode 230. The epitaxial layer 207 can be disposed in a recessed region of the second substrate 201. The height of the lower surface of the epitaxial layer 207 can be lower than the height of the lower surface of the uppermost gate electrode 231, and can be higher than the height of the upper surface of the memory gate electrode 232 disposed below the uppermost gate electrode 231, but some exemplary embodiments are not limited thereto. In some exemplary embodiments, the epitaxial layer 207 may not be disposed, and in this case, the channel region 240 may be directly connected to the second substrate 201 or may be connected to a conductive layer disposed on the second substrate 201.

[0091] The second substrate structure SS2 may further include a cell contact plug 260, a first conductive plug 262, bit lines 265 and 265a, and a second conductive plug 264 as a wiring structure for electrical connection with the first substrate structure SS1. The wiring structure may include a conductive material. The wiring structure may include, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0092] Cell contact plugs 260 may be disposed on the second substrate 201, penetrate the cell region insulating layer 295a, and be connected to the gate electrode 230 and the second substrate 201. Cell contact plugs 260 may be connected to a first conductive plug 262 at their lower end. Each cell contact plug 260 may have a cylindrical shape. In some example embodiments, each cell contact plug 260 may have a sloping side surface with a width decreasing towards the second substrate 201 according to the aspect ratio. In some example embodiments, a portion of the cell contact plug 260 may be configured as a dummy contact plug to which no electrical signal is applied.

[0093] A first conductive plug 262 may be disposed on the lower end of the channel CH and the cell contact plug 260. Bit lines 265 and 265a may be disposed between the first conductive plug 262 and the second conductive plug 264, on the lower end of the first conductive plug 262. Bit lines 265 and 265a may include a bit line 265 connected to the channel CH and a bit line 265a connected to the cell contact plug 260. The bit line 265a connected to the cell contact plug 260 may be a wiring line, which may be formed in the same process at the same height as the bit line 265 connected to the channel CH. The bit line 265a connected to the cell contact plug 260 may be disposed on the lower part of each first conductive plug 262, but some example embodiments are not limited thereto. A second conductive plug 264 may be disposed on the lower part of the bit lines 265 and 265a and may be connected to the second bonding pad 280 of the second bonding structure BS2.

[0094] exist Figure 10 In the process, the first joining structure BS1 and the second joining structure BS2 may be based on Figure 2B and Figure 3 Some example embodiments are shown, but some example embodiments are not limited thereto, and Figures 6 to 9B Some of the example embodiments shown can also be applied to part or all of the first bonding structure BS1 and the second bonding structure BS2.

[0095] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E and Figure 11F This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some example embodiments.

[0096] Figures 11A to 11F Showing with Figure 3 The corresponding cross-section.

[0097] refer to Figure 11A The first insulating layer 195, the first bonding insulating layer 190, and the photosensitive resin layer 300 serving as a mask pattern can be formed sequentially on the first substrate structure SS1 (see [reference]). Figure 2B ).

[0098] refer to Figure 11B A first mask pattern 301, having a portion of the first bonding insulating layer 190 exposed, can be formed by performing a photolithography process on the photosensitive resin layer 300, and can be used as an etching template to partially etch the first insulating layer 195 and the first bonding insulating layer 190. The area of ​​the first bonding insulating layer 190 that is not removed can be... Figure 3 and Figure 6 This corresponds to the first region A shown. The upper surface of the first bonding insulating layer 190 in the first region A can be covered by the first mask pattern 301. The first insulating layer 195, and the areas where the first bonding insulating layer 190 is partially removed, can correspond to... Figure 3 and Figure 6 This corresponds to the second region B shown. The first insulating layer 195 and the first bonding insulating layer 190 can use the first mask pattern 301 as an etching template to partially etch so that a ladder-like portion of the first insulating layer 195 can be formed between the first region A and the second region B. The photolithography process performed on the photosensitive resin layer 300 to form the ladder-like portion of the first insulating layer 195 can be performed for region division rather than for patterning. Therefore, the photolithography process can be performed using a photolithography apparatus with a wavelength relatively longer than that used by the photolithography apparatus used for patterning.

[0099] refer to Figure 11C An additional photosensitive resin can be formed, and a photolithography process for forming a second mask pattern 302 can be performed. The second mask pattern 302 formed on the first bonding insulating layer 190 in the first region A can be configured to be wider than the second mask pattern 302 formed on the first insulating layer 195 in the second region.

[0100] refer to Figure 11D The first trench T1 and the second trench T2 can be formed on the first bonding insulating layer 190 and the first insulating layer 195 using the second mask pattern 302. The width d2 of the first trench T1 can be wider than the width d3 of the second trench T2. The first trench T1 can be formed in at least a portion of the first bonding insulating layer 190 and the first insulating layer 195 in the first region A, and the second trench T2 can be formed in the first insulating layer 195 in the second region B. In the anisotropic etching process, the upper portion of each of the first trench T1 and the second trench T2 can have a width wider than the width of the second mask pattern 302. The first trench T1 and the second trench T2 can be formed such that each of the first bonding insulating layer 190 and the first insulating layer 195 can have sloping sidewalls. After the first trench T1 and the second trench T2 are formed, a process for removing the second mask pattern 302 can be performed.

[0101] refer to Figure 11EThe barrier metal layer BM can be formed on the inner wall of each of the first trench T1 and the second trench T2, and can form the first bonding pad 180 and the first metal pattern 170. The barrier metal layer BM can be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) such as sputtering. The barrier metal layer BM can be a material selected from Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof. Subsequently, the first trench T1 and the second trench T2 in which the barrier metal layer BM is formed can be filled with a conductive material. The conductive material can include, for example, copper or its alloys. After the barrier metal layer BM is formed, the process for filling the conductive material can be performed simultaneously so that the process for forming the first bonding pad 180 and the first metal pattern 170 can be easily performed. A planarization process for the first trench T1 and the second trench T2 filled with conductive material and the barrier metal layer BM can be performed to form the first bonding pad 180 and the first metal pattern 170. The upper surface of the first bonding pad 180 in the first region A can be exposed, and the upper surfaces of the first metal pattern 170 and the first insulating layer 195 in the second region B can be exposed. In some example embodiments, chemical mechanical polishing (CMP) can be used as a planarization process.

[0102] refer to Figure 11F Furthermore, an insulating material identical to the insulating material of the first bonding insulating layer 190 can be deposited on the first bonding pad 180 and the first bonding insulating layer 190 in the first region A, and on the first metal pattern 170 and the first insulating layer 195 in the second region B. Because a ladder-shaped portion can be formed in the first insulating layer 195 in the first region A and the second region B, the height of the upper surface of the first bonding insulating layer 190 on which the insulating material is further deposited can be different in the first region A and the second region B.

[0103] Go back for reference Figure 3 The first bonding structure BS1 can be formed by performing a planarization process. In the planarization process, the upper surface of the first bonding pad 180 in the first region A can be exposed, and the upper surface of the first metal pattern 170 in the second region B can be concealed.

[0104] Figure 12A , Figure 12B , Figure 12C and Figure 12D This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some example embodiments.

[0105] Figures 12A to 12D Showing with Figure 7 The corresponding cross-section.

[0106] refer to Figure 12A The third mask pattern 303 and the fourth mask pattern 304, used to partially expose the first and second regions, can be obtained by... Figure 11A The photosensitive resin layer 300 shown is formed by photolithography. A third mask pattern 303 with relatively narrow spacing can be formed in the second region B, and a fourth mask pattern 304 with relatively wide spacing can be formed in the first region A.

[0107] refer to Figure 12B The third trench T3 and the fourth trench T4 can be formed in the first region A and the second region B, respectively, by performing an etching process using the third mask pattern 303 and the fourth mask pattern 304 as etching masks. The third trench T3 and the fourth trench T4 can be formed in at least a portion of the first bonding insulating layer 190 and the first insulating layer 195. The spacing W1 between the fourth trenches T4 in the second region B can be narrower than the spacing W2 between the third trenches T3 in the first region A.

[0108] refer to Figure 12C A barrier metal layer BM can be formed on the inner wall of each of the third trench T3 and the fourth trench T4. Subsequently, the third trench T3 and the fourth trench T4, in which the barrier metal layer BM is formed, can be filled with a conductive material. The conductive material can be, for example, Cu. Subsequently, the first bonding pad 180 and the first metal pattern 170 can be formed by performing a planarization process. In some example embodiments, a chemical mechanical polishing (CMP) process can be used as the planarization process.

[0109] refer to Figure 12D The conductive material layer of the first metal pattern 170 in the second region B can be formed to be more recessed than the conductive material layer of the first bonding pad 180 in the first region A. When in Figure 12C When performing additional CMP processes after the first bonding pad 180 and the first metal pattern 170 are formed, the areas with lower density between the patterns can be further grounded than the areas with higher density between the patterns, so that the first metal pattern 170 can be recessed deeper in the second region B. The first spacing W1 between the first metal patterns 170 in the second region B is narrower than the spacing between the first bonding pads 180 in the first region A, or the second spacing W2 between the first bonding pads 180 and other patterns including the first metal pattern 170.

[0110] Go back for reference Figure 7 ,exist Figure 12DFollowing the initial process, an insulating material identical to that of the first bonding insulating layer 190 can be deposited on the first bonding pad 180 and the first bonding insulating layer 190 in the first region A, and on the first metal pattern 170 and the first bonding insulating layer 190 in the second region B. Through a planarization process, the upper surface of the first bonding pad 180 in the first region A can be exposed, while the upper surface of the first metal pattern 170 in the second region B can be concealed. The planarization process can be performed using a CMP process.

[0111] Figure 13A , Figure 13B and Figure 13C This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some example embodiments.

[0112] Figures 13A to 13C Showing with Figure 8 The corresponding cross-section.

[0113] refer to Figure 13A It can be done in Figure 11A A photolithography process is performed on the photosensitive resin layer 300 to form a mask pattern for exposing a portion of the first region and a portion of the second region. By using the mask pattern as an etching mask, an etching process is performed, and a fifth trench T5 can be formed in the first region, and a sixth trench T6 can be formed in the second region B. The fifth trench T5 and the sixth trench T6 can be formed in at least a portion of the first bonding insulating layer 190 and the first insulating layer 195. The width d7 of the sixth trench T6 can be wider than the width d6 of the fifth trench T5.

[0114] refer to Figure 13B A barrier metal layer BM can be formed on the inner wall of each of the fifth trench T5 and the sixth trench T6. Subsequently, the fifth trench T5 and the sixth trench T6, in which the barrier metal layer BM is formed, can be filled with a conductive material. Then, a first bonding pad 180 and a first metal pattern 170 having a width wider than the width of the first bonding pad 180 can be formed by performing a planarization process.

[0115] refer to Figure 13C The conductive material layer of the first metal pattern 170 in the second region B can be formed to be more recessed than the conductive material layer of the first bonding pad 180 in the first region A. When in Figure 13B When performing additional CMP processes after the formation of the first bonding pad 180 and the first metal pattern 170, the wider area of ​​the pattern can be grounded further than the narrower area of ​​the pattern, and therefore, the wider first metal pattern 170 can be recessed deeper than the first bonding pad 180.

[0116] Go back for reference Figure 8 ,exist Figure 13C Following the initial process, an insulating material identical to that of the first bonding insulating layer 190 can be deposited on the first bonding pad 180 and the first bonding insulating layer 190 in the first region A, and on the first metal pattern 170 and the first bonding insulating layer 190 in the second region B. Through a planarization process, the upper surface of the first bonding pad 180 in the first region A can be exposed, while the upper surface of the first metal pattern 170 in the second region B can be concealed. The planarization process can be performed using a CMP process.

[0117] Figures 13A to 13C This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some example embodiments.

[0118] Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 14F , Figure 14G , Figure 14H and Figure 14I Showing with Figure 9A and Figure 9B The corresponding area. Figure 14A , Figure 14B , Figure 14C , Figure 14D , Figure 14E , Figure 14F , Figure 14G , Figure 14H and Figure 14I This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some exemplary embodiments of the concept of the present invention.

[0119] refer to Figure 14A A first bonding pad 180, including a first barrier metal layer BM1, may be formed in a first region A, and a first metal pattern 170, including the first barrier metal layer BM1, may be formed in a second region B.

[0120] The trench can be formed using a mask patterning process and an etching process, and a first barrier metal layer BM1 can be formed in the trench. The first bonding pad 180 and the first metal pattern 170 can be formed by filling the first barrier metal layer BM1 with a conductive material and performing a planarization process. The conductive material may include, for example, Cu.

[0121] refer to Figure 14BA first conductive layer 180a and a recessed first metal pattern 170 can be formed on the first bonding pad. The recessed structure formed of conductive material can be formed by performing a chemical mechanical polishing (CMP) process or a dry etching process on the first bonding pad 180 and the first metal pattern 170.

[0122] refer to Figure 14C An insulating material identical to the insulating material of the first bonding insulating layer 190 may be deposited on the first conductive layer 180a of the first bonding pad, as well as the first metal pattern 170 and the first bonding insulating layer 190.

[0123] refer to Figure 14D The upper part of the first conductive layer 180a of the first bonding pad in the first region A can be exposed by performing photolithography and etching processes on the first bonding insulating layer 190 in the first region A.

[0124] Go back for reference Figure 14E The second barrier metal layer BM2 can be formed on the upper part of the first conductive layer 180a. The second barrier metal layer BM2 and the second conductive layer 180b can partially or completely cover the first conductive layer 180a. The second barrier metal layer BM2 can be a material selected from Ta, TaN, TaSiN, Ti, TiN, TiSiN, W, WN, or a combination thereof. The second conductive layer 180b can be formed by applying a conductive material of the same type as the first conductive layer 180a onto the second barrier metal layer BM2.

[0125] Go back for reference Figure 9A and Figure 9B Through a planarization process, the upper surface of the second conductive layer 180b, including the second barrier metal layer BM2, can be exposed in the first region A, and the upper surface of the first bonding insulating layer 190 can be exposed in the second region B. Figure 14E In this context, because the second barrier metal layer BM2 and the second conductive layer 180b can partially or completely cover the first conductive layer 180a, the second width a2 of the first upper bonding pad can be narrower than the first width a1 of the first lower bonding pad, such as... Figure 9B As shown, a first bonding pad 180 having a first conductive layer 180a covered by a second barrier metal layer BM2 can be formed. The second barrier metal layer BM2 can be formed to partially cover the first bonding pad 180 on the upper surface of the first conductive layer 180a.

[0126] refer to Figure 14F ,exist Figures 14A to 14CFollowing the manufacturing process, a third insulating layer 194 can be formed. The third insulating layer 194 may include an insulating material such as silicon oxide and can allow planarization processes to be easily performed, or it may be used as an etch stop layer. A fifth mask pattern 305 may be formed on the third insulating layer 194 to expose the upper portion of the first conductive layer 180a on the first bonding pad.

[0127] refer to Figure 14G The fifth mask pattern 305 can be used as an etching mask to etch the third insulating layer 194 in the first region. The etching process can be an anisotropic etching process.

[0128] refer to Figure 14H The third insulating layer 194 can be used as an etching mask to perform additional etching processes and expose the upper part of the first conductive layer 180a of the first bonding pad.

[0129] refer to Figure 14I The second barrier metal layer BM2 can be formed on the upper part of the first conductive layer 180a. In this case, the second barrier metal layer BM2 and the second conductive layer 180b can completely or partially cover the first conductive layer 180a. The second conductive layer 180b can be formed by providing a conductive material of the same material as the first conductive layer 180a on the second barrier metal layer BM2 and performing a planarization process. Subsequently, through the planarization process, the upper surface of the second conductive layer 180b, including the second barrier metal layer BM2, can be exposed in the first region A, and the upper surface of the first bonding insulating layer 190 can be exposed in the second region B. In this case, the second barrier metal layer BM2 and the second conductive layer 180b can partially cover the first conductive layer 180a, so that... Figure 9B Some of the example embodiments shown can be manufactured.

[0130] According to some example embodiments, in a structure in which two or more substrate structures are joined together, the number of processes and costs can be reduced by forming a metal pattern for wiring and the joining pad on the layer forming the joining pad, and using the metal pattern as input and output wiring.

[0131] While some exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The first structure includes a first joining structure; as well as The second structure, on top of the first structure, includes a second joining structure connected to the first joining structure. The first joining structure includes: First insulating layer, A first bonding insulating layer, on the first insulating layer. The first bonding pad penetrates at least a portion of the first insulating layer and the first bonding insulating layer, and A first metal pattern, located in the first insulating layer, contacts the first bonding insulating layer. Each of the first metal patterns has an upper surface, and the upper surface of the first metal pattern is closer to the lower surface of the first structure than the upper surface of the first bonding pad in a vertical direction extending perpendicularly to the lower surface of the first structure. The second joining structure includes: A second bonding insulating layer is bonded to the first bonding insulating layer; A second insulating layer, on the second bonding insulating layer; and The second bonding pad penetrates at least a portion of the second bonding insulation layer and is connected to a separate corresponding first bonding pad in the first bonding pad.

2. The semiconductor device according to claim 1, wherein, The lower surface of the first bonding pad and the lower surface of the first metal pattern are equidistant from the lower surface of the first structure in the vertical direction.

3. The semiconductor device according to claim 1, wherein, The first bonding insulating layer includes a first region and a second region, and The first bonding insulating layer has a first thickness in the first region and a second thickness in the second region, the second thickness being larger in size than the first thickness.

4. The semiconductor device according to claim 3, wherein, The second thickness is 0.2 μm to 0.3 μm larger in size than the first thickness.

5. The semiconductor device according to claim 3, wherein, Each of the first bonding pads penetrates the first bonding insulation layer in the first region, and Each of the first metal patterns is in contact with the lower surface of the first bonding insulating layer in the second region.

6. The semiconductor device according to claim 1, wherein, The upper surface of the first metal pattern is farther from the lower surface of the first structure in the vertical direction than the lowermost surface of the first bonding insulating layer.

7. The semiconductor device according to claim 1, wherein, The first metal pattern and each of the first bonding pad and the second bonding pad include a conductive layer and a barrier metal layer that partially covers the conductive layer.

8. The semiconductor device according to claim 1, wherein, Each of the first bonding pads includes: First conductive layer; A first barrier metal layer covers the lower surface and side surface of the first conductive layer; A second conductive layer is disposed on the first conductive layer; and A second barrier metal layer covers the lower and side surfaces of the second conductive layer.

9. The semiconductor device according to claim 8, wherein, The second barrier metal layer covers at least a portion of the upper surface of the first conductive layer.

10. The semiconductor device according to claim 1, wherein, The first insulating layer and the first bonding insulating layer comprise different materials.

11. The semiconductor device according to claim 1, wherein, The first bonding insulating layer includes at least one of SiCN, SiO, SiN, SiOC, SiON, or SiOCN.

12. The semiconductor device according to claim 1, further comprising: An intermediate insulating layer, located in at least one region of the first bonding insulating layer, between the first bonding insulating layer and the first metal pattern. The intermediate insulating layer comprises a material different from that of the first bonding insulating layer.

13. The semiconductor device according to claim 1, wherein, The second bonding structure further includes: a second metal pattern in the second insulating layer, the second metal pattern being in contact with the second bonding insulating layer, each of the second metal patterns having a lower surface that is farther away from the lower surface of the first structure in the vertical direction relative to the lower surface of the second bonding pad.

14. The semiconductor device according to claim 1, wherein, The first structure further includes: First substrate; Multiple circuit devices are disposed on the first substrate; and The wiring layer electrically connects the first bonding pad and the first metal pattern to the plurality of circuit devices, and The second structure also includes: Second substrate; Multiple gate electrode layers are stacked between the second substrate and the second bonding structure, and are isolated from each other without direct contact; and The channel structure penetrates the multiple gate electrode layers.

15. A semiconductor device, comprising: The first structure includes a first joining structure; as well as The second structure, on top of the first structure, includes a second joining structure connected to the first joining structure. The first joining structure includes: First insulating layer, A first bonding insulating layer, on the first insulating layer. The first bonding pad penetrates a portion of the first insulating layer and the first bonding insulating layer, and A first metal pattern, within the first insulating layer, contacts the first bonding insulating layer, and... The first bonding insulating layer includes a first region penetrated by the first bonding pad and a second region at one or more lower surfaces of the first bonding insulating layer that contacts the upper surface of the first metal pattern, such that the first bonding insulating layer covers the upper surface of the first metal pattern.

16. The semiconductor device according to claim 15, wherein, The distance from the lower surface of the first bonding insulating layer in the first region to the lower surface of the first structure in a vertical direction perpendicular to the lower surface of the first structure is different from the distance from the lower surface of the second bonding insulating layer in the second region to the lower surface of the first structure in the same vertical direction. The first metal pattern is on the lower part of the second lowest surface of the first bonding insulating layer.

17. The semiconductor device according to claim 15, wherein, The distance from the lower surface of the first bonding insulating layer in the first region to the lower surface of the first structure in a vertical direction perpendicular to the lower surface of the first structure is the same as the distance from the lower surface of the second bonding insulating layer in the second region to the lower surface of the first structure in the same vertical direction. The distance between the upper surface of the first metal pattern and the lower surface of the first structure in the vertical direction is greater than the distance between the first lowermost surface and the second lowermost surface of the first bonding insulating layer and the lower surface of the first structure in the vertical direction.

18. A semiconductor device, comprising: The first bonding structure has a first bonding surface; as well as The second joining structure is on the first joining structure and has a second joining surface that contacts the first joining surface. The first joining structure includes: First insulating layer, A first bonding insulating layer is disposed on the first insulating layer and at least partially defines the first bonding surface. The first bonding pad penetrates at least a portion of the first insulating layer and the first bonding insulating layer, and at least partially defines the first bonding surface. First metal patterns are formed in the first insulating layer and each has an upper surface that is lower than the first bonding surface.

19. The semiconductor device according to claim 18, wherein, The first bonding insulating layer includes a first region where the first bonding pad is located and a second region where the first metal pattern is located, and The distance between the upper surface of the first metal pattern and the first bonding surface is greater than the thickness of the first region of the first bonding insulating layer.

20. The semiconductor device according to claim 18, wherein, The upper surface of the first bonding pad is coplanar with the upper surface of the first bonding insulating layer.

Images