Structure of a silicon-based capacitor element

Abstract

The present application relates to a structure of a silicon-based capacitor element, including a silicon wafer and a plurality of capacitor units arranged on the surface of the silicon wafer with the silicon wafer as a substrate; wherein: the capacitor unit includes one or more capacitors, the capacitor includes a plurality of electrodes, and at least one first electrode and a second electrode among the plurality of electrodes; the second electrode of each capacitor is not connected to the silicon wafer substrate or at least one second electrode of the capacitor is connected to the silicon wafer substrate. The present application not only realizes the multi-potential of a multi-terminal capacitor by making a plurality of mutually insulated capacitor units on a silicon wafer, but also allows users to arbitrarily cut the required capacitor units according to the requirements of various application scenarios, which is more flexible.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to the structure of a silicon-based capacitor element. Background Art

[0002] Capacitors are commonly used components in electronic products. Their basic properties include storing charge; coupling and blocking DC current, allowing only signal components (AC current) to pass; and decoupling, bypassing high-frequency noise. This feature is used in various forms in the circuits of electronic products used in daily life.

[0003] MLCC (Multi-layer Ceramic Capacitors) are widely used due to their low cost. However, existing MLCCs have the disadvantages of large capacitance error, large noise, large parasitic inductance, and large temperature coefficient and voltage coefficient, making them unsuitable for use in special circuits. In addition, existing multi-terminal capacitors have a fixed internal structure and multiple positive electrodes share one negative electrode. At this time, all positive electrodes can only be connected to the same voltage, and the potential of each terminal is the same, so multiple potentials cannot be generated, and the flexibility during use is poor. Summary of the invention

[0004] In order to generate multiple potentials for multi-terminal capacitors so that the capacitors can be flexibly applied to various scenarios according to needs, the present application provides a structure of a silicon-based capacitor element.

[0005] The present application provides a structure of a silicon-based capacitor element, which adopts the following technical solution:

[0006] A structure of a silicon-based capacitor element, comprising a silicon wafer and a plurality of capacitor units arranged on the surface of the silicon wafer with the silicon wafer as a substrate; wherein:

[0007] The capacitor unit includes one or more capacitors, each of which includes multiple electrodes, and at least one first electrode and a second electrode among the multiple electrodes; the second electrode of each capacitor is not connected to the silicon wafer substrate or the second electrode of at least one capacitor is connected to the silicon wafer substrate.

[0008] By adopting the above technical solution, multiple capacitor units that are insulated from each other or connected through a silicon wafer substrate are made on a silicon wafer. Users can obtain one or more capacitor units from the silicon wafer as needed. This not only realizes the multi-potential of multi-terminal capacitors, but also allows users to arbitrarily cut the required capacitor units according to various application scenarios, which is more flexible.

[0009] Optionally, each capacitor of the capacitor unit is the same or different.

[0010] Optionally, the capacitors in each row of the capacitor units are the same and the capacitors in each column of the capacitor units are the same;

[0011] or,

[0012] The capacitors in each row of the capacitor units are the same or the capacitors in each column of the capacitor units are the same.

[0013] Optionally, the number of capacitors included in each capacitor unit on the silicon wafer is the same or different.

[0014] Optionally, the number of capacitors included in each row and each column of the capacitor units on the silicon wafer is the same;

[0015] or,

[0016] The capacitor units in each row or column on the silicon wafer include the same number of capacitors.

[0017] Optionally, the capacitor includes one or more capacitor structures using the silicon wafer as a substrate;

[0018] The capacitor structure includes a deep trench disposed on the silicon wafer and extending perpendicularly to the surface of the silicon wafer, a conductor layer, N first plates, N second plates, a first dielectric layer, a second dielectric layer and a third dielectric layer;

[0019] N first pole plates and N second pole plates are stacked alternately, and the second dielectric layer is arranged between the first pole plates and the second pole plates to form a pole plate structure; the first dielectric layer is stacked on the surface of the first pole plate of the pole plate structure to form a first structure of the capacitor structure;

[0020] The first structure is arranged in the deep trench, and the rest of the space in the deep trench is filled with the conductor layer; the third dielectric layer is covered on the first structure and the conductor layer at the notch of the deep trench, and the conductor layer is insulated from the first electrode plate and the second electrode plate by the first dielectric layer and the third dielectric layer;

[0021] The first electrode plate is connected to the first electrode of the capacitor, and the second electrode plate is connected to the second electrode of the capacitor; the second electrode is connected to or not connected to the conductor layer.

[0022] Optionally, the deep trench includes a low trench and a first sub-trench and a second sub-trench arranged on two first upper edges opposite to the low trench; the first bottom edges of the first sub-trench and the second sub-trench are respectively opposite to the two first upper edges and have the same height, and the second upper edges of the first sub-trench and the second sub-trench respectively opposite to the two first bottom edges are at the same height as the surface of the silicon wafer;

[0023] The opposite ends of the first structure are respectively arranged in the first sub-groove and the second sub-groove, and the surface where the first dielectric layer is located is opposite to the bottom surface formed by the bottom edges of the first sub-groove and the second sub-groove; the remaining part of the first structure is zigzag arranged in the low groove, and the surface where the first dielectric layer is located is opposite to the surface where the first upper edge of the low groove is located.

[0024] Optionally, each of the first electrodes of the capacitor is connected to one or more of the first plates of the capacitor structure; and,

[0025] One of the second electrodes of the capacitor is connected to one or more of the second plates of the capacitive structure.

[0026] Optionally, a scribe groove is provided between each of the capacitor units on the silicon wafer.

[0027] In summary, the present application includes at least one of the following beneficial technical effects:

[0028] 1. This application manufactures multiple capacitor units that are insulated from each other or connected through a silicon wafer substrate on a silicon wafer. Users can obtain one or more capacitor units from the silicon wafer as needed, which not only realizes the multi-potential of the multi-terminal capacitor, but also allows users to arbitrarily cut the required capacitor units according to various application scenarios, which is more flexible.

[0029] 2. The capacitor of the present application adopts a structure of a zigzag arrangement extending perpendicular to the surface of the silicon wafer and a multi-layer plate stacking structure to improve the capacitance density and ensure the capacitance density of a small-sized capacitor unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a schematic structural diagram of a silicon-based capacitor element in which a capacitor unit provided in an embodiment of the present application includes a plurality of capacitors;

[0031] Figure 2 is a schematic structural diagram of a capacitor unit provided in an embodiment of the present application, including a silicon-based capacitor element of a capacitor;

[0032] Figure 3 The embodiment of this application provides Figure 1 and Figure 2 Schematic diagram of the internal circuit of the capacitor;

[0033] Figure 4 It is a schematic structural diagram of a silicon-based capacitor element having six electrodes of a capacitor provided in an embodiment of the present application;

[0034] Figure 5 The embodiment of this application provides Figure 4A schematic diagram of the internal circuit when the second plates of the capacitor are not connected to each other;

[0035] Figure 6 The embodiment of this application provides Figure 4 A schematic diagram of the internal circuit when the second plates of the capacitors are connected to each other;

[0036] Figure 7 It is a schematic structural diagram of a silicon-based capacitor element having five electrodes of a capacitor provided in an embodiment of the present application;

[0037] Figure 8 The embodiment of this application provides Figure 7 Schematic diagram of the internal circuit of the capacitor;

[0038] Fig. 9 This is a schematic diagram of the internal circuit of a traditional four-terminal capacitor;

[0039] Fig.10 This is a schematic diagram of a first structure of a multilayer first electrode plate and a second electrode plate provided in an embodiment of the present application;

[0040] Fig.11 This is a schematic diagram of a capacitor structure provided by an embodiment of the present application when N=1, where the second electrode is not connected to the conductor layer

[0041] Fig.12 It is a schematic diagram of a capacitor structure in which the second electrode is connected to the conductor layer when N=1, provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of this application more clear, the following Figure 1-11 It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] The present application embodiment discloses a structure of a silicon-based capacitor element. Figure 1 and Figure 2 , which is a partial cutout of the structure of a silicon-based capacitor element, the structure of the silicon-based capacitor element includes a silicon wafer 100 and a plurality of capacitor units 200 arranged on one side of the silicon wafer 100 using the silicon wafer 100 as a substrate. In order to maximize the use of the silicon wafer, the capacitor units 200 using the silicon wafer 100 as a substrate are generally arranged continuously on one side of the silicon wafer 100;

[0044] The capacitor unit 200 of this embodiment includes one or more capacitors 210. Figure 1 is a schematic structural diagram of a silicon-based capacitor element in which the capacitor unit 200 includes a plurality of capacitors 210, Figure 2Schematic diagram of the structure of a silicon-based capacitor element in which a capacitor unit 200 includes a capacitor 210; each capacitor 210 includes a plurality of electrodes, among which at least one first electrode 201 and one second electrode 202 are provided, and the number of electrodes of the capacitor unit 200 is the sum of the number of electrodes of each capacitor; when the capacitor 210 has two electrodes, they are the first electrode 201 and the second electrode 202, as shown in FIG. Figure 1 and Figure 2 As shown, at this time, the internal circuit of capacitor 210 is as follows Figure 3 When the capacitor 210 has an even number of electrodes, it may be half of the first electrode 201 and half of the second electrode 202. In this case, one first electrode 201 corresponds to one second electrode 202. Figure 4 The schematic diagram of the structure of the silicon-based capacitor element is shown in FIG. 1 . The number of electrodes of the capacitor is 6 and the internal circuit is as follows: Figure 5 (the second plates are not connected to each other) and Figure 6 As shown (the second plates are connected to each other); it is also possible that the first electrode 201 or the second electrode 202 is greater than half, and the second electrode 202 or the first electrode 201 is less than half, in which case there are multiple first electrodes or second electrodes sharing one second electrode or first electrode, that is, there is a situation where multiple terminals have the same potential; when the number of electrodes of the capacitor 210 is an odd number, there must be a situation where multiple first electrodes 201 or the second electrodes 202 share one second electrode 202 or the first electrode 201, such as Figure 7 The schematic diagram of the structure of the silicon-based capacitor element shown in FIG. 5 has five electrodes and the internal circuit is as follows: Figure 8 As shown, four second plates are connected to each other and share a second electrode. In order to further reduce the size of a single capacitor, the shared second electrode is generally arranged in the middle of the first electrode.

[0045] In the embodiment of the present application, the relationship between the capacitors of the capacitor unit 200 includes the following two situations:

[0046] In the first case, each second electrode 202 of each capacitor 210 is not connected to the silicon wafer 100, so that the corresponding capacitor unit 200 is insulated from other capacitor units; in this case, each first electrode 201 of each capacitor 210 can be connected to a different voltage, and each second electrode 202 of each capacitor 210 can also be connected to a different voltage to generate different potentials;

[0047] In the second case, the second electrode 202 of at least one capacitor 210 (at least one second electrode 202) is connected to the silicon wafer 100, and the capacitors 210 connected with the second electrode 202 and the silicon wafer 100 are connected to each other through the silicon wafer 100, so that the corresponding capacitor unit 200 is connected to other capacitor units 200 (the second electrode 202 of at least one capacitor 210 is connected to the silicon wafer 100) through the silicon wafer substrate; at this time, each first electrode 201 of each capacitor 210 can be connected to a different voltage, all second electrodes 202 connected to the silicon wafer 100 substrate are connected to the same voltage, and the remaining second electrodes 202 can be connected to different voltages, thereby generating different potentials. The structure of a conventional multi-terminal capacitor is fixed, such as a capacitor with two first electrodes and two second electrodes, the two first electrodes are connected internally, the two second electrodes are connected internally, and the internal circuit is such as Fig. 9 ,Although both electrodes have multiple terminals, the multiple terminals of each electrode are internally connected and cannot generate multiple positive potentials.

[0048] By manufacturing multiple capacitor units on a silicon wafer, the embodiment of the present application allows the user to obtain a capacitor unit from the silicon wafer as needed, or multiple capacitor units that are connected and insulated from each other or connected through a silicon wafer substrate. This not only realizes the multi-potential of the multi-terminal capacitor, but also allows the user to arbitrarily cut the required capacitor units according to the requirements of various application scenarios, thereby providing greater flexibility.

[0049] In order to further improve the flexibility of application, in the embodiment of the present application, the number of first electrodes, the number of second electrodes, and the arrangement of the first and second electrodes of each capacitor 210 of the capacitor unit 200 are not limited, nor are the number of capacitors 210 included in each capacitor unit 200 on the same silicon wafer limited. Each capacitor 210 of the capacitor unit 200 can be the same or different; wherein, the same two capacitors 210 means that the number of first electrodes 201, the number of second electrodes 202, and the arrangement of the first electrodes 201 and the second electrodes 202 of the two capacitors are the same. The number of capacitors 210 included in each capacitor unit 200 on the silicon wafer can be the same or different.

[0050] In actual production, in order to facilitate production and manufacture more capacitor units on silicon wafers of the same specification, each capacitor unit 200 on the same silicon wafer is generally not made to include different capacitors. Therefore, in another embodiment, the arrangement of the same capacitor 210 on the same silicon wafer is any of the following:

[0051] (1) The capacitors 210 of each row of the capacitor units 200 are the same and the capacitors 210 of each column of the capacitor units 200 are the same. In this case, each capacitor of the capacitor unit in the row is the same;

[0052] (2) The capacitors 210 in each row of the capacitor unit 200 are the same or the capacitors 210 in each column of the capacitor unit 200 are the same. In this case, the capacitors in each row of a single capacitor unit may be the same and the capacitors in each column may be different; or the capacitors in each row of a single capacitor unit may be different and the capacitors in each column may be the same.

[0053] In another embodiment, the arrangement of the capacitor units with the same number of capacitors 210 on the same silicon chip is any one of the following:

[0054] (1) Each row and column of capacitors on the silicon wafer contains the same number of capacitors;

[0055] (2) Each row or column of capacitor cells on the silicon wafer contains the same number of capacitors.

[0056] When the capacitor units on the same silicon chip are all the same, each row and each column of the capacitor units include the same number of capacitors, and the capacitors are the same.

[0057] In order to facilitate cutting, in this embodiment, a scribe groove 101 is provided between each capacitor unit 200 on the silicon wafer 100; the user can cut one or a plurality of connected capacitor units 200 along the scribe groove 101 according to needs.

[0058] Traditional MLCC chip capacitors are made of ceramic dielectric diaphragms with printed electrodes (inner electrodes) stacked in an offset manner, sintered at high temperature once to form a ceramic chip, and then sealed with a metal layer (outer electrode) at both ends of the chip. This capacitor structure is very difficult to manufacture with high capacitance density, especially as the size is miniaturized. Unlike traditional chip capacitors MLCC, the capacitor 210 of the embodiment of the present application adopts a structure that extends and twists along a perpendicular direction to the surface of the silicon wafer to further improve the capacitance density and ensure the capacitance density of the small-sized capacitor unit. Using the capacitor 210 structure of the embodiment of the present application, a maximum of 200,000 to 300,000 capacitors 210 can be produced on a 12-inch silicon wafer. The capacitor 210 of this embodiment includes one or more capacitor structures using a silicon wafer 100 as a substrate;

[0059] like Fig.10 , Fig.11 and Fig.12 As shown, the capacitor structure includes a deep trench 211 arranged on the silicon wafer 100 and extending perpendicularly to the surface of the silicon wafer 100, a conductor layer, N first plates 212, N second plates 213, a first dielectric layer 214, a second dielectric layer 215 and a third dielectric layer 216; wherein N is a positive integer.

[0060] The first electrode 212 is connected to the first electrode 201 of the capacitor 210, and the second electrode 213 is connected to the second electrode 202 of the capacitor 210. The second electrode 202 is connected to the conductor layer or not connected, that is, the second electrode 202 is connected to the silicon wafer 100 through the conductor layer, or the second electrode 202 is not connected to the silicon wafer 100.

[0061] In this embodiment, each first electrode 201 of the capacitor 210 is connected to the first plate 212 of one or more capacitor structures; and a second electrode 202 of the capacitor 210 is connected to the second plate 213 of one or more capacitor structures, specifically including the following situations:

[0062] (1) Each first electrode 201 of the capacitor 210 is connected to a first plate 212 of a capacitor structure; each second electrode 201 of the capacitor 210 is connected to a second plate 212 of a capacitor structure; in this case, each first plate and each second plate of the capacitor structure can be connected to different voltages, and each pair of first electrodes and second electrodes connected to the same capacitor structure generates different potentials.

[0063] (2) At least one first electrode 201 of the capacitor 210 is connected to the first plates 212 of multiple capacitor structures; each second electrode 201 of the capacitor 210 is connected to the second plate 212 of a capacitor structure; in this case, there is a first electrode sharing situation, and the first plates of the capacitor structures sharing the same first electrode have the same voltage, and the second plates of these capacitor structures can be connected to different voltages, so that different potentials can be generated between the first plates and the second plates of these capacitor structures.

[0064] (3) Each first electrode 201 of the capacitor 210 is connected to a first plate 212 of a capacitor structure; at least one second electrode 201 of the capacitor 210 is connected to a plurality of second plates 212 of capacitor structures; in this case, there is a second electrode sharing situation, and the second plates of the capacitor structures sharing a second electrode have the same voltage, and the first plates of these capacitor structures can be connected to no voltage, so that different potentials can be generated between the first plates and the second plates of these capacitor structures.

[0065] (4) At least one first electrode 201 of the capacitor 210 is connected to the first plates 212 of multiple capacitor structures; at least one second electrode 201 of the capacitor 210 is connected to the second plates 212 of multiple capacitor structures. In this case, the first electrode and the second electrode are shared, and the voltages of the first plates of the capacitor structures that share a first electrode are the same, and the voltages of the second plates of the capacitor structures that share a second electrode are the same; when the first plates of multiple capacitor structures share a first electrode, and the second plates share a second electrode, the same potential is generated between the first plates and the second plates of these capacitor structures; when the first plates of multiple capacitor structures share a first electrode or the second plates share a second electrode, correspondingly, the second plates are connected to different second electrodes or the first plates are connected to different first electrodes, and different voltages can be connected, and different potentials can be generated between the first plates and the second plates of these capacitor structures.

[0066] N first plates 212 and N second plates 213 are stacked alternately, and a second dielectric layer 215 is arranged between the first plates 212 and the second plates 213 to form a plate structure; a first dielectric layer 214 is stacked on the surface of the first plate 212 of the plate structure to form a first structure of a capacitor structure; the N first plates 212 of the first structure are all connected to the same first electrode 201, and the N second plates 213 are connected to the same second electrode 202, such as Fig.10 shown.

[0067] The first structure is arranged in the deep groove 211, and the remaining space in the deep groove 211 is filled with a conductor layer; the third dielectric layer 216 is covered on the first structure and the conductor layer at the opening of the deep groove, and the conductor layer is insulated from the first electrode plate 212 and the second electrode plate 213 by the first dielectric layer 214 and the third dielectric layer 216.

[0068] In this embodiment, the deep trench 211 includes a low trench 2111 and a first sub-trench 2112 and a second sub-trench 2113 disposed on two first upper edges opposite to the low trench 2111; the first bottom edges of the first sub-trench 2112 and the second sub-trench 2113 are respectively opposite to the two first upper edges and have the same height, and the second upper edges of the first sub-trench 2112 and the second sub-trench 2113 respectively opposite to the two first bottom edges are at the same height as the surface of the silicon wafer 100;

[0069] The two opposite ends of the first structure are respectively disposed in the first sub-groove 2112 and the second sub-groove 2113, and the surface where the first dielectric layer 214 is located is opposite to the bottom surface formed by the bottom edges of the first sub-groove 2112 and the second sub-groove 2114; the remaining portion of the first structure is zigzag disposed in the low groove 2111, and the surface where the first dielectric layer 214 is located is opposite to the surface where the first upper edge of the low groove 2111 is located. In some embodiments, the first electrode 201 of the capacitor 210 is disposed in the first sub-groove 2112; the second electrode 202 of the capacitor 210 is disposed in the second sub-groove 2113.

[0070] The above are all preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any feature disclosed in this specification (including the abstract and drawings), unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

Claims

1. A structure of a silicon-based capacitor element, characterized in that: It comprises a silicon wafer and a plurality of capacitor units arranged on the surface of the silicon wafer with the silicon wafer as a substrate; wherein: The capacitor unit includes one or more capacitors, the capacitors include multiple electrodes, and at least one of the multiple electrodes includes a first electrode and a second electrode; the second electrode of each capacitor is not connected to the silicon wafer substrate or the second electrode of at least one capacitor is connected to the silicon wafer substrate, wherein the capacitor includes one or more capacitor structures using the silicon wafer as a substrate; The capacitor structure includes a deep trench disposed on the silicon wafer and extending perpendicularly to the surface of the silicon wafer, a conductor layer, N first plates, N second plates, a first dielectric layer, a second dielectric layer and a third dielectric layer; the first electrode and the second electrode are both located outside the deep trench; N first pole plates and N second pole plates are stacked alternately, and the second dielectric layer is arranged between the first pole plates and the second pole plates to form a pole plate structure; the first dielectric layer is stacked on the surface of the first pole plate of the pole plate structure to form a first structure of the capacitor structure; The first structure is arranged in the deep trench, and the rest of the space in the deep trench is filled with the conductor layer; the third dielectric layer is covered on the first structure and the conductor layer at the notch of the deep trench, and the conductor layer is insulated from the first electrode plate and the second electrode plate by the first dielectric layer and the third dielectric layer; The first electrode plate is connected to the first electrode of the capacitor, and the second electrode plate is connected to the second electrode of the capacitor; the second electrode is connected to or not connected to the conductor layer.

2. The structure according to claim 1, characterized in that: Each of the capacitors in the capacitance unit is the same or different.

3. The structure according to claim 2, characterized in that: The capacitors in each row of the capacitor units are the same and the capacitors in each column of the capacitor units are the same; or, The capacitors in each row of the capacitor units are the same or the capacitors in each column of the capacitor units are the same.

4. The structure according to claim 1, characterized in that The number of capacitors included in each of the capacitor units on the silicon wafer is the same or different.

5. The structure according to claim 4, characterized in that: The number of the capacitors included in each row and each column of the capacitor units on the silicon wafer is the same; or, The capacitor units in each row or column on the silicon wafer include the same number of capacitors.

6. The structure according to claim 1, characterized in that The deep trench comprises a low trench and a first sub-trench and a second sub-trench arranged on two first upper edges opposite to the low trench; the first bottom edges of the first sub-trench and the second sub-trench are respectively opposite to the two first upper edges and have the same height, and the second upper edges of the first sub-trench and the second sub-trench respectively opposite to the two first bottom edges are at the same height as the surface of the silicon wafer; The opposite ends of the first structure are respectively arranged in the first sub-groove and the second sub-groove, and the surface where the first dielectric layer is located is opposite to the bottom surface formed by the bottom edges of the first sub-groove and the second sub-groove; the remaining part of the first structure is zigzag arranged in the low groove, and the surface where the first dielectric layer is located is opposite to the surface where the first upper edge of the low groove is located.

7. The structure according to claim 1, characterized in that Each of the first electrodes of the capacitor is connected to one or more of the first plates of the capacitive structure; and One of the second electrodes of the capacitor is connected to one or more of the second plates of the capacitive structure.

8. The structure according to any one of claims 1 to 7, characterized in that: A scribe groove is provided between each of the capacitor units on the silicon wafer.

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