Event-driven image sensor and method of reading thereof

Abstract

The present disclosure relates to an event-driven sensor comprising: a pixel array (102); a column readout circuit (104) comprising, for each of column output lines, a column register unit (108) configured to activate a column event output signal (addrx) upon its reception of a first token when a detection of an event is indicated on the column output line; and a row readout circuit (106) comprising, for each of row output lines or for each of a plurality of subgroups of row output lines, a row register unit (108) configured to activate a row event output signal (addry) upon its reception of a second token when an event is indicated on the row output line or one of the row output lines of the subgroup.

Description

Technical Field

[0001] This disclosure generally relates to the field of sensor arrays for image or depth detection, and more particularly to event-driven pixel arrays and methods for reading them. Background Technology

[0002] An image sensor, which includes an array of imaging pixels, can detect illumination from an image scene and can temporarily store an electrical signal (usually a charge) representing the detected illumination at each pixel. The signals stored at the pixels are typically read out row by row from the entire array in a synchronous manner.

[0003] The drawback of this readout method is that it is relatively time-consuming and energy-intensive, especially for large pixel arrays. Furthermore, in many applications, particularly those involving some degree of scene tracking, there may be relatively long periods of time during which no points of interest are available to be captured, and / or at any given time, only one or a few relatively small regions of interest may exist within the pixel array. Event-driven pixel arrays are designed to provide significant speed and energy savings for such applications.

[0004] In an event-driven image sensor, each pixel is able to signal to readout circuitry surrounding the array when it detects an event. The readout circuitry then determines the pixel coordinates of the pixel that detected the event and, in some cases, reads out the value stored in the pixel or elsewhere.

[0005] The problem is that the implementation of event-driven sensors in the prior art is relatively complex, which means that the gains in energy efficiency and speed are far from optimal. Summary of the Invention

[0006] There is a need in the art for an improved event-driven pixel array and its readout method, which at least partially solves one or more problems in the prior art.

[0007] According to one embodiment, an event-driven sensor is provided, comprising: a pixel array; column readout circuitry coupled to column output lines of the pixel array, wherein for each of the column output lines, the column readout circuitry includes column register units (108) coupled to the column outputs, the column register units being connected in series with each other to propagate a first token, wherein each column register unit is configured to activate a column event output signal upon receiving the first token when an event is indicated on the column output line; and / or row readout circuitry coupled to row output lines of the pixel array, wherein for each of the row output lines, or for each of a plurality of subgroups of the row output lines, the row readout circuitry includes row register units coupled to one or more row output lines, the row register units being connected in series with each other to propagate a second token, wherein each row register unit is configured to activate a row event output signal upon receiving the second token when an event is indicated on the row output line or on one of the row output lines of the subgroups.

[0008] According to one embodiment, the column output line is a column readout request line, the column readout circuit is also coupled to the confirmation column line of the pixel array, and wherein the row output line is a row readout request line, the row readout circuit is also coupled to the confirmation row line of the pixel array.

[0009] According to one embodiment, the first pixel of the array is configured to, in response to a detected event, perform either: assert a column read request on the column read request line of the first pixel's column, and assert a row read request on the row read request line of the first pixel's row in response to an acknowledgment signal on the acknowledgment line; or assert a row read request on the row read request line of the first pixel's row, and assert a column read request on the column read request line of the first pixel's column in response to an acknowledgment signal on the acknowledgment line.

[0010] According to one embodiment, the first pixel of the array is further configured to deactivate the column and row readout request in response to asserting the confirmation signal on the confirmation column and row lines.

[0011] According to one embodiment, each column output line is a shared column output line coupled to each pixel of its column, and each row output line is a shared row output line coupled to each pixel of its row.

[0012] According to one embodiment, each column output line is daisy-chained to each pixel in its column, and each row output line is daisy-chained to each pixel in its row.

[0013] According to one embodiment, for each of a plurality of subgroups of the line output lines, the line readout circuitry includes a line register unit coupled to the line output lines of the subgroup, and the line readout circuitry further includes a pattern generation circuitry configured to generate a bit pattern indicating the line of the subgroup on which the event has occurred.

[0014] According to another aspect, a method for reading out events from pixels of an event-driven sensor is provided, the method comprising: propagating a first token via a series of column register units of a column readout circuit, wherein the column readout circuit is coupled to column output lines of a pixel array of the sensor, the column readout circuit including one of column register units coupled to the column output line for each column output line; activating a column event output signal by one of the column register units upon receiving the first token when an event is indicated on the column output line; and, before or after the propagation of the first token and the activation of the column event output signal: propagating a second token via a series of row register units of a row readout circuit, wherein the row readout circuit is coupled to row output lines of the pixel array, the row readout circuit including one of row register units coupled to the row output line for each row output line; and activating a row event output signal by one of the row register units upon receiving the second token when an event is indicated on the row output line.

[0015] According to one embodiment, the column output line is a column readout request line, the column readout circuit is also coupled to the confirmation column line of the pixel array, and wherein the row output line is a row readout request line, the row readout circuit is also coupled to the confirmation row line of the pixel array.

[0016] According to one embodiment, the method further includes: in response to a detected event, performing any of the following by a first pixel of the array: asserting a column readout request on a column readout request line of the column of the first pixel, and asserting a row readout request on a row readout request line of the row of the first pixel in response to an acknowledgment signal on the acknowledgment line; or asserting a row readout request on a row readout request line of the row of the first pixel, and asserting a column readout request on a column readout request line of the column of the first pixel in response to an acknowledgment signal on the acknowledgment line.

[0017] According to one embodiment, the method further includes: in response to the confirmation signal being asserted on the confirmation column and row, deactivating the column and row readout request by a first pixel of the array.

[0018] According to one embodiment, for each of a plurality of subgroups of the row output lines, the row readout circuit includes a row register unit coupled to the row output lines of the subgroup, and the method further includes generating a bit pattern by a pattern generation circuit of the row readout circuit indicating on which the event occurred a row of the subgroup. Attached Figure Description

[0019] The above features and advantages, as well as others, will be described in detail in the following description of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings, in which:

[0020] Figure 1 An event-driven sensor is schematically illustrated.

[0021] Figure 2A The pixels of an event-driven sensor according to an example embodiment of the present disclosure are schematically shown;

[0022] Figure 2B A pixel of an event-driven sensor according to another exemplary embodiment of this disclosure is schematically shown;

[0023] Figure 3 An event-driven sensor according to an example embodiment of the present disclosure is illustrated schematically;

[0024] Figure 4 It means in Figure 3 A flowchart of the operations in the method for reading pixels in an event-driven sensor;

[0025] Figure 5 A more detailed schematic illustration is provided based on the example embodiment. Figure 3 Column registers;

[0026] Figure 6 A more detailed schematic illustration is provided based on the example embodiment. Figure 3 The row register;

[0027] Figure 7 This indicates reading Figure 3 A timing diagram of two pixels in the same column of the sensor;

[0028] Figure 8 This indicates reading Figure 3 A timing diagram of two pixels in the same row of the sensor;

[0029] Figure 9 This is a timing diagram illustrating time-of-flight pixel operations according to an exemplary embodiment of the present disclosure;

[0030] Figure 10 A row readout circuit according to an example embodiment of the present disclosure is schematically shown;

[0031] Figure 11 A more detailed schematic illustration is shown. Figure 10 The row register of the row readout circuit;

[0032] Figure 12 The illustration schematically shows an example embodiment of the present disclosure including... Figure 10 Event-driven sensors in the line readout circuit;

[0033] Figure 13 This indicates reading Figure 12 A timing diagram of two pixels in the same column of the sensor; and

[0034] Figure 14 An event-driven sensor according to yet another exemplary embodiment of this disclosure is illustrated. Detailed Implementation

[0035] In the various figures, similar features have been designated by similar reference numerals. In particular, common structural and / or functional features in the various embodiments may have the same reference numerals and may be arranged with the same structure, dimensions, and material properties.

[0036] For clarity, only operations and elements useful for understanding the embodiments described herein are shown and described in detail. In particular, some embodiments described herein relate to image sensors, such as RGB (red, blue, green) sensors, while other embodiments relate to so-called depth sensors based on time-of-flight. Technical implementations of both types of sensors are well known to those skilled in the art and are not described in detail.

[0037] Unless otherwise indicated, when referring to two elements connected together, it means that there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0038] In the following disclosure, unless otherwise indicated, reference is made to the orientation shown in the figures when referring to absolute position qualifiers (such as the terms “front,” “back,” “top,” “bottom,” “left,” “right,” etc.) or relative position qualifiers (such as the terms “above,” “below,” “higher,” “lower,” etc.) or orientation qualifiers (such as “horizontal,” “vertical,” etc.).

[0039] Unless otherwise specified, the expressions “about,” “probably,” “basically” and “approximately” indicate within 10%, and preferably within 5%.

[0040] Figure 1An event-driven sensor 100 is schematically shown, which includes an array 102 of pixels arranged in rows and columns, a column readout circuit 104, and a row readout circuit 106.

[0041] The column readout circuit 104 includes a column event detection circuit 108 for each column and a column encoder (X encoder) 110 coupled to the column event detection circuit 106 that provides the column address (X address).

[0042] The row readout circuit 106 includes a row event detection circuit 112 for each column and a row encoder (Y encoder) 114 coupled to the row event detection circuit 112 which provides the row address (Y address).

[0043] exist Figure 1 The image shows three pixels 116, 118, and 120 of pixel array 102, located at addresses (x1, y1), (x2, y2), and (x2, y1), respectively. Therefore, pixel 120 is in the same row as pixel 116 and in the same column as pixel 118. A challenge of event-driven sensors is avoiding address collisions and thus correctly encoding the pixel address of an event when more than one pixel in the same column and / or row simultaneously signals an event. In practice, if pixels 116 and 118 at addresses (x1, y1) and (x2, y2) both signal events simultaneously, there is a risk that the address (x2, y1) of pixel 120 will be incorrectly assigned the coordinates of either or both events.

[0044] To address this issue, according to embodiments of this disclosure, a handshake protocol is implemented, for example, between the pixel and column and row readout circuits 104, 106, and a token-based priority scheme is implemented, for example, by each of the readout circuits 104, 106, as will now be referred to Figures 2 to 106. Figure 8 A more detailed description.

[0045] Figure 2A The illustration schematically shows examples such as those according to the present disclosure. Figure 1 An array of 100 such as the pixels of an event-driven sensor 200.

[0046] Pixel 200 includes, for example, a photosensitive device 202, which in Figure 2A In the example, it is represented as a photodiode. More generally, device 202 is any device that generates an electrical signal based on the light it receives from the image scene. For example, device 202 could be a pinned photodiode or SPAD (single-photon avalanche diode), or a more complex device that outputs analog or digital output signals such as voltage or current representing light intensity, photon count values, etc.

[0047] Pixel 200 is coupled, for example, to shared column lines 204 and 206 and shared row lines 208 and 210. Shared column lines 204 and 206 are coupled, for example, to at least two pixels in a column of the pixel array, and typically to all pixels, and shared row lines 208 and 210 are coupled, for example, to at least two pixels in a row of the pixel array, and typically to all pixels.

[0048] Shared column line 204 is, for example, a column readout request line, on which pixel 200 asserts a column request signal. This indicates when an event was detected. Shared column line 206 is, for example, an acknowledgment line, on which pixel 200 receives a column acknowledgment signal ackx (described in more detail below) indicating that the request has been registered by the corresponding column event detection circuit.

[0049] Shared line line 208 is, for example, a line readout request line, on which pixel 200 asserts a request signal. This indicates when an event was detected and an acknowledgment (ackx) was received on column acknowledgment line 206. Shared row line 210 is, for example, an acknowledgment line on which pixel 200 receives a row acknowledgment signal (acky) indicating that the request has been registered by the corresponding row event detection circuit (described in more detail below).

[0050] Pixel 200 is configured, for example, to detect an event based on an electrical signal or value generated by device 202, and in response, to assert a request signal on line 204. Then, pixel 200 is configured, for example, to detect when to assert an acknowledgment signal ackx on line 206, and in response to assert a request signal on line 208. Then, pixel 200 is configured, for example, to detect when an assertion acknowledgment signal azy is asserted on line 210, and in response, to reinitialize its event detection mechanism.

[0051] To perform these functions, pixel 200 includes, for example, an event detection circuit (EVENT DET) 212, whose input is coupled to device 202 and whose output is coupled to memory circuit 214. Event detection circuit 212 is activated, for example, by a signal GATE, which is, for example, a common signal for all pixels in the array. Memory circuit 214 is configured to store the event detection state at its output Q until the event has been registered by column and row event detection circuits. In some embodiments, memory circuit 214 is implemented by an SR (set-reset) flip-flop, wherein the set input S of flip-flop 214 receives the output of event detection circuit 212. However, other implementations based on any bistable device are possible.

[0052] In some embodiments, the output of memory circuit 214 is coupled to one input of AND gate 216, and the other input of AND gate 216 is coupled to the output of another memory circuit 218. This other memory circuit, for example, receives a signal INIT at its input, which indicates when pixel circuit 200 becomes active and thus can signal the event to the readout circuit. In some embodiments, memory circuit 218 is implemented by receiving the signal INIT at its set input S of SR flip-flop 218.

[0053] The output of AND gate 216, for example, activates switch 220, which is configured as an assertion request signal. In some embodiments, a request signal The signal is active low, and switch 220 is implemented by a transistor (such as an n-channel MOS (NMOS) transistor) whose gate is coupled to the output of AND gate 216 and whose main conductive node couples line 204 to ground. In this case, line 204 is coupled to the power supply voltage VDD, for example, at one edge of the pixel array via resistor 222. Of course, line 204 can also be active high by replacing the NMOS transistor with a PMOS transistor and inverting its corresponding digital input command.

[0054] When the acknowledgment signal ackx is asserted on line 206, the output of AND gate 216 also causes, for example, a request signal. The assertion is made on line 208. For example, when both switches 224 and 226 are activated, where switch 224 is activated by the output of AND gate 216 and switch 226 is activated by the acknowledgment signal ackx, the request signal is asserted. In some embodiments, a request signal The circuit is active low, and switches 224 and 226 are connected in series between line 208 and ground. For example, switches 224 and 226 are implemented by transistors (such as NMOS transistors) connected in series via their main conductive nodes, with the gate of switch 224 coupled to the output of AND gate 216 and the gate of switch 226 coupled to line 206. In this case, line 208 is coupled to the power supply voltage VDD, for example, at one edge of the pixel array via resistor 228. Of course, line 208 can also be active high by replacing the NMOS transistor with a PMOS transistor and inverting its corresponding digital input command.

[0055] The reinitialization of the event detection mechanism in pixel 200 is performed, for example, by AND gate 230, which couples one of its inputs to acknowledgment line 206, the other input to acknowledgment line 210, and its output to memory circuits 214 and 218 to reset their states. If memory circuits 214 and 218 are SR flip-flops, the output of AND gate 230 is coupled, for example, to the reset input R of these flip-flops.

[0056] The INIT signal is, for example, a global signal for all pixels in the array. However, in some embodiments, the INIT signal can also be common to pixels in rows and / or columns of the pixel array, but independent between rows and / or columns. For example, this would allow sub-regions of the pixel array to be defined as regions of interest, resulting in faster readout of those sub-regions. In cases where the INIT signal is row- and column-based, this would also, for example, allow selection of individual sets of pixels to avoid readout noise or defective sensors. In this case, for example, an additional AND gate is added to the S-input of the drive flip-flop 218 for each pixel. Its inputs would be connected to column and row lines driven by X and Y peripheral circuitry, such as shift registers. For example, an activation sequence for the selected pixels would be performed before image acquisition.

[0057] In an alternative embodiment, pixel 200 is always active and therefore no initialization signal INIT is provided. In such an embodiment, memory circuit 218 and AND gate 216 can be omitted; for example, switches 220 and 224 are directly controlled by the Q output of memory circuit 214.

[0058] Pixel 200, for example, is capable of detecting an event and requesting a readout of the event detection state. Additionally, in some embodiments, besides the event detection state, pixel 200 may also be configured to output a detection value, such as a light intensity value or a photon count. In this case, for example, the output to an additional shared column or row line is provided from each pixel to allow the signal to be output.

[0059] Figure 2B It schematically shows the following based on Figure 2A Alternative embodiments of event-driven sensors (such as Figure 1 The array has 100 pixels and 250 pixels. Figure 2B The embodiments have the same Figure 2A The embodiments share certain features, and these features have been labeled with the same reference numerals and will not be described in detail again.

[0060] exist Figure 2BIn the example, request line 204 is replaced by input request line 252 and output request line 254. Input request line 252 receives signals reqxi from neighboring pixels in the column above pixel 250, while output request line 254 sends signals reqxo to neighboring pixels in the column below pixel 250. For example, a pixel at the top of the column couples its request input line 252 to the 0V ground rail. Similarly, request line 208 is replaced by input request line 256 and output request line 258. Input request line 256 receives signals reqyi from neighboring pixels in the row to the left of pixel 250, while output request line 258 sends signals reqyo to neighboring pixels in the row to the right of pixel 250. For example, a pixel at the leftmost end of the row couples its request input line 256 to the 0V ground rail.

[0061] Therefore, in Figure 2B In the example, the request line is daisy-chained along each row and column of the pixel.

[0062] In addition, Figure 2B In the example, transistors 220, 224, and 226 are replaced by OR gate 262, AND gate 264, and OR gate 266. OR gate 262 receives the output of AND gate 216 at one of its inputs and receives the input request signal reqxi on line 252 at its other input. The output of OR gate 262 provides the output request signal reqxo on line 254.

[0063] AND gate 264 has one input coupled to the output of AND gate 216, and its other input coupled to acknowledgment line 206. The output of AND gate 264 is coupled to one input of OR gate 266. The other input of OR gate 266 receives the input request signal reqyi on line 256. The output of OR gate 266 provides the output request signal reqyo on line 258.

[0064] The operation of pixel 250 is similar to Figure 2A The operation of pixel 200. In fact, when any pixel asserts the column request signal reqxo or the row request signal reqyo, the request signal will be transmitted to the end of the column or row via any intermediate pixels.

[0065] Figure 3 An event-driven sensor 300 according to an example embodiment of the present disclosure is schematically illustrated. The sensor 300 includes, for example, components related to... Figure 1 The array 100 shares some common features, and similar features have been marked with similar reference numerals.

[0066] exist Figure 3In one embodiment, the column readout circuit 104 includes a column event detection circuit 108 implemented by register units forming a column register (X register), wherein the output of each of the circuits 108 is provided to the column encoder (X encoder) 110. Furthermore, the column readout circuit 104 includes, for example, a control circuit (x CTRL) 302 that provides a token signal Ix and a clock signal clkx to the column event detection circuit 108. The circuits 108 are coupled in series with each other, for example, and are configured to propagate the token represented by the token signal Ix from one end of the series circuit 108 to the other. For example, the clock signal clkx is provided to each of the circuits 108. In some embodiments, the scan end detection circuit 303 detects when the last detection circuit 108 in the series releases a token, allowing a new token to be injected again at the beginning of the series.

[0067] Similarly, the row readout circuit 106 includes, for example, a row event detection circuit 112 implemented by register units forming a row register (Y register), the output of each of the circuits 112 being provided to the row encoder (Y encoder) 114. Furthermore, the row readout circuit 106 includes, for example, a control circuit (yCTRL) 304 that provides a token signal Iy and a clock signal clky to the row event detection circuit 112. For example, the token signal Iy is in response to a signal generated in any column. And generated, for example, by signals based on column readout circuit 106 The OR signal addrx is detected by an OR tree (not shown). Circuits 112 are, for example, series coupled to each other and configured to propagate a token, represented by the token signal Iy, from one end of the series circuit 112 to the other. For example, a clock signal clky is provided to each of the circuits 112. In some embodiments, the scan end detection circuit 305 detects when the last detection circuit 112 in the series releases a token, preparing a new token to be injected again at the beginning of the series.

[0068] For example, Figure 3 The pixel array 102 includes Figure 2A 200 pixels, one of which is in Figure 3 As shown, request and confirmation lines 204, 206 are coupled to the corresponding column event detection circuit 108 of their respective columns, and request and confirmation lines 208, 210 are coupled to the corresponding row event detection circuit 112 of their respective rows. (See diagram for reference.) Figure 2A As explained, request and confirmation lines 204 and 206 are shared, for example, within the pixels of each column, and therefore there are, for example, as many request lines 204 and confirmation lines 206 as there are columns in the array. Similarly, request and confirmation lines 208 and 210 are shared, for example, within the pixels of each row, and therefore there are, for example, as many request lines 208 and confirmation lines 210 as there are rows in the array.

[0069] Although Figure 3 An example is shown in which the column and row readout circuits 104, 106 are located at the edges of the array, but in alternative embodiments, these circuits may be located elsewhere, such as in a separate tier in the case of a stacked 3D image sensor. In particular, the array 102 of pixels, or at least the sensor 202 for each pixel, and possibly the event detector 212, may be implemented, for example, in a tier optimized for detection, and the remaining circuitry, including the readout circuitry, may be implemented in another tier that primarily contains digital circuitry and is optimized for speed.

[0070] Figure 4 It means in Figure 3 The flowchart illustrates the operations in a method for reading pixels in an event-driven sensor. This method is, for example, at least partially performed by hardware, and particularly by... Figure 2A or Figure 2B pixel circuit and Figure 3 The column and row readout circuits 104 and 106 are implemented. In some cases, the control circuits 302 and 304 may be implemented entirely in hardware, such as by a state machine, while in alternative embodiments, these circuits may be implemented at least in part by software executed by one or more processors, such as a microprocessor.

[0071] In operation 401, control circuit 302, for example, injects token TOKENx into a series of register cells 108.

[0072] In operation 402, there is a pulse of the clock signal clkx.

[0073] In operation 403, it is determined whether there is a presence at any register unit 108 that has not yet been processed. The event of the signal. If not, it means that the end of the image frame has been reached, as indicated by box 404. However, if at least one event exists, the next operation is operation 405.

[0074] In operation 405, the first register unit 108 of the X register where the event is detected asserts the acknowledgment signal ackx on the acknowledgment line 206. Furthermore, the signal addrx, for example, is asserted by this register unit, causing the X encoder to generate the corresponding X address.

[0075] Then, in operation 406, control circuit 304 injects, for example, token TOKENy into the series of register units 112.

[0076] In operation 407, there is a pulse of the clock signal clky.

[0077] In operation 408, it is determined whether the value exists at any register unit 112. The event of the signal. If none exists, it means the Y scan has been completed, and the method returns to step 402, where a new clock pulse for clock clkx has appeared. However, if at least one event exists, the next operation is operation 409.

[0078] In operation 409, the first register unit 112 of the Y register where the event is detected asserts the acknowledgment signal acky on acknowledgment line 210. Furthermore, the signal addry is asserted by this register unit, causing the Y encoder to generate the corresponding Y address. The method then returns to operation 407, for example, and repeats the loop until no further reading is required. That concludes the event.

[0079] Therefore, each read cycle is initiated, for example, by the injection of a token TOKENx and the appearance of a clock clkx pulse. Once a read cycle ends at the end of frame 404, a new read cycle can be initiated immediately or after a delay. For example, read cycles can be initiated periodically, such as every 10 milliseconds, to detect whether any events have occurred in the image scene. Alternatively, read cycles can be executed back-to-back without any waiting period between cycles.

[0080] Figure 5 The example embodiment is illustrated schematically in more detail. Figure 3 Register unit 108.

[0081] Each of the register units 108 includes, for example, a three-way switch 502 (also known as an SPDT (single-pole double-throw)), an OR gate 504, synchronous memory devices 506 and 508 implemented by flip-flops, an OR gate 510, and an AND gate 512.

[0082] The three-way switch 502 is implemented, for example, by a demultiplexer, and receives the signal Ix directly from the control circuit 302 at its input, in the case of the first circuit register in the series, or via one or more of the other register units in the series at their inputs. Switch 502 selectively supplies the signal Ix to the input of OR gate 504, or via bypass path 514 to the input of OR gate 510. For example, switch 502 is controlled by line 204, and specifically, when a request signal is received... When high (indicating no column event), switch 502 supplies signal Ix to bypass path 514, for example, and when a request signal is received... When the signal is low (indicating the presence of a column event), switch 502 supplies signal Ix to OR gate 504, for example.

[0083] The output of OR gate 504 is coupled, for example, to the data input D1 of flip-flop 506, which is, for example, a D-type flip-flop. The data output Q1 of flip-flop 506 is coupled, for example, to the data input D2 of flip-flop 508, which is also, for example, a D-type flip-flop. The data output Q2 of flip-flop 508 is coupled, for example, to another input of OR gate 510. Flip-flop 506 is timed, for example, by a clock signal clkx, and flip-flop 508 is timed, for example, by a signal on line 204. Timekeeping.

[0084] The output Q1 of flip-flop 506 is further coupled to one input of AND gate 512, and the other input of AND gate 512 receives the request signal on line 204 at the inverting input. The output of AND gate 512 provides an acknowledgment signal ackx on line 206, and this signal is also provided to the other input of OR gate 504.

[0085] The output Q1 of trigger 506 also provides, for example, the output signal addrx of circuit 108, which indicates when an event is detected in a column of pixels in register unit 108. This signal enables... Figure 3 The column decoder 110 generates the x address of one or more pixels that have detected the event.

[0086] The output 516 of OR gate 510 provides signal Ix to the next register unit 108 in the series, or in the case of the last register unit 108 in the series, provides signal Ix to the scan end detection circuit 303.

[0087] Figure 6 The example embodiment is illustrated schematically in more detail. Figure 3 Row register unit 112.

[0088] Each of the register units 112 includes, for example, a three-way switch 602, a synchronous memory device 604 implemented by a flip-flop, an OR gate 606, and an AND gate 608.

[0089] The three-way switch 602 is implemented, for example, by a demultiplexer, and receives the signal Iy directly from the control circuit 304 at its input in the case of the first register unit of the series, or via one or more of the other register units at their inputs in the case of the other register units of the series. Switch 602 selectively supplies the signal Iy to the data input D1 of flip-flop 604, which is, for example, a D-type flip-flop, or via bypass path 610 to the input of OR gate 606. Switch 602 is controlled, for example, by line 208, and specifically, when a request signal is received... When high (indicating no row event), switch 602 supplies signal Iy to bypass path 610, for example, and when a request signal is received... When the signal is low (indicating the presence of a row event), switch 602 supplies signal Iy to trigger 604, for example.

[0090] The data output terminal Q1 of the flip-flop 604 is coupled to another input terminal of the OR gate 606, for example. The flip-flop 604 is timed, for example, by a clock signal clky.

[0091] The output Q1 of flip-flop 604 is further coupled to one input of AND gate 608, and its other input, at the inverting input, receives a request signal on line 208. The output of AND gate 608 provides an acknowledgment signal (acky) on line 210.

[0092] The output Q1 of trigger 604 also provides, for example, the output signal addry of circuit 108, indicating when an event is detected in a row of pixels in register unit 108. This signal enables... Figure 3 The line decoder 114 generates the y address of the pixel that detected the event.

[0093] The output 612 of OR gate 606 provides signal Iy to the next register unit 112 in the series, or in the case of the last register unit 112 in the series, provides signal Iy to the scan end detection circuit 305.

[0094] Figure 5 and Figure 6 Register units 108 and 112 provide Figure 4 At least a portion of the implementation of the method, and particularly when events exist in two pixels in the same column or row, allows for the avoidance of address conflicts, as will now be referred to. Figure 7 and Figure 8 To provide a more detailed description.

[0095] Figure 7 This indicates reading Figure 3 A timing diagram of two pixels in the same column of a sensor. Figure 7 Examples are shown below: signals INIT, GATE, and the request signal for the nth column. Ix, clkx, ackx, X ADDRESS, the end of the x scan signal eox, and the request signal for the m-th line. The request signal on line m' Iy, clky, acky(m) of the m-th row, acky(m) of the m'-th column, Y ADDRESS and eoy of the end of the y scan signal.

[0096] The signal INIT goes low, for example, at time t0 to activate pixels in the pixel array, and the signal GATE has a high pulse starting at time t1 to activate event detection. At time t2, an event is detected by a pixel in the nth column, which is triggered by the signal... Lower the indication. A read cycle is then initiated with an x-scan. Specifically, the signal Ix includes a pulse that begins at time t3 corresponding to the token TOKENx, thereby causing the OR gate 504 (see...) Figure 5 The output of OR gate 504 goes high. The clock signal clkx has a rising edge at time t4, which causes the output of OR gate 504 to be stored at the output Q1 of flip-flop 506, and thus the acknowledgment signal ackx goes high at time t5. In addition, the address encoder receives the signal addrx, and thus generates the x address X ADDRESS at time t6.

[0097] The acknowledgment signal ackx causes the pixel in the m-th row of the n-th column to assert a request signal at time t7. Furthermore, it also causes another pixel in the m'th row of the nth column to assert a request signal at essentially the same time t7. Later, the y-scan of the read cycle begins. Specifically, the signal Iy includes a pulse that begins at time t8 corresponding to the token TOKENy, causing trigger 604 (see...). Figure 6 The data input goes high. The clock signal clky has a rising edge at time t9, which causes the output of flip-flop 604 to go high, and therefore the acknowledgment signal acky(m) of column m goes high shortly thereafter at time t10. The rising of the acknowledgment signal acky(m) will cause the pixels in column n and row m to make a request signal at time t11. It becomes higher. Furthermore, the signal addry in the m-th row will be asserted (see [link]). Figure 6 Therefore, the Y encoder 114 will generate the Y address Y ADDRESS at time t12.

[0098] At time t11, the request signal Approximately simultaneously with the rising edge, pixels in the nth column and mth row will release the request signal. However, this signal remains low because the second pixel in the nth column has not yet been read. Therefore, at the next rising edge of the clock signal clkx at time t13, the token TOKENx is held at register cell 108 in the nth column.

[0099] At the subsequent rising edge of the clock signal clky at time t14, the token TOKENy will propagate to register cell 112 in row m', and therefore, the acknowledgment signal acky(m') will be asserted at time t15. The rising of the acknowledgment signal acky(m') will cause the pixels in column n and row m' to request signals at time t16. and It becomes high, and thus confirms that signals ackx and azy will soon go low. Furthermore, it will assert that the signal addry in row m' (see...) Figure 6 Therefore, the Y encoder 114 will generate a new y address Y ADDRESS at time t17.

[0100] At time t18, the subsequent rising edge of the clock signal clkx causes, for example, the token TOKENx to reach the scan end detection circuit 303, and thus, for example, asserts the end of the x-scan signal eox. This signal is provided, for example, to the x-scan control circuit 302 to allow the initiation of a subsequent x-scan.

[0101] Similarly, at time t19, the subsequent rising edge of the clock signal clky causes, for example, the token TOKENy to reach the scan end detection circuit 305, and thus, for example, asserts the end of the y-scan signal eoy. This signal is provided, for example, to the y-scan control circuit 304 to allow the initiation of a subsequent y-scan.

[0102] Figure 8 This indicates reading Figure 3 A timing diagram of two pixels in the same row of the pixel array of a sensor. Figure 8 Examples are shown below: signals INIT, GATE, and the request signal for the nth column. Request signal of column n' Ix, clkx, ackx(n) of the nth column, ackx(n') of the n'th column, X ADDRESS, eox of the end of the x scan signal, and request signal of the mth row. The Iy, clk, acky, Y ADDRESS and the end of the y scan signal eoy.

[0103] The signal INIT goes low, for example, at time t0 to activate pixels in the pixel array, and the signal GATE has a high pulse starting at time t1 to activate event detection. At time t2, an event is detected by a pixel in the nth column, which is triggered by the signal... The indicator decreases, and around the same time, an event is detected by the n'th column pixel, which is signaled by... Lower the indication. Later, initiate a read cycle starting with an x-scan. Specifically, signal Ix includes a pulse that begins at time t3 corresponding to token TOKENx, thereby causing OR gate 504 (see...) Figure 5 The output of OR gate 504 goes high. The clock signal clkx has a rising edge at time t4, which causes the output of OR gate 504 to be stored at the output Q1 of flip-flop 506, and therefore, the acknowledgment signal ackx(n) goes high at time t5. In addition, the address encoder receives the signal addrx, and therefore generates the x address X ADDRESS at time t6.

[0104] The acknowledgment signal ackx causes the pixel in the m-th row of the n-th column to assert a request signal at time t7. Later, the y-scan of the read cycle begins. Specifically, the signal Iy includes a pulse that begins at time t8 corresponding to the token TOKENy, causing trigger 604 (see...). Figure 6 The data input goes high. The clock signal clky has a rising edge at time t9, which causes the output of flip-flop 604 to go high, and therefore the acknowledge signal acky(m) goes high shortly thereafter at time t10. The rising of the acknowledge signal acky(m) will cause the pixels in the nth column and mth row to request the signal at time t11. The signal goes high, and the acknowledgment signal ackx(n) goes low, but since the second pixel in the m-th row has not yet been read, a request signal is not issued. and Keep it low. Furthermore, the signal addry in the m-th row will be asserted (see [link]). Figure 6 Therefore, the Y encoder 114 will generate the Y address Y ADDRESS at time t12.

[0105] At time t13, at the subsequent rising edge of the clock signal clkx, the token TOKENx will propagate to register cell 108 in row n', and thus at time t14, the acknowledgment signal ackx(n') is asserted, and the address encoder receives the signal addrx, and thus at time t15, the x address X ADDRESS is generated.

[0106] The y-scan of the read cycle will continue shortly. Specifically, because of the request signal... Keeping it low, the token TOKENy remains at register cell 112 in row m. At the next rising edge of the clock signal clky at time t16, flip-flop 604 (see...) Figure 6 The output of ) will go high, and the confirmation signal azy(m) will then go high shortly thereafter at time t17. The rise of the confirmation signal azy(m) will cause the pixels in column n' and row m to request the signal at time t18. and The signal will rise, and shortly thereafter, the confirmation signals ackx(n') and azy(m) will fall.

[0107] At time t19, the subsequent rising edge of the clock signal clkx causes, for example, the token TOKENx to reach the scan end detection circuit 303, and thus, for example, asserts the end of the x-scan signal eox. This signal is provided, for example, to the x-scan control circuit 302 to allow the initiation of a subsequent x-scan.

[0108] Similarly, at time t20, a subsequent rising edge of the clock signal clky causes, for example, the token TOKENy to reach the scan end detection circuit 305, and thus, for example, asserts the end of the y-scan signal eoy. This signal is provided, for example, to the y-scan control circuit 304 to allow the initiation of a subsequent y-scan.

[0109] In image sensor applications, for example, the signal GATE provided to the pixels allows global shutter operation to be applied to the array.

[0110] In Time-of-Flight (ToF) applications, the signal GATE in a pixel can be used to set the range of distances used for detection, as will be referenced now. Figure 9 To provide a more detailed description.

[0111] Figure 9 This is a timing diagram illustrating time-of-flight (ToF) pixel operations according to an example embodiment of the present disclosure. Figure 9 The following examples are shown: signals INIT, GATE, LASER corresponding to the timing of transmitting light pulses into the image scene, Pix ON indicating the signal detected within certain pixels, TDC for controlling the GATE signal, and READOUT.

[0112] exist Figure 9 In the example, the LASER signal goes high at time t0, which corresponds to the time when the laser pulse is sent into the image scene. The pulse will be reflected by any objects present in the image scene, and the returning pulse is captured by the photosensitive device 202 of the pixels in the pixel array. The distance of objects in the image scene will affect the duration required for the pulse to complete its round trip.

[0113] At time t1, for example, a high pulse of the signal GATE begins, this pulse has a duration Tg, and ends at time t2. Therefore, a return pulse returning to any pixel before t1 or after t2 will not be detected by the pixel, and the event will only be generated during the time interval t1 to t2. This is in Figure 9The signal Pix ON, represented by the pixel, indicates that only those detections occurring during the interval t1 to t2 will be considered events. This allows the signal GATE to be used for distance detection of objects present within a certain distance range. The duration tdmin1 between time t0 and time t1 sets the minimum distance at which the object will be detected. The duration Tg of the time interval sets the precision of the distance detection.

[0114] like Figure 9 As indicated, the detection cycle can be repeated at times t0' and t0”, combined with pulses of the signal GATE that begin at times t1' and t1” and end at times t2' and t2”, respectively. The durations tdmin2 and tdmin3 between times t0' and t1” and between times t0” and t1”, respectively, differ from the duration tdmin1, thus allowing the detection of different distances. In this way, a relatively large range of distances in an image scene can be scanned, for example, over several cycles.

[0115] Although Figures 3 to 8 In the embodiments described, full scans were performed in both x and y, but in some embodiments, a y scan can be performed faster by combining rows, as will now be referred to. Figures 10 to 12 As described in more detail.

[0116] Figure 10 A sub-circuit 1002 of a row readout circuit 106 according to an exemplary embodiment of the present disclosure is schematically shown. In this embodiment, the row readout circuit 106 includes, for example, a plurality of sub-circuits 1002. Figure 10 As shown, each sub-circuit 1002 includes, for example, a single register unit 1004 for a plurality of r rows of a pixel array. A NAND gate 1006, for example, combines request signals from the r rows. to The request signal `reqyblck`, which generates a combination of request signals, is provided to register unit 1004 in addition to request signals `reqy(0)` to `reqy(r-1)`. Register unit 1004 generates the signal `addry`, which is similar to the signal generated by... Figure 3 The signal generated by register unit 112 indicates a sub-circuit-level event rather than a row-level event. This signal is used, for example, by the Y group encoder of row readout circuit 106 to generate a sub-circuit address. Furthermore, sub-circuit 1002 includes another latching circuit 1010, which, for example, is used based on a request signal. to The signal addry generates additional bits in the y address, indicating the row of the event in row r. This circuit 1010 includes, for example, latches 1012, each latch 1012 receiving a request signal. to In the corresponding case, latch 1012 is timed, for example, by the addry signal, and provides an r-bit output signal via switch 1014, which indicates the row of pixel events. Switch 1014 is also controlled, for example, by the addry signal.

[0117] Figure 11 A schematic diagram showing more details Figure 10 Register unit 1004. This circuit is, for example, similar to... Figure 6 The register unit 112, and similar features are marked with similar reference numerals, and will not be described in detail again. However, in Figure 11 In this embodiment, there are r AND gates 608_0 to 608_r-1, each receiving a request signal at its inverting input. to Each of these corresponds to one of the signals, and each generates a corresponding acknowledgment signal from akey(0) to akey(r-1). Furthermore, switch 602 is controlled by the combined request signal reqyblck.

[0118] Figure 12 The illustration schematically shows an example embodiment of the present disclosure including... Figure 10 The event-driven sensor 1200 is used in the line readout circuit. For example... Figure 12 As shown, the x-scan circuit, for example, is with Figure 3 The x-scan circuit is the same (control circuit 302 in) Figure 12 (not shown in the image), but the y-scan circuit is... Figure 10 Replace it with sub-circuit 1002, repeating this process multiple times.

[0119] Now refer to Figure 13 describe Figure 12 Operation of array 1200.

[0120] Figure 13 It shows the reading Figure 12 A timing diagram of two pixels in the same column of a pixel array. Figure 13 Examples are shown below: signals INIT, GATE, and the request signal for the nth column. The request signals for group p in rows Ix, clkx, ackx, XADDRESS, eox, and r. The request signal from another group q in line r. The acknowledgment signals acky(Group_p) for group p in row r, acky(Group_q) for group q in row r, Y ADDRESS, and the end of the y scan signal eoy.

[0121] Figure 13 The timing diagram is similar to Figure 7The timing diagram will be provided, and the same aspects will not be described in detail again. However, in Figure 13 In the example, when reading pixels in a row within group p of a row, the group signal addry(group p) is asserted, generating two values. One value is the y group address (Y GROUP ADDRESS) generated by the Y group encoder 1008, indicating the address of group p. The other value is a pattern (Y PIXEL GROUPPATTERN) indicating the position of one or more active rows within group p, corresponding to one or more rows of the one or more pixels read. Similarly, when reading pixels in a row within group q of a row, the group signal addry(group q) is asserted, again generating two values: the y group address, indicating the address of group q; and the pixel group pattern, indicating the position of one or more active rows within group q, corresponding to one or more rows of the one or more pixels read.

[0122] In some embodiments, the readout speed can be further improved by dividing the pixel array 102 and providing separate register units and encoders that operate in parallel, as will now be referred to. Figure 14 Described.

[0123] Figure 14 An event-driven sensor 1400 according to yet another exemplary embodiment of the present disclosure is schematically illustrated, wherein an array 102 of pixels is divided into four regions of substantially equal size, Q1, Q2, Q3, and Q4, and corresponds, for example, quadrants of the pixel array. For example, each quadrant has dedicated X and Y encoders and a corresponding readout system, these elements in... Figure 14 Chinese use and Figure 3 The same reference numerals are used in the accompanying drawings, but the markings "Q1", "Q2", "Q3", and "Q4" indicate the quadrant to which they belong. Therefore, in Figure 14 In one embodiment, four scans can be performed simultaneously, one scan in each of the four quadrants, resulting in a fourfold increase in read speed.

[0124] The advantages of the embodiments described herein are that the solution provides a simple and fast way to read the column and row addresses of pixel events while avoiding address collisions. In particular, this solution is not based on an arbitration tree, which is a relatively bulky circuit used in some prior art methods. This solution also has the advantage of synchronization, for example, reading one address per clock cycle of clock clkx, clky. Furthermore, it has been found that very high readout speeds can be achieved since the clock speed can be 100MHz or higher, and... Figure 12 In this case, the maximum read speed is equal to r times the clock frequency.

[0125] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and other variations will readily conceive of them. For example, it will be apparent to those skilled in the art that… Figure 14 The embodiments can be related to Figure 10 The circuits are used in combination.

[0126] Furthermore, it will be apparent to those skilled in the art that, although embodiments have been described in which each pixel is configured to first respond to the detection of an event and assert a column readout request signal in response to a column acknowledgment signal, each pixel may also be initiated by a row readout request and assert a column readout request in response to a row acknowledgment signal.

[0127] Furthermore, although an embodiment using X and Y encoders to generate addresses has been described, alternative implementations, particularly in the case of relatively small arrays, may instead involve the use of one or more external counters to count the number of "0"s in the addrx and addry signals before finding the first "1", so that the count value indicates the location of the event in the X or Y register, and thus the address.

Claims

1. An event-driven sensor, comprising: -Pixel array (102); A column readout circuit (104) coupled to the column output lines (204, 254) of the pixel array, wherein for each of the column output lines, the column readout circuit includes a column register unit (108) coupled to the column output, the column register units being connected in series with each other to propagate a first token (TOKENx), wherein each column register unit is configured to activate a column event output signal (addrx) upon receiving the first token when an event is indicated on the column output line; and A row readout circuit (106) coupled to the row output lines (208, 258) of the pixel array, wherein for each of a plurality of subgroups of the row output lines, the row readout circuit includes a sub-circuit (1002) comprising a single row register unit (108, 1004) coupled to the plurality of row output lines, the row register units being coupled in series with each other to propagate a second token, wherein each row register unit is configured to, when an event is indicated on one of the plurality of row output lines of the subgroup, activate a row event output signal indicating an event in that subgroup of the row output line upon receiving the second token.

2. The event-driven sensor according to claim 1, wherein, The column output lines (204, 254) are column readout request lines, and the column readout circuit (104) is also coupled to the confirmation column line (206) of the pixel array, wherein the row output line (208) is a row readout request line, and the row readout circuit (104) is also coupled to the confirmation row line (210) of the pixel array.

3. The event-driven sensor according to claim 2, wherein, The first pixel (200) of the array is configured to perform any of the following in response to a detected event: - Assert the column read request on the column read request lines (204, 254) of the first pixel. And in response to the acknowledgment signal (ackx) on the acknowledgment line (206), an assertion is made on the row readout request line (208) of the row of the first pixel. or - Assert the row read request on the row read request lines (208, 258) of the row of the first pixel. And in response to the acknowledgment signal (acky) on the acknowledgment column line (206), an assertion column readout request is made on the column readout request line (210) of the first pixel.

4. The event-driven sensor according to claim 3, wherein, The first pixel (200) of the array is also configured to trigger a column and row readout request in response to asserting the acknowledgment signals (ackx, azy) on the acknowledgment column and row lines (206, 210). Go to activate.

5. The event-driven sensor according to any one of claims 1 to 4, wherein, Each column output line (204, 254) is a shared column output line (204) coupled to each pixel of its column, and each row output line (208, 258) is a shared row output line (208) coupled to each pixel of its row.

6. The event-driven sensor according to any one of claims 1 to 4, wherein, Each column output line (204, 254) is daisy-chained to each pixel in its column, and each row output line (208, 258) is daisy-chained to each pixel in its row.

7. The event-driven sensor according to any one of claims 1 to 6, wherein the row readout circuit further comprises a pattern generation circuit (1010) configured to generate a bit pattern indicating a subgroup of rows on which the event has occurred.

8. A method for reading out an event from a pixel of an event-driven sensor, the method comprising: - A first token (TOKENx) is propagated through a series of column register units (108) of a column readout circuit (104), wherein the column readout circuit (104) is coupled to column output lines (204, 254) of the pixel array of the sensor, and for each column output line, the column readout circuit includes one of the column register units (108) coupled to the column output line; - When an event is indicated on the column output line, one of the column register units (108) activates the column event output signal (addrx) upon receiving the first token; and before or after the propagation of the first token and the activation of the column event output signal: - A second token (TOKENy) is propagated sequentially through the row register unit (112) of the row readout circuit (106), wherein the row readout circuit (106) is coupled to the row output lines (208, 258) of the pixel array, and for each of the plurality of subgroups of the row output lines, the row readout circuit includes a sub-circuit (1002), the sub-circuit including a single row register unit (112) coupled to the plurality of row output lines; and - When an event is indicated on one of the multiple line output lines of the subgroup, one of the line register units (112) activates the line event output signal (addry) indicating the event in the subgroup on the line output line when it receives the second token.

9. The method according to claim 8, wherein, The column output lines (204, 254) are column readout request lines, and the column readout circuit (104) is also coupled to the confirmation column line (206) of the pixel array, wherein the row output line (208) is a row readout request line, and the row readout circuit (104) is also coupled to the confirmation row line (210) of the pixel array.

10. The method of claim 9, further comprising: In response to a detected event, the first pixel (200) of the array performs one of the following: - Assert the column read request on the column read request lines (204, 254) of the first pixel. And in response to the acknowledgment signal (ackx) on the acknowledgment line (206), an assertion is made on the row readout request line (208) of the row of the first pixel. or - Assert the row read request on the row read request lines (208, 258) of the row of the first pixel. And in response to the acknowledgment signal (acky) on the acknowledgment column line (206), an assertion column readout request is made on the column readout request line (210) of the first pixel.

11. The method of claim 10, further comprising: In response to asserting the acknowledgment signals (ackx, azy) on the acknowledgment column and row lines (206, 210), the first pixel (200) of the array makes a column and row readout request. Go to activate.

12. The method according to any one of claims 8 to 11, further comprising: The pattern generation circuit (1010) of the row readout circuit generates a bit pattern indicating the row of the subgroup on which the event has occurred.

13. An event-driven sensor, comprising: -Pixel array (102); A column readout circuit (104) coupled to the column output lines (204, 254) of the pixel array, wherein for each of the column output lines, the column readout circuit includes a column register unit (108) coupled to the column output, the column register units being connected in series with each other to propagate a first token (TOKENx), wherein each column register unit is configured to activate a column event output signal (addrx) upon receiving the first token when an event is indicated on the column output line; and A row readout circuit (106) coupled to the row output lines (208, 258) of the pixel array, for each of the row output lines, or for each of a plurality of subgroups of the row output lines, the row readout circuit includes row register units (108, 1004) coupled to one or more row output lines, the row register units being coupled in series with each other to propagate a second token, wherein each row register unit is configured to activate a row event output signal when it receives the second token when an event is indicated on the row output line or on one of the row output lines of the subgroup; Each column output line (204, 254) is daisy-chained to each pixel in its column, and each row output line (208, 258) is daisy-chained to each pixel in its row.

Images