Polarization coding

Abstract

Embodiments of the present disclosure provide a method, device, and computer-readable medium for performing polar coding. In an example embodiment, the method includes generating an initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order. At least one of the plurality of parity bits is a copy of one of the plurality of information bits. The method also includes generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order in such a manner that at least one of the plurality of parity bits and one of the information bits are processed differently during polar coding of the interleaved sequence. The method also includes encoding the interleaved sequence using a polar code. The method also includes transmitting the encoded sequence to a receiving device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to wireless communications, and particularly to a method, apparatus, and computer-readable medium for performing polar coding. Background Art

[0002] Polar codes are used as a control channel coding solution for enhanced mobile broadband (eMBB) in new radio (NR). Research has shown that polar codes offer the advantages of low complexity, low latency, and no error layer effects. Therefore, they can also be used in ultra-reliable low-latency communications (URLLC) and massive machine-type communications (mMTC).

[0003] In information theory, polar codes are a type of linear block error-correcting code. The code construction is based on multiple recursive concatenations of a short kernel code that transforms a physical channel into a virtual outer channel. As the number of recursions increases, the virtual channels tend to have either high or low reliability (in other words, they become polarized), and data bits are assigned to the most reliable channel. Summary of the Invention

[0004] In general, example embodiments of the present disclosure provide a method, apparatus, and computer-readable medium for performing polar coding.

[0005] In a first aspect, a method for communication is provided. The method includes generating an initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order. At least one of the plurality of parity bits is a repetition of one of the information bits. The method also includes generating an interleaved sequence by changing the initial order such that the at least one of the plurality of parity bits and the one of the information bits are processed differently during polar coding of the interleaved sequence of the plurality of information bits and the plurality of parity bits. The method also includes encoding the interleaved sequence using a polar code. The method also includes transmitting the coded sequence to a receiving device.

[0006] In a second aspect, a method for communication is provided. The method includes: generating an initial sequence including a plurality of information bits and a plurality of parity bits in an initial order; inserting at least one dummy bit into the initial sequence, wherein the value of each dummy bit is known to a receiving device; generating an interleaved sequence of a plurality of information bits, a plurality of parity bits, and the at least one dummy bit by changing the initial order such that the at least one dummy bit precedes the plurality of information bits and the plurality of parity bits; encoding the interleaved sequence using a polar code; and transmitting the encoded sequence to a receiving device.

[0007] In a third aspect, a method for communication is provided. The method includes generating an initial sequence including a plurality of information bits and a plurality of parity bits in an initial order, at least one of the plurality of parity bits having a predefined value; generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order; encoding the interleaved sequence using a polar code; and transmitting the coded sequence to a receiving device.

[0008] In a fourth aspect, an electronic device is provided. The electronic device includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, together with the at least one processor, cause the electronic device to: generate an initial sequence including a plurality of information bits and a plurality of parity bits in an initial order, wherein at least one of the plurality of parity bits is a repetition of one of the information bits; generate an interleaved sequence by changing the initial order such that the at least one parity bit in the plurality of parity bits and the one of the information bits are processed differently during polarization encoding of an interleaved sequence of the plurality of information bits and the plurality of parity bits; encode the interleaved sequence using a polar code; and transmit the encoded sequence to a receiving device.

[0009] In a fifth aspect, an electronic device is provided. The electronic device includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, together with the at least one processor, cause the electronic device to: generate an initial sequence including a plurality of information bits and a plurality of parity bits in an initial order; insert at least one dummy bit into the initial sequence, wherein the value of each dummy bit is known to a receiving device; generate an interleaved sequence including a plurality of information bits, a plurality of parity bits, and the at least one dummy bit by changing the initial order such that the at least one dummy bit precedes the plurality of information bits and the plurality of parity bits; encode the interleaved sequence using a polar code; and transmit the encoded sequence to a receiving device.

[0010] In a sixth aspect, an electronic device is provided. The electronic device includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, together with the at least one processor, cause the electronic device to: generate an initial sequence including a plurality of information bits and a plurality of parity bits in an initial order, at least one of the plurality of parity bits having a predefined value; generate an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order; encode the interleaved sequence using a polar code; and transmit the encoded sequence to a receiving device.

[0011] In a seventh aspect, a computer readable medium having instructions stored thereon is provided. The instructions, when executed on at least one processor of a device, cause the device to perform the method according to the first aspect.

[0012] In an eighth aspect, a computer readable medium having instructions stored thereon is provided, wherein the instructions, when executed on at least one processor of a device, cause the device to perform the method according to the second aspect.

[0013] In a ninth aspect, a computer readable medium having instructions stored thereon is provided, wherein the instructions, when executed on at least one processor of a device, cause the device to perform the method according to the third aspect.

[0014] It should be understood that the summary is not intended to identify the key or essential features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of some embodiments of the present disclosure in the accompanying drawings, in which:

[0016] Figure 1 is a schematic diagram of a communication environment in which embodiments of the present disclosure may be implemented;

[0017] Figure 2 A flowchart illustrating an example method according to some embodiments of the present disclosure is shown;

[0018] Figure 3 is a schematic diagram illustrating an example of an interleaving sequence according to some embodiments of the present disclosure;

[0019] Figure 4 A flowchart illustrating an example method according to some other embodiments of the present disclosure is shown;

[0020] Figure 5 is a schematic diagram illustrating an example of an interleaving sequence according to some other embodiments of the present disclosure;

[0021] Figure 6A is a schematic diagram illustrating an example mapping of interleaving sequences to subchannels according to some other embodiments of the present disclosure;

[0022] Figure 6B is a schematic diagram illustrating an example mapping of interleaving sequences to subchannels according to other embodiments of the present disclosure;

[0023] Figure 7 A flowchart illustrating an example method according to other embodiments of the present disclosure is shown;

[0024] Figure 8 A flowchart illustrating an example method according to other embodiments of the present disclosure is shown;

[0025] Figure 9is a schematic diagram illustrating an example mapping of interleaving sequences to subchannels according to other embodiments of the present disclosure;

[0026] Figure 10 A flowchart illustrating an example method according to some other embodiments of the present disclosure is shown;

[0027] Figure 11 is a schematic diagram of an example polar decoding structure;

[0028] Figure 12 is a graph showing simulation results of performance evaluation according to some embodiments of the present disclosure; and

[0029] Figure 13 is a simplified block diagram of a device suitable for implementing embodiments of the present disclosure.

[0030] Throughout the drawings, the same or similar reference numerals refer to the same or similar elements. DETAILED DESCRIPTION

[0031] The principles of the present disclosure will now be described with reference to some exemplary embodiments. It should be understood that these embodiments are described for illustrative purposes only and to help those skilled in the art understand and implement the present disclosure without placing any limitation on the scope of the present disclosure. The disclosure described herein can be implemented in various other ways in addition to the ways described below.

[0032] In the following description and claims, unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs.

[0033] As used herein, the term "network device" or "base station" (BS) refers to a device that can provide or host a cell or coverage area in which terminal devices can communicate. Examples of network devices include, but are not limited to, NodeB (NodeB or NB), evolved NodeB (eNodeB or eNB), next-generation NodeB (gNB), remote radio unit (RRU), radio head (RH), remote radio head (RRH), low-power nodes (such as femto nodes, pico nodes, etc.). For the purpose of discussion, some embodiments will be described below with reference to eNB or gNB as an example of a network device.

[0034] As used herein, the term "terminal device" refers to any device with wireless or wired communication capabilities. Examples of terminal devices include, but are not limited to, user equipment (UE), personal computers, desktop computers, mobile phones, cellular phones, smartphones, personal digital assistants (PDAs), portable computers, image capture devices (such as digital cameras, gaming devices, music storage and playback devices), or Internet appliances that support wireless or wired Internet access and browsing. For discussion purposes, some embodiments will be described below with reference to UE as an example of a terminal device, and the terms "terminal device" and "user equipment" (UE) may be used interchangeably in the context of this disclosure.

[0035] The term "circuitry" as used herein may refer to one or more or all of the following: (a) a pure hardware circuit implementation (such as an implementation solely in analog and / or digital circuitry); and (b) a combination of hardware circuitry and software, such as, as applicable: (i) a combination of analog and / or digital hardware circuitry and software / firmware, and (ii) any portion of hardware processor(s) (including digital signal processor(s)), software, and memory(s) with software that work in conjunction to cause a device such as a mobile phone or server to perform various functions; and (c) hardware circuit(s) and / or processor(s) that require software (e.g., firmware) to operate (but may be absent when not required for operation), such as microprocessor(s) or portion(s) of microprocessor(s).

[0036] This definition of "circuitry" applies to all uses of this term in this application, including in any claims. As another example, as used in this application, the term "circuitry" also covers an implementation of a purely hardware circuit or processor (or multiple processors) or a portion of a hardware circuit or processor and its (or their) accompanying software and / or firmware. The term "circuitry" also covers (for example, and if applicable to a particular claim element) a baseband integrated circuit or processor integrated circuit for a mobile device, or a similar integrated circuit in a server, cellular network device, or other computing or networking device.

[0037] As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "including" and its variations should be understood as open terms meaning "including but not limited to." The term "based on" should be understood as "based at least in part on." The term "one embodiment" and "an embodiment" should be understood as "at least one embodiment." The term "another embodiment" should be understood as "at least one other embodiment." The terms "first," "second," etc. may refer to different or the same objects. Other definitions (explicit and implicit) may be included below.

[0038] In some examples, values, processes, or devices are referred to as "best," "lowest," "highest," "minimum," "maximum," etc. It should be understood that such descriptions are intended to indicate that a selection may be made among many functional alternatives for use, and that such selection is not necessarily better, lesser, higher, or otherwise preferable to other selections.

[0039] Figure 1 FIG1 is a schematic diagram of a communication environment 100 in which embodiments of the present disclosure may be implemented. The communication environment 100 may include a network device 110 that provides wireless connectivity for multiple terminal devices 120 and 130 within its coverage area. The terminal devices 120 and 130 may communicate with the network device 110 via wireless transmission channels 115 or 125 and / or communicate with each other via transmission channel 135.

[0040] I understand. Figure 1 The number of network devices and terminal devices shown is for illustrative purposes only and does not represent any limitation. Communication environment 100 may include any suitable number of network devices and terminal devices suitable for implementing the embodiments of the present disclosure. In addition, it should be understood that various wireless communications and wired communications (if necessary) may exist between these network devices and terminal devices.

[0041] Communications in the communication environment 100 may conform to any suitable standard, including but not limited to Global System for Mobile Communications (GSM), Extended Coverage Global Mobile Internet of Things (EC-GSM-IoT), Long Term Evolution (LTE), LTE Evolution, Advanced LTE (LTE-A), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access (CDMA), GSM EDGE Radio Access Network (GERAN), etc.

[0042] Furthermore, communications in the communication environment 100 may be performed according to any generation of communication protocols currently known or to be developed in the future. Examples of communication protocols include, but are not limited to, first generation (1G), second generation (2G), 2.5G, 2.75G, third generation (3G), fourth generation (4G), 4.5G, and fifth generation (5G) communication protocols.

[0043] As illustrative examples, the various example implementations or techniques described herein may be applied to various terminal devices, such as machine type communication (MTC) terminal devices, enhanced machine type communication (eMTC) terminal devices, Internet of Things (IoT) terminal devices, and / or narrowband IoT terminal devices.

[0044] In an example implementation, the terminal device or UE may be a UE / terminal device with a URLLC application. A cell (or multiple cells) may include multiple terminal devices connected to the cell, including terminal devices of different types or categories, such as MTC, NB-IoT, URLLC, or other UE categories.

[0045] Various example implementations may be applied to a variety of wireless technologies or wireless networks, such as LTE, LTE-A, 5G, cmWave and / or mmWave frequency band networks, IoT, MTC, eMTC, URLLC, etc., or any other wireless network or wireless technology. These example networks or technologies are provided as illustrative examples only, and various example implementations may be applied to any wireless technology / wireless network.

[0046] As mentioned above, polar codes can be used as a control channel coding scheme for URLLC. The false alarm rate of error detection is crucial for downlink control channels, which require blind decoding. Compared to LTE, URLLC requires a lower false alarm rate, such as 1e-5. Two conventional solutions have been proposed to reduce the false alarm rate.

[0047] In one of the two conventional solutions, more cyclic redundancy check (CRC) differences are employed, which means that a larger CRC polynomial should be used. Because current CRC attachment is optimized for early termination by using an interleaver after CRC generation, larger CRC polynomials should be carefully designed for backward compatibility.

[0048] Another conventional solution uses unused bits in the Downlink Control Information (DCI) message for checking. However, this solution has two problems: even without duplication, the false alarm rate cannot meet the requirements, and not all of the current eight DCI formats contain unused bits.

[0049] In order to at least partially solve the above and other potential problems, embodiments of the present disclosure provide a solution for polar coding. According to an embodiment of the present disclosure, at least one new check bit is introduced, and the at least one new check bit is a copy of one of the multiple information bits. At least one new check bit is inserted into the multiple information bits so that the at least one new check bit and the information bit in the information bits will be processed differently during polar coding. Through the embodiments of the present disclosure, since the at least one new check bit and the information bit in the information bits will be processed differently during polar coding, the probability of an error occurring in the at least one new check bit and one of the multiple information bits can be reduced. Therefore, the inspection effectiveness can be improved. In the following, the polar coding method will be combined with the polar coding method. Figure 2-12 Some embodiments according to the present disclosure are described in detail.

[0050] Figure 2 1 shows a flow chart of an example method 200 according to some embodiments of the present disclosure. In the context of the present disclosure, for ease of discussion and without loss of generality, the network device 110 in the communication environment 100 may be described as a transmitting device, and the terminal device 120 in the communication environment 100 may be described as a receiving device. It should be understood that in some other communication scenarios, the terminal device 120 may be a transmitting device, and the network device 110 may be a receiving device.

[0051] Typically, transmitting device 110 can transmit information to receiving device 120 for communication. For example, the transmitted information can be data information, control information, etc. Before transmission, transmitting device 110 can encode the information using a polar code (such as channel coding) to improve transmission quality. Accordingly, receiving device 120 can receive the encoded information and obtain the information by decoding the encoded information using the polar code.

[0052] At block 210, transmitting device 110 generates an initial sequence, for example, based on control information to be sent to receiving device 120. The initial sequence includes a plurality of information bits and a plurality of parity bits in an initial order. Among the plurality of parity bits, at least one parity bit is a copy of one of the information bits. For example, each parity bit in the at least one parity bit may be a copy of an information bit adjacent to the parity bit. In the context of this disclosure, a parity bit that is a copy of an information bit is also referred to as a new parity bit, and the other parity bits in the plurality of parity bits are also referred to as existing parity bits.

[0053] In some embodiments, at least one new parity bit is different in a downlink control information (DCI) message. In some embodiments, the existing parity bits can be any type of error detection code, such as CRC bits. For ease of discussion and without loss of generality, the existing parity bits will be described using CRC bits as an example. It should be understood that if transmitting device 110 and receiving device 120 employ other error detection schemes, the existing parity bits can be other types of error detection codes.

[0054] In some embodiments, the number of the at least one new check bit can be determined based on the expected false alarm rate and the number of existing check bits. -27 And the number of existing check bits is 2 -24 When , the number of at least one new parity bit can be determined to be 3.

[0055] At block 220, transmitting device 110 generates an interleaved sequence of multiple information bits and multiple parity bits by changing the initial order. The change to the initial order is performed so that at least one new parity bit and one of the multiple information bits are processed differently during polar coding of the interleaved sequence. In the context of this disclosure, an interleaved sequence to be encoded using a polar code may also be referred to as an information block or block.

[0056] In some embodiments, during polar coding of an interleaved sequence, transmitting device 110 may perform an exclusive-OR operation on at least one new parity bit and perform an original output of one of the information bits. Alternatively, during polar coding of an interleaved sequence, transmitting device 110 may perform an exclusive-OR operation on one of the information bits and perform an original output of at least one new parity bit. It should be understood that performing an exclusive-OR operation and performing an original output are merely examples of different processing methods and do not limit the scope of this disclosure. Because the at least one new parity bit and one of the information bits are processed differently during polar coding, the probability of errors in the at least one new parity bit and one of the information bits can be reduced. Consequently, check validity can be improved.

[0057] Generally, after changing the initial order of the initial sequence, multiple parity bits may not be evenly distributed in the interleaved sequence, e.g. Figure 3 shown.

[0058] Figure 3 3GPP TS 38.211. Figure 3 As can be seen in FIG, the parity bits 312 are not evenly distributed in the interleaved sequence 300, which may reduce the effectiveness of the parity check.

[0059] In order to improve the effectiveness of the check, in some embodiments of the present disclosure, the transmitting device 110 changes the initial order of the initial sequence to evenly distribute the multiple check bits to generate an interleaved sequence. In other words, the multiple check bits are evenly distributed in the interleaved sequence. This means that for any two parts of the interleaved sequence, the difference between the ratio of the check bits to the information bits in one part of the two parts and the ratio of the check bits to the information bits in the other part of the two parts is lower than the threshold difference. Figure 4One such embodiment is described.

[0060] Figure 4 FIG. 4 is a flow chart showing an example method 400 for generating an interleaved sequence according to some other embodiments of the present disclosure. Figure 1 For the purpose of discussion, reference will be made to the sending device 110. Figure 1 and 3 The method 400 is described from the perspective of the transmitting device 110. For example, the method 400 may be as follows: Figure 2 An example implementation of block 220 is shown. It should be understood that method 400 may include additional blocks not shown and / or may omit some of the blocks shown, and the scope of the present disclosure is not limited in this regard.

[0061] At block 410 , the transmitting device 110 sets the index x of the DCRC portion to 1. At block 415 , the transmitting device 110 evenly distributes N parity bits in the first DCRC portion 314 , where N represents the number of new parity bits as described above.

[0062] At block 420, transmitting device 110 calculates a first average number of information bits between two parity bits in DCRC part x and a second average number of information bits between two parity bits in DCRC part x+1.

[0063] At block 425 , transmitting device 110 determines whether the first average number of information bits in DCRC portion x is less than the second average number of information bits in DCRC portion x+1. If the first average number is not less than the second average number, transmitting device 110 increments index x by one at block 430 .

[0064] At block 435, the transmitting device 110 determines whether the value of index x is less than or equal to the total number of DCRC parts. Figure 3 In the example shown, the total number of DCRC parts is equal to three. If the value of index x is equal to 1, transmitting device 110 may determine that the value of index x is less than the total number of DCRC parts.

[0065] If it is determined at block 435 that the value of index x is less than or equal to the total number of DCRC parts, transmitting device 110 determines at block 440 whether there are any parity bits that need to be moved to the next DCRC part.

[0066] If it is determined in block 440 that no parity bits need to be moved to the next DCRC section, the transmitting device 110 arranges the parity bits and information bits, which will be processed differently during polar coding, on the f-node and the g-node, respectively. To arrange the parity bits and information bits on the f-node and the g-node, respectively, if both the parity bits and the information bits are arranged on the f-node or the g-node, the transmitting device 110 may shift one of the parity bits and the information bits to the left or right by up to one bit.

[0067] On the other hand, if it is determined at block 425 that the first average number is not less than the second average number, the transmitting device 110 moves one parity bit in DCRC part x to DCRC part x+1 and evenly distributes the parity bits in DCRC part x at block 450. The method 400 then returns to block 420.

[0068] Furthermore, if it is determined at block 435 that the value of index x is greater than the total number of DCRC portions, the transmitting device 110 increments index x by 1 at block 455 . The method 400 then returns to block 420 .

[0069] Furthermore, if it is determined at block 440 that no parity bits need to be moved to the next DCRC portion, the transmitting device 110 sets the index x of the DCRC portion to 1 at block 460 . The method 400 then returns to block 420 .

[0070] Through the method 400, multiple parity bits are evenly distributed in the interleaved sequence, for example, Figure 5 shown. Figure 5 is a schematic diagram showing an example of an interleaving sequence 500 according to some other embodiments of the present disclosure. Figure 3 Compared to the example shown in Figure 5 In the example shown, existing parity bits 511 and new parity bits 512 are evenly distributed in interleaved sequence 500, thereby improving parity effectiveness. Note that parity bit sequence 313 is not moved because the subchannel to which parity bits 313 will be mapped has higher reliability.

[0071] Reference again Figure 2 At block 230, the transmitting device 110 encodes the interleaved sequence using a polarization code. During polarization coding, various coding algorithms may be used, including existing polarization coding algorithms and other polarization coding algorithms that may be developed in the future.

[0072] At block 240 , the transmitting device 110 transmits the encoded sequence to the receiving device 120 .

[0073] Generally, polar coding has the following characteristics: at a certain breakpoint, the index of the first subchannel to which the information bits or parity bits are mapped changes to half its value. For example, for an information block of a certain size, if the index of the first subchannel is 256, then even if only one additional bit is added to the information block, the index of the first subchannel becomes 128. Generally, the receiving device 120 will start decoding from the first subchannel. If the index of the first subchannel is greatly reduced, the decoding delay will increase significantly, which will be combined with the Figure 6A and 6B Provide explanation.

[0074] Figure 6A is a schematic diagram illustrating an example mapping of interleaving sequences to sub-channels of channel 600 according to some other embodiments of the present disclosure, and Figure 6B is a diagram illustrating an example mapping of interleaving sequences to sub-channels of channel 605 according to other embodiments of the present disclosure.

[0075] like Figure 6A As shown, channel 600 includes subchannel 611 and subchannel 612. Existing parity bits or information bits in an information block are mapped to subchannel 611 for polar coding. Therefore, in the context of this disclosure, subchannel 611 to which existing parity bits or information bits are mapped is also referred to as a first-type occupied subchannel 611. No existing parity bits or information bits are mapped to subchannel 612, but frozen bits are mapped to subchannel 612. Because the values of the frozen bits are known to receiving device 120, receiving device 120 excludes the encoded frozen bits from decoding. Therefore, in the context of this disclosure, subchannel 612 to which frozen bits are mapped is also referred to as a first-type blank subchannel 612.

[0076] like Figure 6A As shown, the first type of initially occupied subchannel 611 is adjacent to the first type of blank subchannel 612. Upon receiving the encoded information block, the receiving device 120 begins decoding from the first type of initially occupied subchannel 611. Information bits or parity bits are mapped to the first type of initially occupied subchannel 611.

[0077] If an additional bit is added to the information block, the position of the subchannel that starts to be occupied can be changed. Figure 6BAs shown, the position of the starting occupied subchannel is changed so that it is located between the first type of blank subchannels 612. The starting occupied subchannel located between the first type of blank subchannels 612 can be referred to as the second type of occupied subchannel 613. Upon receiving the encoded information block, the receiving device 120 will begin decoding from the second type of occupied subchannel 613. In other words, the receiving device 120 will take more time to decode the encoded information block. In other words, the decoding delay is significantly increased.

[0078] In order to reduce the decoding delay, in some embodiments, the transmitting device 110 may insert at least one dummy bit before the check bit and the information bit, which will be referred to below. Figure 7 Provide a description.

[0079] Figure 7 700 according to some embodiments of the present disclosure. For example, the method 700 may be performed in Figure 1 100 is implemented at the network device 110 shown in the figure. It should be understood that method 700 may include additional blocks not shown and / or may omit some blocks shown in the figure, and the present disclosure is not limited in this regard. In the context of the present disclosure, for ease of discussion and without loss of generality, the network device 110 in the communication environment 100 may be described as a sending device, and the terminal device 120 in the communication environment 100 may be described as a receiving device. It should be understood that in some other communication scenarios, the terminal device 120 may be a sending device, and the network device 110 may be a receiving device.

[0080] At block 710 , the transmitting device 110 generates an initial sequence including a plurality of information bits and a plurality of parity bits in an initial order.

[0081] At block 720, the transmitting device 110 inserts at least one dummy bit into the initial sequence, the value of each dummy bit being known to the receiving device.

[0082] At block 730 , the transmitting device 110 generates an interleaved sequence of a plurality of information bits, a plurality of parity bits, and at least one dummy bit by changing the initial order such that the at least one dummy bit is arranged before the plurality of information bits and the plurality of parity bits.

[0083] At block 740 , the transmitting device 110 encodes the interleaved sequence using a polar code.

[0084] At block 750 , the transmitting device 110 transmits the encoded sequence to the receiving device 120 .

[0085] In some embodiments, the at least one dummy bit is determined based on an identification of the receiving device 120 .

[0086] Because receiving device 120 knows the value of each dummy bit, it will bypass at least one dummy bit and begin encoding the information bits or check bits after the at least one dummy bit. In other words, receiving device 120 will exclude decoding of at least one dummy bit. Therefore, decoding speed is accelerated and decoding delay is reduced.

[0087] Figure 8 FIG. 8 is a flow chart illustrating an example method 800 for inserting at least one dummy bit according to other embodiments of the present disclosure. Figure 1 For the purpose of discussion, reference will be made to the sending device 110. Figure 1 Method 800 is described from the perspective of transmitting device 110. For example, method 800 may be Figure 7 An example implementation of method 700 is shown. It should be understood that method 800 may include additional blocks not shown and / or may omit some of the blocks shown, and the scope of the present disclosure is not limited in this regard.

[0088] As shown in the figure, at block 810, the transmitting device 110 generates a first additional sequence by combining a frozen bit sequence with an interleaved sequence. Figure 6B In the example shown, the first additional sequence may be a sequence including bits mapped onto subchannels 611 , 612 , and 613 .

[0089] At block 820, the transmitting device 110 determines the number of frozen bits in the subset of frozen bits between the start bit and the first bit in the first additional sequence. Figure 6B In the example shown, the starting bit may be a bit mapped to subchannel 613, the first bit may be a bit mapped to subchannel 611 after subchannel 613, and the subset of frozen bits may include frozen bits mapped to subchannel 612 between subchannel 613 and subchannel 611.

[0090] At block 830, the transmitting device 110 determines whether the number of frozen bits in the subset of frozen bits exceeds a threshold number. In some embodiments, the threshold number may be determined as 2^abs(log2(P)-1), where P represents the index of the subchannel to which the starting bit in the first additional sequence is mapped. For example, Figure 6B In the example shown, P represents the index of subchannel 613. It should be understood that 2^abs(log2(P)-1) is only an example of a threshold value and does not limit the scope of the present disclosure. Depending on the specific application scenario, the threshold value can be determined to be any appropriate value.

[0091] If it is determined at block 830 that the number of frozen bits in the subset of frozen bits exceeds the threshold number, the transmitting device 110 marks the starting bit x as “D” (also referred to as bit “D”) at block 840. On the other hand, if it is determined at block 830 that the number of frozen bits in the subset of frozen bits does not exceed the threshold number, the transmitting device 110 may perform any appropriate action at block 890.

[0092] At block 850, the transmitting device 110 inserts a dummy bit labeled "Y" (also referred to as bit "Y"). At block 860, the transmitting device 110 interleaves the dummy bits, the parity bits, and the information bits.

[0093] At block 870, the transmitting device 110 determines whether bit "Y" precedes bit "D." If it is determined at block 870 that bit "Y" does not precede bit "D," the transmitting device 110 swaps the positions of bit "D" and bit "Y" at block 880. On the other hand, if it is determined at block 870 that bit "Y" precedes bit "D," the transmitting device 110 may perform any appropriate action at block 890.

[0094] It should be understood that method 800 may be repeated if more dummy bits are to be inserted.

[0095] Figure 9 9 is a diagram showing an example mapping of interleaving sequences to sub-channels of channel 900 according to other embodiments of the present disclosure. Figure 9 The example shown is the same as Figure 6B Compared to the example shown, the dummy bits are mapped to the subchannel 614 (also referred to as the second type of blank subchannel 614). Figure 6B The starting parity bits or information bits are shown mapped to subchannel 613 (also referred to as the second type of occupied subchannel 613). In this way, when receiving an encoded information block, the receiving device 120 will bypass subchannel 614 and start encoding from subchannel 611 after subchannel 614. In other words, decoding speed is accelerated and decoding delay is reduced.

[0096] Figure 10 FIG. 1 is a flow chart showing an example method 1000 for generating an interleaved sequence according to some other embodiments of the present disclosure. Figure 1 For the purpose of discussion, reference will be made to the sending device 110. Figure 1 Method 1000 is described from the perspective of transmitting device 110. It should be understood that method 1000 may include additional blocks not shown and / or may omit some of the blocks shown, and the scope of the present disclosure is not limited in this regard.

[0097] At block 1010, the transmitting device 110 generates an initial sequence including a plurality of information bits and a plurality of parity bits in an initial order, wherein at least one parity bit in the plurality of parity bits has a predefined value.

[0098] In some embodiments, the predefined value may be 0 or 1.

[0099] At block 1020 , the transmitting device 110 generates an interleaved sequence of a plurality of information bits and a plurality of parity bits by changing an initial order.

[0100] At block 1030 , the transmitting device 110 encodes the interleaved sequence using a polar code.

[0101] At block 1040 , the transmitting device 110 transmits the encoded sequence to the receiving device 120 .

[0102] In some embodiments, at least one of the plurality of parity bits is a bit in a downlink control information message.

[0103] In some embodiments, the plurality of parity bits are evenly distributed in the interleaved sequence.

[0104] In the following, reference will be made to Figure 11 The decoding operation performed at the receiving device 120 is described. Figure 11 1 is a schematic diagram of an exemplary polarization decoding structure 1100. As shown in the figure, the exemplary polarization decoding structure 1100 includes f-nodes 1111 to 1114 and g-nodes 1121 to 1124.

[0105] In some embodiments, the calculations performed at the f-nodes 1111 to 1114 may be represented by the following equation (1), and the calculations performed at the g-nodes 1121 to 1124 may be represented by the following equation (2):

[0106] f(a,b)=sign(a)sign(b)min(|a|,|b|) (1)

[0107] g(a,b)=(-1)^u+b (2)

[0108] Wherein, a and b represent input parameters of the f nodes 1111 to 1114 and input parameters of the g nodes 1121 to 1124, respectively, and u represents a decoded information bit or a decoded check bit.

[0109] For leaf nodes in the code tree for polar decoding, f nodes 1111 to 1114 are odd-indexed nodes, and g nodes 1121 to 1124 are even-indexed nodes. The leaf nodes are indexed so that the first node is decoded first in a successive elimination decoder.

[0110] As described above, during polar coding, transmitting device 110 can arrange information bits and parity bits, which are copies of the information bits, at f-nodes and g-nodes, respectively, so that they are processed differently. Accordingly, during polar decoding, receiving device 120 can arrange the encoded information bits at one of f-nodes 911 and 912, and the encoded parity bits at one of g-nodes 921 and 922. Because calculations 911 to 914 performed at the f-nodes and calculations performed at the g-nodes 921 to 924 are not strongly correlated, verification efficiency can be improved.

[0111] Figure 12 1 is a graph 1200 showing simulation results for performance evaluation according to some embodiments of the present disclosure. In the simulation, an example solution according to an embodiment of the present disclosure is compared with a conventional encoding / decoding solution. Figure 12 In FIG, curve 1210 represents a conventional encoding / decoding scheme, and curve 1220 represents an example scheme according to an embodiment of the present disclosure. Figure 12 In FIG, the horizontal axis represents SNR and the vertical axis represents BLER.

[0112] In the simulation, a block size of K = 6 and 6 CRC bits were considered, where two new check bits were introduced. Therefore, there are 8 information bits. The two new check bits are set to bit 8 and bit 6, which are obtained by duplicating information bits 5 and 4 respectively. The list size used is 16. These check bits are used to perform tree pruning without performing duplication. Figure 12 As can be seen in , a gain of about 0.3 dB needs to be achieved. It is also observed that the gain is higher for larger list sizes, which is especially useful for URLLC, as URLLC may use larger list sizes to achieve better performance.

[0113] In some embodiments, an apparatus for executing method 200 (e.g., network device 110 or terminal devices 120, 130) may include corresponding modules for executing corresponding steps in method 200. These modules may be implemented in any suitable manner. For example, they may be implemented by circuit systems or software modules.

[0114] In some embodiments, the apparatus includes: means for generating an initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order, at least one of the plurality of parity bits being a copy of one of the information bits; means for generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order in such a manner that at least one of the plurality of parity bits and one of the information bits will be processed differently during polar coding of the interleaved sequence; means for encoding the interleaved sequence using a polar code; and means for transmitting the encoded sequence to a receiving device.

[0115] In some embodiments, at least one parity bit of the plurality of parity bits is a bit in a downlink control information message.

[0116] In some embodiments, the means for generating an interleaved sequence includes a component for changing an initial order to evenly distribute a plurality of parity bits to generate the interleaved sequence.

[0117] In some embodiments, an apparatus for executing method 700 (e.g., network device 110 or terminal devices 120, 130) may include corresponding modules for executing corresponding steps in method 700. These modules may be implemented in any suitable manner. For example, they may be implemented by circuit systems or software modules.

[0118] In some embodiments, the apparatus includes: means for generating an initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order; means for inserting at least one dummy bit into the initial sequence, the value of each dummy bit being known to a receiving device; means for generating an interleaved sequence of a plurality of information bits, a plurality of parity bits, and the at least one dummy bit by changing the initial order in such a manner that the at least one dummy bit is arranged before the plurality of information bits and the plurality of parity bits; means for encoding the interleaved sequence using a polar code; and means for transmitting the encoded sequence to a receiving device.

[0119] In some embodiments, the at least one dummy bit is determined based on an identification of the receiving device.

[0120] In some embodiments, an apparatus for executing method 1000 (e.g., network device 110 or terminal devices 120, 130) may include corresponding modules for executing corresponding steps in method 1000. These modules may be implemented in any suitable manner. For example, they may be implemented by circuit systems or software modules.

[0121] In some embodiments, the apparatus includes: means for generating an initial sequence, the initial sequence including a plurality of information bits and a plurality of parity bits in an initial order, at least one of the plurality of parity bits having a predefined value; means for generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order; means for encoding the interleaved sequence using a polar code; and means for transmitting the encoded sequence to a receiving device.

[0122] In some embodiments, at least one parity bit of the plurality of parity bits is a bit in a downlink control information message.

[0123] In some embodiments, the plurality of parity bits are evenly distributed in the interleaved sequence.

[0124] Figure 13 is a simplified block diagram of a device 1300 suitable for implementing embodiments of the present disclosure. The device 1300 can be considered as Figure 1 A further exemplary embodiment of the network device 110 and the terminal devices 120, 130 is shown. Thus, the device 1300 may be implemented at the network device 110 or the terminal devices 120, 130 or as at least a part thereof.

[0125] As shown, device 1300 includes a processor 1310, a memory 1320 coupled to processor 1310, a suitable transmitter (TX) and receiver (RX) 1340 coupled to processor 1310, and a communication interface coupled to TX / RX 1340. Memory 1320 stores at least a portion of program 1330. TX / RX 1340 is configured for bidirectional communication. TX / RX 1340 has at least one antenna to facilitate communication, but in practice, the access nodes referred to in this application may have multiple antennas. The communication interface may represent any interface required for communication with other network elements, such as an X2 interface for bidirectional communication between eNBs, an S1 interface for communication between a Mobility Management Entity (MME) / Serving Gateway (S-GW) and an eNB, a Un interface for communication between an eNB and a relay node (RN), or a Uu interface for communication between an eNB and a terminal device.

[0126] Assume that the program 1330 includes program instructions that, when executed by the associated processor 1310, enable the device 1300 to operate in accordance with embodiments of the present disclosure, as described herein with reference to Figures 2 to 10The embodiments herein may be implemented by computer software executable by the processor 1310 of the device 1300, or by hardware, or by a combination of software and hardware. The processor 1310 may be configured to implement various embodiments of the present disclosure. Furthermore, the combination of the processor 1310 and the memory 1320 may form a processing device 1350 suitable for implementing various embodiments of the present disclosure.

[0127] Memory 1320 may be of any type suitable for the local technology network and may be implemented using any suitable data storage technology, such as, by way of non-limiting example, non-transitory computer-readable storage media, semiconductor-based storage devices, magnetic storage devices and systems, optical storage devices and systems, fixed memory, and removable memory. Although only one memory 1320 is shown in device 1300, several physically distinct memory modules may be present in device 1300. Processor 1310 may be of any type suitable for the local technology network and, by way of non-limiting example, may include one or more of a general-purpose computer, a special-purpose computer, a microprocessor, a digital signal processor (DSP), and a processor based on a multi-core processor architecture. Device 1300 may have multiple processors, such as application-specific integrated circuit chips that are time-slave to a clock synchronized with a main processor.

[0128] The components included in the apparatus and / or equipment of the present disclosure can be implemented in various ways, including software, hardware, firmware or any combination thereof. In one embodiment, one or more units can be implemented using software and / or firmware, such as machine executable instructions stored on a storage medium. In addition to or instead of machine executable instructions, some or all of the units in the apparatus and / or equipment can be implemented at least in part by one or more hardware logic components. For example, and not limitation, illustrative types of hardware logic components that can be used include field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chip (SOCs), complex programmable logic devices (CPLDs), etc.

[0129] In general, various embodiments of the present disclosure may be implemented in hardware or dedicated circuits, software, logic, or any combination thereof. Some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software that may be executed by a controller, microprocessor, or other computing device. Although various aspects of the embodiments of the present disclosure are shown and described as block diagrams, flow charts, or using some other graphical representation, it should be understood that, as non-limiting examples, the blocks, devices, systems, techniques, or methods described herein may be implemented in hardware, software, firmware, dedicated circuits or logic, general-purpose hardware or a controller or other computing device, or some combination thereof.

[0130] The present disclosure also provides at least one computer program product tangibly stored on a non-transitory computer readable storage medium. The computer program product includes computer executable instructions, such as computer executable instructions included in a program module, which are executed in a device on a target real or virtual processor to perform the above referenced Figure 2 、 4 and 7. Generally, program modules include routines, programs, libraries, objects, classes, components, data types, and the like that perform specific tasks or implement specific abstract data structures. The functionality of program modules can be combined or split between program modules as needed in various embodiments. Machine-executable instructions for program modules can be executed on local or distributed devices. In distributed devices, program modules can be located on local and remote storage media.

[0131] The program code for executing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that these program codes, when executed by the processor or controller, cause the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0132] The above program code can be embodied on a machine-readable medium, which can be any tangible medium that can contain or store a program for use by an instruction execution system, device or equipment or used in combination with it. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, device or equipment, or any suitable combination thereof. More specific examples of machine-readable storage media include an electrical connection with one or more wires, a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0133] In addition, although the operations are described in a particular order, this should not be understood as requiring such operations to be performed in the particular order shown or in a continuous order or to perform all the operations shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Equally, although the above discussion includes several specific implementation details, these details should not be interpreted as limiting the scope of the present disclosure, but should be interpreted as being descriptions of features that are specific to a particular embodiment. Some features described in the context of a separate embodiment may also be combined in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments or in any suitable sub-combination.

[0134] Although the disclosure has been described in language specific to structural features and / or methodological acts, it should be understood that the disclosure defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. An electronic device comprising: at least one processor; as well as at least one memory including computer program code; The at least one memory and the computer program code are configured to, together with the at least one processor, cause the electronic device to: generating an initial sequence, the initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order, at least one parity bit of the plurality of parity bits being a copy of one of the plurality of information bits, and the number of the at least one parity bit being determined based on an expected false alarm rate and the number of other parity bits in the plurality of parity bits; generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order in the following manner: so that the at least one parity bit among the plurality of parity bits and the one information bit among the information bits are processed in different manners during polar coding of the interleaved sequence, comprising: performing an exclusive-OR output of the at least one parity bit and performing an original output of the one information bit among the information bits, or performing an original output of the at least one parity bit and performing an exclusive-OR output of the one information bit among the information bits; encoding the interleaved sequence using a polar code; and The encoded sequence is sent to a receiving device. 2 . The electronic device of claim 1 , wherein the at least one parity bit of the plurality of parity bits is a bit in a downlink control information message. The electronic device according to claim 1 , wherein the plurality of parity bits are evenly distributed in the interleaved sequence.

4. An electronic device comprising: at least one processor; as well as at least one memory including computer program code; The at least one memory and the computer program code are configured to, together with the at least one processor, cause the electronic device to: generating an initial sequence, wherein the initial sequence includes a plurality of information bits and a plurality of check bits in an initial order; combining a frozen bit sequence with the initial sequence to generate a first additional sequence; determining the number of frozen bits in the frozen bit subset between a start bit and a subsequent bit in the first additional sequence; determining whether the number of the frozen bits in the frozen bit subset exceeds a threshold number; If it is determined that the number of the frozen bits in the frozen bit subset exceeds a threshold number, inserting at least one dummy bit into the initial sequence, the value of each dummy bit being known to a receiving device; generating an interleaved sequence of the plurality of information bits, the plurality of parity bits, and the at least one dummy bit by changing the initial order in such a manner that the at least one dummy bit is arranged before the plurality of information bits and the plurality of parity bits; Encoding the interleaved sequence using a polar code; as well as The encoded sequence is sent to the receiving device. The electronic device of claim 4 , wherein the at least one dummy bit is determined based on an identification of the receiving device.

6. A communication method, comprising: generating an initial sequence, the initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order, at least one parity bit of the plurality of parity bits being a copy of one of the plurality of information bits, and the number of the at least one parity bit being determined based on an expected false alarm rate and the number of other parity bits in the plurality of parity bits; generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order in the following manner: so that the at least one parity bit among the plurality of parity bits and the one information bit among the information bits are processed in different manners during polar coding of the interleaved sequence, comprising: performing an exclusive-OR output of the at least one parity bit and performing an original output of the one information bit among the information bits, or performing an original output of the at least one parity bit and performing an exclusive-OR output of the one information bit among the information bits; encoding the interleaved sequence using a polar code; and The encoded sequence is sent to a receiving device.

7. The method of claim 6, wherein the at least one parity bit of the plurality of parity bits is a bit in a downlink control information message. The method according to claim 6 , wherein the plurality of parity bits are evenly distributed in the interleaved sequence.

9. A communication method, comprising: generating an initial sequence, wherein the initial sequence includes a plurality of information bits and a plurality of check bits in an initial order; combining a frozen bit sequence with the initial sequence to generate a first additional sequence; determining the number of frozen bits in the frozen bit subset between a start bit and a subsequent bit in the first additional sequence; determining whether the number of the frozen bits in the frozen bit subset exceeds a threshold number; If it is determined that the number of the frozen bits in the frozen bit subset exceeds a threshold number, inserting at least one dummy bit into the initial sequence, the value of each dummy bit being known to a receiving device; generating an interleaved sequence of the plurality of information bits, the plurality of parity bits, and the at least one dummy bit by changing the initial order in such a manner that the at least one dummy bit is arranged before the plurality of information bits and the plurality of parity bits; Encoding the interleaved sequence using a polar code; as well as The encoded sequence is sent to the receiving device.

10. The method of claim 9, wherein the at least one dummy bit is determined based on an identification of the receiving device.

11. A computer-readable medium having instructions stored thereon, which, when executed on at least one processor of a device, cause the device to at least perform the following operations: generating an initial sequence, the initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order, at least one parity bit of the plurality of parity bits being a copy of one of the plurality of information bits, and the number of the at least one parity bit being determined based on an expected false alarm rate and the number of other parity bits in the plurality of parity bits; generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order in the following manner: so that the at least one parity bit among the plurality of parity bits and the one information bit among the information bits are processed in different manners during polar coding of the interleaved sequence, comprising: performing an exclusive-OR output of the at least one parity bit and performing an original output of the one information bit among the information bits, or performing an original output of the at least one parity bit and performing an exclusive-OR output of the one information bit among the information bits; encoding the interleaved sequence using a polar code; and The encoded sequence is sent to a receiving device.

12. A computer-readable medium having stored thereon instructions, which, when executed on at least one processor of a device, cause the device to at least perform the following operations: generating an initial sequence, wherein the initial sequence includes a plurality of information bits and a plurality of check bits in an initial order; combining a frozen bit sequence with the initial sequence to generate a first additional sequence; determining the number of frozen bits in the frozen bit subset between a start bit and a subsequent bit in the first additional sequence; determining whether the number of the frozen bits in the frozen bit subset exceeds a threshold number; If it is determined that the number of the frozen bits in the frozen bit subset exceeds a threshold number, inserting at least one dummy bit into the initial sequence, the value of each dummy bit being known to a receiving device; generating an interleaved sequence of the plurality of information bits, the plurality of parity bits, and the at least one dummy bit by changing the initial order in such a manner that the at least one dummy bit is arranged before the plurality of information bits and the plurality of parity bits; Encoding the interleaved sequence using a polar code; as well as The encoded sequence is sent to a receiving device.

13. A communication device comprising: a component for generating an initial sequence, the initial sequence comprising a plurality of information bits and a plurality of parity bits in an initial order, at least one parity bit of the plurality of parity bits being a copy of one of the plurality of information bits, and a number of the at least one parity bit being determined based on an expected false alarm rate and a number of other parity bits of the plurality of parity bits; means for generating an interleaved sequence of the plurality of information bits and the plurality of parity bits by changing the initial order in the following manner: so that the at least one parity bit among the plurality of parity bits and the one information bit among the information bits are processed in different manners during polar coding of the interleaved sequence, comprising: performing an exclusive-OR output of the at least one parity bit and performing an original output of the one information bit among the information bits, or performing an original output of the at least one parity bit and performing an exclusive-OR output of the one information bit among the information bits; means for encoding the interleaved sequence using a polar code; and Means for transmitting the encoded sequence to a receiving device.

14. The apparatus of claim 13, wherein the at least one parity bit of the plurality of parity bits is a bit in a downlink control information message. The apparatus according to claim 13 , wherein the plurality of parity bits are evenly distributed in the interleaved sequence.

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