Semiconductor structure and method of manufacturing the same

Abstract

The semiconductor structure and the manufacturing method thereof provided by the present disclosure can effectively control the depth / degree of the bonding interface recess in the CMP process by setting the bonding pad of the same size on the different size pads and then performing the CMP process, so as to avoid the electrical failure phenomenon as much as possible.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor structures and their manufacturing methods. Background Technology

[0002] Bonding technology is a crucial foundation of 3D integration technology. For example, hybrid bonding can simultaneously achieve wafer bonding and electrical connections between wafers, reducing post-bonding electrical connection processes, offering high bonding efficiency, and meeting the requirements of high-density I / O (Input / Output), high electrical performance, and mixed matching of different sizes. In actual semiconductor structure design, small-sized I / O pads are primarily used for signal transmission, but power and ground still require large-sized I / O pads. Therefore, the bonding interface contains I / O pads of different sizes. Under these conditions, in the CMP process to planarize the bonding interface surface, large-sized I / O pads have a larger depth of concavity (Cu dish), while small-sized I / O pads have a smaller depth of concavity. The varying degrees of concavity at the bonding interface affect the electrical properties of the bonding joint, and the reduced contact area of ​​large-sized I / O pads may lead to electrical failures. Summary of the Invention

[0003] This disclosure provides semiconductor structures and methods for manufacturing them.

[0004] In a first aspect, this disclosure provides a semiconductor structure comprising:

[0005] A first semiconductor structure, including at least one first pad;

[0006] A second semiconductor structure, wherein the first semiconductor structure is disposed on the second semiconductor structure, the second semiconductor structure includes at least one second pad and at least one bonding pad of the same size, the bonding pad is disposed between the first pad and the second pad, the bonding pad is electrically connected to the second pad, the bonding pad is bonded to the first pad, and the second pad includes a first-size pad and a second-size pad, wherein the first size is smaller than the second size.

[0007] In some alternative embodiments, the second semiconductor structure further includes:

[0008] A bonding dielectric layer, wherein the upper surface of the bonding dielectric layer is coplanar with the upper surface of the bonding pad.

[0009] In some alternative embodiments, a space is provided between the bonding pad and the first pad, the width of which is smaller than the width of the bonding pad.

[0010] In some alternative embodiments, the side and bottom surfaces of the bonding pad are provided with a first seed layer.

[0011] In a second aspect, this disclosure provides a semiconductor structure comprising:

[0012] A first semiconductor structure, including at least one first pad;

[0013] A second semiconductor structure, wherein the first semiconductor structure is disposed on the second semiconductor structure, the second semiconductor structure includes at least one second pad and at least one bonding pad, the bonding pad is disposed between the first pad and the second pad, the bonding pad is electrically connected to the second pad, and the bonding pad is bonded to the first pad;

[0014] A via extends from the first semiconductor structure to the first pad, the via covering the second pad and the bonding pad.

[0015] In some alternative embodiments, the second semiconductor structure further includes:

[0016] A bonding dielectric layer, wherein the upper surface of the bonding dielectric layer is coplanar with the upper surface of the bonding pad.

[0017] In some alternative embodiments, the side and bottom surfaces of the bonding pad are provided with a first seed layer.

[0018] In some alternative embodiments, the side and bottom surfaces of the via are provided with a second seed layer.

[0019] In some alternative embodiments, a space is provided between the bonding pad and the first pad, the width of which is smaller than the width of the bonding pad.

[0020] Thirdly, this disclosure provides a method for manufacturing a semiconductor structure, the method comprising: providing a second electronic component having at least one second pad, the second pad including a first-sized pad and a second-sized pad, the first size being different from the second size;

[0021] At least one bonding pad of the same size is formed on the first electronic component, and the bonding pad is electrically connected to the second pad. The surface of the bonding pad is chemically and mechanically polished to obtain a second semiconductor structure.

[0022] A first semiconductor structure having at least one first pad is provided;

[0023] The first semiconductor structure is disposed on the second semiconductor structure, and the bonding pad is bonded to the first pad.

[0024] Fourthly, this disclosure provides a method for manufacturing a semiconductor structure, the method comprising:

[0025] A second electronic component is provided having at least one second pad, the second pad comprising a first-sized pad and a second-sized pad, the first size being smaller than the second size;

[0026] At least one bonding pad of the same size is formed on the first electronic component, and the bonding pad is electrically connected to the second pad. The surface of the bonding pad is chemically and mechanically polished to obtain a second semiconductor structure.

[0027] A first semiconductor structure having at least one first pad is provided;

[0028] The first semiconductor structure is disposed on the second semiconductor structure, and the bonding pad is bonded to the first pad;

[0029] A via is fabricated extending from the first semiconductor structure to the first pad, the via having a size larger than that of the first pad.

[0030] To address the technical problem that different-depth depressions occur on I / O pads of different sizes during the surface planarization CMP process, and that varying degrees of depression at the bonding interface can affect the electrical properties of the bonding, with larger I / O pads resulting in smaller contact areas and potentially electrical failures, the semiconductor structure and manufacturing method disclosed herein provide a solution. By setting bonding pads of the same size on pads of different sizes before performing the CMP process, the size of the bonding pads can be smaller than the size of the largest pad among the different sizes. This effectively controls the depth / degree of depression at the bonding interface during the CMP process, thereby minimizing the occurrence of electrical failures. Attached Figure Description

[0031] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0032] Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0033] Figure 2 This is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure;

[0034] Figures 3A to 3E This is a schematic diagram of the structure in the first manufacturing process of the semiconductor structure according to the present disclosure;

[0035] Figures 4A to 4C This is a schematic diagram of the second manufacturing process of the semiconductor structure according to the present disclosure.

[0036] Symbol explanation:

[0037] 1-First semiconductor structure, 11-First pad, 12-First dielectric layer, 13-First electronic component, 2-Second semiconductor structure, 21-Bonding pad, 22-Second pad, 221-First dimensional pad, 222-Second dimensional pad, 23-Bonding dielectric layer, 24-Space, 25-First seed layer, 26-Second dielectric layer, 27-Second electronic component, 3-Through hole, 31-Through hole opening, 4-Second seed layer, 5-External electrical connector, 51-Conductive pad, 6-Photoresist layer. Detailed Implementation

[0038] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0039] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0040] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified.

[0041] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. Figure 1 As shown, the semiconductor structure includes a first semiconductor structure 1 and a second semiconductor structure 2. The first semiconductor structure 1 may be disposed on the second semiconductor structure 2.

[0042] In this embodiment, the first semiconductor structure 1 may include at least one first pad 11. The second semiconductor structure 2 may include at least one second pad 22 and at least one bonding pad 21 of the same size. The bonding pad 21 may be disposed between the first pad 11 and the second pad 22. The bonding pad 21 may be electrically connected to the second pad 22. The bonding pad 21 may be bonded to the first pad 11.

[0043] In this embodiment, the side and bottom surfaces of the bonding pad 21 are provided with a first seed layer 25. The first seed layer 25 may include a titanium (Ti) layer and a copper (Cu) layer disposed from top to bottom. During the manufacturing process, the first seed layer 25 can provide conductivity to the electroplated bonding pad 21 to facilitate electroplating.

[0044] In this embodiment, the second semiconductor structure 2 may include a bonding dielectric layer 23. The upper surface of the bonding dielectric layer 23 may be coplanar with the upper surface of the bonding pad 21. During the fabrication process, the bonding dielectric layer 23 and the bonding pad 21 may serve as a bonding interface.

[0045] In this embodiment, a space 24 may be provided between the bonding pad 21 and the first pad 11. The width of the space 24 may be smaller than the width of the bonding pad 21. During the CMP process, a depression is formed on the surface of the bonding pad 21, that is, a space 24 appears between the bonding pad 21 and the first pad 11.

[0046] In this embodiment, the second pad 22 may include a first-size pad 221 and a second-size pad 222. The first size may be smaller than the second size. The first-size pad 221 may be an I / O pad for connecting signal transmission. The second-size pad 222 may be an I / O pad for connecting power or ground.

[0047] In this embodiment, the size of the bonding pad 21 can be larger than that of the first size pad 221. This requires adjusting the pitch between the second pads 22 to avoid affecting the electrical properties.

[0048] In this embodiment, the size of the bonding pad 21 can be smaller than that of the second-size pad 222. Using the bonding pad 21 as the bonding interface for CMP processing, compared to performing CMP processing directly on the second-size pad 222, can effectively reduce the depth of the bonding interface and increase the contact area.

[0049] In the scenario described above where the size of the bonding pad 21 can be smaller than that of the second-sized pad 222, the smaller size of the bonding pad 21 reduces the pad size, leading to an increase in resistance. Please refer to... Figure 2 , Figure 2It is shown that by providing a via 3 on the second-sized pad 222, the size of the via 3 can be larger than the size of the bonding pad 21, so as to increase the conductive area and reduce the resistance.

[0050] like Figure 2 As shown, the semiconductor structure includes a first semiconductor structure 1, a second semiconductor structure 2, and a via 3. The first semiconductor structure 1 may be disposed on the second semiconductor structure 2. The first semiconductor structure 1 may include at least one first pad 11. The second semiconductor structure 2 may include at least one second pad 22 and at least one bonding pad 21. The bonding pad 21 may be disposed between the first pad 11 and the second pad 22. The bonding pad 21 may be electrically connected to the second pad 22. The bonding pad 21 may be bonded to the first pad 11. The upper surface of the bonding dielectric layer 23 is coplanar with the upper surface of the bonding pad 21. A space 24 may be provided between the bonding pad 21 and the first pad 11. The width of the space 24 may be smaller than the width of the bonding pad 21.

[0051] In this embodiment, the via 3 can extend from the first semiconductor structure 1 to the first pad 11. The via 3 can cover the second pad 22 and the bonding pad 21. The size of the via 3 can be larger than the size of the bonding pad 21 to increase the conductive area and reduce the resistance.

[0052] In this embodiment, the side and bottom surfaces of the bonding pad 21 may be provided with a first seed layer 25. The side and bottom surfaces of the via 3 are provided with a second seed layer 4. During the manufacturing process, the first seed layer 25 can provide conductivity to the electroplated bonding pad 21 to facilitate electroplating. The second seed layer 4 can provide conductivity to the electroplated via 3 to facilitate electroplating. The second seed layer 4 may include a titanium layer and a copper layer disposed from top to bottom.

[0053] The semiconductor structure disclosed herein utilizes a CMP process where bonding pads 21 of the same size are placed on the second pad 22. The size of the bonding pads 21 can be smaller than that of the second-sized pads 222, effectively controlling the depth / degree of bonding interface depression during the CMP process to minimize electrical failure. Furthermore, vias 3 can be placed on the second-sized pads 222, with the vias 3 having a larger size than the bonding pads 21, to increase the conductive area and reduce resistance.

[0054] Please refer to Figures 3A to 3E , Figures 3A to 3E It is based on Figure 1 The diagram shows a schematic representation of the semiconductor structure during its manufacturing process.

[0055] Please refer to Figure 3AA second dielectric layer 26 is disposed on the second electronic component 27, the second dielectric layer 26 is patterned, and at least one second pad 22 is electroplated in the patterned second dielectric layer 26. The second pad 22 includes a first-sized pad 221 and a second-sized pad 222, the first size being different from the second size.

[0056] Please refer to Figure 3B A bonding dielectric layer 23 is disposed on the second pad 22, the bonding dielectric layer 23 is patterned, and a first seed layer 25 and at least one bonding pad 21 of the same size are electroplated in the patterned bonding dielectric layer 23.

[0057] Please refer to Figure 3C The surface of the bonding pad 21 is chemically and mechanically polished to obtain the second semiconductor structure 2.

[0058] Please refer to Figure 3D A first dielectric layer 12 is disposed on the first electronic component 13, the first dielectric layer 12 is patterned, and a first pad 11 is electroplated in the patterned first dielectric layer 12 to obtain a first semiconductor structure 1.

[0059] Please refer to Figure 3E The first semiconductor structure 1 is flipped onto the second semiconductor structure 2, and the first pad 11 is bonded to the bonding pad 21.

[0060] Please refer to Figures 3A to 3E as well as Figures 4A to 4C , Figures 3A to 3E as well as Figures 4A to 4C yes Figure 2 The diagram shows a schematic representation of the semiconductor structure during its manufacturing process.

[0061] Please refer to Figure 3A A second dielectric layer 26 is disposed on the second electronic component 27, the second dielectric layer 26 is patterned, and at least one second pad 22 is electroplated in the patterned second dielectric layer 26. The second pad 22 includes a first-sized pad 221 and a second-sized pad 222, the first size being different from the second size.

[0062] Please refer to Figure 3B A bonding dielectric layer 23 is disposed on the second pad 22, the bonding dielectric layer 23 is patterned, and a first seed layer 25 and at least one bonding pad 21 of the same size are electroplated in the patterned bonding dielectric layer 23.

[0063] Please refer to Figure 3C The surface of the bonding pad 21 is chemically and mechanically polished to obtain the second semiconductor structure 2.

[0064] Please refer to Figure 3DA first dielectric layer 12 is disposed on the first electronic component 13, the first dielectric layer 12 is patterned, and a first pad 11 is electroplated in the patterned first dielectric layer 12 to obtain a first semiconductor structure 1.

[0065] Please refer to Figure 3E The first semiconductor structure 1 is flipped onto the second semiconductor structure 2, and the first pad 11 is bonded to the bonding pad 21.

[0066] Please refer to Figure 4A A photoresist layer 6 is disposed on the first semiconductor structure 1.

[0067] Please refer to Figure 4B A patterned photoresist layer 6 is provided, and a via opening 31 is provided.

[0068] In this embodiment, to avoid the via fabrication process being affected by unevenly flat hole bottoms within the via opening 31, thus impacting the electrical properties of the via, the first pad 11 and bonding pad 21 can be removed after the via opening 31 is formed, preventing uneven hole bottoms. During the etching process to remove the first pad 11 and bonding pad 21, isotropic etching may result in voids at the edges of the second pad 22, creating a space between the second dielectric layer 26 and the second pad 22.

[0069] In this embodiment, after the via opening 31 is provided, without removing the first pad 11 and the bonding pad 21, if the first seed layer 25 is an easily oxidized metal (e.g., titanium), the first seed layer 25 disposed on the side surface of the bonding pad 21 is removed to avoid increasing the resistance. If the first seed layer 25 is a non-oxidized metal (e.g., tantalum), it does not need to be removed.

[0070] Please refer to Figure 4C A second seed layer 4 and conductive material are electroplated in the via opening 31 to form the via 3. The patterned photoresist layer 6 is removed, and a conductive pad 51 and an external electrical connector 5 are sequentially disposed on the via 3. The conductive pad 51 can be, for example, an under-ball metallurgy (UBM) pattern. The external electrical connector 5 can be, for example, a solder ball, a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, or a microbump.

[0071] The manufacturing method of the semiconductor packaging device in this embodiment can achieve the technical effects of the semiconductor packaging device described above, and will not be repeated here.

[0072] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual equipment due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and drawings should be considered illustrative rather than restrictive. Modifications may be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor structure, comprising: A first semiconductor structure, including at least one first pad; A second semiconductor structure is provided on the first semiconductor structure. The second semiconductor structure includes at least one second pad and at least one bonding pad of the same size. The bonding pad is disposed between the first pad and the second pad and is electrically connected to the second pad. The bonding pad is bonded to the first pad. The second pad includes a first-sized pad and a second-sized pad, where the first size is smaller than the second size. The bonding pad is larger than the first size and smaller than the second size. A space is provided between the bonding pad and the first pad, where the width of the space is smaller than the width of the bonding pad. A first seed layer is provided on the side surface and bottom surface of the bonding pad. The second semiconductor structure also includes: A bonding dielectric layer, wherein the upper surface of the bonding dielectric layer is coplanar with the upper surface of the bonding pad.

2. A semiconductor structure, comprising: A first semiconductor structure, including at least one first pad; A second semiconductor structure is provided on the first semiconductor structure. The second semiconductor structure includes at least one second pad and at least one bonding pad. The bonding pad is disposed between the first pad and the second pad and is electrically connected to the second pad. The bonding pad is bonded to the first pad. The second pad includes a first-sized pad and a second-sized pad. The first size is smaller than the second size. The size of the bonding pad is larger than the first size and smaller than the second size. A space is provided between the bonding pad and the first pad. The width of the space is smaller than the width of the bonding pad. A first seed layer is provided on the side surface and the bottom surface of the bonding pad. A via extends from the first semiconductor structure to the first pad, the via covering the second pad and the bonding pad; The second semiconductor structure also includes: A bonding dielectric layer, wherein the upper surface of the bonding dielectric layer is coplanar with the upper surface of the bonding pad.

3. A method for manufacturing a semiconductor structure, comprising: A second electronic component is provided having at least one second pad, the second pad comprising a first-sized pad and a second-sized pad, the first size being different from the second size, wherein the first size is smaller than the second size; At least one bonding pad of the same size is formed on the second electronic component, the bonding pad is electrically connected to the second pad, and the surface of the bonding pad is chemically and mechanically polished to obtain a second semiconductor structure. A bonding dielectric layer is disposed on the second pad, the bonding dielectric layer is patterned, a first seed layer and at least one bonding pad of the same size are electroplated in the patterned bonding dielectric layer, the upper surface of the bonding dielectric layer is coplanar with the upper surface of the bonding pad, the size of the bonding pad is larger than the first size, and the size of the bonding pad is smaller than the second size. A first semiconductor structure having at least one first pad is provided; The first semiconductor structure is disposed on the second semiconductor structure, and the bonding pad is bonded to the first pad. A space is provided between the bonding pad and the first pad, the width of the space being smaller than the width of the bonding pad. A first seed layer is provided on the side surface and bottom surface of the bonding pad.

4. A method for manufacturing a semiconductor structure, comprising: A second electronic component is provided having at least one second pad, the second pad comprising a first-sized pad and a second-sized pad, the first size being smaller than the second size; At least one bonding pad of the same size is formed on the second electronic component, the bonding pad is electrically connected to the second pad, and the surface of the bonding pad is chemically and mechanically polished to obtain a second semiconductor structure. A bonding dielectric layer is disposed on the second pad, the bonding dielectric layer is patterned, a first seed layer and at least one bonding pad of the same size are electroplated in the patterned bonding dielectric layer, the upper surface of the bonding dielectric layer is coplanar with the upper surface of the bonding pad, the size of the bonding pad is larger than the first size, and the size of the bonding pad is smaller than the second size. A first semiconductor structure having at least one first pad is provided; The first semiconductor structure is disposed on the second semiconductor structure, and the bonding pad is bonded to the first pad. A space is provided between the bonding pad and the first pad, the width of the space is smaller than the width of the bonding pad, and a first seed layer is provided on the side surface and bottom surface of the bonding pad. A via is fabricated extending from the first semiconductor structure to the first pad, the via having a size larger than that of the first pad.

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