Semiconductor package structure and method of manufacturing the same

Abstract

The semiconductor package structure and the manufacturing method thereof provided by the present disclosure stack the first stacked chip set and the second stacked chip set up and down through the electrical connectors (e.g. conductive pillars) and achieve electrical connection. Since the first stacked chip set and the second stacked chip set are stacked up and down, there is no gap between the side-by-side stacked chip sets in the existing stacked package structure, and there is no need to use, for example, through silicon via (TSV) or other via methods with re-distribution layers, which shortens the electrical path and reduces the overall size of the stacked package structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to semiconductor packaging structures and their manufacturing methods. Background Technology

[0002] As electronic products continue to be updated and upgraded, there is an increasing demand for storage architectures with higher digital information processing efficiency, larger storage capacity, and greater flexibility. To meet this demand, stacked packaging technology is developing rapidly.

[0003] To meet the demands for high capacity, the number of chips integrated (such as memory chips) is increasing daily. Figure 1 The existing stacked packaging structure not only increases process complexity and manufacturing cost, but also increases package size due to the necessary gap (Gap > 80µm) between existing stacked chipsets 11, and increases impedance due to longer electrical paths. Furthermore, it requires a thicker substrate 12 (Thickness > 0.2mm) and longer wires to achieve inter-chip signal transmission, and the existing stacked packaging structure is difficult to reduce overall size, hindering the miniaturization of semiconductor packaging. Summary of the Invention

[0004] This disclosure provides a semiconductor packaging structure and a method for manufacturing the same.

[0005] In a first aspect, this disclosure provides a semiconductor packaging structure, the semiconductor packaging structure comprising:

[0006] A redistribution layer having opposing first and second surfaces;

[0007] A first stacked chip group and a second stacked chip group are disposed on the redistribution layer. The first stacked chip group includes at least two first chips stacked in a staggered manner, and the second stacked chip group includes at least two second chips stacked in a staggered manner. Adjacent first chips are bonded together with an adhesive layer, and adjacent second chips are bonded together with an adhesive layer. The second stacked chip group is stacked on top of the first stacked chip group and electrically connected.

[0008] In some alternative implementations, conductive pillars are provided between the first stacked chipset and the second stacked chipset for electrical connection.

[0009] In some alternative embodiments, the active surface of the first chip is provided with bumps, and an bonding layer is provided between the conductive post and the bumps.

[0010] In some alternative implementations, the bonding layer is solder.

[0011] In some embodiments, the active surface of the first chip is provided with a first bonding pad and a second bonding pad, the first bonding pad and the second bonding pad are respectively disposed on two sides of the bump.

[0012] In some embodiments, a wire is disposed between the first bonding pad of a first chip and the second bonding pad of an adjacent first chip to electrically connect.

[0013] In some embodiments, a wire is disposed between the first bonding pad of a first chip and the second bonding pad of an adjacent first chip to electrically connect.

[0014] In some embodiments, a wire or a conductive pillar is disposed between the first stack of chips and the redistribution layer to electrically connect.

[0015] In some embodiments, the semiconductor package structure further comprises:

[0016] A mold encapsulation layer is disposed on the first surface, the mold encapsulation layer encapsulates the first stack of chips and the second stack of chips.

[0017] In some embodiments, the semiconductor package structure further comprises:

[0018] An external electrical connector is disposed on the second surface.

[0019] In some embodiments, the semiconductor package structure further comprises:

[0020] A bottom filler encapsulates the connection between the adjacent first chips and the connection between the first stack of chips and the second stack of chips.

[0021] In some embodiments, the distance between the first / second bonding pad and the bump is between 15 microns and 60 microns.

[0022] In some embodiments, the diameter of the bump or the conductive pillar is between 10 microns and 30 microns.

[0023] In some embodiments, the diameter of the wire is between 10 microns and 100 microns.

[0024] In some embodiments, the first chip and / or the second chip is a memory chip.

[0025] In a second aspect, the disclosure provides a method for manufacturing a semiconductor package structure, the method comprising:

[0026] providing a redistribution layer;

[0027] stacking at least two first chips on the rewiring layer in a staggered manner, and disposing an adhesive layer between adjacent first chips to form a first stacked chip group;

[0028] disposing a wire between adjacent first chips for electrical connection;

[0029] stacking at least two second chips in a staggered manner, and disposing an adhesive layer between adjacent second chips to form a second stacked chip group;

[0030] disposing a conductive pillar and a bonding layer on each second chip;

[0031] turning over the second stacked chip group and stacking it on the first stacked chip group, the first stacked chip group and the second stacked chip group being electrically connected through the conductive pillar;

[0032] forming a mold encapsulation layer covering the first stacked chip group and the second stacked chip group.

[0033] To solve the technical problem of the existing stacked packaging structure that the length of the electrical path is increased and the overall size of the packaging structure is difficult to reduce, the semiconductor packaging structure and the manufacturing method thereof provided by the present disclosure are provided. The first stacked chip group and the second stacked chip group are stacked up and down through the electrical connector (such as the conductive pillar) and are electrically connected. Since the first stacked chip group and the second stacked chip group are stacked up and down, there is no gap between the stacked chip groups in the existing stacked packaging structure, and there is no need to use, for example, a through silicon via (TSV) or other via method in combination with a rewiring layer, thereby shortening the electrical path and reducing the overall size of the stacked packaging structure. BRIEF DESCRIPTION OF DRAWINGS

[0034] Other features, objects, and advantages of the present disclosure will become more apparent from the following detailed description of non-limiting embodiments made with reference to the following drawings:

[0035] Figure 1 is a stacked packaging structure in the prior art;

[0036] Figures 2-10 is a first structure schematic diagram to a ninth structure schematic diagram of one embodiment of the semiconductor packaging structure according to the present disclosure;

[0037] Figures 10A to 10H is a structure schematic diagram in the manufacturing process of the semiconductor packaging structure according to the present disclosure.

[0038] SYMBOL DESCRIPTION:

[0039] 1 - redistribution layer, 2 - first stacked chip group, 21 - first chip, 211 - bump, 212 - first bonding pad, 213 - second bonding pad, 22 - active surface, 3 - second stacked chip group, 31 - second chip, 4 - adhesive layer, 5 - conductive pillar, 6 - bonding layer, 7 - mold encapsulation layer, 8 - external electrical connection, 9 - underfill material, 10 - wire, 11 - existing stacked chip group, 12 - existing substrate. DETAILED DESCRIPTION

[0040] The specific embodiments of the present disclosure will be described below with reference to the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems solved by the present disclosure and the technical effects produced by the present disclosure through the content recorded in the present specification. It should be understood that the specific embodiments described herein are only used to explain the related application, and not to limit the application. In addition, only the parts related to the application are shown in the drawings for ease of description.

[0041] It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the specification are only used to cooperate with the content recorded in the specification for the understanding and reading of those skilled in the art, and do not define the limiting conditions for the implementation of the present disclosure, so they do not have technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects produced by the present disclosure and the purposes achieved, should still fall within the scope of the technical content disclosed by the present disclosure. At the same time, the terms such as "upper", "first", "second" and "one" used in the specification are only for the convenience of clear description, and not to limit the scope of the implementation of the present disclosure. The change or adjustment of the relative relationship without substantial change of the technical content should also be considered as the implementation of the present disclosure.

[0042] In addition, the embodiments in the present disclosure and the features in the embodiments can be combined with each other without conflict. The present disclosure will be described in detail below with reference to the drawings and embodiments. Figures 2-10 The present disclosure will be described in detail below with reference to the drawings and embodiments.

[0043] Figures 2-10 is the first structure schematic diagram to the ninth structure schematic diagram of one embodiment of the semiconductor package structure according to the present disclosure.

[0044] Figure 2 The first structure schematic diagram of the semiconductor package structure of the present disclosure is shown. As shown in FIG. 1, the semiconductor package structure 100 includes a first stacked chip group 2, a second stacked chip group 3, an adhesive layer 4, a conductive pillar 5, a bonding layer 6, a mold encapsulation layer 7, an external electrical connection 8, an underfill material 9, a wire 10, an existing stacked chip group 11 and an existing substrate 12. Figure 2As shown, the semiconductor package structure includes a redistribution layer 1, a first stacked chip set 2, and a second stacked chip set 3. The first stacked chip set 2 and the second stacked chip set 3 can be disposed on the redistribution layer 1. The first stacked chip set 2 can include at least two first chips 21 stacked in a staggered manner. An adhesive layer 4 can be disposed between adjacent first chips 21. A wire 10 can be disposed between adjacent first chips 21 to electrically connect the first chips 21. The wire 10 can have a diameter of 10 microns to 100 microns. The second stacked chip set 3 can include at least two second chips 31 stacked in a staggered manner. An adhesive layer 4 can be disposed between adjacent second chips 31. The adhesive layer 4 can be a liquid or a film of an organic material, such as a non-conductive paste (NCP), a non-conductive film (NCF), an anisotropic conductive paste (ACP), an anisotropic conductive film (ACF), polyimide (PI), epoxy, resin, PP (PrePreg, a semi-cured resin or a semi-cured sheet), ABF (Ajinomoto Build-up Film), glue, or the like. The first chips 21 and / or the second chips 31 can be memory chips.

[0045] In the present embodiment, the redistribution layer 1 can include a conductive material and a dielectric material. The dielectric material can include an organic material, such as polyamide (PA), polyimide (PI), epoxy, poly-p-phenylenebenzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, a semi-cured resin or a semi-cured sheet), ABF (Ajinomoto Build-up Film), or the like, and / or an inorganic material, such as silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, or the like. The conductive material can include a seed layer and a metal layer. Here, the seed layer can be titanium (Ti), tungsten (W), nickel (Ni), or the like, and the metal layer can be gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

[0046] In the present embodiment, the second stacked chip set 3 can be stacked on and electrically connected with the first stacked chip set 2. Specifically, the first stacked chip set 2 and the second stacked chip set 3 can be electrically connected by conductive pillars 5. The active surface 22 of the first chip 21 can be provided with bumps 211. The diameter of the bumps 211 or the conductive pillars 5 can be between 10 microns and 30 microns. The conductive pillars 5 can include gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof. The conductive pillars 5 and the bumps 211 can be provided with a bonding layer 6 therebetween. The bonding layer 6 can be solder. The active surface 22 of the first chip 21 can be provided with a first bonding pad 212 and a second bonding pad 213. The first bonding pad 212 and the second bonding pad 213 can be provided on both sides of the bumps 211, respectively. The distance between the first bonding pad 212 / second bonding pad 213 and the bumps 211 can be between 15 microns and 60 microns. The first bonding pad 212 of one of the first chips 21 and the second bonding pad 213 of another of the first chips 21 can be electrically connected by a wire 10.

[0047] In the present embodiment, Figure 2 The semiconductor package structure shown can further include a molding layer 7 and external electrical connectors 8. The molding layer 7 can cover the first stacked chip set 2 and the second stacked chip set 3. The molding layer 7 can be formed of various molding compounds. For example, the molding compounds can include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc. The external electrical connectors 8 can be, for example, solder balls, C4 bumps, micro bumps, etc.

[0048] Figure 3 A second structural schematic diagram of the semiconductor package structure of the present disclosure is shown. As shown in FIG. 2, the semiconductor package structure can include a first stacked chip set 2 and a second stacked chip set 3. The first stacked chip set 2 and the second stacked chip set 3 can be electrically connected by conductive pillars 5. Figure 3 The first chip 21 and the redistribution layer 1 in the semiconductor package structure shown can be electrically connected by conductive pillars 5.

[0049] Figure 4 A third structural schematic diagram of the semiconductor package structure of the present disclosure is shown. As shown in FIG. 3, the semiconductor package structure can include a first stacked chip set 2 and a second stacked chip set 3. The first stacked chip set 2 and the second stacked chip set 3 can be electrically connected by conductive pillars 5. Figure 4 As shown in FIG. 3, the semiconductor package structure shown can further include a first redistribution layer 1 and a second redistribution layer 2. The first redistribution layer 1 and the second redistribution layer 2 can be electrically connected by conductive pillars 5. Figure 2 The difference between the semiconductor package structure shown in FIG. 3 and the semiconductor package structure shown in FIG. 2 is that, Figure 4The semiconductor package structure shown can also include a bottom filler 9. The bottom filler 9 can coat the joints between adjacent first chips 21 and the joints between the first stacked chip group 2 and the second stacked chip group 3. The bottom filler 9 can be, for example, a capillary underfill (CUF), a molded underfill (MUF), a non-conductive paste (NCP), etc. The bottom filler 9 can fill the gaps for the purpose of reinforcement and protection.

[0050] Figure 5 A fourth structural schematic diagram of the semiconductor package structure of the present disclosure is shown. Figure 6 A fifth structural schematic diagram of the semiconductor package structure of the present disclosure is shown. Figure 5 and Figure 6 A wire 10 can be provided between the first chip 21 and the redistribution layer 1 in the semiconductor package structure shown for electrical connection.

[0051] Figure 7 A sixth structural schematic diagram of the semiconductor package structure of the present disclosure is shown. A conductive pillar 5 can be provided between the second chip 31 and the redistribution layer 1 for electrical connection.

[0052] Figure 8 A seventh structural schematic diagram of the semiconductor package structure of the present disclosure is shown. Figure 9 An eighth structural schematic diagram of the semiconductor package structure of the present disclosure is shown. As Figure 8 The horizontal distance between chips at the same vertical height in the left stack structure A and the right stack structure B in the semiconductor package structure shown decreases from top to bottom. As Figure 9 The horizontal distance between chips at the same vertical height in the left stack structure A and the right stack structure B in the semiconductor package structure shown increases from top to bottom.

[0053] Figure 10 A ninth structural schematic diagram of the semiconductor package structure of the present disclosure is shown. As Figure 10 The top view shown in (a) of the first chip 21 and the adhesive layer 4 on the second chip 31 shows that the first chip 21 and the second chip 31 are stacked vertically, and the arrangement is in a single row. As Figure 10 The top view shown in (b) shows that the first chip 21 and the second chip 31 are stacked vertically, and the arrangement is in multiple rows. As Figure 10 The top view shown in (c) shows that the first chip 21 and the second chip 31 are stacked vertically, and the arrangement is in a radial arrangement.

[0054] Figures 10A to 10H A schematic diagram of the manufacturing process of the semiconductor packaging structure disclosed herein is shown.

[0055] like Figure 10A As shown, a redistribution layer 1 is formed. Specifically, the redistribution layer 1 can be formed using currently known or future-developed redistribution layer 1 techniques, which are not specifically limited in this disclosure. For example, redistribution layer 1 can be formed using processes including but not limited to photolithography, physical vapor deposition, electroplating, electroless plating, and printing.

[0056] like Figure 10B As shown, at least two first chips 21 can be stacked sequentially in a staggered manner on the redistribution layer 1 using the bonding head of the bonding device. An adhesive layer 4 is provided between adjacent first chips 21.

[0057] like Figure 10C As shown, wires 10 are provided between adjacent first chips 21 for electrical connection by wire bonding.

[0058] like Figure 10D As shown, the first stacked chipset 2 is obtained.

[0059] like Figure 10E As shown, at least two second chips 31 are stacked in a staggered manner, and an adhesive layer 4 is provided between adjacent second chips 31 to form a second stacked chip group 3.

[0060] like Figure 10F As shown, conductive pillars 5 and bonding layers 6 are provided on each second chip 31;

[0061] like Figure 10G As shown, the second stacked chipset 3 can be flipped and stacked on the first stacked chipset 2 through the bonding head of the bonding device, and the first stacked chipset 2 and the second stacked chipset 3 can be electrically connected through the conductive post 5.

[0062] like Figure 10H As shown, a molding layer 7 is formed to cover the first stacked chipset 2 and the second stacked chipset 3.

[0063] The semiconductor package structure and the manufacturing method thereof provided by the present disclosure, the first stacked chip set 2 and the second stacked chip set 3 are stacked up and down by the electrical connection (such as the conductive column 5) and realize the electrical connection. Since the first stacked chip set 2 and the second stacked chip set 3 are stacked up and down, there is no gap between the parallel stacked stacked chip sets in the existing stacked package structure, and there is no need to use, for example, a through silicon via (TSV) or other via method and cooperate with a redistribution layer 1, which shortens the electrical path and reduces the overall size of the stacked package structure.

[0064] Although the present disclosure has been described and illustrated with reference to specific embodiments, these are intended only to illustrate the present disclosure and are not limiting. Various changes and modifications can be apparent to those skilled in the art and can be made within the true spirit and scope of the present disclosure as defined by the appended claims. The drawings are not necessarily to scale. There can be differences between the technical reproduction and actual implementation in the present disclosure due to variables in the manufacturing process, etc. There can be other embodiments of the present disclosure that are not specifically illustrated. The specification and drawings should be considered illustrative rather than restrictive. Modifications can be made to adapt a particular situation, material, composition of matter, method or process to the purpose, spirit and scope of the present disclosure. All such modifications are within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or re-ordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, the order and grouping of operations are not limiting to the present disclosure unless specifically indicated herein.

Claims

1. A semiconductor package structure, comprising: A redistribution layer having opposing first and second surfaces; A first stacked chipset and a second stacked chipset are disposed on the redistribution layer. The first stacked chipset includes at least two first chips stacked in a staggered manner, and the second stacked chipset includes at least two second chips stacked in a staggered manner. Adjacent first chips are bonded together with an adhesive layer, and adjacent second chips are bonded together with an adhesive layer. The second stacked chipset is stacked vertically on top of the first stacked chipset and electrically connected. The second stacked chipset is flipped and stacked on top of the first stacked chipset. Conductive pillars are provided between the first stacked chipset and the second stacked chipset for electrical connection. The active surface of the first chip has bumps. A bonding layer is provided between the conductive pillars and the bumps. The active surface of the first chip has first bonding pads and second bonding pads. The first bonding pads and the second bonding pads are respectively disposed on both sides of the bumps. A wire is provided for electrical connection between the first bonding pads of adjacent first chips and the second bonding pads of another first chip.

2. The semiconductor packaging structure according to claim 1, wherein, The first stacked chipset and the redistribution layer are electrically connected by wires or conductive pillars.

3. The semiconductor packaging structure according to claim 1, wherein, The semiconductor packaging structure further includes: A molding layer is disposed on the first surface, the molding layer covering the first stacked chipset and the second stacked chipset.

4. The semiconductor packaging structure according to claim 1, wherein, The semiconductor packaging structure further includes: The bottom filler material covers the connection between the adjacent first chips and the connection between the first stacked chipset and the second stacked chipset.

5. The semiconductor packaging structure according to claim 1, wherein, The first chip and / or the second chip are memory chips.

6. A method for manufacturing a semiconductor package structure, comprising: Provide a rewiring layer; At least two first chips are stacked in a staggered manner on the redistribution layer, and an adhesive layer is provided between adjacent first chips to form a first stacked chip group; A wire is provided between adjacent first chips for electrical connection; At least two second chips are stacked in a staggered manner, and an adhesive layer is provided between adjacent second chips to form a second stacked chip group; Conductive pillars and bonding layers are sequentially disposed on each of the second chips; The second stacked chip group is flipped and stacked on top of the first stacked chip group, and the first stacked chip group and the second stacked chip group are electrically connected through the conductive pillars; A molding layer is formed to cover the first stacked chipset and the second stacked chipset.

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