Range-Based Explicit Dataflow Processor and Associated Computer-Readable Medium and Method

Abstract

Exemplary range-based explicit data flow processor and related computer-readable media and methods. The range-based explicit data flow processor is configured to support execution of producer instructions, where the producer instructions are encoded using explicit naming of consumer instructions that are intended to consume the values produced by the producer instructions. The range-based explicit data flow processor is configured to, as a result of processing the producer instructions, provide available produced values as inputs to the explicitly named consumer instructions. The range-based explicit data flow processor supports execution of producer instructions that explicitly name consumer instructions based on using the producer instructions as a relative reference point from the producer instructions. This range-based explicit naming architecture does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions, and thus is not limited to explicit naming of consumer instructions only within the same instruction block as the producer instructions.

Description

Technical Field

[0001] The technology of the present disclosure relates to the execution of instructions by a central processing unit (CPU) processor, and more particularly to a CPU processor that supports explicit data flow communication of production values from producer instructions to (multiple) dependent consumer instructions. Background Art

[0002] Microprocessors (also referred to as "processors") perform computational tasks for various applications. Conventional microprocessors include a central processing unit (CPU) that includes one or more processor cores (also referred to as "CPU cores") that execute software instructions. The software instructions direct the CPU to perform operations based on data. The CPU performs operations according to the instructions to generate a result, i.e., a production value. The production value can then be provided as an output to an I / O device or made available (i.e., communicated) as an input value to another consumer instruction executed by the CPU. Thus, the consumer instruction depends on the production value that is generated by a "producer" instruction and is used as an input value for the consumer instruction to be executed. These producer and consumer instructions are also collectively referred to as "dependent instructions".

[0003] Traditionally, communication between dependent instructions has been done implicitly using the general-purpose register (GPR) namespace as a rendezvous point. This communication is referred to as "implicit" because the producer instruction that produces (i.e., writes) a value into the GPR does not know which (multiple) consumer instructions will consume (i.e., read) the production value. This communication method may have limitations. As one limitation, the GPR namespace has a limited size because the names of the consumer instructions are encoded as instructions of a finite length. Moreover, the number of GPRs is less than the number of values generated by the computation, such that multiple production values must be communicated using the same name of the producer instruction - i.e., alias usage occurs within the producer instruction set and the consumer instruction set. Further, since the producer instruction has no reference to the consumer instruction for its production value, there is no direct way to notify the consumer instruction that the value it will consume has been produced. These problems have been addressed in different ways in modern CPU implementations, but the costs and trade-offs associated with the solutions vary.

[0004] An alternative method of communicating between dependent instructions is to explicitly name the consumer instruction, which consumes the production value in the producer instruction. This is referred to as "explicit" communication. CPUs built on the explicit communication model have already been referred to as explicit data flow graph execution (EDGE) CPUs. Explicit communication solves the problem of notifying the consumer instruction related to implicit communication of the production value. Since the producer instruction directly encodes the name of the consumer instruction in the explicit communication model, it is easy to notify the consumer when the producer instruction generates its production value to provide the input value for the consumer instruction. A problem that may still exist in explicit communication is the size allocated to encode the consumer name in the producer instruction. The number of bits allocated to encode the consumer name in the producer instruction must be sufficient to name the possible consumer instructions required based on the design. An instruction format that provides a larger bit encoding size for the consumer instruction name provides greater flexibility in the explicit naming of consumer instructions, but also consumes a larger amount of memory space for storing the instructions. Conventional EDGE processors have solved the size of the instruction name by dividing the data flow graph of the complete computation into multiple segments (sometimes referred to as instruction blocks), where explicit consumer naming is based on the start of the instruction block. EDGE processors are designed to adopt an execution model that explicitly conveys the production value to the consumer instruction within the same block local namespace, such that the maximum number of instructions in the block is determined and limited by the size of the name that can be encoded in the instruction.

[0005] Thus, while EDGE processors have the advantage of reduced complexity compared to the implicit communication model, the disadvantage of EDGE processors is that they are limited in explicitly conveying the production value to the consumer instruction within the same instruction block. Further, since the consumer name is only valid within a given instruction block, there is a problem in conveying the production value across the block boundary into the instruction block. Previous EDGE CPUs used implicit communication (via the memory namespace or the GPR namespace) to externally convey the production value across the instruction block boundary. Although for a reasonable block size, inter-block communication is less frequent than intra-block communication, the use of implicit communication weakens the advantage of explicit communication for dependent instructions. Constraining the instruction block to have a maximum size also places a burden on the programmer or compiler, who must decide which instructions are most suitable to place in each instruction block based on the communication pattern and associated cost between dependent instructions. Summary of the Invention

[0006] Exemplary aspects disclosed herein include a reach-based explicit data flow processor and associated computer-readable media and methods. The reach-based explicit data flow processor is configured to support execution of producer instructions that are explicitly named encoded with consumer instructions that are intended to consume values produced by the producer instructions. The reach-based explicit data flow processor is configured to, as a result of processing the encoded producer instructions, provide the produced values or make them available as inputs to explicitly named consumer instructions. In the exemplary aspects disclosed herein, the reach-based explicit data flow processor supports execution of producer instructions that explicitly name consumer instructions based on using the producer instruction as a reference point and naming the consumer instructions relative to that reference point. The name assigned by the producer instruction to the consumer instruction is referred to as the target distance. The maximum target distance allowed by the reach-based explicit data flow processor is referred to as the "reach" of the processor. The reach of the processor defines the maximum set of consumer instructions that can be explicitly named by the producer instructions. In this way, by way of example, such reach-based explicit naming does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions and is thus limited to explicitly naming consumer instructions only within the instruction block of the producer instruction. Thus, removing the architectural limitation of instruction blocks in the data flow processor can allow the data flow processor to be designed to support explicit data flow communication on larger computational graphs that are not limited by the instruction block size. Reach-based explicit consumer naming may also have the advantage of requiring less consumer encoding namespace ("reach namespace") because the consumer naming is relative to the location of the producer instruction rather than a fixed reference location that may more frequently be distant from the consumer instruction.

[0007] In other exemplary aspects disclosed herein, the target distance of a consumer instruction named by a producer instruction is encoded as a target distance value in the range namespace of the producer instruction. The bit size selected for the range namespace defines the maximum target distance or range of the set of consumer instructions with which the producer instruction can directly communicate explicitly. The bit size of the range namespace in the detailed implementation is a design decision determined by the desired trade-off between the instruction memory size required to store a given number of instructions and the desired range namespace. If a consumer instruction is outside the range of the producer instruction, the range-based explicit data flow processor can also support the use of (one or more) intermediate consumer instructions named by the producer instruction for the indirect naming of the consumer instruction. In this regard, the (one or more) intermediate consumer instructions can name (one or more) other consumer instructions, which can name the final intended consumer instruction to provide the production value to the final intended consumer instruction. Further, if the target distance is greater than the range value and, for example, the programmer or compiler does not see the need to use intermediate consumer instructions, the range-based explicit producer / consumer communication does not preclude the ability of the range-based explicit data flow processor to support implicit producer / consumer communication.

[0008] In this regard, in one exemplary aspect, a processor is provided. The processor is configured to receive, from an instruction memory, a plurality of instructions in an instruction stream to be executed, the plurality of instructions including a plurality of producer instructions and a plurality of consumer instructions. The processor is further configured to dispatch a consumer instruction among the plurality of consumer instructions to be executed in response to at least one operand of the consumer instruction being available. The processor is further configured to execute a producer instruction among the plurality of producer instructions to generate a production value, the producer instruction being configured to include at least one explicit consumer name, each explicit consumer name including a consumer target distance value and an associated consumer operand value, the consumer target distance representing the relative instruction distance in the instruction stream from the producer instruction. The processor is further configured to determine whether the executed producer instruction includes an explicit consumer name. In response to determining that the executed producer instruction includes an explicit consumer name, the processor is further configured to write the production value of the executed producer instruction to at least one operand of the consumer instruction identified as being located at a distance from the producer instruction in the instruction stream equal to the consumer target distance value of the executed producer instruction.

[0009] In another exemplary aspect, a method is provided for explicitly naming consumers based on consumer instructions to provide a production value as input to the consumer instructions from producer instructions executed by a processor. The method includes receiving, from an instruction memory, a plurality of instructions in a stream of instructions to be executed, the plurality of instructions including a plurality of producer instructions and a plurality of consumer instructions. The method also includes executing a producer instruction of the plurality of producer instructions to generate a production value, the producer instruction being configured to include at least one explicit consumer name, each explicit consumer name including a consumer target distance value and an associated consumer operation value, the consumer target distance value representing a relative instruction distance in the instruction stream from the producer instruction. The method also includes determining whether the executed producer instruction includes an explicit consumer name. In response to determining that the executed producer instruction includes an explicit consumer name, the method also includes writing the production value of the executed producer instruction to at least one operand of a consumer instruction, the consumer instruction being identified as being located at a distance from the producer instruction in the instruction stream equal to the consumer target distance value of the executed producer instruction. The method also includes dispatching a consumer instruction of the plurality of consumer instructions to be executed in response to at least one operand of the consumer instruction being stored.

[0010] In another exemplary aspect, a non-transitory computer-readable medium having stored thereon an instruction program is provided, the instruction program including a plurality of computer-executable instructions for execution by a processor. The plurality of computer-executable instructions include: a producer instruction including an instruction type and an explicit consumer name, the explicit consumer name including a consumer target distance value and an associated consumer operation value, the consumer target distance value representing a relative instruction distance in the instruction stream from the producer instruction. The plurality of computer-executable instructions include a consumer instruction including an instruction type and an operand, the consumer instruction being located at an instruction distance from the producer instruction in the instruction program equal to the consumer target distance value of the producer instruction, and the associated consumer operation value of the producer instruction being mapped to the operand of the consumer instruction.

[0011] After reading the following detailed description of the preferred embodiments in connection with the accompanying drawings, those skilled in the art will understand the scope of the present disclosure and realize its additional aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The drawings incorporated in and forming a part of this specification illustrate various aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0013] Figure 1 is an exemplary list of computer instructions to illustrate the possibility of range-based explicit consumer naming of (multiple) consumer instructions in producer instructions with a range of four (4) for a range-based explicit data flow processor;

[0014] Figure 2A Illustrated is an exemplary producer instruction encoded using an instruction data format that includes a range-based explicit consumer namespace for encoding one or more range-based explicit consumer instructions identified as consuming values produced by the producer instruction;

[0015] Figure 2B Illustrated is for Figure 2A the producer instruction in

[0016] Figure 3A An exemplary instruction stream of computer instructions encoded using range-based explicit consumer naming and configured to be processed by a range-based explicit data stream processor, where the instruction list includes branch instructions that create write-after-write (WAW) hazards and includes WAW instructions after the branch instructions to resolve the WAW hazards;

[0017] Figure 3B Illustrated is the Figure 3A exemplary instruction stream in

[0018] Figure 4 compared to other instruction streams that allow a processor to perform the same operations based on implicit consumer naming and explicit consumer naming in an instruction block architecture;

[0019] Figure 5 A flowchart illustrating an exemplary process of a range-based explicit data stream processor, such as the Figure 4 range-based explicit data stream processor in

[0020] Figure 6A An exemplary instruction stream of computer instructions encoded using range-based explicit consumer naming and configured to be processed by a range-based explicit data stream processor, where the instruction list includes WAW hazards attributed to branch instructions and does not include intermediate WAW instructions to resolve the WAW hazards;

[0021] Figure 6B Is Figure 6A the exemplary instruction stream of the computer instructions in

[0022] Figure 7 is an exemplary instruction stream that utilizes range-based explicit consumer / naming encoded computer instructions and is configured to be processed by a range-based explicit data flow processor, where the instruction list includes branch instructions encoded to cause the range-based explicit data flow processor to invalidate production values when a branch is taken to resolve a WAW hazard; and

[0023] Figure 8 is a block diagram of an exemplary processor-based system that includes a range-based explicit data flow processor (including but not limited to Figure 4 the range-based data flow processor in ), and is configured to support execution of producer instructions that are encoded using range-based explicit naming of consumer instructions that are intended to consume values produced by the producer instructions. DETAILED DESCRIPTION

[0024] Exemplary aspects disclosed herein include a range-based explicit data flow processor and related computer-readable media and methods. The range-based explicit data flow processor is configured to support execution of producer instructions that are encoded using explicit naming of consumer instructions that are intended to consume values produced by the producer instructions. The range-based explicit data flow processor is configured to provide a production value or make it available as input to an explicitly named consumer instruction as a result of processing an encoded producer instruction. In the exemplary aspects disclosed herein, the range-based explicit data flow processor supports execution of producer instructions that explicitly name consumer instructions based on using the producer instruction as a reference point and naming the consumer instructions relative to that reference point. The name assigned by a producer instruction to a consumer instruction is referred to as the target distance. The maximum target distance allowed by the range-based explicit data flow processor is referred to as the "range" of the processor. The range of the processor defines the maximum set of consumer instructions that can be explicitly named by a producer instruction. In this way, by way of example, this range-based explicit naming does not require instructions to be grouped in instruction blocks to support a fixed block reference point for explicit naming of consumer instructions and is thus limited to explicitly naming consumer instructions only within the instruction block of the producer instruction. Thus, removing the architectural limitation of instruction blocks in a data flow processor can allow the data flow processor to be designed to support explicit data flow communication on larger computational graphs that are not limited by instruction block size. Range-based explicit consumer naming can also have the advantage of requiring less consumer encoding namespace ("range namespace") because consumer naming is relative to the location of the producer instruction rather than a fixed reference location that may be more frequently distant from the consumer instruction.

[0025] In this regard, Figure 1is an exemplary instruction stream 100 extracted from an instruction program stored in a computer memory, which includes a series of computer instructions I0 to I6 to be executed by a processor to illustrate an example of an explicit named range-based explicit consumer communication model of expected consumer instructions in producer instructions. A producer instruction is an instruction that generates a production value when executed by the processor based on the instruction type and (multiple) operands of the producer instruction. This production value can then be provided as an output value to an I / O device or made available (i.e., communicated) as an input value in the specified operands to another consumer instruction in the instruction stream executed in the processor. Thus, a consumer instruction that uses (i.e., consumes) the production value generated by executing a producer instruction is dependent on the producer instruction. Dependent instructions are used in both in-order and out-of-order processors. For example, if Figure 1 instruction I2 in the instruction stream 100 in Figure 1 consumes the production value generated by executing instruction I0 in the processor, then instruction I2 will be a consumer instruction of producer instruction I0, thus creating a producer-consumer dependency between instruction I0 and I2. Communication of the production value between dependent instructions can be implicitly done in an implicit communication model using the general-purpose register (GPR) namespace as a rendezvous point. However, due to the limited size of the GPR namespace and because producer instructions have no direct way to notify consumer instructions that their production value has been generated, the implicit communication model may have limitations.

[0026] In this regard, as discussed in more detail below, the range-based explicit consumer communication model disclosed herein for use by a processor to communicate a production value from a producer instruction to a consumer instruction during execution is an explicit consumer communication model based on "range". In this model, the processor is configured to process instructions using a supported instruction format that includes the ability of a producer instruction to explicitly name (i.e., encode) the expected (multiple) dependent consumer instructions within the producer instruction. This explicit consumer naming provides a notification recognized during execution by a processor that supports the range-based explicit consumer communication model to communicate the production value from the producer instruction to the named target consumer instruction for consumption. In an explicit data flow communication model, a method is needed to encode the location of the expected consumer instruction in the producer instruction. In the example of the range-based explicit consumer communication model disclosed herein, the explicit naming of the consumer instruction in the producer instruction is based on encoding a "target distance" value in the producer instruction. The "target distance" value is based on using the location of the producer instruction in the instruction stream as a relative reference point to indicate the location of the expected consumer instruction in the instruction stream. In other words, the "target distance" value defines the distance between the expected consumer instruction and its producer instruction in the instruction stream. This is in Figure 1is shown by way of example in the instruction stream 100. For example, if in an instruction set architecture (ISA) of a range-based explicit data flow processor configured to process the instruction stream 100, the "range" (i.e., the maximum target distance) is set to four (4), this means that any instruction I0 to I6 in the instruction stream 100 can explicitly name a consumer instruction within four (4) instruction locations of the producer instruction in the instruction stream 100. For example, as a producer instruction, instruction I0 can name any of the instructions I1 to I4 as a consumer instruction with a maximum target distance of four (4). Similarly, as shown in Figure 1 , as producer instructions, instructions I1 and I2 can name any of the instructions I2 to I5 and instructions I3 to I6 respectively as consumer instructions with a maximum target distance of four (4). However, in this example, for instance, instruction I0 cannot directly target instruction I5 because I5 is located five (5) instruction positions away from instruction I0, exceeding the maximum target distance of four (4). Depending on the ISA to be explicitly named in the producer instruction, the target consumer instruction must also be located at a distance equal to or less than the maximum target distance. However, by naming one of the intermediate instructions I1 to I4 as a consumer, and then that intermediate instruction naming instruction I5 as the final consumer, instruction I0 can indirectly target instruction I5. Otherwise, as discussed in more detail below, intermediate consumer / producer instructions or implicit data flow communication can be employed.

[0027] In this way, by way of example, this range-based explicit consumer communication model does not require instructions to be grouped in instruction blocks, which support fixed block reference points for explicit naming of consumer instructions and are thus limited to producer instructions that can explicitly name consumer instructions only within their same instruction block. Thus, removing the architectural limitation of instruction blocks in a data flow processor can allow the data flow processor to be designed to support explicit data flow communication on larger computational graphs not limited by instruction block size. Each producer instruction in the range-based explicit consumer communication model can have a private set of consumer names, which allows an infinite number of consumers to be named (i.e., reached) in the instruction stream and thus allows a computational graph over the entire instruction stream if needed. However, the bits allocated in the supported range namespace will control the maximum target distance that can be encoded in the producer instruction and processed by a compatible processor. The bit size of the range namespace is a design decision determined by the desired trade-off between the instruction memory size required to store a given number of instructions and the desired range namespace. In any case, range-based explicit consumer naming has the advantage of requiring fewer consumer encoding namespaces ("range namespaces") compared to the block atomic execution model because consumer naming is relative to the producer instruction rather than a fixed reference that may be more frequently far from the consumer instruction.

[0028] Figure 2A Illustrated is an exemplary range - based explicit consumer naming instruction format 200 (“instruction format 200”) for producer instruction 202, which includes a range - based explicit consumer namespace for encoding one or more consumer instructions according to an exemplary range - based explicit naming instruction set architecture (ISA). Figure 2B Illustrated is an example of an ADD producer instruction 204 that uses the instruction format 200 of the producer instruction 202 in Figure 2A to explicitly name consumers based on a range. A processor compatible with the range - based explicit consumer communication model and instruction format 200 in Figure 2A communicates the production value generated by the execution of the producer instruction 202 to the named consumer instructions. In this example, as shown in Figure 2A , the instruction format 200 has an instruction type INST. For example, the instruction type of the addition instruction type is shown as the ADD producer instruction 204 in Figure 2B . Further, as shown in Figure 2A , the instruction format 200 also includes an optional operand OP that provides input operands for the producer instruction 202. For example, the operand in the ADD producer instruction 204 in Figure 2B is register R1. Note that if a previous producer instruction in the instruction stream targets the ADD producer instruction 204 as its production value, the operand may not be required.

[0029] Also as shown in the example in Figure 2A , the instruction format 200 also includes a consumer namespace 206 to annotate one or more target consumers of the producer instruction 200. In Figure 2BIn the example, two named consumers 208(1) and 208(2) are provided, which are respectively identified by the symbol pair <+TD, ‘t’>, where “TD” is the target distance, and ‘t’ is one of the set {0, 1, …, N, P}. In this example, +TD indicates the relative target distance from the producer instruction 202, where the consumer instruction for the producer instruction 202 is located in the instruction stream. ‘t’ indicates the operand of the named consumer instruction named by the producer instruction 202 for passing its production value. For example, a ‘t’ value of ‘0’ means operand 0 of the consumer instruction, ‘1’ means operand ‘1’ of the consumer instruction, ‘N’ means operand ‘N’ of the consumer instruction to represent any other number of operands that may be in the possible instruction format 200, and if the consumer instruction is a predicate instruction, ‘P’ means the predicate of the consumer instruction. Therefore, the interpretation of the consumer namespace format <+TD, ‘t’> is that the production value from the producer instruction 200 should be delivered to the consumer instruction at a position ‘TD’ distance forward from the producer instruction in the instruction stream, and the production value is used as input ‘t’ to the consumer instruction.

[0030] Thus, for example, as Figure 2B shown by the ADD producer instruction 204 in Figure 2B the first named consumer is provided as <+3:0>, meaning that the production value from executing the ADD producer instruction 204 will be delivered as operand 0 to the consumer instruction at a forward distance of three (3) instructions from the producer instruction 204. Also as

[0031] shown by the ADD producer instruction 204 in Figure 3A the second named consumer is provided as <+8:1>, which means that the production value from executing the ADD producer instruction 204 will be delivered as operand 1 to the consumer instruction at a forward distance of eight (8) instructions from the producer instruction. If the maximum target distance is eight (8), then three (3) bits can be provided in the instruction format 200 to encode the target distance +TD. Figure 3AAs shown, instruction I0 is of the ADD instruction type and includes the named consumer instruction at a forward target distance of '3' from instruction I0 to receive the produced value in operand 0. Thus, the consumer instruction of instruction I0 is instruction I3. The test-if-equal-to-0 instruction (TEQZ.B), instruction I1 is a conditional branch instruction that has the conditional branch location of instruction I5 if the condition is true. Since the conditional branch instruction I1 is located between the producer instruction I0 and the expected consumer instruction I3, the conditional branch instruction I1 will be executed before the consumer instruction I3. In this example, the distance of the conditional branch instruction I1 from the producer instruction I0 is less than the named consumer target distance value '3'. Only when the conditional branch in instruction I1 is evaluated to be not true, the third instruction after instruction I0 (for the target distance value '3') is instruction I3, and thus this branch is not taken. If the branch is not taken from the execution of instruction I1, instruction I2 is executed, which names instruction I3's operand 1 as the consumer of the produced value from instruction I2, such that instruction I3 adds the produced results from instruction I0 and instruction I2 and stores the result in register R6. However, if the branch is taken in the conditional branch instruction I1, the third instruction after instruction I0 will be instruction I6, which is the instruction taken by the branch in the flow path taken by the branch for the conditional branch instruction I1. If the branch in the conditional branch instruction I1 is taken, this will create a write-after-write (WAW) hazard because the intention of instruction stream 300 is for instruction I3 to consume the result produced from the execution of instruction I0. This WAW hazard is a result of the range-based explicit consumer communication model using relative target distance values based on the location of the producer instruction in the instruction stream to name the expected consumer instruction. If the consumer name is at a relatively fixed location in the instruction stream 300 (such as, for example, the start of an instruction block), then instruction I0 can specifically name instruction I3 as its consumer to avoid the WAW hazard. However, as previously described, the range-based explicit consumer communication model can have the advantages of supporting range-based explicit data stream communication on larger computation graphs not limited by instruction block size and requiring less range naming space.

[0032] Thus, in this example, to prevent the production value from being erroneously delivered to the consumer instruction I6 when the execution of the conditional branch instruction I1 that creates a WAW hazard is taken in the branch, the instruction I5 is provided to perform a WAW operation in the data flow path 302 taken by the branch from the execution of the instruction I1 in the instruction stream 300, which also designates the instruction I6 as its consumer. The instruction I5 is considered a WAW instruction located between the instruction I6 taken by the branch in the instruction stream 300 and the consumer instruction I3. In this way, if the branch in the conditional branch instruction I1 is not taken to avoid the instruction I6 consuming an unexpected result from the instruction I0, the production value from the instruction I0 is rewritten by the producer instruction I5. A programmer or compiler that generates instructions according to a range-based explicit consumer communication model can be configured to identify such a WAW hazard and prevent the production value from being erroneously delivered to the consumer instruction I6 when taking the branch from the execution of the conditional branch instruction I1 by employing another producer instruction (e.g., the instruction I5 in Figure 3A ) in the hazardous flow path to perform a write-after-write (WAW) operation. This additional producer instruction I5 names the operand (e.g., operand 0) of the unexpected consumer instruction (e.g., the instruction I6 in Figure 3A ) and the producer instruction that creates the WAW hazard (e.g., the instruction I0 in Figure 3A ). This has the effect of causing the rewrite of the unexpected production value to be consumed by the unexpected consumer instruction.

[0033] For comparison purposes, compared to two other similar instruction streams 302, 304, Figure 3B illustrates Figure 3A the exemplary instruction stream 300 in

[0034] Figure 4

[0034] Figure 4 The instruction stream 302 is encoded using an implicit consumer communication model. The instruction stream 304 is encoded using an explicit consumer communication model that uses the encoding location based on the start of the instruction block, respectively. The instruction stream 302 based on the implicit consumer communication model includes the instructions I10 to I16. These instructions I10 to I16 have the same instruction type as the instructions I0 to I6 in the instruction stream 300 and are encoded to cause the processor to generate the same result, but the instruction stream 302 uses register names to perform implicit consumer naming in the producer instructions. The instruction stream 304 includes the instructions I20 to I26. These instructions I20 to I26 have the same instruction type as the instructions I0 to I6 in the instruction stream 300 and are encoded to cause the processor to generate the same result, but the instruction stream 304 uses explicit naming based on the absolute instruction location relative to the start of the instruction block to name consumers in the producer instructions.FIG. 0 is a schematic diagram of a processor-based system 400, including an exemplary range-based explicit data flow processor 402 (“processor 402”), which is configured to support a range-based explicit consumer communication model. The processor 402 includes instruction processing circuitry 404, which is configured to process instructions to be executed. As an example, the processor 402 can be an in-order or out-of-order processor (OoP). Instructions 406 are extracted from an instruction memory 410 by an instruction fetch circuit 408 provided in the instruction processing circuitry 404. As an example, the instruction memory 410 can be provided in or as part of the system memory in the processor-based system 400. An instruction cache 412 can also be provided in the processor 402 to cache the instructions 406 fetched from the instruction memory 410 to reduce latency in the instruction fetch circuit 408. The instruction fetch circuit 408 in this example is configured to provide the instructions 406, which are the fetched instructions 406F, to one or more instruction pipelines I0 to I N as an instruction stream 411 to be preprocessed in the instruction processing circuitry 404. The fetched instructions 406F in the instruction stream 411 include producer instructions and consumer instructions, which consume production values as a result of the instruction processing circuitry 404 executing the producer instructions. The instruction pipelines I0 to I N are provided across different processing circuits or stages of the instruction processing circuitry 404 to preprocess and process the fetched instructions 406F in a series of steps, which can be executed concurrently to increase throughput before the fetched instructions 406F are executed in the execution circuitry 414.

[0035] A control flow prediction circuit 416 (e.g., a branch prediction circuit) is also provided in Figure 4 the instruction processing circuitry 404 in the processor 402 to speculate or predict the target address of the fetched instructions 406F for the control flow (such as a conditional branch instruction). The prediction of the target address by the control flow prediction circuit 416 is used by the instruction fetch circuit 408 to determine the next fetched instruction 406F to be fetched based on the predicted target address. The instruction processing circuitry 404 also includes an instruction decoding circuit 418, which is configured to decode the fetched instructions 406F fetched by the instruction fetch circuit 408 into decoded instructions 406D to determine the instruction type and required actions, which can also be used to determine in which instruction pipeline I0 to I N the decoded instructions 406D should be placed. The decoded instructions 406D are then placed in the instruction pipelines I0 to I Nin one or more of the instruction pipelines and is then provided to the rename circuit 420 in the instruction processing circuit 404. The rename circuit 420 is configured to determine whether any register names in the decoded instruction 406D need to be renamed to break any register dependencies that would prevent parallel or out-of-order processing. The rename circuit 420 is configured to call the register map table (RMT) 422 to rename the logical source register operands and / or write the destination register operand of the decoded instruction 406D to an available physical register 424(1) to 424(X) (P0, P1, …, P x ) in the physical register file (PRF) 426. The register map table (RMT) 422 contains a plurality of map entries, each entry being mapped to a corresponding logical register R0 to R p (i.e., associated therewith). The map entries are configured to store information in the form of an address pointer to point to the physical registers 424(1) to 424(X) in the physical register file (PRF) 426. Each of the physical registers 424(1) to 424(X) in the physical register file (PRF) 424 contains a data entry configured to store data for the source and / or destination register operands of the decoded instruction 406D.

[0036] Figure 4 The instruction processing circuit 404 in the processor 402 also includes a register access circuit 428 before the dispatch circuit 430. The register access circuit 428 is configured to access the physical registers 424(1) to 424(X) in the physical register file (PRF) 426 based on the map entries of the logical registers R0 to R p in the register map table (RMT) 422 that are mapped to the source register operands of the decoded instruction 405D to retrieve the produced values from the executed instruction 406E in the execution circuit 414. The register access circuit 428 is also configured to provide the produced values retrieved from the executed, decoded instruction 406E as the source register operands of the decoded instruction 406D to be executed. Moreover, in the instruction processing circuit 404, the dispatch circuit 430 is provided in the instruction pipelines I0 to I N and is configured to dispatch the decoded instruction 406D to be executed to the execution circuit 414 when all source register operands for the decoded instruction 406D are available. For example, the dispatch circuit 430 is responsible for ensuring that the necessary values of the operands for the decoded consumer instruction 406D are available before dispatching the decoded consumer instruction 406D to the execution circuit 414 for execution. The operands of the decoded instruction 406D can include immediate values, values stored in memory, and produced values from other decoded instructions 406D, which are considered producer instructions for the consumer instruction.

[0037] The execution circuitry 414 is configured to execute the decoded instruction 406D received from the dispatch circuitry 430. The decoded instruction 406D that generates a production value to be consumed by a consumer instruction in the instruction processing circuitry 404 is considered a producer instruction. As discussed above, in the range-based explicit consumer communication model supported by the Figure 4 processor 402 in, the decoded producer instruction 406D may name a consumer instruction and, in this case, will include a consumer target distance value TD+ encoded explicit consumer name and an associated consumer operand value 't' representing the relative instruction distance in the instruction stream 411 to the decoded producer instruction 406D. The execution circuitry 414 is configured to determine whether the executed producer instruction 406D includes an explicit consumer name. If so, the write circuitry 432 in the instruction processing circuitry 404 is configured to write the production value generated by the executed producer instruction 406D to the operand of the consumer instruction 406D in the instruction processing circuitry 404, which consumer instruction 406D is identified as being located at a distance of the consumer target distance value TD+ from the producer instruction 406D in the instruction stream 411. In this example, the instruction processing circuitry 404 includes a production value storage circuitry 434 that is configured to receive and store production values from the write circuitry 432, which production values are generated by the execution circuitry 414 by executing the producer instruction 406D that names the consumer instruction 406D. The production value storage circuitry 434 is configured to make the produced results available to the dispatch circuitry 430 such that the production values can be provided and made available for the named consumer instruction 406D to be executed.

[0038] Note that the producer instruction 406D may also include more than one explicitly named consumer instruction 406D, in which case the write circuitry 432 may store the produced results associated with the more than one consumer instruction in the production value storage circuitry 434 to be provided to the dispatch circuitry 430. Also note that, as discussed above, by Figure 4The range-based explicit consumer communication model supported by the processor 402 in [[ ]] supports providing the produced result from the executed producer instruction 406D as a predicate for a conditional consumer instruction 406D, such as a conditional branch instruction. In this example, the producer instruction 406D can include an explicit consumer name for the expected conditional consumer instruction 406D, which includes a consumer target distance value TD+ and a consumer predicate value as the operand value 't'. The write circuit 432 can store the produced result as a predicate associated with the named conditional consumer instruction 406D in the production value storage circuit 434 to be provided to the dispatch circuit 430 when preparing to dispatch the conditional consumer instruction 406D to be executed.

[0039] If the decoded instruction being executed does not explicitly name a consumer instruction 406D in the instruction stream 411, the write circuit 432 can write the produced result to the physical registers P0 to P in the physical register file 426 X and / or the memory called in the decoded instruction 406D. If the expected consumer instruction 406D for the producer instruction 406D is further from the producer instruction 406D in the instruction stream 411 than the maximum consumer target distance value that can be encoded in the producer instruction 406D, the write circuit can write the produced result to the physical registers P0 to P in the physical register file 426 X to provide implicit communication of the produced result to the consumer instruction 406D waiting to be dispatched to the execution circuit 414 for execution.

[0040] Figure 5 is a flowchart illustrating an exemplary process 500 of a range-based explicit data flow processor, such as Figure 4 the range-based explicit data flow processor 402 in [[ ]], communicating the production value from the executed producer instruction to be consumed by a consumer instruction identified by the range-based explicit consumer instruction in the executed producer instruction. As an example, Figure 5 the process 500 in [[ ]] will be discussed in conjunction with Figure 4 the operation of the processor 402 in [[ ]].

[0041] In this regard, the instruction processing circuit 404 receives a plurality of instructions 406( Figure 5in box 502). The instruction fetch circuit 408 in the processor 402 is configured to fetch the instruction 406 from the instruction memory 410 and / or the instruction cache 412 if the instruction 406 is first fetched or prefetched into the instruction cache 412. Instructions may include a plurality of producer instructions and a plurality of consumer instructions. The execution circuit 414 executes the producer instruction 406D for the consumer instruction 406D to generate a production value, and the producer instruction is configured to include at least one explicit consumer name, each explicit consumer name including a consumer target distance value and an associated consumer operation value( Figure 5 in box 504), and the consumer target distance value represents the relative instruction distance in the instruction stream from the producer instruction. The execution circuit 414 determines whether the executed producer instruction 406D includes an explicit consumer name( Figure 5 in box 506). In response to determining that the executed producer instruction 406D includes an explicit consumer name, the write circuit 432 stores the production value of the executed producer instruction 406D in the production value storage circuit 434 into at least one operand (‘t’) of the consumer instruction 406D, and the consumer instruction 406D is identified as being located at a distance from the producer instruction 406D in the instruction stream 411 that is the consumer target distance value (TD+) of the executed producer instruction( Figure 5 in box 508). In response to at least one operand ‘t’ of the consumer instruction 406D being available in the production value storage circuit 434, the dispatch circuit 430 dispatches the consumer instruction 406D to be executed to the execution circuit 414( Figure 5 in box 510).

[0042] As discussed above in Figure 3A the example instruction stream 300, when a conditional branch instruction is located between a producer instruction and its expected target instruction such that the relative target distance from the producer instruction can change based on whether the branch is taken, range-based explicit consumer naming may create a WAW hazard. As discussed above in Figure 3A one way to address this hazard is to provide the producer instruction in the taken path of the branch, e.g., if the expected named consumer in an earlier producer instruction is in the not-taken path, write or rewrite the produced result. An example of this is shown by the WAW instruction I5 in Figure 3A . However, there are other ways to construct an instruction stream that can address the WAW hazard.

[0043] In this regard, Figure 6A is an exemplary instruction stream 600 of computer instructions I0 to I11, which is encoded using range-based explicit consumer instruction naming and is configured to be processed by a range-based data flow processor, such as Figure 4The processor 402 in []. In this example instruction stream 600, there is a WAW hazard due to the conditional branch instruction I6. If the condition in the conditional branch instruction I6 is resolved as the taken branch, the instruction I5 creates a WAW hazard using the producer instruction I3. The producer instruction I3 names the instruction I5 as the consumer, where the instruction I5 then names the consumer instruction with a target distance of '+2'. The instruction I6 is a conditional branch instruction after the instruction I5. Therefore, if the branch is taken in the conditional branch instruction I6, the production value from the execution of the instruction I5 (based on consuming the production value from the instruction I3) is communicated to the consumer instruction I9 instead of the expected consumer instruction I7. Thus, this WAW hazard will incorrectly supply the production value from the instruction I5 to the consumer instruction I9 instead of the instruction I7, which is not the behavior expected by the programmer in this example.

[0044] To resolve Figure 6A this WAW hazard in the instruction stream 600 in []. Figure 6B is an alternative exemplary instruction stream 602 with instructions I0 to I12, which, when executed by a range-based explicit data flow processor (such as Figure 4 the processor 402 in []), performs Figure 6A the same expected operations of the instruction stream 600 in []. Figure 6B The instructions I0 to I4 between the instruction stream 602 in [] and Figure 6A the instruction stream 600 in [] are the same. Moreover, Figure 6B the instructions I7 to I12 in the instruction stream 602 in [] and Figure 6A the instructions I6 to I11 in the instruction stream 600 in [] are the same instruction types, having the same expected operands and consumed values. To resolve Figure 6A the WAW hazard in the instruction stream 600 in []. Figure 6B the instruction stream 602 in [] includes an additional conditional branch instruction I5 between the contents of the instructions I4 and I6 in Figure 6A the instruction stream 600 in []. Moreover, Figure 6B the instruction I6 (based on Figure 6A the instruction I5 in the instruction stream 600 in []) is changed to a predicate instruction I6 (subtraction - SUB). The predicate instruction I6 is located between the producer instruction I3 and the conditional branch instruction I7. A conditional branch instruction I5 (having the same predicate as the conditional branch instruction I7) as a predicate production instruction is inserted before the prediction instruction I6 such that when the condition of the inserted conditional branch instruction I5 is resolved as not taken, the predicate instruction I6 only generates a predicate production value. The conditional branch instruction I5 as a conditional branch instruction is inserted at the target distance from the named consumer instruction in the producer instruction I3. In this way, Figure 6AThe instructions in the instruction stream 602 are arranged such that the instructions for the production values from the producer instruction I2 are only valid for the non-taken flow path of the conditional branch instruction I7 to avoid the WAW hazard created by the conditional branch instruction I7.

[0045] Figure 7 Another exemplary instruction stream 700 of computer instructions is encoded using range-based explicit consumer instruction naming and is configured to be processed by a range-based data flow processor, where the WAW hazard is resolved. As discussed below, the WAW hazard is resolved by providing instructions and encoding such that if the branch from the resolved conditional branch instruction is taken, the production value is not communicated to an unintended consumer instruction. In this regard, as Figure 7 shown, the instruction I2 is a producer instruction that names the instruction I5 as a consumer instruction based on the consumer naming <+3,0> indicating that the target distance from the instruction I2 is '3'. However, the instruction I4 between the producer instruction I2 and the intended consumer instruction I5 is a conditional branch instruction. In this example, the WAW hazard is resolved by providing an encoding mechanism to support invalid operands included in the conditional branch instruction. The invalid operand is included in a special invalid conditional branch instruction I4 that is configured to direct the processor to invalidate the production value generated from the execution of the producer instruction I2 if the conditional branch instruction I4 is resolved as the taken branch. In this way, when the branch is taken from the conditional branch instruction I4, the production value from the instruction I3 is not communicated to an unintended consumer instruction in the taken data flow path of the instruction stream 300. For example, the special invalid conditional branch instruction can be annotated by the uniqueness or variation of the opcode similar to the conditional branch instruction.

[0046] Figure 8 is a block diagram of an exemplary processor-based system 800, including a range-based explicit data flow processor 802 ("processor 802") that is configured to support the execution of producer instructions that are encoded with range-based explicit naming of consumer instructions that are intended to consume the values produced by the producer instructions. For example, Figure 8 the processor 802 in Figure 4Processor 402 in. The processor-based system 800 can be one or more circuits included in an electronic board, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, and can represent, for example, a server or a user's computer. In this example, the processor-based system 800 includes a processor 802. Processor 802 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc. More specifically, processor 802 can be an EDGE instruction set microprocessor or other processor implementing an instruction set that supports explicit consumer naming for communicating production values generated by executing producer instructions. Processor 802 is configured to execute the processing logic in the instructions for performing the operations and steps discussed herein. In this example, processor 802 includes an instruction cache 804 for temporarily and quickly accessing memory storage of instructions and an instruction processing circuit 810. Instructions fetched or prefetched from memory (such as system memory 808) via system bus 806 are stored in instruction cache 804. Instruction processing circuit 810 is configured to process the instructions fetched into instruction cache 804 and process the instructions for execution. Instruction processing circuit 810 is compatible with a range-based explicit consumer communication model and instruction encoding, such that instruction processing circuit 810 supports the execution of producer instructions encoded with range-based explicit naming of consumer instructions, such that these production values are communicated as input values to the named consumer instructions for their execution.

[0047] Processor 802 and system memory 808 are coupled to system bus 806 and can interconnect the peripheral devices included in processor-based system 800. As is well known, processor 802 communicates with these other devices by exchanging address, control, and data information on system bus 806. For example, processor 802 can convey a bus transaction request to a memory controller 812 in system memory 808, which is an example of a slave device. Although not shown in Figure 8 the figure, multiple system buses 806 can be provided, where each system bus constitutes a different architecture. In this example, memory controller 812 is configured to provide memory access requests to a memory array 814 in system memory 808. The memory array includes an array of storage bit cells for storing data. As a non-limiting example, system memory 808 can be read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM), etc.), and static memory (such as flash memory, static random access memory (SRAM), etc.).

[0048] Other devices can be connected to system bus 806. As Figure 8Illustrated by way of example, these devices may include a system memory 808, one or more input devices 816, one or more output devices 818, a modem 824, and one or more display controllers 820. The (multiple) input devices 816 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The (multiple) output devices 818 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. The modem 824 may be any device configured to allow data exchange with a network 826. The network 826 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH TM networks, and the Internet. The modem 824 may be configured to support any type of communication protocol desired. The processor 802 may also be configured to access the (multiple) display controllers 820 via the system bus 806 to control the information sent to one or more displays 822. The (multiple) displays 822 may include any type of display, including but not limited to cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma displays, etc.

[0049] Figure 8 The processor-based system 800 in may include an instruction set 828, which may be encoded with a range-based explicit consumer naming model for execution by the processor 802 for any application required by the instructions. The instructions 828 may be stored in the system memory 808, the processor 802, and / or the instruction cache 804 as examples of non-transitory computer-readable media 830. During its execution, the instructions 828 may also reside entirely or at least partially within the system memory 808 and / or the processor 802. The instructions 828 may also be transmitted or received over the network 826 via the modem 824, such that the network 826 includes computer-readable media 830.

[0050] Although the computer-readable storage medium 830 is shown as a single medium in the exemplary embodiments, the term "computer-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more instruction sets. The term "computer-readable medium" should also be understood to include any medium that is capable of storing, encoding, or carrying an instruction set for execution by a processing device and that causes the processing device to perform any one or more of the methods disclosed herein. The term "computer-readable medium" should correspondingly be understood to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0051] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be implemented in machine-executable instructions that may be used to program a general-purpose or special-purpose processor using the instructions to perform these steps. Alternatively, these steps may be performed by a combination of hardware and software.

[0052] The embodiments disclosed herein may be provided as a computer program product or software that may include a machine-readable medium (or computer-readable medium) having instructions stored thereon that may be used to program a computer system (or other electronic device) to perform a process in accordance with the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes: machine-readable storage media (e.g., ROM, random access memory (“RAM”), magnetic disk storage media, optical storage media, flash devices, etc.).

[0053] Unless otherwise specifically stated and apparent from the foregoing discussion, it is to be understood that throughout this description, discussions using terms such as “processing,” “computing,” “determining,” “displaying,” etc., refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities within the registers of the computer system and transforms them into other data similarly represented as physical quantities within the computer system memory or registers or other such information storage, transmission, or display devices.

[0054] The algorithms and displays presented herein are in themselves not related to any particular computer or other apparatus. According to the teachings herein, various systems may be used with the program, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The structure required for various such systems will become apparent from the foregoing description. Additionally, the embodiments described herein are not described with reference to any particular programming language. It is to be understood that various programming languages may be used to implement the teachings of the embodiments described herein.

[0055] Those skilled in the art will also appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, instructions stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, the components of the distributed antenna system described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of desired information. To clearly illustrate this interchangeability, the various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How this functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each particular application, but such implementation decisions should not be construed as causing a departure from the scope of the present embodiments.

[0056] The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a controller can be a processor. The processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0057] The embodiments disclosed herein can be implemented in hardware and instructions stored in hardware and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable medium known in the art. The exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. In the alternative, the processor and the storage medium can reside as discrete components in a remote station, a base station, or a server.

[0058] It should also be noted that the operational steps described in any exemplary embodiment of this article are described to provide examples and discussions. The described operations can be performed in many different sequences except for the illustrated sequence. In addition, the operations described in a single operational step can actually be performed in a plurality of different steps. Additionally, one or more operational steps discussed in the exemplary embodiment can be combined. It will also be understood by those skilled in the art that information and signals can be represented using any of a variety of techniques and technologies. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0059] Unless otherwise expressly stated, any method set forth herein is in no way intended to be construed as requiring that its steps be performed in a specific order. Thus, in the event that a method claim does not actually recite the order in which its steps are to be followed, or in the absence of otherwise specific statements in the claims or description that the steps are to be limited to a specific order, any particular order is in no way intended to be inferred.

[0060] It is obvious to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, sub-combinations and variations of the disclosed embodiments that include the spirit and essence of the present invention may be conceived by those skilled in the art, the present invention should be interpreted as including all contents within the scope of the appended claims and their equivalents.

Claims

1. A processor, configured to: Receive a plurality of instructions in an instruction stream to be executed from an instruction memory, the plurality of instructions including a plurality of producer instructions and a plurality of consumer instructions; Dispatch the consumer instructions in response to a plurality of operands of a consumer instruction among the plurality of consumer instructions to be executed being available, wherein the consumer instruction further includes a plurality of operand positions, and each operand among the plurality of operands of the consumer instruction corresponds to an operand position among the plurality of operand positions of the consumer instruction; Execute a producer instruction among the plurality of producer instructions to generate a production value, the producer instruction being configured to include at least one explicit consumer name, each explicit consumer name including a consumer target distance value and an associated consumer operand value, the consumer target distance value representing a relative instruction distance from the producer instruction in the instruction stream, the associated consumer operand value including at least one operand number, and each operand number identifies the operand among the plurality of operands of the consumer instruction to be written by the producer instruction by indicating an operand position of the operand among the plurality of operands of the consumer instruction; Determine whether the executed producer instruction includes an explicit consumer name; And In response to determining that the executed producer instruction includes an explicit consumer name, write the production value of the executed producer instruction to the consumer instruction, the consumer instruction being identified as being located at a distance from the producer instruction in the instruction stream equal to the consumer target distance value of the executed producer instruction, and write the production value of the executed producer instruction to each operand among the plurality of operands of the consumer instruction at the operand position identified by the at least one operand number of the associated consumer operand value; Wherein there is a conditional branch instruction between the producer instruction and the consumer instruction, the conditional branch instruction including a predicate and a conditional branch position, and the conditional branch instruction is located at a distance from the producer instruction less than the consumer target distance value of the producer instruction; There is a predicate instruction between the producer instruction and the conditional branch instruction, the predicate instruction including the predicate of the conditional branch instruction; There is a predicate producer instruction between the predicate instruction and the conditional branch instruction, the predicate producer instruction including the predicate of the conditional branch instruction and a second explicit consumer name, the second explicit consumer name including a second consumer target distance value and a second associated consumer operand value, the second consumer target distance value representing a second relative instruction distance from the predicate producer instruction, and the predicate producer instruction is located at a distance from the consumer instruction equal to the second consumer target distance value; The predicate producer instruction is configured to cause the processor to execute only the predicate producer instruction in response to the predicate of the predicate instruction being resolved to the not-taken state of the conditional branch instruction, to generate a predicate production value for at least one of the plurality of operands of the consumer instruction.

2. The processor according to claim 1, further configured to: dispatch the second consumer instruction among the plurality of consumer instructions to be executed in response to at least one second operand of a second consumer instruction being available, wherein the second consumer instruction further includes a plurality of second operand positions, and each second operand of the plurality of second operands of the second consumer instruction corresponds to a second operand position among the plurality of second operand positions of the second consumer instruction; determine whether the executed producer instruction includes a second explicit consumer name, the second explicit consumer name including a second consumer target distance value and an associated second consumer operand value, the second consumer instruction distance representing a second relative instruction distance in the instruction stream from the producer instruction, and the associated second consumer operand value including at least one second operand number, each second operand number identifying the second operand among the plurality of second operands of the consumer instruction to be written by the producer instruction by indicating the second operand position of the second operand among the plurality of second operands of the second consumer instruction value; and in response to determining that the executed producer instruction includes a second explicit consumer name, write the production value of the executed producer instruction to the second consumer instruction, the second consumer instruction being identified as being at a second distance from the producer instruction in the instruction stream that is the second consumer target distance value of the executed producer instruction, and write the production value of the executed producer instruction to each second operand among the plurality of second operands of the second consumer instruction at the second operand position identified by the at least one second operand number of the associated second consumer operand value.

3. The processor according to claim 1, configured to: dispatch the consumer instruction including a conditional consumer instruction to be executed in response to the predicate of the consumer instruction being available; and in response to determining that the executed producer instruction includes an explicit consumer name, write the production value of the executed producer instruction to the predicate of the conditional consumer instruction in the instruction processing circuit, the conditional consumer instruction being identified as being at a distance from the producer instruction in the instruction stream that is the consumer target distance value of the executed producer instruction, and write the production value of the executed producer instruction to each operand among the plurality of operands of the consumer instruction at the operand position identified by the at least one operand number of the associated consumer operand value.

4. The processor according to claim 1, comprising: an instruction processing circuit configured to receive the plurality of instructions in the instruction stream to be executed from the instruction memory, the plurality of instructions including the plurality of producer instructions and the plurality of consumer instructions; and the instruction processor circuit includes: a production value storage circuit configured to store production values associated with the plurality of operands of the received consumer instruction among the plurality of consumer instructions; a dispatch circuit configured to: in response to the production values for the plurality of operands of the consumer instruction being available in the production value storage circuit, dispatch the consumer instruction to be executed to an execution circuit; the execution circuit configured to execute the producer instruction among the plurality of producer instructions to generate the production value; and a write circuit configured to: determine whether the executed producer instruction includes an explicit consumer target distance value; and in response to determining that the executed producer instruction includes an explicit consumer target distance value, write the production value of the executed producer instruction associated with the consumer instruction to the production value storage circuit, the consumer instruction being identified as being located at a distance from the producer instruction in the instruction stream equal to the consumer target distance value of the executed producer instruction, and write the production value of the executed producer instruction associated with the operand of the consumer instruction to each of the plurality of operands of the consumer instruction at the operand position, the operand position being identified by at least one of the associated consumer operand values.

5. The processor according to claim 4, wherein the instruction processing circuit further includes a decoder circuit configured to: decode the received producer instruction into a decoded producer instruction; and decode the received consumer instruction into a decoded consumer instruction; and wherein: the production value storage circuit is configured to store the production value associated with at least one of the plurality of operands of the decoded consumer instruction; the dispatch circuit is configured to, in response to the production value associated with the plurality of operands of the consumer instruction being available in the production value storage circuit, dispatch the decoded consumer instruction to be executed to an execution circuit; the execution circuit is configured to execute the decoded producer instruction to generate the production value, the decoded producer instruction including the explicit consumer target distance value and the associated consumer operand value, the explicit consumer target distance value representing the relative instruction distance from the producer instruction in the instruction stream; and The write circuit is configured to, in response to determining that the decoded producer instruction being executed includes the explicit consumer target distance value, write the production value of the decoded producer instruction executed on the decoded consumer instruction to the production value storage circuit, where the decoded consumer instruction is identified as being located at the distance indicated by the explicit consumer target distance value of the producer instruction in the instruction stream, and write the production value of the decoded producer instruction executed on the decoded consumer instruction to each of the multiple operands of the consumer instruction at the operand position, the operand position being identified by the at least one operand number of the associated consumer operand value.

6. The processor according to claim 4, wherein: The instruction processing circuit is further configured to map the multiple operands of the consumer instruction to physical registers; and The instruction processing circuit is configured to, in response to determining that the executed producer instruction does not include the explicit consumer target distance value, write the production value for the executed producer instruction to the physical register mapped to at least one of the multiple operands of the consumer instruction.

7. The processor according to claim 6, wherein the instruction processing circuit further includes a register access circuit, the register access circuit being configured to: Access the physical register mapped to at least one of the operands of the consumer instruction to retrieve the production value of the executed producer instruction; and Provide the retrieved production value as at least one of the multiple operands of the consumer instruction.

8. The processor according to claim 6, further comprising: A physical register file, including multiple physical registers; And A register mapping table, including multiple mapping entries, each mapping entry being configured to store at least one address pointer pointing to an address of a physical register in the physical register file; Wherein: The instruction processing circuit is configured to map the at least one operand to a mapping entry in the register mapping table, the mapping entry being mapped to a physical register among the multiple physical registers in the physical register file; And In response to determining that the executed producer instruction does not include the explicit consumer target distance value, write the production value for the executed producer instruction to the logical register mapped to the mapping entry in the register mapping table, the mapping entry being mapped to at least one of the multiple operands of the consumer instruction.

9. The processor according to claim 4, further comprising: The instruction memory, configured to store the multiple instructions.

10. The processor according to claim 1, including an out-of-order processor OoP.

11. A method for providing a production value as an input to a consumer instruction from a producer instruction executed by a processor based on explicit naming of the consumer instruction, including: Receiving a plurality of instructions in an instruction stream to be executed from an instruction memory, the plurality of instructions including a plurality of producer instructions and a plurality of consumer instructions; Dispatching a consumer instruction in response to a plurality of operands of the consumer instruction in the plurality of consumer instructions to be executed being available, wherein the consumer instruction further includes a plurality of operand positions, and each operand in the plurality of operands of the consumer instruction corresponds to an operand position in the plurality of operand positions of the consumer instruction; Executing a producer instruction in the plurality of producer instructions to generate a production value, the producer instruction being configured to include at least one explicit consumer name, each explicit consumer name including a consumer target distance value and an associated consumer operand value, the consumer target distance representing a relative instruction distance from the producer instruction in the instruction stream, and the associated consumer operand value including at least one operand number, each operand number identifying the operand of the plurality of operands of the consumer instruction to be written by the producer instruction by indicating the operand position of the operand in the plurality of operands of the consumer instruction; Determining whether the executed producer instruction includes an explicit consumer name; And In response to determining that the executed producer instruction includes an explicit consumer name, writing the production value of the executed producer instruction to the consumer instruction, the consumer instruction being identified as being located at a distance from the producer instruction in the instruction stream equal to the consumer target distance value of the executed producer instruction, and writing the production value of the executed producer instruction to each operand in the plurality of operands of the consumer instruction at the operand position identified by the at least one operand number of the associated consumer operand value; Wherein there is a conditional branch instruction between the producer instruction and the consumer instruction, the conditional branch instruction including a predicate and a conditional branch position, and the conditional branch instruction is located at a distance from the producer instruction less than the consumer target distance value of the producer instruction; There is a predicate instruction between the producer instruction and the conditional branch instruction, the predicate instruction including the predicate of the conditional branch instruction; There is a predicate producer instruction between the predicate instruction and the conditional branch instruction, the predicate producer instruction including the predicate of the conditional branch instruction and a second explicit consumer name, the second explicit consumer name including a second consumer target distance value and a second associated consumer operand value, the second consumer target distance value representing a second relative instruction distance from the predicate producer instruction, and the predicate producer instruction is located at a distance from the consumer instruction equal to the second consumer target distance value; The predicate producer instruction is configured to cause the processor to execute only the predicate producer instruction in response to the predicate of the predicate instruction being resolved to an untaken state of the conditional branch instruction, to generate a predicate production value for at least one of the plurality of operands of the consumer instruction.

12. The method according to claim 11, further comprising: dispatching the second consumer instruction among the plurality of consumer instructions to be executed in response to at least one second operand of a second consumer instruction being available, wherein the second consumer instruction further comprises a plurality of second operand positions, and wherein each second operand of the plurality of second operands of the second consumer instruction corresponds to a second operand position among the plurality of second operand positions of the second consumer instruction; determining whether the executed producer instruction comprises a second explicit consumer name, the second explicit consumer name comprising a second consumer target distance value and an associated second consumer operand value, the second consumer instruction distance representing a second relative instruction distance from the producer instruction in the instruction stream, and the associated second consumer operand value comprising at least one second operand number, each second operand number identifying the second operand among the plurality of second operands of the second consumer instruction to be written by the producer instruction by indicating the second operand position of the second operand among the plurality of second operands of the second consumer instruction value; and in response to determining that the executed producer instruction comprises a second explicit consumer name, writing the production value of the executed producer instruction to the second consumer instruction, the second consumer instruction being identified as being at a second distance from the producer instruction in the instruction stream by the second consumer target distance value of the executed producer instruction, and writing the production value of the executed producer instruction to each second operand among the plurality of second operands of the second consumer instruction in the second operand position, the second operand position being identified by the at least one second operand number of the associated second consumer operand value.

13. The method according to claim 11, comprising: dispatching the consumer instruction comprising a conditional consumer instruction to be executed in response to a predicate of the consumer instruction being available; and in response to determining that the executed producer instruction comprises an explicit consumer name, writing the production value of the executed producer instruction to the predicate of the conditional consumer instruction in the instruction processing circuit, the conditional consumer instruction being identified as being at a distance from the producer instruction in the instruction stream by the consumer target distance value of the executed producer instruction, and writing the production value of the executed producer instruction to each operand among the plurality of operands of the consumer instruction in the operand position, the operand position being identified by the at least one operand number of the associated consumer operand value.

14. The method according to claim 13, further comprising: mapping at least one of the plurality of operands of the consumer instruction to a physical register; and in response to determining that the executed producer instruction does not include an explicit consumer target distance value, writing the production value of the executed producer instruction to the physical register mapped to at least one of the plurality of operands of the consumer instruction.

15. The method according to claim 14, further comprising: accessing the physical register mapped to at least one of the operands of the consumer instruction to retrieve the production value of the executed producer instruction; and providing the retrieved production value as at least one of the plurality of operands of the consumer instruction.

16. A non-transitory computer-readable medium having stored thereon an instruction program, the instruction program including a plurality of computer-executable instructions for execution by a processor, the plurality of computer-executable instructions including: a consumer instruction, including a plurality of operands and a plurality of operand positions, wherein each of the plurality of operands of the consumer instruction corresponds to an operand position among the plurality of operand positions of the consumer instruction; a producer instruction, including an instruction type and an explicit consumer name, the explicit consumer name including a consumer target distance value and an associated consumer operand value, the consumer target distance value representing a relative instruction distance in the instruction stream from the producer instruction, the associated consumer operand value including at least one operand number, each of the operand numbers identifying, by indicating an operand position of an operand among the plurality of operands of the consumer instruction, the operand among the plurality of operands of the consumer instruction to be written by the producer instruction; and a consumer instruction, including an instruction type and a plurality of operands, the consumer instruction being located at an instruction distance from the producer instruction in the instruction program that is the consumer target distance value of the producer instruction, and for each of the plurality of operands of the consumer instruction, the operand position being identified by at least one of the operand numbers of the associated consumer operand value; and the plurality of computer-executable instructions further include: a conditional branch instruction, including a predicate and a conditional branch position, the conditional branch instruction being located between the producer instruction and the consumer instruction in the instruction program, the conditional branch instruction being located in the instruction program at a distance from the producer instruction that is less than the consumer target distance value of the producer instruction; a predicate instruction, including the predicate of the conditional branch instruction, the predicate instruction being located between the producer instruction and the conditional branch instruction in the instruction program; and A predicate producer instruction, located between the predicate instruction and the conditional branch instruction in the instruction program, the predicate producer instruction including the predicate of the conditional branch instruction and a second explicit consumer name, the second explicit consumer name including a second consumer target distance value and a second associated consumer operation value, the second consumer target distance value representing a second relative instruction distance from the predicate producer instruction in the instruction program, the predicate producer instruction being located at a distance of the second consumer target distance value from the consumer instruction in the instruction program; The predicate producer instruction is configured to, in response to the predicate of the predicate instruction being resolved to an untaken state of the conditional branch instruction, cause only the processor to execute the predicate producer instruction to generate a predicate production value for at least one of the plurality of operands of the consumer instruction.

17. The non-transitory computer-readable medium according to claim 16, wherein: The plurality of computer-executable instructions further include a second consumer instruction, the second consumer instruction including a plurality of second operands and a plurality of second operand positions, wherein each second operand of the plurality of second operands of the second consumer instruction corresponds to a second operand position of the plurality of second operand positions of the second consumer instruction; and The producer instruction includes a second explicit consumer name, the second explicit consumer name including a second consumer target distance value and a second associated consumer operation value, the second consumer instruction distance representing a second relative instruction distance from the producer instruction in the instruction stream, the second associated consumer operation value including at least one second operand number, each second operand number identifying, by indicating a second operand position of the second operand of the plurality of second operands of the second consumer instruction, the second operand of the plurality of second operands of the second consumer instruction to be written by the producer instruction.

18. The non-transitory computer-readable medium according to claim 16, the plurality of computer-executable instructions further including: A branch taken instruction, including an evaluation operand, the branch taken instruction being located at the conditional branch position in the conditional branch instruction in the instruction program; And A write-after-write WAW instruction, located between the branch taken instruction and the consumer instruction in the instruction program, the WAW instruction being configured to produce the evaluation operand of the branch taken instruction.

19. A non-transitory computer-readable medium having stored thereon an instruction program, the instruction program including a plurality of computer-executable instructions for execution by a processor, the plurality of computer-executable instructions including: Producer instructions, including an instruction type and an explicit consumer name, the explicit consumer name including a consumer target distance value and an associated consumer operation value, the consumer target distance value representing a relative instruction distance from the producer instruction in an instruction stream, and the associated consumer operation value identifying an operand to be written by the producer instruction; and Consumer instructions, including an instruction type and an operand, the consumer instructions being located at an instruction distance from the producer instruction in the instruction program that is the consumer target distance value of the producer instruction, and the associated consumer operation value of the producer instruction being mapped to the operand of the consumer instruction, The plurality of computer-executable instructions further includes: A conditional branch instruction, including a predicate and a conditional branch position, the conditional branch instruction being located between the producer instruction and the consumer instruction in the instruction program, the conditional branch instruction being located in the instruction program at a distance from the producer instruction that is less than the consumer target distance value of the producer instruction; A predicate instruction, including the predicate of the conditional branch instruction, the predicate instruction being located between the producer instruction and the conditional branch instruction in the instruction program; and A predicate producer instruction, located between the predicate instruction and the conditional branch instruction in the instruction program, the predicate producer instruction including the predicate of the conditional branch instruction and a second explicit consumer name, the second explicit consumer name including a second consumer target distance value and a second associated consumer operation value, the second consumer target distance value representing a second relative instruction distance from the predicate producer instruction in the instruction program, and the predicate producer instruction being located at a distance from the consumer instruction in the instruction program that is the second consumer target distance value; The predicate producer instruction is configured to, in response to the predicate of the predicate instruction resolving to an untaken state of the conditional branch instruction, cause the processor to execute only the predicate producer instruction to generate a predicate production value for the operand of the consumer instruction.

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