Single-event interference stable memory cell

Abstract

A single-event disturbance (SEU) stable memory cell includes: a latch portion including cross-coupled latches; and at least one cross-coupled circuit path in the latch portion including a first pair of vertical resistors connected in series.

Description

Background Technology

[0001] This invention relates to integrated circuit technology. More specifically, this invention relates to memory cells for user-configurable integrated circuits and memory cells stable by single-event disturbance (SEU).

[0002] First see Figure 1 The schematic diagram illustrates an exemplary memory cell 10 including a cross-coupled latch portion (within dashed line 12). This memory cell 10 is disclosed in co-pending U.S. Patent Application Serial No. 16 / 249,291, filed January 16, 2019, and assigned to the same assignee as this application.

[0003] In the cross-coupled latch section 12, the first p-channel transistor 14 and the first p-channel bias transistor 16 are coupled in series to the first voltage supply node V. DD (18) and the first output node 20. The first n-channel transistor 22 and the first n-channel bias transistor 24 are coupled in series to the second voltage supply node V. SS (26) and the first output node 20 (denoted as Out). The gates of the first p-channel transistor 14 and the first n-channel transistor 22 are connected together. The gate of the first p-channel bias transistor 16 is connected to the P-bias voltage source 28, and the gate of the first n-channel bias transistor 24 is connected to the N-bias voltage source 30.

[0004] The second p-channel transistor 32 and the second p-channel bias transistor 34 are coupled in series at the voltage supply node V. DD (18) and the second output node 36 (denoted as Out!). The second n-channel transistor 38 and the second n-channel bias transistor 40 are coupled in series at the voltage supply node V. SS (26) Between the second output node 36 and the second p-channel transistor 32. The gates of the second p-channel transistor 32 and the second n-channel transistor 38 are connected together. The gate of the second p-channel bias transistor 34 is connected to the P-bias voltage source 28, and the gate of the second n-channel bias transistor 40 is connected to the N-bias voltage source 30.

[0005] The first output node 20 is connected via a resistive random access memory (ReRAM) device 42 to the common connection of the gates of the second p-channel transistor 32 and the second n-channel transistor 38. The ReRAM device 42 is a “primitive” ReRAM device, meaning it is identical to a conventional ReRAM device in every way except that it cannot be programmed or erased, and therefore it always remains in a fully erased state at the time of manufacture. This is a high-impedance state, where its resistance depends on the electric field strength but is greater than about 10 MΩ, typically about 1 GΩ. This primitive ReRAM device 42 is very useful because it provides extremely high impedance while taking up almost no layout area on the integrated circuit, as it can be fabricated on existing contacts or inter-metal vias in the integrated circuit structure. The polarity of the ReRAM device 42 is irrelevant. A non-limiting example of a ReRAM device is described in U.S. Patent 8,415,650, issued April 9, 2013, the entire contents of which are incorporated herein by reference. The ReRAM device is essentially two metal plates separated by a solid electrolyte layer. ReRAM devices are typically programmed by applying a voltage potential with polarity that drives metal ions from one of the metal plates into a solid electrolyte layer, and erased by applying a voltage potential with polarity that drives metal ions back to the source metal plate.

[0006] The second output node 36 is connected to the common connection of the gates of the first p-channel transistor 14 and the first n-channel transistor 22. The connection between the output node and the gates of the opposing p-channel and n-channel transistors is known in the art as cross-coupling, and causes one of the output nodes 20, 36 to be in a low logic state while the other output node 20, 36 is in a high logic state. This cross-coupling forces each output node to control the gates of the opposing p-channel and n-channel transistors, thereby resulting in a stable state of the cross-coupled latch portion 12 of the memory cell 10. The first and second p-channel and n-channel bias transistors 16, 34, 24, 40 control the amount of current allowed to flow through the first and second p-channel and n-channel transistors 14, 22, 32, 38 of the cross-coupled latch portion 12 of the memory cell 10.

[0007] In the conventions used herein, the memory cell in question is considered programmed when the first output node 20 is in a high logic state and the second output node 36 is in a low logic state. Conversely, the memory cell in question is considered erased when the first output node 20 is in a low logic state and the second output node 36 is in a high logic state.

[0008] Select transistor 44 is used to couple the first output node 20 to bit line 46 for reading from and writing to the latch portion 12 of memory cell 10. Select transistor 44 is shown as an n-channel transistor, but may also be a p-channel transistor. Bit line 46 is associated with all memory cells in a column of an array of such memory cells. The gate of select transistor 44 is connected to word line 48. Word line 48 is associated with all memory cells in a row of an array of such memory cells. Those skilled in the art will understand that the row and column arrangement of bit line 46 and word line 48 in the memory array of memory cell 10 is conventional in the art, but may be reversed.

[0009] Those skilled in the art will understand that one or both of the first output node 20 and the second output node 36 can be used to control circuit nodes, such as switching transistors, circuit nodes for configuring user-programmable integrated circuits, or programmable connections between the inputs of logic elements such as lookup tables (LUTs) that require a predetermined logic level. Such uses of the memory cell 10 and these connections are well known to those skilled in the art and are therefore not shown to avoid unduly complicating this disclosure.

[0010] SEU immunity is one of the key requirements for FPGA user-programmable integrated circuits used in space applications. The structure of the cross-coupled latch memory cell 10 is designed to support SEU immunity. A native ReRAM 42 is used within the latch to generate the RC delay for SEU immunity. Specifically, if the first output node 20 is high and a particle impact momentarily pulls it down, the combination of the high resistance of the native ReRAM device 42, its capacitance, and the capacitance of the gates of the second n-channel transistor 32 and the second p-channel transistor 38 provides a sufficiently long RC time delay (longer than the duration of the transient) to prevent the voltage at the gates of the second n-channel transistor 32 and the second p-channel transistor 38 from dropping fast enough to turn on the second p-channel transistor 32 and turn off the second n-channel transistor 38. Therefore, the memory cell 10 will retain its state during an SEU event that may occur only at the source / drain (e.g., diffusion of the select transistor 44) rather than at the gate. This type of SEU immunity is achieved at the cost of write speed of memory cell 10, because the write pulse must be applied for a period of time longer than the aforementioned RC time constant. In applications such as cross-coupled latch sections 12 used in user-configurable circuitry, this additional programming overhead is not a problem. Such memory cells with SEU immunity may be referred to herein as SEU-stable memory cells.

[0011] Test chip results have shown that the resistance of the original ReRAM device 42 undergoes significant variations. Furthermore, some ReRAM devices 42 may short-circuit and will not provide the expected SEU protection. Another issue is that the original ReRAM device 42 may be subjected to programming interference conditions during its lifetime, which will change its resistance and adversely affect the SEU immunity of the circuitry in which it is used. Summary of the Invention

[0012] According to one aspect of the invention, a single-event disturbance (SEU) stable memory cell includes: a latch portion including cross-coupled latches; and at least one cross-coupled circuit path located in the latch portion and including a first pair of vertical resistors connected in series.

[0013] According to another aspect of the invention, the memory cell includes a latch portion comprising a cross-coupled latch having complementary output nodes, a first cross-coupled circuit path and a second cross-coupled circuit path, the first cross-coupled circuit path comprising a pair of original resistive random access memory (ReRAM) devices connected in series, and the second cross-coupled circuit path comprising a pair of original resistive random access memory (ReRAM) devices connected in series.

[0014] According to another aspect of the invention, a programmable read-only memory (PROM) portion is coupled to one of the complementary output nodes of a latch portion, the PROM portion including a programmable and erasable ReRAM device.

[0015] According to another aspect of the invention, the programmable and erasable ReRAM device is coupled to one of the complementary output nodes of the latch portion via an access transistor.

[0016] According to another aspect of the invention, the latching portion includes a first p-channel transistor coupled between a first voltage supply node and a first complementary output node in a complementary output node, a first n-channel transistor coupled between the first complementary output node and a second voltage supply node in the complementary output node, a second p-channel transistor coupled between the first voltage supply node and the first complementary output node in the complementary output node, and a second n-channel transistor coupled between the first complementary output node and the second voltage supply node in the complementary output node. The gates of the first p-channel transistor and the first n-channel transistor are together connected to the second complementary output node in the complementary output node, and the gates of the second p-channel transistor and the second n-channel transistor are together connected to the first complementary output node in the complementary output node.

[0017] According to another aspect of the invention, the gates of the second p-channel transistor and the second n-channel transistor are connected together to the first complementary output node in the complementary output node via a pair of original ReRAM devices connected in series.

[0018] According to another aspect of the invention, the gates of the first p-channel transistor and the first n-channel transistor are connected together to a second complementary output node in the complementary output node via a pair of original ReRAM devices connected in series.

[0019] According to another aspect of the invention, the gates of the second p-channel transistor and the second n-channel transistor are connected together to the first complementary output node in the complementary output node via a first pair of original ReRAM devices connected in series, and the gates of the first p-channel transistor and the first n-channel transistor are connected together to the second complementary output node in the complementary output node via a second pair of original ReRAM devices connected in series.

[0020] According to another aspect of the invention, a first p-channel transistor is coupled between a first voltage supply node and a first complementary output node in the complementary output node array via a first p-channel bias transistor; a first n-channel transistor is coupled between the first complementary output node and a second voltage supply node in the complementary output node array via a first n-channel bias transistor; a second p-channel transistor is coupled between the first voltage supply node and the first complementary output node in the complementary output node array via a second p-channel bias transistor; and a second n-channel transistor is coupled between the first complementary output node and the second voltage supply node in the complementary output node array via a second n-channel bias transistor. The first p-channel bias transistor and the second p-channel bias transistor have gates coupled to a P-bias line in the array, and the first n-channel bias transistor and the second n-channel bias transistor have gates coupled to an N-bias line in the array.

[0021] According to another aspect of the invention, memory cells are arranged in an array of memory cells. One of the complementary output nodes of the cross-coupled latch portion is coupled to a bit line in the array via an n-channel access transistor having a gate coupled to a word line in the array, and a p-channel access transistor having a gate coupled to a PROM word line in the array. Attached Figure Description

[0022] The invention will now be explained in more detail with reference to the embodiments and accompanying drawings, in which:

[0023] Figure 1 This is a schematic diagram of the cross-coupled latch section of a memory cell;

[0024] Figure 2This is a schematic diagram of the cross-coupled latch portion of a SEU-stable memory cell according to an aspect of the present invention;

[0025] Figure 3 This is a schematic diagram of an alternative embodiment of the cross-coupled latch portion of a SEU-stable memory cell according to an aspect of the present invention;

[0026] Figure 4 This is a schematic diagram of another alternative embodiment of the cross-coupled latch portion of the SEU-stable memory cell according to an aspect of the present invention;

[0027] Figure 5 This is a schematic diagram of yet another alternative embodiment of the cross-coupled latch portion of the SEU-stable memory cell according to aspects of the present invention;

[0028] Figure 6 This is a schematic diagram of a PROM cell based on ReRAM, which can be used in conjunction with the latch portion of the SEU-stable memory cell of the present invention, which is cross-coupled.

[0029] Figure 7 This is a schematic diagram of an exemplary circuit for providing power to the latch portion of the memory cell of the present invention with high impedance.

[0030] Figure 8 This is a schematic diagram of an exemplary switching transistor circuit that can be used when the memory cell of the present invention is used as a configuration memory cell in a user programmable integrated circuit;

[0031] Figure 9 This is a voltmeter showing the typical voltages applied during different operating modes of the memory cells of the present invention;

[0032] Figure 10 A cross-sectional view of an example of an anti-fuse device structure that can be used as a vertical resistor in an embodiment of the present invention;

[0033] Figure 11 This is a cross-sectional view of an example of the original ReRAM device structure that can be used as a vertical resistor in an embodiment of the present invention;

[0034] Figure 12 A cross-sectional view of an example of another high-resistance structure that can be used as a vertical resistor in an embodiment of the present invention;

[0035] Figure 13 This is a block diagram illustrating the features of an array of SEU-stable memory cells according to an aspect of the present invention;

[0036] Figure 14 This is a flowchart illustrating an exemplary method for operating the memory cell of the present invention;

[0037] Figure 15A and Figure 15B These are schematic diagrams of a pair of ReRAM devices connected in series according to aspects of the present invention, and cross-sectional views of ReRAM devices formed as a stack implemented in silicon; and

[0038] Figures 16A to 16F yes Figure 15B A cross-sectional view of the ReRAM stack shows the selected progressive manufacturing steps used to manufacture the ReRAM stack as part of a semiconductor manufacturing process. Detailed Implementation

[0039] Those skilled in the art will recognize that the following description of the invention is merely exemplary and not intended to be limiting in any way. Other embodiments of the invention will be readily apparent to those skilled in the art.

[0040] See now Figure 2 The schematic diagram illustrates an embodiment of a cross-coupled latch portion (within dashed lines 52) of a memory cell 50 according to an aspect of the invention. The latch portion 52 of the memory cell 50 is similar to... Figure 1 The latch portion 12 of the memory cell 10, and similar elements in the two circuits will be referred to using the same reference numerals.

[0041] exist Figure 2 In the cross-coupled latch section 52 of the memory cell 50, the first p-channel transistor 14 and the first p-channel bias transistor 16 are coupled in series between the first voltage supply node VDD (18) and the first output node 20 (denoted as Out). The first n-channel transistor 22 and the first n-channel bias transistor 24 are coupled in series between the second voltage supply node VDD (18) and the first output node 20 (denoted as Out). SS (26) and the first output node 20. The gates of the first p-channel transistor 14 and the first n-channel transistor 22 are connected together. The gate of the first p-channel bias transistor 16 is connected to the P-bias voltage source 28, and the gate of the first n-channel bias transistor 24 is connected to the N-bias voltage source 30.

[0042] The second p-channel transistor 32 and the second p-channel bias transistor 34 are coupled in series at the voltage supply node V. DD (18) and the second output node 36 (denoted as Out!). The second n-channel transistor 38 and the second n-channel bias transistor 40 are coupled in series at the voltage supply node V. SS(26) Between the second output node 36 and the second p-channel transistor 32. The gates of the second p-channel transistor 32 and the second n-channel transistor 38 are connected together. The gate of the second p-channel bias transistor 34 is connected to the P-bias voltage source 28, and the gate of the second n-channel bias transistor 40 is connected to the N-bias voltage source 30.

[0043] The first output node 20 is connected to the common connection of the gates of the second p-channel transistor 32 and the second n-channel transistor 38 via a pair of series-connected resistive random access memory (ReRAM) devices 54 and 56.

[0044] ReRAM devices 54 and 56 are “original” ReRAM devices, as described above regarding ReRAM device 42. The polarity of ReRAM devices 54 and 56 is not critical, but they occupy a minimal layout area when oriented face-to-face (their ion source regions facing away from each other) or back-to-back (their ion source regions facing each other). As will be further described below, ReRAM devices 54 and 56 are specific embodiments of vertical resistors.

[0045] The second output node 36 is connected to the common connection of the gates of the first p-channel transistor 14 and the first n-channel transistor 22. The connection between the output node and the gates of the opposing p-channel and n-channel transistors is known in the art as cross-coupling, and causes one of the output nodes 20, 36 to be in a low logic state while the other output node 20, 36 is in a high logic state. This cross-coupling forces each output node to control the gates of the opposing p-channel and n-channel transistors, thereby resulting in a stable state of the cross-coupled latch portion 12 of the memory cell 10. The first and second p-channel and n-channel bias transistors 16, 34, 24, 40 control the amount of current allowed to flow through the first and second p-channel and n-channel transistors 14, 22, 32, 38 of the cross-coupled latch portion 12 of the memory cell 10.

[0046] Select transistor 44 is used to couple the first output node 20 to bit line 46 for reading from and writing to the latch portion 12 of memory cell 10. Select transistor 44 is shown as an n-channel transistor, but may also be a p-channel transistor. Bit line 46 is associated with all memory cells in a column of an array of such memory cells. The gate of select transistor 44 is connected to word line 48. Word line 48 is associated with all memory cells in a row of an array of such memory cells. Those skilled in the art will understand that the row and column arrangement of bit line 46 and word line 48 in the memory array of memory cell 50 is conventional in the art, but may be reversed.

[0047] Those skilled in the art will understand that one or both of the first output node 20 and the second output node 36 can be used to control circuit nodes, such as switching transistors, circuit nodes for configuring user-programmable integrated circuits, or programmable connections between the inputs of logic elements such as lookup tables (LUTs) that require a predetermined logic level. Such uses of memory cell 50 and these connections are well known to those skilled in the art and are therefore not shown to avoid unduly complicating this disclosure.

[0048] The memory cell 50 of this invention provides enhanced SEU protection. Specifically, if the first output node 20 is in a high state and a particle impact momentarily pulls it down, the combination of the high resistance of the original ReRAM devices 54 and 56, their capacitance, and the capacitance of the gates of the second n-channel transistor 32 and the second p-channel transistor 38 provides a sufficiently long RC time delay (longer than the duration of the transient) to prevent the voltage at the gates of the second n-channel transistor 32 and the second p-channel transistor 38 from dropping fast enough to turn on the second p-channel transistor 32 and turn off the second n-channel transistor 38 during the transient (typically between approximately 1 ns and 10 ns). The typical RC time constant of a pair of original ReRAM devices and gate capacitances connected in series is approximately 1 μs. During the transient, this RC time delay holds the gate transistors 14 and 22 feed node 20 in the state it was in before the transient to prevent the cross-coupled latch portion 12 in the memory cell 50 from changing state. Therefore, by utilizing a pair of original ReRAM devices 54 and 56 connected in series, the memory cell 50 is protected from particle impacts in its high state. Those skilled in the art will recognize that erasing the memory cell 50 to a low state would require a longer pulse than would be required without the pair of original ReRAM devices 54 and 56 connected in series; however, since the memory cell 50 is not frequently reprogrammed or erased, this is not a problem.

[0049] The two series-connected ReRAM devices 54 and 56 allow for redundancy against ReRAM device short circuits and also tighten ReRAM impedance spread without reducing SRAM speed. The back-to-back connection of the two series-connected ReRAM devices 54 and 56 eliminates any ReRAM device interference conditions. Therefore, this memory cell 50 provides a robust SEU immunity solution.

[0050] See now Figure 3 The schematic diagram illustrates an alternative embodiment of the latch portion 62 of the memory cell 60 according to an aspect of the invention. The memory cell 60 is similar to... Figure 2 The memory unit 50, and similar elements in both embodiments will be indicated using the same reference numerals.

[0051] Figure 3 memory cell 60 and Figure 2 The difference between the memory cells 50 is that, compared to the cross-coupled latch section 52, the cross-coupled latch section 62 employs an additional pair of original ReRAM devices 64 and 66 connected in series. As will be further described below, the ReRAM devices 64 and 66 are a specific implementation of vertical resistors. Figure 2 In memory cell 50, as in Figure 3 In memory cell 60, the first output node 20 is connected to the common connection of the gates of the second p-channel transistor 32 and the second n-channel transistor 38 via a first pair of series-connected original ReRAM devices 54 and 56. Figure 3 In one implementation, the second output node 36 is also connected to the common connection of the gates of the first p-channel transistor 14 and the first n-channel transistor 22 via a second pair of original ReRAM devices 64 and 66 connected in series.

[0052] Those skilled in the art will readily understand, Figure 3 In the implementation scheme, the two pairs of original ReRAM devices 54 and 56 and 64 and 66 are connected in series to... Figure 2 The original ReRAM devices 54 and 56, connected in series in the implementation scheme, function in exactly the same way. Figure 3 The implementation uses two pairs of series-connected original ReRAM devices 54 and 56, and 64 and 66, to provide additional redundancy in case one or both of the ReRAM devices 54, 56, 64, and 66 short-circuit due to manufacturing defects. Furthermore, the additional original ReRAM devices 64 and 66 provide symmetrical fault recovery from the two output nodes Out 20 and Out 36.

[0053] In some applications where transients (e.g., the routing path of control clock signals) are intolerable, a filtered output can be obtained from a node shared by the gates of one of the original ReRAM devices (56 or 64) and the transistors (32 and 38 or 14 and 22) in the cross-coupled latch section 62 driven by it. This node is a high-impedance output node but has greater transient immunity than output nodes 20 and 36.

[0054] See now Figure 4 The schematic diagram illustrates another alternative embodiment of an SEU-stabilized memory cell 70 including a cross-coupled latch portion 72 according to an aspect of the invention. Figure 4 memory cell 70 and Figure 2The difference between the memory cells 50 is that the first output node 20 of the cross-coupled latch section 72 is connected to the common connection of the gates of the second p-channel transistor 32 and the second n-channel transistor 38 via a pair of vertical resistors 74 and 76 connected in series (which, as described above, can be embodied in the original ReRAM device or other embodiments of vertical resistors).

[0055] Vertical resistors 74 and 76 are high-resistivity resistors formed from continuous layers during semiconductor manufacturing processes. Vertical resistors typically have a resistance in the range of about 1 MΩ to about 1 GΩ. As will be disclosed herein, vertical resistors 74 and 76 can take any of several forms. Examples of vertical resistors contemplated for use in the present invention are... Figures 9 to 11 The symbols at reference numerals 74 and 76, used to specify the vertical resistors, will be used to specify all of the several forms the vertical resistors may take. This document will disclose the operation of vertical resistors 74 and 76 in providing radiation tolerances to memory cell 70.

[0056] A pair of vertical resistors 74 and 76 connected in series stabilize memory cell 70 to prevent transient pulses from radiation, as described above with respect to the ReRAM devices 54 and 56 of the cross-coupled latch section 52. In prior art cross-coupled latch memory cells, a particle impact can cause a transient that pulls down one of the output nodes 20 and 36 held at a high logic level because its p-channel transistor is turned on and its n-channel transistor is turned off from the low logic level at the complementary output node. The high output node pulled down by the particle impact is directly coupled to the gates of both the p-channel transistor and the n-channel transistor, which are coupled in series with the complementary output node held low. This action tends to turn on the p-channel transistor and turn off the n-channel transistor, which is coupled in series with the output node held low. Due to the cross-coupling of the output node and the transistor gates, the state of the memory cell can easily flip to an error state.

[0057] In the memory cell 70 of the present invention, if the first output node 20 is in a high state and a particle impact momentarily pulls it down, the combination of the high resistance of a pair of series-connected vertical resistors 74 and 76, their capacitance, and the capacitance of the gates of the second n-channel transistor 32 and the second p-channel transistor 38 provides a sufficiently long RC time delay (longer than the duration of the transient) to prevent the voltage at the gates of the second n-channel transistor 32 and the second p-channel transistor 38 from dropping sufficiently quickly during the time the voltage at the first output node 20 is transiently reduced (typically between about 1 ns and 10 ns) to turn on the second p-channel transistor 32 and turn off the second n-channel transistor 38. The typical RC time constant of the vertical resistors (with a typical resistance on the order of about 1 MΩ to greater than about 1 GΩ) and the gate capacitance according to the present invention is about 1 μS, thereby preventing the output node from changing state during the transient duration. Therefore, the memory cell 70 is protected against particle impacts from the series-connected pair of vertical resistors 74 and 76. Those skilled in the art will recognize that erasing memory cell 70 to a low state would require a longer pulse than would be required in the absence of a pair of vertical resistors 74 and 76 connected in series; however, memory cell 70 is not frequently reprogrammed or erased, so this is not a concern.

[0058] See now Figure 5 The schematic diagram illustrates another alternative embodiment of an SEU-stable memory cell 80 including a cross-coupled latch portion 82 according to aspects of the present invention. The memory cell 80 is similar to... Figure 4 The memory cell 70, and similar elements in both embodiments will be referred to using the same reference numerals.

[0059] Figure 5 memory cell 80 and Figure 4 The difference between the memory cells 70 is the use of an additional pair of vertical resistors 84 and 86 connected in series in the cross-coupled latch 82. (As in...) Figure 4 In memory cell 70, as in Figure 5 In the memory cell 80, the first output node 20 is connected to the common connection of the gates of the second p-channel transistor 32 and the second n-channel transistor 38 via a first pair of vertical resistors 74 and 76 connected in series. Figure 5 In the implementation scheme, the second output node 36 is also connected to the common connection of the gates of the first p-channel transistor 14 and the first n-channel transistor 22 via a second pair of vertical resistors 84 and 86 connected in series. SEU protection mechanism and related Figure 4 The same applies, but this also extends to the second output node 36.

[0060] Outputs from memory cells 50, 60, 70, and 80 can be obtained from output node 20 or from output node 36, and it is not required that both output nodes be available outside the memory cells. This disclosure has shown a selection transistor 44 connected to output node 20; however, those skilled in the art will readily understand that in some embodiments of the invention, selection transistor 44 can be configured to couple bit line 46 to output node 36.

[0061] See now Figure 6 The schematic diagram illustrates a ReRAM-based programmable read-only memory (PROM) cell 90, which can be used in conjunction with the cross-coupled latch portion of the memory cell of the present invention. According to one aspect of the invention, a first output node 20 or a second output node 36 of the cross-coupled latch portion 12 of any memory cell of the present invention can be coupled to a ReRAM-based PROM cell 90, which includes a ReRAM device 92 coupled to the output node 20 (or 36) via a PROM select transistor 94. The PROM select transistor 94 is shown as a p-channel transistor, but may also be an n-channel transistor. The ReRAM device 92 is also coupled to a bias voltage source VB (96). The gate of the p-channel PROM select transistor 94 is coupled to the PROM word line shown by reference numeral 98 in the reference numeral.

[0062] The ReRAM-based PROM cell 90 can be used to initialize the cross-coupled latch portions 52, 62, 72, and 82 of the memory cells under the circuit conditions disclosed herein. Therefore, for each cross-coupled latch portion 52, 62, 72, and 82, there is an associated ReRAM-based PROM cell 90. As will be further described below, this arrangement allows data to be loaded from the associated ReRAM-based PROM cell 90 into the cross-coupled latches 52, 62, 72, and 82, while preferably further providing the ability to directly write data into the cross-coupled latch portions 52, 62, 72, and 82 in the event of a failure of the associated ReRAM-based PROM cell 90.

[0063] During the "normal operation" of the memory cells 50, 60, 70, or 80 of the present invention (meaning when the corresponding cross-coupled latch portions 52, 62, 72, or 82 are used to control one or more circuit nodes in the integrated circuit, unlike the programming or erasing operation of the memory cells 50, 60, 70, or 80), it is preferable to use V DDVoltage node 18 provides a voltage source with an output impedance greater than approximately 10 kΩ. Connecting 1.5V to the P+ source of transistors 14 and 32 via a low-impedance voltage source is dangerous, as this can cause SCR latch-up. Those skilled in the art will recognize that a parasitic PNPN bipolar device is formed by the p+ contacts supplying power to p-channel transistors 14 and 32, the n-wells forming them, any adjacent p-wells containing the n-channel transistors, and the n+ region forming the source or drain of the n-channel transistor within the p-well. This n+ region is typically grounded. Particle impacts momentarily forward bias the junction between the p+ contacts supplying power to the p-channel transistors and the n-well forming the p-channel transistor, which is typically at V... DD The lower bias provides a potential that causes these parasitic bipolar transistors (SCRs) to latch up. Since two Vbe, or approximately 1V, are required to induce latch-up, if V... DD If the voltage is less than 1V, the latch can be ignored. Typically, approximately 1mA of current is required to maintain the latch in order to keep the voltage drop in the trap. Therefore, according to one aspect of the invention, at V... DD When the power supply provides a voltage greater than about 1V, it is preferable to apply the voltage with an impedance greater than about 1KΩ, preferably about 10KΩ. DD The voltage is set to provide a reasonable margin, where the impedance provides a voltage drop sufficient to prevent latch-up. This can be accomplished using a resistor or a transistor, preferably an n-channel transistor.

[0064] Figure 7 This is a schematic diagram of circuit 100, which shows the use of an n-channel transistor 102 to provide this type of high-impedance voltage source. In the desired V... DD In the 1.5V implementation, the drain 104 of the n-channel transistor 102 is driven by a 1.5V voltage source, the gate 106 of the n-channel transistor 102 is driven by a 1.9V voltage source, and the source 108 of the n-channel transistor 102 serves as the V source for the memory cell 50. DD Voltage supply node 18. Preferably, an n-channel transistor 102 configured to provide the required impedance described above is used instead of a p-channel transistor, even though a p-channel transistor can provide a constant current when configured as a source follower. Using an n-channel transistor 102 biased above ground and formed in the semiconductor substrate prevents the circuit from experiencing SCR latch-up operation.

[0065] Figure 2 , Figure 3 , Figure 4 and Figure 5 SEU-stable memory cells are particularly well-suited for use as configuration memory cells to configure circuit functions and interconnect paths in user-programmable integrated circuits such as FPGAs. In such applications, the output node Out or Out! 20 or 36 drives the switching transistor 110 (shown as an n-channel transistor), as... Figure 8As shown, the gate 112 of the switching transistor 110 is shown as connected to Figure 2 , Figure 3 , Figure 4 and Figure 5 The SEU-stable memory cell 50, 60, 70, or 80 has an Out node 20. The drain 114 and source 116 of the switching transistor 110 form a configurable circuit path that is connected when the output node of the SEU-stable memory cell is in a high logic state.

[0066] See now Figure 9 The voltmeter displays a representative voltage applied to the SEU-stabilized memory cell of the present invention during various operating modes. Figure 9 The first row of the voltmeter shows an exemplary voltage applied during normal operating mode (i.e., when the cell is used to control the switching transistor). Figure 9 The voltmeter used is V DD The power supply voltage is 1.5V.

[0067] During normal operation of the memory cell of this invention, a high-impedance 1.5V voltage source is coupled to V. DD Node 16, and V SS Node 24 is at 0V. The bit line 46 of the memory cell in the array is biased to 0.8V, the common word line 48 of the memory cell is biased to 0V, and the common P-bias line 28 and N-bias line 30 of the memory cell are biased to 0.8V. During operation mode, this sets the current level across the memory cell in this exemplary embodiment to approximately 50μA. This current level prevents any interference with the state of the memory cell during read operations and limits Vds on all word line select transistors 44 to a maximum of 0.8V.

[0068] The VB node 96 of the ReRAM-based PROM cell 90 associated with the memory cell is biased to 0.8V, and the PROM word line 98 controlling the gate of the p-channel PROM select transistor 94 is biased to 1.5V. Under these conditions, the select transistor 44 of the memory cell is turned off. The PROM select transistor 94 of the memory cell has 1.5V on its gate and is also turned off, thereby disconnecting the PROM ReRAM device 92 from the first output node 20 of the cross-coupled latch section 12 in the memory cell.

[0069] Figure 9 The second row of the voltmeter shows an exemplary voltage applied according to an aspect of the invention to program a selected ReRAM device 92 of a PROM-based ReRAM cell 90, the selected ReRAM device being associated with a memory cell in a selected row of an array of such memory cells.

[0070] The ReRAM device 92 of a specific memory cell in the row will be programmed, that is, set to its low impedance state, while other ReRAM devices 92 in other memory cells in the selected row will not be programmed, but will remain in their previous state.

[0071] Therefore, V DD Node 18 is provided with 1V at high impedance, and V SS Node 26 is provided with 1V. The row-shared word line 48 containing the ReRAM device 92 to be programmed is biased at 1.3V to control the programming current. This turns on the select transistor 44 for all memory cells in the selected row. The row-shared PROM word line 98 containing the ReRAM device 92 to be programmed is biased at -0.8V, thereby turning on the PROM select transistor 94 in that row. The VB line 96, shared by one or more memory cells in the array (depending on the designer's architectural preference), is biased at 1.8V. The row-shared P-bias line 28 containing the ReRAM device 92 to be programmed is biased at 1.8V, thereby turning off all p-channel bias transistors 16 and 34 in the selected row. The row-shared N-bias line 30 containing the ReRAM device 92 to be programmed is biased at 0V, thereby turning off all n-channel bias transistors 24 and 40 in the selected row. DD and V SS With all transistors set to the same voltage (1V) and all p-channel and n-channel bias transistors turned off, the cross-coupled latch 12 of the memory cell in the selected row is disabled. The voltage at the first output node 20 of the cross-coupled latch 12 of the memory cell in the row to be programmed changes as the programming process proceeds.

[0072] If bit line 46 in the column containing the ReRAM device 92 to be programmed is set to 0V, this voltage is applied to the first output node 20 of the latch section 12 of the memory cell containing the ReRAM device 92 to be programmed. This applies 1.8V to the ReRAM device 92 (1.8V at VB 96, and 0V from bit line 46 via select transistor 44 and PROM select transistor 94). This causes the ReRAM device 92 to draw current, thus programming it to a low-impedance state. As the resistance of the ReRAM device 92 decreases, the voltage at the output node 20 of the memory cell rises toward 1.8V when the ReRAM device 92 reaches its lowest resistance state.

[0073] If bit line 46 in a column containing an unprogrammed ReRAM device 92 is set to 1.8V, this voltage is applied to the first output node 20 of the latch section 12 containing the memory cell containing the unprogrammed ReRAM device 92. This places zero volts on the ReRAM device 92 (1.8V at VB and 1.8V at the first output node 20), which prevents it from being programmed or erased.

[0074] Figure 9 The third row of the voltmeter shows exemplary voltages applied to memory cells in unselected rows of an array of such memory cells according to aspects of the invention, to prevent programming of any ReRAM devices 92 in the unselected rows.

[0075] In the unselected rows of memory cells, all voltage potentials applied to various circuit nodes are related to... Figure 9 The second row of the voltmeter is the same as shown, but with two exceptions. The PROM word line 98 shared by the unselected rows is biased at 1.8V. This turns off all p-channel PROM select transistors 94 in the unselected rows. Applying 0V to word line 48 turns off all n-channel select transistors 44 in the unselected rows, causing the first output node 20 of all cross-coupled latch portions of the memory cells in the unselected rows to float. No voltage potential is applied to any ReRAM device 92 in the unselected rows, and thus prevents programming or erasing of any ReRAM device 92 in the unselected rows.

[0076] Figure 9 The fourth row of the voltmeter shows an exemplary voltage applied according to an aspect of the invention to erase a selected ReRAM device 92 associated with a memory cell in a selected row of an array of such memory cells.

[0077] V DD Node 18 is provided with 1V at high impedance, and V SS Node 26 is provided with 1V. The row-shared word line 48 containing the ReRAM device 92 to be erased is biased to 2.5V. The VB line 96 connected to the ReRAM device 92 to be erased is biased to 0V. The row-shared P-bias line 28 containing the ReRAM device 92 to be erased is biased to 1.8V, thereby turning off all p-channel bias transistors 16 and 34 in that row. The row-shared N-bias line 30 containing the ReRAM device 92 to be erased is biased to 0V, thereby turning off all n-channel bias transistors 24 and 36 in that row. DD and V SS With all transistors set to the same voltage (1V) and all p-channel and n-channel bias transistors turned off, all cross-coupled latches 12 of the memory cell are disabled.

[0078] The row-shared word line 48 containing the ReRAM device 92 to be erased is biased to 2.5V. The row-shared PROM word line 98 containing the ReRAM device 92 to be erased is biased to 0.5V. Under these conditions, the select transistor 44 in the selected row is turned on, and the PROM select transistor 98 is coupled to the ReRAM device 92 in the selected row.

[0079] Bit line 46 in the column containing ReRAM device 92 is set to 1.8V, which is applied to the first output node 20 of the latch portion 52, 62, 72, or 82 of the memory cell associated with the ReRAM device 92 to be erased. This places 1.8V on the ReRAM device 92 to be erased (0V at VB and 1.8V at the first output node 20 in response to bit line 44 of select transistor 44). This causes the ReRAM device 92 to draw current, thereby creating an erase current. As the resistance of the ReRAM device 92 increases, the voltage at the output node 20 of the memory cell associated with the ReRAM device 92 rises from 0V at node 96 of VB, eventually reaching 1.8V as the ReRAM device 92 reaches its highest resistance state and stops drawing measurable current. Those skilled in the art will understand that the polarity of this erase voltage is opposite to the polarity of the voltage applied for programming, such as... Figure 9 The second row of the table is shown.

[0080] The bit line 46 in the column containing the ReRAM device 92 is set to 0V, and this voltage is applied to the first output node 20 of the latch section 52, 62, 72, or 82 of the memory cell via its selection transistor 44. This places zero volts on the ReRAM device 92 (0V at VB and 0V at the first output node 20), which prevents it from being erased.

[0081] Figure 9 The fifth row of the voltmeter shows an exemplary voltage applied to memory cells in an unselected row of an array of such memory cells according to an aspect of the invention to prevent erasure of any ReRAM device 92 in the unselected row.

[0082] In the unselected rows of memory cells, all voltage potentials applied to various circuit nodes are related to... Figure 9The fourth row of the table is the same, but with two exceptions. The PROM word line 98 shared by the unselected rows is biased at 1.8V. This turns off all PROM select transistors 94 in the unselected rows. The 0V applied to word line 48 turns off all n-channel select transistors 44 in the unselected rows, thereby floating the first output node 20 of all latch portions 52, 62, 72, or 82 in the unselected rows. This results in no voltage potential being applied to any ReRAM device 92 in the unselected rows and prevents erasure of any ReRAM device 92 in the unselected rows.

[0083] Figure 9 The sixth row of the voltmeter shows an exemplary voltage applied to a selected row of memory cells in an array of such memory cells to write a cross-coupled latch portion in a memory cell according to the invention, without reference to data stored in the associated ReRAM-based PROM cell 90.

[0084] V DD Node 18 is provided with 0.8V at high impedance, and V SS Node 26 is provided with 0V. The word line 48 shared by the selected row is biased at 1.5V. The PROM word line 98 shared by the selected row is biased at 0.8V. The VB line 96 connected to the memory cell is biased at 0.8V. The P-bias line 28 shared by the selected row is biased at 0.4V. The N-bias line 28 shared by the selected row is biased at 0.4V. This allows approximately 1μA of current to flow through all p-channel bias transistors 16 and 34 and n-channel bias transistors 24 and 40 in the selected row.

[0085] Under these conditions, the select transistor 44 in the selected row is turned on, and the PROM select transistor 94 coupled to the ReRAM device 92 in the selected row is turned off.

[0086] Bit line 46 in the column of latch sections 52, 62, 72, or 82 containing the memory cell to be written is set to 0V, and this voltage is applied to the first output node 20 of latch sections 52, 62, 72, or 82. The voltage at the gate of the second p-channel transistor 32 and the second n-channel transistor 38 drops to 0V with a time constant equal to the resistance of the vertical resistors 74 and 76, which can be achieved as described above by... Figure 2 This is achieved using the original ReRAM devices 54 and 56, along with the combined capacitance of the gates of the second p-channel transistor 32 and the second n-channel transistor 38. As the voltage at the gates of the second p-channel transistor 32 and the second n-channel transistor 38 decreases, the second p-channel transistor 32 turns on as the second n-channel transistor 38 turns off. This action pulls the second output node 36 up to 0.8V, i.e., to V. DDThis turns off the first p-channel transistor 14 and turns on the first n-channel transistor 22, causing the first output node 20 to drop to zero volts, thus completing the writing of the cross-coupled latch section 12 to the logic 0 state.

[0087] If bit line 46 in the column of latch section 12 containing the memory cell to be written is set to 0.8V, this voltage is applied to the first output node 20 of latch section 12. The voltage at the gates of the second p-channel transistor 32 and the second n-channel transistor 38 rises to 0.8V with a time constant equal to the resistance of the vertical resistors 74 and 76, as described above, which can be achieved by the combined capacitance of the original ReRAM devices 54 and 56 and the gates of the second p-channel transistor 32 and the second n-channel transistor 38. As the voltage at the gates of the second p-channel transistor 32 and the second n-channel transistor 38 rises, the second p-channel transistor 32 turns off and the second n-channel transistor 38 turns on. This action pulls the second output node 36 down to 0V, thereby turning on the first p-channel transistor 14 and turning off the first n-channel transistor 22, thereby pulling the first output node 20 up to 0.8V to write the cross-coupled latch sections 52, 62, 72, or 82 of the memory cell to a logic 1 state.

[0088] Figure 9 The seventh row of the voltmeter shows an exemplary voltage applied according to the invention to memory cells in an unselected row of an array of such memory cells to prevent writing to cross-coupled latches in memory cells in an unselected row.

[0089] Apply to Figure 9 The voltage of the memory cell in the seventh row of the voltmeter is related to the voltage applied to... Figure 9 The voltages in the sixth row of the voltmeter are the same, except that the voltage at word line 48, which is shared by all memory cells in the unselected row, is set to 0V. Because the selection transistor 44 is turned off, the voltage at bit line 46 is not transmitted to the first output node 20 of any of the latch portions 12 of the memory cells, thereby preventing writes to any of the cross-coupled latch portions 52, 62, 72, or 82 in the unselected row.

[0090] Figure 9 The eighth row of the voltmeter shows an exemplary voltage applied according to the invention to the latch portion 12 of the memory cells to write zero (i.e. erase) to all memory cells in the rows of the array at startup.

[0091] In order to perform this write operation, V DD Node 18 is provided with 0.8V at high impedance, and V SS Node 26 is provided with 0V. All bit lines 46 are set to 0V.

[0092] The row-shared word line 48 is biased at 1.5V, thereby turning on all select transistors 44. The row-shared PROM word line 98 is biased at 0.8V, thereby turning off all PROM select transistors 94. The row-associated VB line 96 is biased at 0.8V. The row-shared P-bias line 28 is biased at 0.4V. The row-shared N-bias line 30 is biased at 0.4V. This allows approximately 1μA of current to pass through all p-channel bias transistors 14 and 32 and n-channel bias transistors 22 and 28.

[0093] With bit line 46 at 0V and select transistor 44 on, 0V is applied to the first output node 20 of all latch portions 12 in the row. After an RC time delay from the resistances of vertical resistors 74 and 76, the second output node 36 drops to 0V, turning on p-channel transistor 32 and turning off n-channel transistor 38. As noted above, this RC time delay can be achieved by the original ReRAM devices 54 and 56 combined with the combined capacitance of p-channel transistor 32 and n-channel transistor 38. This action pulls the second output node 36 up to 0.8V, turning off the first p-channel transistor 14 and turning on the first n-channel transistor 22, thereby writing all cross-coupled latch portions 12 of the memory cells in the selected row to a zero logic state.

[0094] Figure 9 The ninth row of the voltmeter shows an exemplary voltage applied to the memory cell by a cross-coupled latch 12 to write the contents of all ReRAM-based PROM cells 90 in all rows to the memory cell.

[0095] In accordance with the above reference Figure 9 After all cell zero write processes described in the eighth row of the table, the contents of all ReRAM-based PROM cells 90 in all rows are now written to the cross-coupled latches 12 of their associated memory cells. DD Node 18 is provided with a high impedance of 0.8V to minimize stress on the transistor source and drain, and V SS Node 26 is provided with 0V. Bit line 46 is set to 0V.

[0096] The word line 48 shared by rows of memory cells containing the contents of associated ReRAM-based PROM cells 90 is biased at 0V, thereby turning off all select transistors 44. The row-shared PROM word line 98 is biased at 0.5V, thereby turning on all PROM select transistors 94 in that row, limiting the current flowing through them to approximately 10μA or the voltage across them to approximately 0.4V. The P-bias line 28 shared by all rows containing memory cells is biased at 0.4V. The N-bias line 30 shared by all rows is biased at 0.4V. This allows approximately 1μA of current to flow through all p-channel bias transistors 16 and 34 and all n-channel bias transistors 24 and 40.

[0097] After all these voltage potentials have been applied, the VB line 96 connected to all cells in the array or block to be written to ramps up from 0V to 0.8V. This causes the voltage at the first output node 20 in the memory cell whose PROM ReRAM has been programmed to be in its ON state to rise. After a delay through the original ReRAM devices 54 and 56, the voltage at the common gate of the second p-channel transistor 32 and the second n-channel transistor 38 rises, turning off the second p-channel transistor 32 and turning on the second n-channel transistor 38, thereby pulling down the second output node 36. This pulls down the voltage at the common gate of the first p-channel transistor 14 and the second n-channel transistor 22, thereby turning on the first p-channel transistor 14 and turning off the first n-channel transistor 22, thereby latching the voltage on the first output node 20 to program the configuration memory cell to a logic 1 state.

[0098] The voltage at the first output node 20 of the memory cell in the PROM ReRAM device 92 that has been erased to its off state (i.e., its high impedance state) will not change from 0V because the PROM ReRAM device 92 is erased to its off state even if the voltage at the VB line 96 rises. Therefore, these memory cells remain in the logic 0 state set, as described with respect to line 8.

[0099] Figure 9 The tenth line of the voltmeter shows an aspect of the invention in which reference has been performed. Figure 9 The second line of the voltmeter discloses an exemplary voltage applied to the memory cell after the write process to verify (read) the state of the multiple PROM ReRAM devices 92.

[0100] V DD Node 18 is provided with 0.8V, optionally at high impedance, and V SSNode 26 is provided with 0V. The PROM word line 98 shared by the row of memory cells containing the state of the PROM ReRAM device 92 to be verified is biased at approximately 0.4V, thereby turning on all PROM select transistors 94 in that row. The VB line 96 associated with the selected row in the array is biased at 0.8V. The P-bias line 28 shared by the row of memory cells 50, 60, 70, or 80 containing the state to be verified is biased at 0.8V. The N-bias line 28 shared by the row of memory cells containing the state to be verified is biased at 0V. This turns off all p-channel bias transistors 16 and 34 and n-channel bias transistors 24 and 40 in the selected row, so that there will be no current from latch sections 52, 62, 72, or 82 to interfere with the reading of the ReRAM state. At this time, the state of the cross-coupled latches 52, 62, 72, or 82 in the array is uncertain, but will be programmed from the PROM later.

[0101] Bit line 46 is precharged to 0.4V, the midpoint voltage, and then word line 48, shared with the selected row, is raised from 0V to 0.8V, thereby turning on the word line select transistor 44 in the selected row. If the ReRAM in the cell is programmed, bit line 46 will be pulled up towards 0.8V on VB. If the ReRAM is not programmed, the bit line will remain floating at 0.4V.

[0102] Figure 9 The eleventh row of the voltmeter shows an exemplary voltage applied to memory cells 50, 60, 70, or 80 to read the state of multiple cross-coupled latch portions in the memory cells of a selected row of the array.

[0103] V DD Node 18 provides 0.8V, and V SS Node 28 is provided with 0V. P-bias line 28 is biased at 0.4V. N-bias line 30 is biased at 0.4V. During this process, this will set the current level on both sides of the cross-coupled latch portions 52, 62, 72, 82 of the memory cell in this exemplary embodiment to approximately 50μA.

[0104] The PROM word line 98, shared by the rows of memory cells 50, 60, 70, or 80 containing the state to be read, is biased at 0.8V, thereby turning off all PROM select transistors 94. The VB line 96 is biased at 0.8V. The bit line 46 is precharged to 0.4V and then allowed to float. The word line 48, shared by the rows of memory cells 50, 60, 70, or 80 containing the state of the latch portion to be read, is raised from 0V to 0.8V, thereby gradually turning on all select transistors 44 in the selected row.

[0105] When the voltage on word line 48 ramps up, selection transistor 44 is turned on. The turning on of selection transistor 44, connected to latch portions 52, 62, 72, 82 of memory cells 50, 60, 70, or 80 storing low logic levels, causes the 0.4V floating voltage on bit line 46 to discharge downwards towards the 0V level present on the first output node 20. The turning on of selection transistor 44, connected to latch portions 52, 62, 72, 82 of memory cells 50, 60, 70, or 80 storing high logic levels, causes the 0.4V floating voltage on bit line 46 to charge upwards towards the 0.8V level present on the first output node 20.

[0106] After the voltage on all bit lines 46 has been allowed to stabilize to its drive value, the voltage on word line 48 returns to 0V to turn off select transistor 44. A suitable sense amplifier circuit can then be used to sense the voltage on bit lines 46.

[0107] Figure 9 The twelfth row of the voltmeter shows an exemplary voltage applied to the memory cells to suppress readings of the state of cross-coupled latches 52, 62, 72, 82 in memory cells 50, 60, 70, or 80 in the unselected rows of the array.

[0108] The voltage potential applied to the memory cells in the unselected rows of memory cells 50, 60, 70, or 80 is similar to... Figure 9 The same voltage is applied as shown in row eleven of the table, except that word line 48 of the unselected row is biased at 0V, thus keeping the select transistor 44 in the unselected row off. This is necessary to avoid contention for control bit line 46 among memory cells in more than one row.

[0109] See now Figure 10 The cross-sectional view illustrates the structure of a representative unprogrammed antifuse device, which can be used as a vertical resistor in an embodiment of the invention. The unprogrammed antifuse device 120 is formed over one of a transistor gate, a metal interconnect layer, or a substrate or a well (shown as layer 122). Layer 124 is the lower electrode of the antifuse device 120, and layer 126 is an antifuse material layer formed over the lower electrode 124, which can be formed of a material such as doped or undoped amorphous silicon. An upper electrode 128 is formed over the antifuse material 126. Layers 124, 126, and 128 can then be etched as a stack. In some embodiments, layer 122 can be used as an etch stop layer, and in other embodiments, a separate etch stop layer (not shown) can be formed over layer 122. In some embodiments, a diffusion barrier layer 130 is also formed on the stack and etched together with the stack.

[0110] Then, a dielectric layer 132 is formed over the stack of layers 124, 126, and 128, and a metal layer is formed and attached to the top layer of the stack (130 or 128). Figure 9 In this configuration, the metal layer is shown as an inlaid copper layer 134 surrounded by a liner 136, as is known in the art. Prior to the formation of the liner 136 and the copper metal line 134, a via 138 is formed to connect to the top layer 128 or 130 of the antifuse, as is known in the art.

[0111] Antifuse devices such as those described above are well known. A non-limiting illustrative example of an antifuse device 120 is shown in U.S. Patent No. 5,770,885, the entire contents of which are incorporated herein by reference. The antifuse device 120, particularly layers 124, 126, and 128, remains unprogrammed and in this state has a resistance on the order of about 1 MΩ to greater than about 1 GΩ.

[0112] Now for reference Figure 11 The cross-sectional view illustrates the structure of a representative original ReRAM device structure 140, which can be used as another form of vertical resistor in embodiments of the invention. This form of vertical resistor (54, 56, 64, and 66 in the prior art figures) is very useful because it can provide extremely high impedance while taking up almost no layout area on the integrated circuit, as it can be fabricated on existing contacts or inter-metal vias in the integrated circuit structure. The polarity of the ReRAM device is irrelevant.

[0113] Figure 11 Some of the structural elements shown in the implementation scheme are similar to Figure 10 Some of the structural elements shown. Therefore, Figure 11 The existence of in Figure 10 The components in the text will be used in conjunction with the components in the text. Figure 10 The same reference numerals are used to designate them.

[0114] An unprogrammed (“raw”) ReRAM device 140 is formed over one of a transistor gate, a metal interconnect layer, or a substrate or well (shown as layer 122). Layer 142 is a diffusion barrier layer and / or an adhesion layer. Layer 144 is the lower electrode of the raw ReRAM device 140. Layer 146 is a solid electrolyte layer formed over the lower electrode 144. An upper electrode 148 is formed over the solid electrolyte layer 146. In some embodiments, a diffusion barrier layer 130 is also formed over the upper electrode 148. Layers 142, 144, 146, 148, and 130 (if present) can then be etched as a stack. In some embodiments, layer 122 can be used as an etch stop layer, and in other embodiments, a separate etch stop layer (not shown) can be formed over layer 122.

[0115] As in Figure 10 In one implementation, a dielectric layer 132 is then formed over the stack of layers 142, 144, 146, and 148, and a metal layer is formed and attached to the top layer of the stack (130 or 148). Figure 11 In this embodiment, the metal layer is shown as an inlaid copper layer 134 surrounded by a liner 136, as is known in the art. Prior to forming the liner 136 and the copper metal lines 134, vias 138 are formed to connect to the top layer 148 or 130 of the original ReRAM device 140, as is known in the art.

[0116] See now Figure 12 The cross-sectional view shows the structure of another representative high-resistance device 150 that can be used as a vertical resistor in an embodiment of the present invention. Figure 12 Some structures shown in the implementation scheme are similar to Figure 10 and Figure 11 Some of the structures shown. Therefore, Figure 12 The existence of in Figure 10 and Figure 11 The components corresponding to the components in the implementation scheme will be designated using the same reference numerals as those used in the figures.

[0117] A high-resistivity device 150 is formed over one of a diffusion layer in a transistor gate, a metal interconnect layer, or a substrate or well (shown as layer 122). Layer 152 is a diffusion barrier layer and / or an adhesion layer. Layer 154 is a high-resistivity material layer formed over layer 152. A second diffusion barrier layer 156 is formed over the high-resistivity material layer 154. In some embodiments, an additional diffusion barrier layer 130 (such as in...) Figure 10 and Figure 11 In the structure, layer 122 is also formed on the second diffusion barrier layer 156. Layers 152, 154, 156 and 130 (if present) can then be etched as a stack. In some embodiments, layer 122 can be used as an etch stop layer, and in other embodiments, a separate etch stop layer (not shown) can be formed above layer 122.

[0118] As in Figure 10 and Figure 11 In one implementation, a dielectric layer 132 is then formed over the stack of layers 152, 154, 156, and 130, and a metal layer is formed and attached to the top layer of the stack (130 or 156). Figure 12 In this configuration, the metal layer is shown as an inlaid copper layer 134 surrounded by a liner 136, as is known in the art. Prior to forming the liner 136 and the copper metal lines 134, vias 138 are formed to connect to the top layer 156 or 130 of the high-resistance device, as is known in the art.

[0119] A variety of materials can be used to form the high-resistivity layer 154. A non-exhaustive list includes silicon-rich SiO2, tantalum-rich Ta2O5, titanium-rich TiO2, aluminum-rich Al2O3, and silicon-rich SiN. Such films can be formed using CVD, PECVD, and other deposition processes. Other process-compatible, stable, high-resistivity materials will be readily apparent to those skilled in the art. The thickness and chemical composition of these materials, as well as the deposition conditions required to deposit them to produce the desired resistance value, can be readily determined experimentally for use in specific embodiments of the invention. These design parameters are readily adjustable by those skilled in the art to achieve resistance values ​​from approximately 1 MΩ to greater than 1 GΩ.

[0120] Those skilled in the art will understand that, although Figures 10 to 12 The diagram illustrates an inlaid copper metallization structure, but other types of metallization layers can be used alternatively. Those skilled in the art will readily understand how such other metallization schemes can be integrated into this invention.

[0121] See now Figure 13 The block diagram illustrates features of an architecture 160 according to an aspect of the invention, comprising an array 162 of SEU-stable memory cell arrays 50, 60, 70, or 80. A controller 164 is coupled to a word line decoder / driver 166, a bit line decoder / driver / sensor amplifier 168, and a VB line decoder / driver 170. A data memory 172 is coupled to the controller 164 for holding data to be written into memory cells (shown as small squares representing any one of memory cells 50, 60, 70, and 80 of the various embodiments shown herein). An error memory 174 maintains the location of known defective memory cells in array 162 and preferably holds copies of the correct data at those locations.

[0122] The word line decoder / driver 166 is controlled by the controller 164 to... Figure 9 The voltmeter provides the necessary voltages for driving the word lines 48 of the memory cells in various operating modes of the array. The bit line decoder / driver / sensor amplifier 168 is controlled by the controller 164 to adjust according to... Figure 9 The voltmeter provides the necessary voltages for driving the bit lines 46 of the memory cells in various operating modes of the array, and according to... Figure 9 The table shows several operating modes for sensing the contents of memory cells.

[0123] VB line decoder / driver according to Figure 9 The voltmeter provides the voltage required to drive the VB line 96 of the memory cell. Those skilled in the art will understand that, although... Figure 13Each row of VB line 96 is shown, but they can be grouped according to rows of memory array 162, blocks of memory array 162, or the entire array as determined by the memory array designer.

[0124] Given the disclosure of the operating modes of the memory cells described herein, those skilled in the art will be able to readily configure the controller 164 for any particular array conceived within the scope of this invention. The controller is specifically configured to execute reference... Figure 14 The method described above will now be discussed.

[0125] See now Figure 14 The flowchart illustrates an exemplary method 180 for operating the memory cell of the present invention. The method begins at reference numeral 182.

[0126] At reference numeral 184, upon power-up of the integrated circuit, the cross-coupled latches 52, 62, 72, and 82 of memory cells 50, 60, 70, or 80 are powered to 0.8V and set to a predetermined state. As described above, this utilizes a maximum voltage of 0.8V for the cross-coupled latches 52, 62, 72, and 82 of memory cells 50, 60, 70, or 80. Next, at reference numeral 186, data from the ReRAM associated with the memory cell in the PROM is loaded into memory cells 50, 60, 70, or 80, as relative to... Figure 9 As stated in the table.

[0127] Next, at reference 188 in the attached diagram, use the above combination. Figure 9 The operation described above writes corrective data to known faulty locations in memory (the locations where ReRAM-based PROM cells have failed) to a selected latch. These known faulty locations have previously been stored in error memory, either on-chip error memory 174 or off-chip error memory, containing information identifying both the location of the faulty ReRAM-based PROM cell on the integrated circuit and the correct data. A verification operation is performed at reference numeral 190 to determine whether memory cells 50, 60, 70, or 80 all contain correct data, or whether any additional ReRAM-based PROM cells have failed. (The above is in contrast to...) Figure 9 The verification operation is described.

[0128] If memory cells 50, 60, 70, or 80 all contain correct data, the method proceeds to reference numeral 192, where V DD The voltage is increased to 1.5V to enable operation, then proceeds to reference numeral 194, where the integrated circuit core is switched on. The process ends at reference numeral 196.

[0129] If all memory cells 50, 60, 70, or 80 do not contain correct data due to a failure of one or more additional ReRAM-based PROM cells, the method proceeds to reference numeral 198, where forward error correction (FEC) codes (such as ECC error codes used in memory applications) stored in on-chip or off-chip FEC memory (not shown) are used to determine the location of the incorrect data. Figure 13 The controller 164 can perform the FEC function required for this operation. At reference numeral 200, the correct data calculated from the FEC code is written to a cross-coupled latch in the memory cell, as described above relative to... Figure 9 The process then proceeds as described above. At reference numeral 202, the locations of the faulty data and the corrective data are written to the error storage memory. The method returns to reference numeral 190, where a verification operation is performed again to determine if memory cells 50, 60, 70, or 80 all contain the correct data. This loop through reference numerals 190 to 202 is performed until it is determined that all memory cells 50, 60, 70, or 80 contain the correct data.

[0130] See now Figure 15A and Figure 15B According to an aspect of the invention, an exemplary pair of ReRAM devices 54 and 56 connected in series are shown respectively. Figure 3 A schematic diagram and a cross-sectional view of a ReRAM device formed as a stack 210 implemented in silicon are shown. The stack 210 is shown formed on a first metal layer metal line 212. A first electrode 214 for the ReRAM device 54, formed of a material such as TiN or TaN, is deposited above the metal line 212. In one embodiment of the invention, the first electrode 214 may have The thickness is within the range of 50 Å. The two-part switching layer (sometimes referred to as the solid electrolyte layer) is formed by a layer 216a of a material such as tungsten (W) deposited above the first electrode 214 and a layer 216b of a material such as undoped amorphous silicon deposited above layer 216a. In one embodiment of the invention, layer 216a may have a thickness in the range of 50 Å, and layer 216b may have a thickness of approximately 50 Å. Thickness within the range.

[0131] A second electrode 218, formed of a material such as Al, for both ReRAM devices 54 and 56, is deposited above the switching layers 216a / 216b. In one embodiment of the invention, the thickness of the second electrode 218 can be approximately [missing information]. Within the range. A two-part switching layer for the ReRAM device 56, formed of a layer 220a of a material such as undoped amorphous silicon, is deposited over the second electrode 218, and a layer 220b of a material such as W is deposited over layer 220a. In one embodiment of the invention, the switching layer 220a may have a thickness in the range of about 30 Å, and the layer 220b may have a thickness in the range of about The thickness is within the specified range. The W layer is used to smooth the interface layer between the Si layer 216b and the first electrode 214, and is believed to contribute to durability. For both ReRAM devices 54 and 56, the W layer can be omitted from the switching layer.

[0132] A first electrode 222 for the ReRAM device 54, formed of a material such as TiN or TaN, is deposited above the switching layer 220b. In one embodiment of the invention, the first electrode 222 may have… Thickness within the range.

[0133] Figures 16A to 16F yes Figure 15B A cross-sectional view of the ReRAM stack 210 shows selected progressive manufacturing steps used to fabricate it as part of a semiconductor manufacturing process.

[0134] The process begins after forming and defining the metal line 212 using known deposition and etching techniques. The first electrode 214 of the ReRAM device 54 is deposited over the metal line 212, achieving, for example... The thickness is within the range. Then, a switching layer 216a (W) is deposited over the first electrode 212 to a thickness, for example, in the range of 50 Å, and a layer 216b (amorphous silicon) is formed over layer 216a to a thickness, for example, approximately... Thickness within the range.

[0135] Then, the second electrode 218 for both ReRAM devices 54 and 56 is deposited over the switching layer 216b, reaching, for example, approximately The thickness is within the range of 30 Å. A two-part switching layer for the ReRAM device 56, formed of layer 220a of a material such as undoped amorphous silicon, is deposited over the second electrode 218, and a layer 220b of a material such as W is deposited over layer 220a. In one embodiment of the invention, the switching layer 220a may have a thickness in the range of about 30 Å, and the layer 220b may have a thickness in the range of about 30 Å. The thickness is within the specified range. The W layer is used to smooth the interface between Si and adjacent electrodes and is believed to contribute to durability. For both ReRAM devices 54 and 56, the W layer can be omitted from the switching layer.

[0136] Then, the first electrode 222 of the ReRAM device 54 is deposited over the switching layer 220b, achieving, for example... Thickness within the range. Figure 16A The structure obtained after these processing steps are shown.

[0137] Now for reference Figure 16B A mask layer 228 is formed over the stack of layers 214, 216a / 216b, 218, 220a / 220b and 222, and a metal line 212 is used as an etch stop layer to etch the stack to define the outline of ReRAM devices 54 and 56. Figure 16B The structure obtained after these processing steps are shown.

[0138] See now Figure 16C Interlayer dielectric (ILD) 224 is deposited in Figure 16B The exposed surface of the structure shown is above the entire stack forming ReRAM devices 54 and 56. Figure 16C The structure obtained after this processing step is shown.

[0139] Now for reference Figure 16D The top surface of the ILD 224 is planarized using a process such as CMP (chemical mechanical polishing) to expose the top surface of the first electrode 222 for the ReRAM device 54. Figure 16D The structure obtained after this processing step is shown.

[0140] See now Figure 16E Metal line 226 is deposited above the planarized surface of ILD 224, thereby making electrical contact with the first electrode 222. Mask layer 230 is formed above the planarized surface of ILD 222, and ILD 224 is used as an etch stop layer to etch away the exposed portion of the first electrode 226 to define metal line 226. Figure 16E The structure of the process up to the etching step is shown.

[0141] See now Figure 16F The mask layer 230 has been removed to expose the defined metal line 226. Figure 16F The completed ReRAM device stack structure is shown. Conventional semiconductor back-end processing steps (not shown) are then performed to complete the integrated circuit containing the stacked ReRAM device.

[0142] Those skilled in the art will know that, Figure 7 and Figure 9The voltage and current values ​​given in the tables are representative values ​​for exemplary memory cells according to the present invention, and these voltage values ​​will vary depending on the individual integrated circuits employing different transistor designs and design rules. The bias current level in any design is set such that during a read operation, the latch operates with sufficient current to prevent read operations from interfering with the cell. Similarly, the bias current level in any design is set such that during a write operation, the latch operates with a lower current value to allow the write source to overcome existing latch states. These design parameters are entirely within the scope of those skilled in the art.

[0143] While embodiments and applications of the invention have been shown and described, it will be apparent to those skilled in the art that further modifications can be made without departing from the inventive concept herein. Therefore, the invention is not limited except in the spirit of the appended claims.

Claims

1. A single event upset (SEU) stable memory cell, the memory cell comprising: a first p-channel transistor coupled between a first voltage supply node and a first complementary output node; a first n-channel transistor coupled between the first complementary output node and a second voltage supply node; a second p-channel transistor coupled between the first voltage supply node and a second complementary output node, wherein gates of the first p-channel transistor and the first n-channel transistor are connected together and coupled to the second complementary output node; and a second n-channel transistor coupled between the second complementary output node and the second voltage supply node, wherein gates of the second p-channel transistor and the second n-channel transistor are connected together and coupled to the first complementary output node through a first pair of pristine resistive random access memory (ReRAM) devices connected in series, wherein one of the first complementary output node and the second complementary output node is coupled to a programmable read only memory (PROM) cell, the PROM cell comprising a programmable and erasable ReRAM device.

2. The SEU stable memory cell of claim 1, wherein the first pair of pristine ReRAM devices connected in series comprises a single vertical stack.

3. The SEU stable memory cell of claim 1, wherein: the memory cell is disposed in an array of memory cells; one of the first complementary output node and the second complementary output node is coupled to a bit line in the array through a select transistor having a gate coupled to a word line in the array; and the programmable and erasable ReRAM device is coupled to the one of the first complementary output node and the second complementary output node through a PROM select transistor having a gate coupled to a PROM word line in the array.

4. The SEU stable memory cell of claim 1, wherein the gates of the first p-channel transistor and the first n-channel transistor are coupled to the second complementary output node through a second pair of pristine ReRAM devices connected in series.

5. The SEU stable memory cell of claim 1, wherein: the first p-channel transistor is coupled to the first complementary output node through a first p-channel bias transistor; the first n-channel transistor is coupled to the first complementary output node through a first n-channel bias transistor; the second p-channel transistor is coupled to the second complementary output node through a second p-channel bias transistor; and the second n-channel transistor is coupled to the second complementary output node through a second n-channel bias transistor.

6. The SEU stable memory cell of claim 5, wherein: ​ ​ ​ The first and second p-channel bias transistors have gates coupled to a P bias line in the array; and The first and second n-channel bias transistors have gates coupled to an N bias line in the array.

7. A single event upset (SEU) stable memory cell, the memory cell comprising: a first p-channel transistor coupled between a first voltage supply node and a first complementary output node; a first n-channel transistor coupled between the first complementary output node and a second voltage supply node; a second p-channel transistor coupled between the first voltage supply node and a second complementary output node, wherein gates of the first p-channel transistor and the first n-channel transistor are connected together and coupled to the second complementary output node; a second n-channel transistor coupled between the second complementary output node and the second voltage supply node, wherein gates of the second p-channel transistor and the second n-channel transistor are connected together and coupled to the first complementary output node through a first pair of series connected vertical resistors, wherein the first pair of series connected vertical resistors are formed as a vertical stack comprising a first electrode of a first ReRAM device disposed above a metal segment of a first metallization layer in an integrated circuit, a switching layer of the first ReRAM device disposed above the first electrode of the first ReRAM device, a second electrode of both the first ReRAM device and a second ReRAM device disposed above the switching layer of the first ReRAM device, a switching layer of the second ReRAM device disposed above the second electrode of the first ReRAM device and the second ReRAM device, and a first electrode of the second ReRAM device disposed above the switching layer of the second ReRAM device.

8. The SEU stable memory cell of claim 7, wherein: the switching layer of the first ReRAM device comprises two layers; and the switching layer of the second ReRAM device comprises two layers.

9. The SEU stable memory cell of claim 7, wherein: the two layers of the switching layer of the first ReRAM device comprise a first layer formed of tungsten and a second layer formed of amorphous silicon; and the two layers of the switching layer of the second ReRAM device comprise a first layer formed of amorphous silicon and a second layer formed of tungsten.

10. The SEU stable memory cell of claim 7, wherein: the first electrodes of the first ReRAM device and the second ReRAM device comprise one of TiN and TaN.

11. The SEU stable memory cell of claim 7, wherein: the second electrodes of both the first ReRAM device and the second ReRAM device comprise Al.

12. A single event upset (SEU) hardened memory cell, the memory cell comprising: a latch portion, the latch portion comprising cross-coupled latches; and at least one cross-coupled circuit path in the latch portion, the at least one cross-coupled circuit path comprising a first pair of vertical resistors connected in series formed as a vertical stack, wherein the vertical stack comprises a first electrode of a first ReRAM device disposed above a metal segment of a first metallization layer in an integrated circuit, a switching layer of the first ReRAM device disposed above the first electrode of the first ReRAM device, a second electrode of both the first ReRAM device and a second ReRAM device disposed above the switching layer of the first ReRAM device, a switching layer of the second ReRAM device disposed above the second electrode of the first ReRAM device and the second ReRAM device, and a first electrode of the second ReRAM device disposed above the switching layer of the second ReRAM device.

13. The SEU hardened memory cell of claim 12, wherein: the switching layer of the first ReRAM device comprises two layers; and the switching layer of the second ReRAM device comprises two layers.

14. The SEU hardened memory cell of claim 12, wherein: the two layers of the switching layer of the first ReRAM device comprise a first layer formed of tungsten and a second layer formed of amorphous silicon; and the two layers of the switching layer of the second ReRAM device comprise a first layer formed of amorphous silicon and a second layer formed of tungsten.

15. The SEU hardened memory cell of claim 12, wherein: the first electrodes of the first ReRAM device and the second ReRAM device comprise one of TiN and TaN.

16. The SEU hardened memory cell of claim 12, wherein: the second electrodes of both the first ReRAM device and the second ReRAM device comprise Al.

17. A method for operating an array of SEU hardened memory cells in an integrated circuit, the method comprising: applying power to the integrated circuit at a reduced supply voltage; setting cross-coupled latches of the memory cells to an initial predetermined state; loading data from ReRAM in a PROM associated with the memory cells into the memory cells; writing correction data from an error memory to known locations where ReRAM-based PROM cells have failed; performing a verify operation to determine if the memory cells all contain correct data; if the memory cells all contain correct data, raising the supply voltage to an operating level and turning on a core of the integrated circuit; if none of the memory cells contain correct data, using a forward error correction (FEC) code to determine locations of incorrect data; writing correct data computed from the FEC code into cross-coupled latches of memory cells identified as having incorrect data; writing locations of the incorrect data and the correction data into error memory; and re-performing a verify operation to determine whether the memory cells all contain correct data.

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