Method and apparatus for data synchronization in a system having multiple clock domains and reset domains

Abstract

Various embodiments of the present disclosure relate to methods and devices for data synchronization in a system having multiple clock domains and reset domains. A data synchronization unit includes: a first flip-flop, operating on a first clock domain and resetting a second clock domain, sampling data from the first clock domain; a second flip-flop, operating in the first clock domain, sampling a request signal when enabled by a request pulse; a request signal path, configured to delay the request signal by a first delay, and generate an enable signal for a recycling multiplexer based on the delayed request signal; a reset signal synchronization path, configured to delay the reset signal of the first clock domain by a second delay, wherein the second delay is shorter than the first delay; and a multiplexer, having a first input for receiving an output of the recycling multiplexer, a second input for receiving a reset value of a programmable register, the multiplexer being configured to selectively output the signal at the input to the output.

Description

Technical Field

[0001] The present invention generally relates to apparatus and methods for data synchronization in a system having multiple clock and reset domains. Background Art

[0002] like Figure 1 As shown, a conventional two-flip-flop synchronizer 100 is used to synchronize a single bit level signal Sig1. Flip-flop A 105 operates in clock A domain 107, and flip-flop B1 110 and flip-flop B2 112 operate in clock B domain 114. Clock A domain 107 and clock B domain 114 are asynchronous clock domains. Flip-flop A 105 receives input signal Sig1 at the "D" input and is clocked by the first clock signal CLK1 at the clock input. As is well known in the art, the input signal Sig1 is clocked by the first clock signal CLK A The action of is transmitted to the "Q" output of flip-flop A 105. Flip-flops B1 110 and B2 112 are driven by the second clock signal CLK B The clock control is performed and the output signal at the “Q” output of flip-flop A 105 is serially transmitted through each of flip-flops B1 110 and B2 112 to the final “Q” output at output node 120 .

[0003] Figure 2A Shows Figure 1 A first timing diagram 200 of an exemplary conventional synchronizer 100 is shown. A signal (track 205), the "Q" output of flip-flop A (track 207), CLK B The waveforms associated with the signal (trace 209), the "Q" output of flip-flop B1 (trace 211), and the "Q" output of flip-flop B2 (trace 213). B At the same time as the input “D” is sampled in the clock domain, the “Q” output of flip-flop B1 may enter a metastable state 215. However, at the CLK associated with the metastable state 215 B Within one clock cycle of the clock signal, the output "Q" of flip-flop B1 may stabilize to a certain stable value (in Figure 2A In the case shown, the stable value is a logical one value.) If flip-flop B1 does not settle to a stable value during the one clock cycle time associated with metastable state 215, the output of flip-flop B2 may also enter a metastable state, but the probability of flip-flop B2 becoming metastable within a full clock cycle is very close to zero.

[0004] If CLK BIf the frequency is too high, the output of flip-flop B1 may not be able to settle to a stable value when flip-flop B2 samples the output of flip-flop B1. In this case, three flip-flop synchronizers can be used instead of two flip-flop synchronizers to allow more time for the metastable signal to stabilize.

[0005] Figure 2B Shown with Figure 1 A second timing diagram 250 associated with an exemplary conventional synchronizer 100 is shown. A signal (tracking 255), the "Q" output of flip-flop A (tracking 257), CLK B The timing diagram 250 illustrates a waveform associated with the source signal (trace 259), the "Q" output of flip-flop B1 (trace 261), and the "Q" output of flip-flop B2 (trace 263). Timing diagram 250 illustrates a phenomenon associated with multi-flip-flop synchronizers, known as cycle uncertainty. In cycle uncertainty, additional clock cycles of the destination clock may be required to synchronize the source signal (the output of flip-flop A 105) to the destination clock domain. The cycle uncertainty may depend on whether the output of an intermediate flip-flop settles to the correct logic value. As Figure 2A As shown, two active clock edges of the destination clock are required to synchronize the source signal in the destination clock domain. This is because after the metastable state 215, the output of flip-flop B1 110 settles to the correct logic level 1. However, as Figure 2B As shown, the output of flip-flop B1 110 settles to an incorrect logic level 0 after the metastable state 265. Due to this incorrect behavior, an additional target clock cycle is required to synchronize the source signal in the target clock domain. Therefore, there is uncertainty as to whether synchronization requires two clock cycles or three clock cycles of the target clock. Summary of the invention

[0006] According to one embodiment, a data synchronization unit is provided. The data synchronization unit includes a first flip-flop having an input for receiving data from a first clock domain, a reset coupled to a reset signal of a second clock domain, and an output for providing sampled data, the first flip-flop being enabled by a request enable signal; a second flip-flop having an input coupled to an inverted output of the second flip-flop, an output for providing a request signal, and a reset coupled to the reset signal of the first clock domain, the second flip-flop being enabled by the request enable signal; a request signal path having an input coupled to a request signal, and an output for providing an enable signal synchronized to the second clock domain, the request signal path being configured to synchronize the request signal and delay the first delay signal , and generates an enable signal based on the synchronized request signal; a synchronous reset signal path having an input coupled to the reset signal of the first clock domain, and an output for providing a reset signal synchronized to the second clock domain, the synchronous reset signal path being configured to synchronize and delay the reset signal of the first clock domain by a second delay, wherein the second delay is shorter than the first delay; and a multiplexer having a first input for receiving an output of the recycling multiplexer, a second input for receiving a reset value of a programmable register storing data in the first clock domain, and a select input for receiving the synchronized reset signal, the multiplexer being configured to selectively output a signal at the input of the multiplexer to the output of the multiplexer.

[0007] According to another embodiment, a system is provided. The system includes: a first clock domain circuit having an output for providing data clocked by a clock of the first clock domain; a second clock domain circuit having an input for receiving data from the first clock domain circuit, the received data being clocked by a clock of the second clock domain; and a data synchronization circuit operably coupled between the first clock domain circuit and the second clock domain circuit, the data synchronization circuit being configured to synchronize a reset signal of the first clock domain to the second clock domain and prevent metastable values ​​from propagating into the second clock domain circuit.

[0008] According to another embodiment, a method is provided. The method includes synchronizing a reset of a first clock domain to a second clock domain, and ensuring that synchronization and delay of a request signal from the first clock domain in the second clock domain are slower than synchronization and delay of the reset of the first clock domain in the second clock domain. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] For a more complete understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 A schematic diagram of an exemplary conventional synchronizer is shown;

[0011] Figure 2A Shown with Figure 1A first timing diagram associated with an exemplary conventional synchronizer;

[0012] Figure 2B Shown with Figure 1 a second timing diagram associated with an exemplary conventional synchronizer of;

[0013] Figure 3 A system is shown that highlights prior art recirculating multiplexer (mux) technology for passing multi-bit data between clock domains;

[0014] Figure 4 A prior art system with two reset domains is shown;

[0015] Figure 5 A timing diagram is shown which highlights that, as identified by the inventors of the present application, Figure 4 Scenarios that may lead to metastable states in prior art systems;

[0016] Figure 6 shows a high-level view of a system with multiple clock domains according to embodiments presented herein, highlighting signals that span multiple clock domains and reset domains;

[0017] Figure 7 shows a detailed view of a system highlighting a data synchronization unit according to embodiments presented herein;

[0018] Figure 8 FIG. 1 shows a first exemplary data cross-clock domain display according to an embodiment proposed in this document. Figure 7 Timing diagram of the system;

[0019] Fig. 9 FIG. 1 shows a second exemplary data cross-clock domain according to an embodiment proposed in this document. Figure 7 Timing diagram of the system;

[0020] Fig. 10A A system highlighting unidirectional data crossing clock domains according to embodiments proposed herein is shown;

[0021] Fig. 10B A system highlighting bidirectional data crossing clock domains according to embodiments proposed herein is shown;

[0022] Fig.11A A flowchart illustrating exemplary operations occurring in a system having multiple clock domains and reset domains according to embodiments presented herein; and

[0023] Fig. 11B A flow chart illustrating exemplary operations occurring in ensuring that a reset value reaches a data flip-flop before a metastable value according to embodiments presented herein.

[0024] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0025] In the following description, one or more specific details are shown to provide an understanding of the examples of the embodiments. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail, so some aspects of the embodiments will not be covered.

[0026] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to one and the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or characteristics may be combined in any suitable manner.

[0027] References used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0028] Electronic systems, such as automotive systems, may be implemented as a system on a chip (SoC), which is an integrated circuit that includes all components of the system, such as components that are typically associated with different and asynchronous clock domains. Crossing clock domains occurs when data is transferred from a flip-flop driven by a first clock (source flip-flop) to a flip-flop driven by a second clock (destination flip-flop). Depending on the relationship between the clocks, problems may arise in the data transfer between the source flip-flop and the destination flip-flop. As an example, if a transition at the output of the source flip-flop occurs very close to the active edge of the second clock, a setup or retention violation may occur at the destination flip-flop. This may cause the output of the second flip-flop to oscillate, become unstable, and may not settle down to a stable value before the next active edge of the second clock. This condition is called metastable.

[0029] Metastable states can also occur when there are cross-reset domain issues. Cross-reset domain issues can occur when data is transferred between flip-flops that operate on different resets, even if they share the same clock domain. For example, if the reset of the source flip-flop is asserted (and the reset of the destination flip-flop is not asserted) while the destination flip-flop is sampling data, the data at the input of the destination flip-flop may not meet the reset or retention requirements. This can result in a metastable state at the output of the destination flip-flop.

[0030] Figure 3 A system 300 is shown that highlights prior art recirculating multiplexer (mux) techniques for transferring multi-bit data between clock domains. Figure 3 As shown, system 300 can be used to synchronize multi-bit data from a source domain to a target domain, where it is important to maintain data coherence in the target domain (i.e., all data bits must change simultaneously (or nearly simultaneously, within timing differences caused by manufacturing process tolerance differences, propagation delay differences, etc.). Due to this requirement, simple multi-trigger synchronization schemes (such as Figure 1 The one shown in Figure 3 cannot be used to synchronize each individual data bit because cycle uncertainty (as explained above) may cause data incoherence. System 300 includes two clock domains, a first clock domain 305 and a second clock domain 307. The first clock domain 305 includes a software (SW) programmable register 310 that can be used to store data and a trigger 312 for storing and retaining the data stored in the SW programmable register 310. The SW programmable register 310 can be implemented as a trigger, for example. The number of triggers in each of the SW programmable register 310 and the trigger 312 is equal to the width of the data bus. As an example, in a system with a 64-bit data bus, 64 triggers can be used to enable the SW programmable register 310. Similarly, the trigger 312 can include 64 triggers.

[0031] The first clock domain 305 also includes a flip-flop 314 for generating a request signal (REQ) for indicating that a request has been made to read the data stored in the SW programmable register 310. For example, the request signal (REQ) can be generated from a request enable signal (REQ_PULSE). The request enable signal (REQ_PULSE) is used to enable the flip-flop 312 and the flip-flop 314, which means that an active signal on the request enable signal (REQ_PULSE) starts the operation of the flip-flop 312 and the flip-flop 314. For example, once the software writes multi-bit data to the SW programmable register 310, the request enable signal (REQ_PULSE) is generated to indicate that the source multi-bit data (in the first clock domain 305) is ready to be read in the second clock domain 307.

[0032] Although the SW programmable register 310, flip-flop 312, and flip-flop 314 are not shown as being clocked, they are clocked by a clock common to the first clock domain 305. The clock lines are omitted to simplify Figure 3 .

[0033] The second clock domain 307 includes a recycling multiplexer 320 that selectively outputs the output of a flip-flop 322 (which is data stored in a SW programmable register 310 in the second clock domain 307) or the output of a flip-flop 312 according to a request signal (REQ). The number of recycling multiplexers 320 is equal to the width of the data bus. As an example, if the request signal is valid, the recycling multiplexer 320 selects the output of the flip-flop 312 to output, and if the request signal is invalid, the recycling multiplexer 320 selects the output of the flip-flop 322 as the output (in other words, the recycling multiplexer 320 recycles the output of the flip-flop 322, resulting in its name). The data stored in the flip-flop 322 may be irrelevant to the data stored in the SW programmable register 310 until an update of the flip-flop 322 occurs. The output of the flip-flop 322 is the multi-bit data stored in the SW programmable register 310 in the second clock domain 307.

[0034] The second clock domain 307 also includes a synchronizer 324 configured to synchronize a request signal (REQ) to the second clock domain 307, which is referred to herein as a request signal (REQ_DST). Figure 3 As shown, the synchronizer 324 includes two flip-flops (flip-flop 326 and flip-flop 328). The second clock domain 307 also includes a pulse generator 329. The pulse generator 329 includes a flip-flop 330 and an exclusive OR (XOR) logic gate 332, a first input of which is coupled to the output of the flip-flop 330, and a second input of which is coupled to the input of the flip-flop 330 (or equivalently, the output of the flip-flop 328). Whenever the request signal (REQ_DST) changes, the pulse generator 329 (flip-flop 330 and XOR logic gate 332) is used to generate a pulse, which is one target clock cycle in duration. For example, whenever the request signal (REQ_DST) changes from 0 to 1 or from 1 to 0, the pulse generator 329 outputs a pulse. For example, the output of the pulse generator 329 is used as a selection signal of the recycling multiplexer 320.

[0035] A single reset signal (RST_B) 335 is used to reset the flip-flops in system 300. When activated, reset signal (RST_B) 335 resets the contents stored in the flip-flops in system 300. Therefore, although system 300 includes two clock domains, there is only one reset domain. Flip-flops 314, 326, 328, and 330 are single flip-flops, while flip-flops 312 and 322 are multiple flip-flop arrays, each of which contains as many flip-flops as the width of the data bus supported by system 300. Similarly, recirculating multiplexer 320 is a linear array of recirculating multiplexers, which has as many recirculating multiplexers as the width of the data bus.

[0036] Figure 4 A prior art system 400 with two reset domains is shown. The system 400 includes two clock domains (a first clock domain 405 and a second clock domain 407) and two reset domains (a first reset domain associated with a first reset signal (RST_B) 415 and a second reset domain (POR_B) 434 associated with a second reset signal (RST_B). Figure 4 As shown, the flip-flops (SW programmable register (e.g., implemented as flip-flops) 410, flip-flops 412, and flip-flops 414) in the first clock domain 405 are part of the first reset domain controlled by the first reset signal (RST_B) 415, and the flip-flops (flip-flops 422, flip-flops 426, flip-flops 428, and flip-flops 430) in the second clock domain 407 are part of the second reset domain controlled by the second reset signal (POR_B) 434. For example, the first reset domain can be part of a programming interface, and the second reset domain can be part of a runtime interface. Multiple reset domains may be required to support operations, such as when the runtime interface measures events that occur during a functional chip reset. In this case, the reset value (e.g., the value of the reset flip-flop) needs to be correctly propagated to the target domain (the second clock domain 407).

[0037] The flip-flop 422 may become metastable due to the two reset domain configuration of the system 400. As an example, when the flip-flop 422 is sampling multi-bit data from the flip-flop 412, the first reset signal (RST_B) 415 may be asserted, causing the multi-bit data from the flip-flop 412 (D_SRC) to change within the setup or hold boundaries of the flip-flop 422. This may cause the flip-flop 422 to become metastable, and therefore, other circuits utilizing the multi-bit data (D_DST) from the flip-flop 422 may become metastable or use corrupted values.

[0038] Figure 5 A timing diagram 500 is shown which highlights that, as identified by the inventors of the present application, Figure 4Scenario that may lead to a metastable state in the prior art system 400. Timing diagram 500 shows traces representing the clock of the second clock domain 407 (trace 505), the output (ENP) of the XOR logic gate 432 (trace 507), the good output of the flip-flop 412 (trace 509), and the bad output of the flip-flop 412 (trace 511). If the first reset signal (RST_B) 415 is asserted within the interval 515, the flip-flop 422 may enter a metastable state. This may be due to violating the setup or retain boundaries of the flip-flop 422, thus causing subsequent circuits to become metastable or use corrupted values.

[0039] In the case where the resets of the two clock domains occur at different times (more specifically, when the source domain reset can be asserted independently of the target domain reset), techniques for handling cross-clock domains (e.g., recirculating multiplexers or handshake synchronizers) may fail. Failure may lead to metastability and its propagation, ultimately causing system functional failure. Therefore, there is a need for methods and apparatus for data synchronization in systems with multiple clock domains and reset domains.

[0040] According to one embodiment, a method and apparatus for data synchronization in a system having multiple clock domains and reset domains is provided. The method and apparatus provided herein can operate in a system of any digital design domain having multiple clock domains, and wherein the reset domains of the multiple clock domains are different.

[0041] In one embodiment, data from a source clock domain is reset by a reset signal of a target clock domain. Data from a source clock domain, such as stored in a circuit storing data (e.g., the circuit includes one or more flip-flops, the number of flip-flops depending on the width of a data bus), can be reset when a reset signal of a target clock domain becomes a specified value. Resetting data from a source clock domain using a reset signal of a target clock domain (e.g., a power on reset (POR_B) signal) helps prevent any changes in the data when the data is sampled in the target clock domain because the reset signal comes from the target clock domain. For example, when the reset signal of the target clock domain is valid, data from a source clock domain is reset, and when the reset signal of the target clock domain is not valid, data from a source clock domain is not reset, even when the reset of the source clock domain becomes valid (e.g., becomes a logic zero value).

[0042] In one embodiment, sampling of data from the source clock domain is synchronized according to a reset signal of the source clock domain. Sampling of data from the source clock domain by circuits in the target clock domain is synchronized with the source clock domain by a reset signal of the source clock domain (e.g., a reset (RST_B) signal). As an example, when the reset signal of the source clock domain is invalid (e.g., the reset signal of the source clock domain is a logic one value), the circuits in the target clock domain sample data from the source clock domain (e.g., the circuits include one or more flip-flops, the number of flip-flops depending on the width of the data bus), and when the reset signal of the source clock domain is valid (e.g., the reset signal of the source clock domain becomes a logic zero value), the circuits in the target clock domain do not sample data from the source clock domain.

[0043] Figure 6 6 shows a high-level view of a system 600 with multiple clock domains according to an embodiment of the present disclosure, highlighting signals that span multiple clock domains and reset domains. Figure 6 As shown, system 600 includes two clock domains (domain A 605 and domain B 607), where domain A 605 is a source clock domain and domain B 607 is a destination clock domain. Signals flowing from domain A 605 to domain B 607 include a data signal (D_SRC) 610, a source reset signal (SRC_RST) 612, and a request signal (REQ) 614. Signals flowing from domain B 607 to domain A 605 include a destination reset signal (DST_RST) 616. Although in Figure 6 In FIG. 6 , domain A 605 and domain B 607 are shown as the source domain and the target domain, but for different data signals, domain A 605 and domain B 607 can also be the target domain and the source domain, respectively. In this opposite case, the direction of the signal should be opposite.

[0044] A destination reset signal (DST_RST) 616 provided by domain B 607 may be used to reset data from domain A 605 stored in data synchronization unit 610. Resetting data from domain A 605 using destination reset signal (DST_RST) 616 helps prevent changes in data in domain A 605 when data is sampled in domain B 607.

[0045] The sampling of data from domain A 605 in domain B 607 is synchronized with a source reset signal (SRC_RST) 612 provided by domain A 605. As an example, when the source reset signal (SRC_RST) 612 is valid, the data synchronization unit 612 samples the data from domain A 605. Synchronizing the sampling of data in domain B 607 with the source reset signal (SRC_RST) 612 also helps prevent the data in domain A 605 from being altered when the data is sampled in domain B 607.

[0046] The system 600 also includes a data synchronization unit, wherein the data synchronization unit 610 is associated with the domain A 605, and the data synchronization unit 612 is associated with the domain B 607. The data synchronization unit includes a circuit associated with a method and apparatus for performing data synchronization in a system having multiple clock domains and reset domains. The circuit includes, for example, a flip-flop and a logic gate. In one embodiment, the data synchronization units 610 and 612 include circuits for providing data synchronization in a system having multiple clock domains and reset domains when the domain A 605 is the source domain and the domain B 607 is the target domain. In other words, the data synchronization units 610 and 612 include circuits for providing data synchronization when only the domain A 605 is the source domain and the domain B 607 is the target domain. As an example, the data synchronization unit 610 includes a circuit for providing data synchronization in a system having multiple clock domains and reset domains, wherein the domain A 605 is the source domain, and the data synchronization unit 612 includes a circuit for performing data synchronization in a system having multiple clock domains and reset domains, wherein the domain B 607 is the target domain.

[0047] In another embodiment, data synchronization units 610 and 612 include circuits for providing data synchronization in a system with multiple clock domains and reset domains when domain A 605 is the source domain or the target domain and domain B 607 is the target domain or the source domain. In other words, data synchronization units 610 and 612 include circuits for providing data synchronization when domain A 605 or domain B 607 can be the source domain or the target domain. As an example, data synchronization unit 610 and data synchronization unit 612 each include circuits for providing data synchronization in a system with multiple clock domains and reset domains. A detailed discussion of an example embodiment of a data synchronization unit is provided below.

[0048] Figure 7 Detailed view of a system 700 highlighting a data synchronization unit according to an embodiment of the present disclosure is shown. System 700 includes two clock domains (clock domain 705 and clock domain 707), where clock domain 705 is a source domain and clock domain 707 is a target domain. Figure 7 As shown, circuits in the target domain (clock domain 707) sample data in the source domain (clock domain 705). Both clock domains include circuits, namely data synchronization units, to provide data synchronization in system 700.

[0049] The circuit in the source domain includes a SW programmable register (e.g., implemented as a flip-flop) 710 that stores data sampled by the circuit in the source domain. In other words, the SW programmable register 710 stores data that will be sampled by the target domain and will cross the clock domain. The SW programmable register 710 can store any value provided at its input.

[0050] The circuit in the source domain also includes a data synchronization unit 712, which includes a circuit for providing data synchronization for the source domain. The data synchronization unit 712 includes a flip-flop 714 that samples and holds the data stored in the SW programmable register 710, and a flip-flop 716 that generates and holds a request signal (REQ) that can implement a recycling multiplexer 722 in the target domain, and the value of selecting any one of the outputs of the flip-flop 714 or the flip-flop 720 (the sampled value of the data in the source domain) depends on the value of the request signal (REQ). For example, the request signal (REQ) can be generated from the request enable signal (REQ_PULSE).

[0051] The input of the flip-flop 714 is referred to as the value (D_REG) stored in the SW programmable register 710, and the output of the flip-flop 714 is referred to as the data of the source domain (D_SRC). The flip-flop 714 is enabled by the request enable signal (REQ_PULSE). The request enable signal (REQ_PULSE) is usually generated when data is written to the SW programmable register 710, and indicates that the data can be synchronized in the target domain. When enabled by the request enable signal (REQ_PULSE), the flip-flop 714 samples the value stored in the SW programmable register 710, and when not enabled by the request enable signal (REQ_PULSE), the flip-flop 714 maintains its current value. When enabled by the request enable signal (REQ_PULSE), the flip-flop 716 switches between the zero and one values ​​of the request signal (REQ). When not enabled by the request enable signal (REQ_PULSE), the flip-flop 716 maintains the current value of the request signal (REQ).

[0052] The SW programmable register 710 and the flip-flop 716 can be reset by a reset signal (RST_B) which is a reset signal of the source domain. When the reset signal (RST_B) is valid, the SW programmable register 710 and the flip-flop 716 are reset to a default value, which can be defined by an operator of the system 700 or a technical standard for managing the operation of the system 700. The flip-flop 714 can be reset by a reset signal (POR_B), which is a reset signal of the target domain. When the reset signal (POR_B) is valid, the flip-flop 714 is reset. The flip-flop 714 reset by the reset signal of the target domain allows the target domain to know and control when the flip-flop 714 is stable, thereby preventing a violation of the boundary of the target domain from being set or maintained. The flip-flop 714 and the flip-flop 716 constitute the data synchronization unit 712 of the source domain.

[0053] The circuit in the target domain includes a flip-flop 720 that stores data sampled from the source domain. The circuit in the target domain also includes a recirculating multiplexer 722 that operates in a manner similar to that previously described. Figure 4 The recycling multiplexer 420 operates in a manner similar to that of the recirculating multiplexer 420 .

[0054] The circuit in the target domain also includes a data synchronization unit 724, which includes a circuit that provides data synchronization for the target domain. The data synchronization unit 724 includes a request signal path 726 that propagates the request signal (REQ) output by the flip-flop 716, and propagates a reset signal (RST_B) to select the sampled value of the flip-flop 714 or the reset value of the SW programmable register 710 (RST_VAL). The reset value of the SW programmable register 710 can be a predetermined value or a predefined value loaded into the SW programmable register 710 when the SW programmable register 710 is reset. The reset value is available to the system 700 in the form of a parameter or is hard-coded in the system 700.

[0055] The request signal path 726 includes a synchronizer 728, which synchronizes the request signal (REQ) in the target domain. The synchronizer 728 is implemented as a linear sequence of flip-flops (three flip-flops in this example embodiment, but other numbers of flip-flops can be used). Due to the flip-flops in the synchronizer 728, the request signal (REQ) is delayed by a first specified amount. The delay applied to the request signal (REQ) may be a function of the number of flip-flops and the clock rate of the target domain. The request signal path 726 also includes a pulse generator 729 (including a flip-flop 730 and an XOR logic gate 732), which is used to generate an enable signal (ENP) for the recycling multiplexer 722. In this example embodiment, the enable signal (ENP) is valid within one cycle of the clock of the target domain. When the state of the request signal (REQ_DST) changes in a continuous clock cycle, the combination of the flip-flop 730 and the XOR logic gate 732 produces a valid value. If the request signal (REQ_DST) does not change in a continuous clock cycle, an invalid value is generated. If the enable signal (ENP) is valid, the recycling multiplexer 722 outputs the output of the flip-flop 714, and if the enable signal (ENP) is invalid, the recycling multiplexer 722 outputs the output of the flip-flop 720 (the data in the target domain (D_DST)).

[0056] The reset path 736 synchronizes the reset signal (RST_B) in the target domain and generates a synchronized reset signal (RST_B_SRC_2_DEST). The reset path 736 is implemented as a linear sequence of flip-flops. Due to the flip-flops in the reset path 736, the reset signal (RST_B) is delayed by a second specified amount. The delay applied to the reset signal (RST_B) may be a function of the number of flip-flops and the clock rate of the target domain. Figure 7As shown, reset path 736 is implemented by two flip-flops. However, other numbers of flip-flops may be used. The output of reset path 736 (synchronized reset signal (RST_B_SRC_2_DEST)) is provided to multiplexer 734 to select from the output of recycling multiplexer 722 (the sampled output of flip-flop 714 or the output of flip-flop 720), or the reset value (RST_VAL) of SW programmable register 710 (which is available, for example, in the form of a hard-coded parameter).

[0057] Since the reset path 736 is implemented by two flip-flops, while the synchronizer 728 of the request signal path 726 is implemented by three flip-flops, the delay associated with the reset path 736 is less than the delay associated with the request signal path 726. Therefore, the change to the reset signal (RST_B) will reach the multiplexer 734 before the change to the request signal (REQ) reaches the recycling multiplexer 722. Therefore, the reset signal (RST_B) can be used to select (using the multiplexer 734) the reset value of the SW programmable register 710 for output, while the sampled data (the output of the flip-flop 714) can be metastable. If the reset signal (RST_B) is invalid, the multiplexer 734 will select the output of the recycling multiplexer 722, and once the request signal (REQ) has arrived at the target domain in a synchronized manner, the recycling multiplexer 722 will then sample the data from the source domain. Since the request signal (RST_B) is invalid, the output of the flip-flop 714 will not violate the setup or retention boundaries of the flip-flop 720.

[0058] Due to the cycle uncertainty in the multi-flip flop synchronizer (as described above), the reset signal (RST_B) may take three cycles of the target domain clock to synchronize with the target domain, rather than two cycles of the target domain clock. Therefore, it is possible that the recycling multiplexer 722 is unaware of the potential metastable data (D_SRC) at approximately the same time as the multiplexer 734 is transparent to the reset value (RST_VAL). However, since the multiplexer 734 is located after the recycling multiplexer 722 in the data path, it can be determined that the flip flop 720 captures the reset value (RST_VAL) instead of the output of the recycling multiplexer 722 even if the delay caused by the reset signal (RST_B) is approximately equal to the delay caused by the request signal (REQ).

[0059] The flip-flops of the target domain (ie, flip-flop 720, and the flip-flops in synchronizer 728 and reset path 736) are reset by the reset signal (POR_B), as is flip-flop 714, so the target domain controls the sampling and propagation of the sampled data from the source domain to the target domain.

[0060] When the reset signal (RST_B) of the source domain is asserted, the flip-flop 714 may become metastable. This is possible because the flip-flop 714 is reset by the reset signal (POR_B) of the target domain, rather than being reset asynchronously by the reset signal (RST_B), and the output of the SW programmable register 710 may not meet the setup or retention boundaries for the flip-flop 714. As an example, this may occur when the request enable signal (REQ_PULSE) is valid (thus enabling the flip-flop 714) and the reset signal (RST_B) is asserted too close to the active edge of the clock of the source domain, so that the data input of the flip-flop 714 changes within the setup or retention boundaries of the flip-flop 714. Since the flip-flops 714 are not in a reset state, they can sample unstable data at their inputs, resulting in a metastable output at the output of the flip-flop 714. The metastable state of the flip-flop 714 can propagate to the flip-flop 720. However, propagation does not occur until the request signal (REQ) reaches the target domain and enables the recycling multiplexer 722 (in the form of the enable signal (ENP)). For example, the previous value of the request signal (REQ) may be a logic 1, and due to the assertion of the reset signal (RST_B), the request signal (REQ) switches, becoming a logic 0. This change in the request signal (REQ) can be captured in the target domain, resulting in the generation of the enable signal (ENP). In one embodiment, the synchronizer 728 and the reset path 736 are designed so that the propagation of the request signal (REQ) in the target domain is slower than the propagation of the reset signal (RST_B). Therefore, the reset value (RST_VAL) of the SW programmable register 710 is routed to the flip-flop 720 instead of the output of the flip-flop 714.

[0061] Figure 8 FIG. 1 shows a first example of data crossing clock domains according to an embodiment of the present disclosure. Figure 7 The signal names shown in the timing diagram 800 correspond to Figure 7, wherein trace 805 represents a reset signal (POR_B) in the target domain, trace 807 represents a reset signal (RST_B) in the source domain, trace 809 represents a clock (SRC_CLK) in the source domain, trace 811 represents data (D_REG) of the SW programmable register 710 (a multi-value signal), trace 813 represents a request enable signal (REQ_PULSE), trace 815 represents an output of the flip-flop 716 (a request signal (REQ)), trace 817 represents sampled data (D_SRC) of the flip-flop 714 (a multi-value signal), trace 819 represents a clock (DST_CLK) in the target domain, trace 821 represents a synchronous request signal (REQ_DST), trace 823 represents an enable signal (ENP), trace 825 represents a synchronous reset signal (RST_B_SRC_2_DEST), and trace 827 represents data (D_DST) in the target domain (a multi-value signal).

[0062] like Figure 8 As shown, the reset signal (RST_B) is asserted at time 830, causing the SW programmable register 710 to be reset and the reset value (RST_VAL) to be loaded into the SW programmable register 710. However, the request enable signal (REQ_PULSE) is inactive, and the flip-flop 714 holds the pre-reset value ("D0") of the flip-flop 710, which was sampled by the flip-flop 714 when it was last enabled (e.g., during the active high level 832 of the request enable signal (REQ_PULSE)).

[0063] Since the sampled data (D_SRC) has not been reset by the reset signal (POR_B) and the flip-flop 714 has not been enabled by the request enable signal (REQ_PULSE), the sampled data (D_SRC) is irrelevant to the data (D_REG), and the effective high level of the enable signal (ENP) causes the recycling multiplexer 722 to select the sampled data (D_SRC) to be output, so the data (D_DST) takes the value "D0" from the flip-flop 714. However, at the falling edge 834 of the synchronous reset signal (RST_B_SRC_2_DEST), the multiplexer 734 selects the reset value (RST_VAL) to be output, so the data (D_DST) is changed to the reset value (RST_VAL) at the subsequent edge of the clock (DST_CLK).

[0064] Fig. 9 FIG. 1 shows a second example of data crossing clock domains according to an embodiment of the present disclosure. Figure 7 The signal names shown in the timing diagram 900 correspond to Figure 7 Signal names shown in .

[0065] like Fig. 9As shown, the reset signal (RST_B) is asserted at approximately time 905, causing the SW programmable register 710 to be reset and the reset value (RST_VAL) to be loaded into the SW programmable register 710. In digital circuits, the inputs of a flip-flop must generally meet the setup or retention requirements of the flip-flop to ensure that the flip-flop has a value corresponding to the input. The setup or retention requirements of the flip-flop 714 are shown as a "setup or retention" window 907, which means that the inputs of the flip-flop 714 should be relatively stable within the window 907 to ensure that the flip-flop 714 accurately captures the values ​​at the input and output and does not become metastable.

[0066] However, if Fig. 9 As shown, the input (data (D_REG)) of flip-flop 714 has a value D1 909 before time 905 and a value RST_VAL 911 after time 905, with a change in value at approximately time 905. Therefore, the input of flip-flop 714 does not meet the setup or retention requirements within window 907. As a result, flip-flop 714 becomes metastable 913 after time 905.

[0067] The logic 1 level 915 of the enable signal (ENP) corresponding to the request enable signal (REQ_PULSE) 917 causes the recycling multiplexer 722 to pass the D_SRC data (D0) from the flip-flop 714 to its output, causing the data (D_DST) 827 to change to D0. A second pulse 921 of the request enable signal (REQ_PULSE) is generated at approximately time 905, approximately the same time as the reset signal (RST_B) is asserted. Since the reset path delay is shorter than the request path delay, the multiplexer 734 samples the reset value (RST_VAL) of the source data instead of the metastable value 913 of D_SRC 817. This causes the data (D_DST) to change to the reset value (RST_VAL).

[0068] According to one embodiment, a data synchronization unit is provided as an interface between clock domains of a system whenever data crosses a clock domain. Whenever data crosses from a source domain to a target domain, a data synchronization unit provides circuitry to ensure that a metastable state does not propagate into the target domain. In one embodiment, a data synchronization unit is provided for each direction of data flow between any two clock domains. As an example, if data flows in only one direction (e.g., from a first clock domain to a second clock domain), a single data synchronization unit is sufficient. As an example, if data flows in two directions (e.g., from a first clock domain to a second clock domain and from a second clock domain to a first clock domain), a first data synchronization unit is used to ensure that a metastable state does not propagate into the second clock domain (due to data from the first clock domain), and a second data synchronization unit is used to ensure that a metastable state does not propagate into the first clock domain (due to data from the second clock domain).

[0069] Fig. 10A A system 1000 is shown that highlights unidirectional data crossing clock domains according to an embodiment of the present disclosure. The system 1000 includes domain A 1005 and domain B 1007, and data crosses the clock domain only from domain A 1005 to domain B 1007. The system 1000 also includes a data synchronization unit 1009, which ensures that the metastable state does not propagate into domain B 1007.

[0070] Fig. 10B A system 1050 is shown that highlights bidirectional data crossing clock domains according to an embodiment of the present disclosure. The system 1050 includes a domain A 1055 and a domain B 1057, and data crosses the clock domain from domain A 1055 to domain B 1057, and from domain B 1057 to domain A 1055. The system 1050 also includes a first data synchronization unit 1059 that ensures that a metastable state does not propagate into domain B 1057, and a second data synchronization unit 1061 that ensures that a metastable state does not propagate into domain A 1055.

[0071] In one embodiment, in a system with more than two clock domains, a data synchronization unit exists between any two clock domains where data crosses the clock domains.

[0072] Fig.11A A flow diagram is shown of exemplary operations 1100 occurring in a system having multiple clock domains and reset domains in accordance with an embodiment of the present disclosure. Operations 1100 may be indicative of operations occurring in a system having multiple clock domains and reset domains.

[0073] Operation 1100 begins by resetting the data flip-flops in domain A with a reset signal from domain B (block 1105). Resetting the data flip-flops in domain A with a reset signal from domain B ensures that the target domain data flip-flops do not become metastable when the circuits in domain B sample the data in domain A. The reset from domain A is synchronized in domain B (block 1107). The reset of domain A will be synchronized in domain B to help ensure that domain B knows when to sample the reset value of the source data from domain A. However, to help prevent the propagation of metastable values, the reset value of the data flip-flops in domain A arrives at the data flip-flops in domain B before the metastable value (block 1109). One way to ensure that the reset value arrives before the metastable value is to ensure that the request synchronization path in the target domain has a greater delay than the reset synchronization path in the target domain.

[0074] Fig. 11BA flow chart illustrating exemplary operations 1150 occurring in ensuring a reset value reaches a data flip-flop before a metastable value in accordance with an embodiment of the present disclosure. Operations 1150 may be indicative of operations occurring in a system while the system ensures a reset value reaches a data flip-flop before a metastable value.

[0075] Operation 1150 begins by setting a delay in a signal path of a reset value to a first delay value (block 1155). A delay in a signal path of a potential metastable data value is set to a second value, wherein the first delay value is less than the second delay value (block 1157). The delay value may be set using flip-flops inserted into the signal path, and a signal path with a greater number of flip-flops will have a greater delay than a signal path with a lesser number of flip-flops (assuming the flip-flops are the same type of flip-flops manufactured using the same technology). In addition to inserting delays, flip-flops in a signal path may also be used to synchronize signals in the signal path to a target domain.

[0076] Although the present invention has been described with reference to illustrative embodiments, the description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the exemplary embodiments and other embodiments of the present invention will be apparent to those skilled in the art by reference to the specification. Therefore, it is intended that the appended claims cover any such modifications or embodiments.

Claims

1. A data synchronization unit, comprising: a first flip-flop having an input for receiving data from the first clock domain, a reset coupled to a reset signal of the second clock domain, and an output for providing sampled data, the first flip-flop being enabled by a request enable signal; a second flip-flop having an input coupled to an inverted output of the second flip-flop, an output for providing a request signal, and a reset coupled to a reset signal of the first clock domain, the second flip-flop being enabled by the request enable signal; a request signal path having an input coupled to the request signal and an output for providing an enable signal synchronized to the second clock domain, the request signal path being configured to synchronize and delay the request signal by a first delay and to generate the enable signal based on the synchronized request signal; a synchronous reset signal path having an input coupled to the reset signal of the first clock domain and an output for providing a synchronous reset signal, the synchronous reset signal path being configured to synchronize the reset signal of the first clock domain and delay it by a second delay, wherein the second delay is shorter than the first delay; as well as A multiplexer having a first input for receiving the output of the recycling multiplexer, a second input for receiving the reset value of the programmable register, and a select input for receiving the synchronous reset signal, the multiplexer being configured to selectively output the signal at the input of the multiplexer to the output of the multiplexer. 2 . The data synchronization unit of claim 1 , wherein the request signal path comprises three flip-flops coupled in series, wherein each flip-flop has a reset coupled to the reset signal of the second clock domain.

3. The data synchronization unit according to claim 2, wherein the request signal path further comprises a fourth trigger having an input coupled to the three flip-flops coupled in series; and a logic gate having a first input for receiving an output of the fourth trigger, a second input for receiving an output of the three flip-flops coupled in series, and an output for providing a single cycle pulse in response to detecting a switching state of the request signal. The data synchronization unit according to claim 3 , wherein the logic gate comprises an XOR logic gate. 5 . The data synchronization unit of claim 3 , wherein the fourth flip-flop comprises a reset coupled to a reset signal of the second clock domain. 6 . The data synchronization unit according to claim 3 , wherein the three serially coupled flip-flops and the fourth flip-flop are clock-controlled by a clock of the second clock domain.

7. The data synchronization unit of claim 1, wherein the synchronous reset signal path comprises two flip-flops coupled in series, wherein each flip-flop has a reset coupled to the reset signal of the second clock domain.

8. The data synchronization unit according to claim 1, wherein the first flip-flop and the second flip-flop are “D” flip-flops. 9 . The data synchronization unit according to claim 1 , wherein the first flip-flop and the second flip-flop are clock-controlled by a clock of the first clock domain. 10 . The data synchronization unit according to claim 1 , wherein the reset signal of the first clock domain and the reset signal of the second clock domain are different reset signals.

11. The data synchronization unit of claim 1, wherein the reset value of the programmable register is a hard-coded parameter.

12. An electronic system comprising: first clock domain circuitry having an output for providing data clocked by a clock of the first clock domain; a second clock domain circuit having an input for receiving data from the first clock domain circuit, the received data being clocked by a clock of the second clock domain; as well as a data synchronization circuit operatively coupled between the first clock domain circuit and the second clock domain circuit, the data synchronization circuit being configured to synchronize a reset signal of the first clock domain to the second clock domain and prevent a metastable value from propagating into the second clock domain circuit; The data synchronization circuit comprises: a first flip-flop having an input for receiving data from the first clock domain circuit, a reset coupled to a reset signal of the second clock domain, and an output for providing sampled data, the first flip-flop being enabled by a request enable signal; a second flip-flop having an input coupled to an inverted output of the second flip-flop, an output for providing a request signal, and a reset coupled to the reset signal of the first clock domain, the second flip-flop being enabled by the request enable signal; a request signal path having an input coupled to the request signal and an output for providing an enable signal synchronized to the second clock domain, the request signal path being configured to synchronize and delay the request signal by a first delay and to generate the enable signal based on the synchronized request signal; a synchronous reset signal path having an input coupled to the reset signal of the first clock domain and an output for providing a synchronous reset signal, the synchronous reset signal path being configured to synchronize the reset signal of the first clock domain and delay it by a second delay, wherein the second delay is shorter than the first delay; and A multiplexer having a first input for receiving the output of the recycling multiplexer, a second input for receiving the reset value of the programmable register, and a select input for receiving the synchronized reset signal, the multiplexer being configured to selectively output the signal at the input of the multiplexer to the output of the multiplexer.

13. The system of claim 12, wherein the request signal path comprises three flip-flops coupled in series, wherein each flip-flop has a reset coupled to the reset signal of the second clock domain.

14. The system of claim 13 , wherein the request signal path further comprises a fourth flip-flop having an input coupled to the three serially coupled flip-flops; and an XOR gate having a first input for receiving an output of the fourth flip-flop, a second input for receiving an output of the three serially coupled flip-flops, and an output for providing an enable signal for the recycling multiplexer, the enable signal being synchronized to the second clock domain.

15. The system of claim 12, wherein the synchronous reset signal path comprises two flip-flops coupled in series, wherein each flip-flop has a reset coupled to the reset signal of the second clock domain.

16. The system of claim 12, wherein the first flip-flop and the second flip-flop are clocked by a clock of the first clock domain.

17. A method performed by the electronic system of any one of claims 12 to 16, comprising: Synchronizing a reset of the first clock domain to the second clock domain; as well as It is ensured that synchronization and delay of the request signal from the first clock domain in the second clock domain are slower than synchronization and delay of the reset of the first clock domain in the second clock domain.

18. The method according to claim 17, further comprising: The data sampling trigger in the first clock domain is reset by utilizing the reset of the second clock domain.

19. The method of claim 17, wherein the reset of the first clock domain and the reset of the second clock domain are different resets.

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