Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor package device and a manufacturing method thereof. The semiconductor package device includes a redistribution layer including an upper redistribution layer and a lower redistribution layer, a reinforcement layer disposed between the upper redistribution layer and the lower redistribution layer, the reinforcement layer having a bonding interface, a first electronic component and a second electronic component disposed on the redistribution layer. The reinforcement layer provides a rigid support to the redistribution layer, and the reinforcement layer can provide a pulling force to the redistribution layer to reduce the warpage of the redistribution layer, and thus reduce the risk of breaking of the conductive lines due to the warpage of the redistribution layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] In current fan-out chip-on-substrate (FOCOS) structures, the coefficient of thermal expansion of the dielectric material in the redistribution layer is significantly greater than that of the conductive metal material. Therefore, as the number of redistribution layers increases, the warpage of the entire redistribution layer easily increases due to the difference in the coefficients of thermal expansion. Since the conductive lines in the redistribution layer cannot withstand the stretching caused by this warpage, problems such as… Figure 1 The problem of a broken conductive line is shown in the dashed line section. Summary of the Invention

[0003] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0004] The redistribution layer includes the upper redistribution layer and the lower redistribution layer;

[0005] A reinforcement layer is disposed between the upper redundancy layer and the lower redundancy layer, and the reinforcement layer has a bonding interface;

[0006] The first electronic component and the second electronic component are disposed on the redistribution layer.

[0007] In some alternative embodiments, the reinforcement layer is provided with a wiring layer that is electrically connected to the upper heavy-duty wiring layer and the lower heavy-duty wiring layer.

[0008] In some alternative implementations, the circuit layer has gaps at the bonding interface.

[0009] In some alternative embodiments, the circuit layer has a misalignment structure at the bonding interface.

[0010] In some optional embodiments, the redistribution layer further includes a first via, and the reinforcement layer is provided with a second via, the diameter of the second via being smaller than the diameter of the first via.

[0011] In some alternative embodiments, the apparatus further includes:

[0012] Electrical connectors are disposed below the redistribution layer.

[0013] In some alternative embodiments, the apparatus further includes:

[0014] A substrate is disposed below the redistribution layer and is electrically connected to the redistribution layer via the electrical connector.

[0015] In some alternative embodiments, the apparatus further includes:

[0016] The circuit is located at the interface.

[0017] In some optional embodiments, the reinforcement layer includes a first sub-reinforcement layer and a second sub-reinforcement layer sequentially disposed on the bonding interface, the second sub-reinforcement layer being disposed between the first sub-reinforcement layer and the upper redistribution layer, and the adhesion between the second sub-reinforcement layer and the upper redistribution layer being greater than the adhesion between the first sub-reinforcement layer and the upper redistribution layer.

[0018] In some alternative implementations, the rigidity of the reinforcement layer is greater than that of the redistribution layer.

[0019] In some alternative implementations, the coefficient of thermal expansion of the reinforcement layer is less than that of the redistribution layer.

[0020] Secondly, this disclosure provides a semiconductor packaging apparatus, comprising:

[0021] The reinforcement layer includes an upper reinforcement layer and a lower reinforcement layer;

[0022] A redundancy layer is disposed between the upper reinforcement layer and the lower reinforcement layer;

[0023] The first electronic component and the second electronic component are disposed on the reinforcing layer.

[0024] Thirdly, a method for manufacturing a semiconductor packaging device includes:

[0025] A first carrier board is provided, and a first sub-reinforcement layer is provided on the first carrier board, wherein the first sub-reinforcement layer is provided with a first sub-circuit layer;

[0026] An upper redundancy layer is provided on the first sub-reinforcement layer;

[0027] A second carrier board is provided, and a second sub-reinforcement layer is provided on the second carrier board, the second sub-reinforcement layer being provided with a second sub-circuit layer;

[0028] A lower redundancy layer is provided on the second sub-reinforcement layer;

[0029] Remove the first carrier board and the second carrier board;

[0030] The first sub-reinforcing layer is bonded to the second sub-reinforcing layer to form a reinforcing layer. The reinforcing layer has a bonding interface. The first sub-circuit layer and the second sub-circuit layer are electrically connected at the bonding interface to form a circuit layer.

[0031] A first electronic component and a second electronic component are disposed on the upper redistribution layer.

[0032] The semiconductor packaging apparatus and manufacturing method disclosed herein are designed to include: a redistribution layer comprising an upper redistribution layer and a lower redistribution layer; a reinforcing layer disposed between the upper and lower redistribution layers, the reinforcing layer having a bonding interface; and a first electronic component and a second electronic component disposed on the redistribution layer. The reinforcing layer strengthens the redistribution layer, providing greater rigidity support, and also provides tensile force to the redistribution layer, thereby reducing warping of the redistribution layer due to thermal expansion during the thermal process, and thus reducing the risk of conductive line breakage due to warping during the thermal process. Attached Figure Description

[0033] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0034] Figure 1 This is a longitudinal cross-sectional structural diagram of an embodiment of a semiconductor packaging device in the prior art;

[0035] Figure 2A This is a schematic diagram of the longitudinal cross-sectional structure of the semiconductor packaging apparatus 200a according to an embodiment of the present disclosure;

[0036] Figure 2B and 2C for Figure 2A A longitudinal cross-sectional schematic diagram of the partial structure of the dashed section in some embodiments;

[0037] Figure 2D and 2E These are schematic diagrams of the longitudinal cross-sectional structures of the semiconductor packaging devices 200d and 200e according to the present disclosure;

[0038] Figures 3A to 3H This is a longitudinal cross-sectional structural diagram of a semiconductor packaging device manufactured at different stages according to an embodiment of the present disclosure.

[0039] Symbol explanation:

[0040] 11-Redundancy layer; 111-Upper redundancy layer; 112-Lower redundancy layer; 12-Reinforcing layer; 121-Upper reinforcing layer; 1211-First sub-reinforcing layer; 1212-Second sub-reinforcing layer; 122-Lower reinforcing layer; 123-Connection interface; 13-First electronic component; 14-Second electronic component; 15-Circuit layer; 151-First sub-circuit layer; 152-Second sub-circuit layer; 16-First via; 17-Second via; 18-First electrical connector; 19-Substrate; 20-Circuit; 21-Gap; 31-First carrier board; 32-Second carrier board; 33-Through hole; 34-Second electrical connector; 35-First underfill; 36-Second underfill; 37-Encapsulation material; 38-Encapsulation cap. Detailed Implementation

[0041] The specific embodiments of this disclosure will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this disclosure and the resulting technical effects through the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0042] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are merely for illustrative purposes to aid those skilled in the art in understanding and reading the content described herein, and are not intended to limit the implementation conditions of this disclosure. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and purpose of this disclosure, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of this disclosure's implementation.

[0043] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0044] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified.

[0045] refer to Figure 2A , Figure 2A This is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor packaging apparatus 200a according to an embodiment of the present disclosure.

[0046] like Figure 2AAs shown, the semiconductor packaging device 200a includes: a redistribution layer 11, a hardening layer 12, a first electronic component 13, and a second electronic component 14. Wherein:

[0047] The redistribution layer 11 includes an upper redistribution layer 111 and a lower redistribution layer 112.

[0048] The redistribution layer 11 can be a redistribution layer composed of conductive and dielectric materials. Here, the dielectric material can include organic and / or inorganic materials, wherein organic materials can be, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while inorganic materials can be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material can include a seed layer and a metal layer. Here, the seed layer can be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or their alloys.

[0049] A reinforcement layer 12 is disposed between the upper redundancy layer 111 and the lower redundancy layer 112, and the reinforcement layer 12 has a bonding interface 123.

[0050] The reinforcing layer 12 can be a reinforcing layer composed of inorganic materials. Here, the inorganic material can be, for example, silicon oxide, silicon nitride, etc. The reinforcing layer 12 can reinforce the redistribution layer 11.

[0051] In some alternative embodiments, the Young's modulus of the reinforcing layer 12 is greater than that of the redistribution layer 11, thus providing support for the redistribution layer 11. Furthermore, the coefficient of thermal expansion of the reinforcing layer 12 is less than that of the redistribution layer 11.

[0052] In some alternative embodiments, the reinforcing layer 12 includes an upper reinforcing layer 121 and a lower reinforcing layer 122, which are bonded together at a bonding interface 123. Optionally, the upper reinforcing layer 121 bonds the lower reinforcing layer 122 via hybrid bonding (HBI) to form the bonding interface 123.

[0053] The first electronic component 13 and the second electronic component 14 are disposed on the redistribution layer 11.

[0054] This disclosure does not specifically limit the types of the first electronic component 13 and the second electronic component 14. The first electronic component 13 and the second electronic component 14 may include, for example, a die, an ASIC (Application Specific Integrated Circuit) chip, or an HBM (High Bandwidth Memory) chip.

[0055] The technical effects that the semiconductor packaging apparatus 200a of the above embodiments provided in this disclosure can achieve include, but are not limited to: reinforcing the redistribution layer 11 by the reinforcing layer 12, the reinforcing layer 12 can provide greater rigid support for the redistribution layer 11, and the reinforcing layer 12 can provide tensile force on the redistribution layer 11 to reduce the warping of the redistribution layer 11 due to thermal expansion during the thermal process, thereby reducing the risk of conductive line breakage due to warping of the redistribution layer 11 during the thermal process.

[0056] In some alternative implementations, such as Figure 2A As shown, the reinforcement layer 12 is provided with a wiring layer 15, which is electrically connected to the upper heavy wiring layer 111 and the lower heavy wiring layer 112.

[0057] The circuit layer 15 can be a circuit layer composed of a conductive material. Here, the conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0058] Continue to refer to Figure 2B , Figure 2B for Figure 2A The dashed section is a longitudinal cross-sectional view of a portion of the structure in some embodiments. In some alternative embodiments, such as... Figure 2B As shown, the wiring layer 15 has a staggered structure at the bonding interface 123. It can be understood that electrical connection can be achieved by partially connecting the wiring layer 15 at the bonding interface.

[0059] Continue to refer to Figure 2C , Figure 2C for Figure 2A A longitudinal cross-sectional view of the partial structure within the dashed line portion in some embodiments. In some alternative embodiments, such as Figure 2CAs shown, the circuit layer 15 has a gap 21 at the bonding interface 123. It is understood that in actual manufacturing, the connection point of the circuit layer 15 at the bonding interface 123 may not be a completely flat surface. Therefore, the circuit layer 15 has a gap 21 at the bonding interface 123. When the circuit layer 15 establishes an electrical connection at the bonding interface 123, the fault tolerance of the semiconductor packaging device 200a can be improved.

[0060] In some alternative implementations, such as Figure 2A As shown, the redistribution layer 11 also includes a first guide hole 16, and the reinforcement layer 12 is provided with a second guide hole 17, the diameter of the second guide hole 17 being smaller than the diameter of the first guide hole 16.

[0061] In some alternative embodiments, the aperture of the second guide hole 17 is less than 10 micrometers.

[0062] In some alternative implementations, such as Figure 2A As shown, the structures of the upper reinforcing layer 121 and the lower reinforcing layer 122 are symmetrical relative to the bonding interface 123. Taking the upper reinforcing layer 121 as an example, the upper reinforcing layer 121 may include a first sub-reinforcing layer 1211 and a second sub-reinforcing layer 1212 sequentially disposed on the bonding interface 123. The second sub-reinforcing layer 1212 is disposed between the first sub-reinforcing layer 1211 and the upper redundancy layer 111. The adhesion between the second sub-reinforcing layer 1212 and the upper redundancy layer 111 is higher than that between the first sub-reinforcing layer 1211 and the upper redundancy layer 111. By disposing of the second sub-reinforcing layer 1212 between the first sub-reinforcing layer 1211 and the upper redundancy layer 111, the adhesion between the reinforcing layer 12 and the redundancy layer 11 can be improved, thereby enhancing the fixing effect of the reinforcing layer 12 on the redundancy layer 11.

[0063] Here, the first sub-reinforcing layer 1211 may be, for example, a reinforcing layer composed of silicon oxide, and the second sub-reinforcing layer 1212 may be, for example, a reinforcing layer composed of silicon nitride.

[0064] In some alternative implementations, such as Figure 2A As shown, the semiconductor packaging device 200a further includes a first electrical connector 18 disposed below the redistribution layer 11. The redistribution layer 11 can be electrically connected to the outside world through the first electrical connector 18.

[0065] Continue to refer to Figure 2D , Figure 2D The semiconductor packaging device 200d shown is similar to Figure 2A The semiconductor packaging device 200a shown is different in that, in the semiconductor packaging device 200d: the redistribution layer 11 is disposed between the upper reinforcing layer 121 and the lower reinforcing layer 122, and the first electronic component 13 and the second electronic component 14 are disposed on the upper reinforcing layer 121.

[0066] Continue to refer to Figure 2E , Figure 2E The semiconductor packaging device 200e shown is similar to Figure 2A The semiconductor packaging device 200a shown differs in that the semiconductor packaging device 200e also includes: line 20.

[0067] Line 20 is disposed on the bonding interface 123. Here, line 20 may be part of line layer 15, line 20 may be a conductive line electrically connected to line layer 15, or line 20 may not be electrically connected to line layer 15.

[0068] The following is for reference. Figures 3A to 3H , Figure 3A , 3B Schematic diagram of longitudinal cross-sectional structure of semiconductor packaging devices 300a, 300b, 300c, 300d, 300e, 300f, 300g and 300h manufactured at different stages according to an embodiment of the present disclosure.

[0069] refer to Figure 3A First, a first carrier board 31 is provided.

[0070] Then, a first sub-reinforcing layer 1211 and a second sub-reinforcing layer 1212 are sequentially disposed on the first carrier plate 31 to form an upper reinforcing layer 121.

[0071] Here, a first sub-reinforcing layer 1211 and a second sub-reinforcing layer 1212 can be sequentially formed on the first carrier plate 31 by chemical vapor deposition (CVD).

[0072] refer to Figure 3B A through hole 33 is made in the upper reinforcing layer 121.

[0073] Through hole 33 penetrates the upper reinforcing layer 121.

[0074] Here, the through hole 33 can be obtained by etching, and the etching method may include laser etching or plasma etching, etc.

[0075] refer to Figure 3C First, a first sub-circuit layer 151 is formed on the upper reinforcing layer 121, and the first sub-circuit layer 151 includes a second via 17.

[0076] Here, techniques such as electroplating, electroless plating, or similar techniques are used on the partial surface of the via 33 and the upper reinforcing layer 121 at the port of the via 33. For example, a seed layer can be formed on the partial surface of the via 33 and the upper reinforcing layer 121 at the port of the via 33, and a metal material layer can be formed on the upper surface of the seed layer to form the first sub-circuit layer 151.

[0077] Then, an upper rewiring layer 111 is provided on the upper reinforcement layer 121, and the upper rewiring layer 111 is electrically connected to the first sub-line layer 151.

[0078] The substrate formation process can employ currently known or future-developed substrate formation technologies, and this disclosure does not specifically limit it. For example, the upper redistribution layer 111 can be formed using methods including but not limited to photolithography, electroplating, and electroless plating. The upper redistribution layer 111 can include dielectric materials and various conductive materials, such as titanium (Ti), tungsten (W), nickel (Ni), gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0079] refer to Figure 3D A second electrical connector 34 is provided on the upper wiring layer 111, and the second electrical connector 34 is electrically connected to the upper wiring layer 111.

[0080] refer to Figure 3E First, a second carrier board 32 is provided, a lower reinforcing layer 122 is provided on the carrier board 32, and a second sub-circuit layer 152 is formed on the lower reinforcing layer 122.

[0081] Then, a lower redundancy layer 112 is provided on the lower reinforcement layer 122.

[0082] Here, the specific method for setting a lower reinforcement layer 122 on the second carrier board 32, forming a second sub-circuit layer 152 on the lower reinforcement layer 122, and setting a lower redistribution layer 112 on the lower reinforcement layer 122 is as follows: Figures 3A to 3C The methods for setting an upper reinforcing layer 121 on the first carrier board 31, forming a first sub-circuit layer 151 on the upper reinforcing layer 121, and setting an upper redistribution layer 111 on the upper reinforcing layer 121 are exactly the same or corresponding, and can be referred to. Figures 3A to 3C The corresponding methods will not be elaborated here.

[0083] Finally, a first electrical connector 18 is provided on the lower redundancy layer 112.

[0084] In electrical connection processes, techniques such as flip chip bonding (FCB), thermal compression bonding (TCB), or similar technologies can be used.

[0085] refer to Figure 3F First, remove the first carrier plate 31 and the second carrier plate 32.

[0086] Then, the upper reinforcing layer 121 and the lower reinforcing layer 122 are positioned opposite each other and bonded to form a reinforcing layer 12. The reinforcing layer 12 has a bonding interface 123. The first sub-circuit layer 151 and the second sub-circuit layer 152 are electrically connected at the bonding interface 123 to form a circuit layer 15.

[0087] In the bonding process, techniques such as flip chip bonding (FCB), thermal compression bonding (TCB), or similar technologies can be used.

[0088] refer to Figure 3G A first electronic component 13 and a second electronic component 14 are disposed on the upper redistribution layer 111. After bonding, the first electronic component 13 and the second electronic component 14 are electrically connected to the upper redistribution layer 111 respectively.

[0089] refer to Figure 3H First, a substrate 19 is disposed under the lower redundancy layer 112, and the substrate 19 is electrically connected to the lower redundancy layer 112 through a first electrical connector 18.

[0090] Then, a first underfiller 35 is filled between the upper redistribution layer 111 and the first electronic component 13 and the second electronic component 14, and a second underfiller 36 is filled between the lower redistribution layer 112 and the first electrical connector 18.

[0091] Then, the packaging material 37 is used for encapsulation, and a packaging cover (Lid) 38 is fitted to obtain a semiconductor packaging device 300h.

[0092] The encapsulation material 37 can be formed from various molding compounds. For example, molding compounds may include epoxy molding compounds (EMC), epoxy resin, fillers, catalysts, pigments, release agents, flame retardants, coupling agents, hardeners, low stress absorbers, adhesion promoters, ion trapping agents, etc. The encapsulation cap 38 can be a cap lid formed from a metallic material.

[0093] In actual manufacturing processes, the packaging device can be flipped as needed; no specific limitations are made here.

[0094] The method for manufacturing semiconductor structures disclosed herein can achieve similar technical effects to the aforementioned semiconductor structures, and will not be described in detail here.

[0095] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent components can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: a redistribution layer, comprising an upper redistribution layer and a lower redistribution layer; a reinforcement layer, disposed between the upper redistribution layer and the lower redistribution layer, the reinforcement layer having an interface; a first electronic component and a second electronic component, disposed on the redistribution layer; the reinforcement layer comprises an upper reinforcement layer and a lower reinforcement layer, the upper reinforcement layer is bonded to the lower reinforcement layer by a hybrid bond, forming the interface; the upper reinforcement layer comprises a first sub-reinforcement layer and a second sub-reinforcement layer disposed in sequence on the interface, the second sub-reinforcement layer is disposed between the first sub-reinforcement layer and the upper redistribution layer, the adhesion of the second sub-reinforcement layer to the upper redistribution layer is greater than the adhesion of the first sub-reinforcement layer to the upper redistribution layer; the reinforcement layer is provided with a circuit layer, the circuit layer electrically connects the upper redistribution layer and the lower redistribution layer; the circuit layer has a gap at the interface; the circuit layer has a misalignment structure at the interface; the redistribution layer further comprises a first via, the reinforcement layer is provided with a second via, the aperture of the second via is smaller than the aperture of the first via.

2. The apparatus of claim 1, wherein, the device further comprises: an electrical connector, disposed below the redistribution layer.

3. The apparatus of claim 2, wherein, the device further comprises: a substrate, disposed below the redistribution layer, electrically connected to the redistribution layer through the electrical connector.

4. The apparatus of claim 1, wherein, the device further comprises: a circuit, disposed on the interface.

5. The apparatus of claim 1, wherein, the reinforcement layer has a rigidity greater than that of the redistribution layer.

6. The apparatus of claim 1, wherein, the reinforcement layer has a coefficient of thermal expansion less than that of the redistribution layer. 7.A method for manufacturing a semiconductor packaging device, comprising: providing a first carrier, and disposing an upper reinforcement layer on the first carrier, the upper reinforcement layer being provided with a first sub-circuit layer; disposing an upper redistribution layer on the upper reinforcement layer; providing a second carrier, and disposing a lower reinforcement layer on the second carrier, the lower reinforcement layer being provided with a second sub-circuit layer; disposing a lower redistribution layer on the lower reinforcement layer; removing the first carrier and the second carrier; bonding the upper reinforcement layer to the lower reinforcement layer, forming a reinforcement layer, the reinforcement layer having an interface, the first sub-circuit layer and the second sub-circuit layer being electrically connected at the interface, forming a circuit layer; disposing a first electronic component and a second electronic component on the upper redistribution layer.

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