Semiconductor package structure

Abstract

A semiconductor package structure includes a front redistribution layer, a first semiconductor die disposed above the front redistribution layer, a first capacitor disposed above the front redistribution layer and electrically coupled to the first semiconductor die, a conductive terminal disposed below the front redistribution layer and electrically connected to the front redistribution layer, and a back redistribution layer disposed above the first semiconductor die. Compared with a semiconductor package structure with pad-side capacitors, the semiconductor package structure according to the present application has capacitors that do not occupy conductive terminal space, which can increase design flexibility.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor packaging structure. Background Technology

[0002] With the increasing demand for smaller devices with more functions, three-dimensional integrated circuit (3DIC) packaging technology, which vertically stacks two or more semiconductor chips or dies, is becoming increasingly popular. 3D IC packaging technology uses interconnection methods such as wire bonding and flip chip to achieve vertical stacking. Therefore, manufacturing costs can be reduced in 3D IC packaging, and performance improvements can be achieved with lower power consumption and a smaller footprint compared to traditional two-dimensional (2D) IC packaging technologies.

[0003] However, while existing semiconductor packaging structures are generally sufficient, they are not satisfactory in every aspect. 3D IC packaging technology introduces new challenges, such as thermal and power delivery network (PDN) design issues. These problems reduce the reliability of semiconductor packaging structures. Therefore, further improvements to semiconductor packaging structures are needed. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor packaging structure to solve the above problems.

[0005] According to a first aspect of the present invention, a semiconductor package structure is disclosed, comprising:

[0006] Frontal redistribution layer;

[0007] The first semiconductor die is disposed above the front redistribution layer;

[0008] A first capacitor is disposed above the front redistribution layer and electrically coupled to the first semiconductor die;

[0009] Conductive terminals are disposed below the front redistribution layer and electrically connected to the front redistribution layer; and

[0010] A back redistribution layer is disposed above the first semiconductor die.

[0011] According to a second aspect of the present invention, a semiconductor packaging structure is disclosed, comprising:

[0012] The substrate has a wiring structure;

[0013] A semiconductor die is disposed above the substrate and electrically coupled to the wiring structure;

[0014] The bump structure is located adjacent to the semiconductor die;

[0015] Molding material surrounding the semiconductor die and the bump structure; and

[0016] A capacitor structure is disposed on the molding material and coupled to the semiconductor die through the bump electrical coupling and the wiring structure.

[0017] According to a third aspect of the present invention, a semiconductor packaging structure is disclosed, comprising:

[0018] Redistribution layer;

[0019] A multi-capacitor structure is disposed below the redistribution layer;

[0020] A bottom semiconductor die, disposed above the redistribution layer and having a via, wherein the bottom semiconductor die is electrically coupled to the multi-capacitor structure through the redistribution layer; and

[0021] A top semiconductor die is disposed above the bottom semiconductor die and electrically coupled to the multi-capacitor structure through the via and the redistribution layer.

[0022] The semiconductor package structure of the present invention includes: a front redistribution layer; a first semiconductor die disposed above the front redistribution layer; a first capacitor disposed above the front redistribution layer and electrically coupled to the first semiconductor die; a conductive terminal disposed below the front redistribution layer and electrically connected to the front redistribution layer; and a back redistribution layer disposed above the first semiconductor die. Compared with semiconductor package structures having pad-side capacitors, the semiconductor package structure according to the present invention has a capacitor that does not occupy the space of the conductive terminals, which can increase design flexibility. Attached Figure Description

[0023] Figure 1A This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;

[0024] Figure 1B This is a top view of a multi-terminal multi-capacitor structure of an exemplary semiconductor package structure according to some embodiments;

[0025] Figure 2A This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;

[0026] Figure 2B This is a top view of a multi-terminal multi-capacitor structure of an exemplary semiconductor package structure according to some embodiments;

[0027] Figure 3This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;

[0028] Figure 4 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;

[0029] Figure 5A and 5B This is a cross-sectional view of a multi-capacitor structure based on an exemplary semiconductor package structure according to some embodiments;

[0030] Figure 6 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;

[0031] Figure 7 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;

[0032] Figure 8 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments;

[0033] Figure 9 These are cross-sectional views of exemplary semiconductor package structures according to some embodiments; and

[0034] Figure 10 This is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments. Detailed Implementation

[0035] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0036] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0037] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0038] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0039] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0040] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0041] Semiconductor package structures including capacitors are described according to some embodiments of the present invention. Compared to embodiments that remove some conductive terminals to make room for the capacitor, embodiments of the present invention can retain more conductive terminals. Furthermore, in some embodiments, the complexity of manufacturing the semiconductor package structure can be reduced.

[0042] Figure 1A This is a cross-sectional view of a semiconductor package structure 100 according to some embodiments of the present invention. Additional features can be added to the semiconductor package structure 100. For different embodiments, some features described below can be replaced or eliminated. For the sake of simplicity, only a portion of the semiconductor package structure 100 is shown.

[0043] like Figure 1A As shown, according to some embodiments, the semiconductor package structure 100 includes a redistribution layer, which may include multiple conductive layers RDL1, RDL2, RDL3, and RDL4. Four conductive layers RDL1, RDL2, RDL3, and RDL4 are shown for illustrative purposes only, but there may be more or fewer than four conductive layers.

[0044] In some embodiments, the redistribution layer includes a plurality of passivation layers (in... Figure 1A (omitted and not shown), and conductive layers RDL1, RDL2, RDL3 and RDL4 are disposed in the passivation layer. Conductive layers RDL1, RDL2, RDL3 and RDL4 can be electrically coupled to each other through multiple conductive vias 116 in the passivation layer.

[0045] The conductive layers RDL1, RDL2, RDL3, and RDL4 can be formed of metals, such as copper, titanium, tungsten, aluminum, or combinations thereof. The conductive via 116 can be formed of metals, such as copper, titanium, tungsten, aluminum, or combinations thereof.

[0046] In some embodiments, the passivation layer comprises a polymer layer, such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, or combinations thereof. Alternatively, the passivation layer may comprise a dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof.

[0047] like Figure 1A As shown, according to some embodiments, the semiconductor package structure 100 includes a first semiconductor die 102 and a second semiconductor die 104 vertically stacked above a redistribution layer. The first semiconductor die 102 and the second semiconductor die 104 may also be referred to as the top semiconductor die 102 and the bottom semiconductor die 104, respectively.

[0048] According to some embodiments, the first semiconductor die 102 and the second semiconductor die 104 each independently include a system-on-chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, or any combination thereof.

[0049] For example, the first semiconductor die 102 and the second semiconductor die 104 may each independently include a micro control unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a global positioning system (GPS) device, an accelerated processing unit (APU) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input-output (I / O) die, a dynamic random access memory (DRAM) controller, a static random-access memory (SRAM), a high bandwidth memory (HBM), or any combination thereof.

[0050] According to some embodiments, the semiconductor package structure 100 also includes one or more passive elements (not shown), such as resistors, capacitors, inductors, or combinations thereof.

[0051] like Figure 1A As shown, the first semiconductor die 102 may have an XPU core 106, and the second semiconductor die 104 may have an XPU core 108. The XPU core 108 of the second semiconductor die 104 may be electrically coupled to a redistribution layer. The second semiconductor die 104 may have vias therein. The XPU core 106 of the first semiconductor die 102 may be electrically coupled to the redistribution layer through the vias in the second semiconductor die 104.

[0052] like Figure 1AAs shown, according to some embodiments, the semiconductor package structure 100 includes a multi-terminal multi-capacitor structure 110 disposed below the redistribution layer. The multi-terminal multi-capacitor structure 110 may have a plurality of terminals 112 and can be electrically coupled to a first semiconductor die 102 and a second semiconductor die 104 through the redistribution layer and the terminals 112.

[0053] The multi-terminal multi-capacitor structure 110 may have one or more capacitors and one or more terminals 112, wherein these capacitors are electrically coupled to the first semiconductor die 102 and the second semiconductor die 104, respectively. That is, the multi-terminal multi-capacitor structure 110 may be a multi-capacitor structure.

[0054] Compared to embodiments where the semiconductor package structure includes separate capacitors for the first semiconductor die 102 and the second semiconductor die 104, the semiconductor package structure 100 uses a multi-terminal multi-capacitor structure 110 for the first semiconductor die 102 and the second semiconductor die 104, which can reduce the space occupied. Furthermore, it can improve design flexibility.

[0055] like Figure 1A As shown, the first semiconductor die 102 and the second semiconductor die 104 can overlap the multi-terminal multi-capacitor structure 110 in a direction substantially parallel to the stacking direction of the first semiconductor die 102 and the second semiconductor die 104.

[0056] In some embodiments, two semiconductor dies, the first semiconductor die 102 and the second semiconductor die 104, share a multi-terminal multi-capacitor structure 110, but the invention is not limited thereto. For example, more than two semiconductor dies may share the multi-terminal multi-capacitor structure 110. Alternatively, more than one multi-terminal multi-capacitor structure may be used for multiple semiconductor dies.

[0057] Figure 1B This is a top view of the multi-terminal multi-capacitor structure 110 of a semiconductor package structure 100 according to some embodiments. For example... Figure 1B As shown, the multi-terminal multi-capacitor structure 110 may include multiple first terminals 112a, multiple second terminals 112b, and multiple ground terminals 112c.

[0058] The first terminal 112a can be electrically coupled to the power supply terminal of the first semiconductor die 102. The second terminal 112b can be electrically coupled to the power supply terminal of the second semiconductor die 104. The ground terminal 112c can be electrically coupled to the ground terminals of the first semiconductor die 102 and the second semiconductor die 104. Specifically, the ground terminals of the first semiconductor die 102 and the second semiconductor die 104 can be connected to each other and grounded. Alternatively, the ground terminals of the first semiconductor die 102 and the second semiconductor die 104 can be grounded separately.

[0059] In some embodiments, the first terminal 112a may be arranged along a first line, the second terminal 112b may be arranged along a second line, and the ground terminal 112c may be arranged along a third line. The first line, the second line, and the third line may be parallel to each other.

[0060] The grounding terminal 112c can be disposed between a column of first terminals 112a and a column of second terminals 112b, or between two columns of second terminals 112b. The number and arrangement of the first terminals 112a, second terminals 112b, and grounding terminal 112c shown in the figures are merely exemplary and are not intended to limit the invention. For example, the first terminals 112a can be arranged along two lines, and the grounding terminal 112c can be disposed between two columns of first terminals 112a.

[0061] Return to reference Figure 1A According to some embodiments, the semiconductor package structure 100 includes a plurality of conductive terminals 114 disposed below the redistribution layer and adjacent to the multi-terminal multi-capacitor structure 110. That is, the multi-terminal multi-capacitor structure 110 may be disposed between the conductive terminals 114.

[0062] The conductive terminal 114 can be electrically coupled to the redistribution layer. In some embodiments, the conductive terminal 114 is formed of a conductive material, such as a metal. The conductive terminal 114 may include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, or combinations thereof.

[0063] like Figure 1A As shown, the multi-terminal multi-capacitor structure 110 can occupy the area of ​​the conductive terminals 114. Furthermore, since the first semiconductor die 102 and the second semiconductor die 104 are vertically stacked and have the same projected area, according to available resources, the number of available conductive terminals 114 below the first semiconductor die 102 and the second semiconductor die 104 can be less than that of semiconductor dies arranged side-by-side.

[0064] As the demand for more functionality and smaller devices continues to increase, these issues make it more difficult to integrate individual capacitors for different semiconductor chips. In view of this, the semiconductor package structure 100 of the present invention uses a multi-terminal multi-capacitor structure 110 instead of individual capacitors, which can reduce the area occupied by capacitors and retain more conductive terminals 114.

[0065] Figure 2A This is a cross-sectional view of a semiconductor package structure 200 according to some embodiments of the present invention. It should be noted that the semiconductor package structure 200 may include... Figure 1A The semiconductor package structure 100 shown contains the same or similar components, which will not be described again for simplicity. In the following embodiments, a multi-terminal multi-capacitor structure is disposed under the substrate.

[0066] like Figure 2A As shown, according to some embodiments, the semiconductor package structure 200 includes a substrate 202. The substrate 202 may have wiring structures therein. In some embodiments, the wiring structures in the substrate 202 include conductive layers, conductive vias, conductive pillars, etc., or combinations thereof. The wiring structures in the substrate 202 may be formed of a metal, such as copper, aluminum, etc., or combinations thereof.

[0067] The wiring structure in substrate 202 can be disposed in an inter-metal dielectric (IMD) layer. In some embodiments, the IMD layer can be formed of organic materials such as polymer substrates, inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, etc., or combinations thereof. Substrate 202 may include an insulating core, such as a glass fiber reinforced resin core, to prevent substrate 202 from warping.

[0068] It should be noted that the configuration of the substrate 202 shown in the figure is merely exemplary and is not intended to limit the present invention. Any desired semiconductor component can be formed in and on the substrate 202. However, for the sake of simplicity, only a flat substrate 202 is shown.

[0069] like Figure 2A As shown, according to some embodiments, the semiconductor package structure 200 includes a multi-terminal multi-capacitor structure 210 disposed below a substrate 202. The multi-terminal multi-capacitor structure 210 may have a plurality of terminals 212 and is electrically connected to a first semiconductor die 102 and a second semiconductor die 104 through a redistribution layer, conductive terminals 114, wiring structures in the substrate 202, and terminals 212.

[0070] The multi-terminal multi-capacitor structure 210 may have one or more capacitors and one or more terminals 212, wherein these capacitors are electrically coupled to the first semiconductor die 102 and the second semiconductor die 104, respectively. That is, the multi-terminal multi-capacitor structure 210 may be a multi-capacitor structure.

[0071] As described above, according to some embodiments, the use of a multi-terminal multi-capacitor structure 210 for the first semiconductor die 102 and the second semiconductor die 104 in the semiconductor package structure 200 can reduce the space occupied and improve design flexibility. In this embodiment, both the multi-terminal multi-capacitor structure 110 and the multi-terminal multi-capacitor structure 210 can be used simultaneously, thus further reducing the space occupied and improving design flexibility.

[0072] Figure 2B This is a top view of the multi-terminal multi-capacitor structure 210 of a semiconductor package structure 200 according to some embodiments. For example... Figure 2B As shown, the multi-terminal multi-capacitor structure 210 may include multiple first terminals 212a, multiple second terminals 212b, and multiple ground terminals 212c.

[0073] The first terminal 212a can be electrically coupled to the power supply terminal of the first semiconductor die 102. The second terminal 212b can be electrically coupled to the power supply terminal of the second semiconductor die 104. The ground terminal 212c can be electrically coupled to the ground terminals of the first semiconductor die 102 and the second semiconductor die 104. Specifically, the ground terminals of the first semiconductor die 102 and the second semiconductor die 104 can be connected to each other and grounded. Alternatively, the ground terminals of the first semiconductor die 102 and the second semiconductor die 104 can be grounded separately.

[0074] The first terminal 212a, the second terminal 212b, and the grounding terminal 212c can be similar to Figure 1B The first terminal 112a, the second terminal 112b, and the ground terminal 112c shown will not be described in detail here.

[0075] Return to reference Figure 2A The semiconductor package structure 200 may further include a multi-terminal multi-capacitor structure 110 disposed between the substrate 202 and the redistribution layer. The multi-terminal multi-capacitor structure 110 may be similar to... Figure 1A The multi-terminal multi-capacitor structure 110 shown will not be described in detail here. The multi-terminal multi-capacitor structure 110 is optional. In some other embodiments, the multi-terminal multi-capacitor structure 110 is replaced by conductive terminals 114.

[0076] Figure 3 This is a cross-sectional view of a semiconductor package structure 300 according to some embodiments of the present invention. It should be noted that the semiconductor package structure 300 may include... Figure 1A The semiconductor package structure 100 shown contains the same or similar components, which will not be described further for simplicity. In the following embodiments, the capacitor is disposed on the back redistribution layer to retain more conductive terminals on the front redistribution layer. The front redistribution layer may be a redistribution layer disposed at the end of the die having conductive pads.

[0077] like Figure 3 As shown, according to some embodiments, the semiconductor package structure 300 includes a first package structure 300a and a second package structure 300b stacked vertically. The first package structure 300a may have a front side and a back side opposite to the front side. In some embodiments, the first package structure 300a has a front redistribution layer 302 disposed on the front side and a back redistribution layer 324 disposed on the back side.

[0078] The front redistribution layer 302 may include one or more conductive layers and passivation layers, wherein the conductive layers may be disposed within the passivation layers. The conductive layers may include metals, such as copper, titanium, tungsten, aluminum, or combinations thereof.

[0079] In some embodiments, the passivation layer comprises a polymer layer, such as polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy resin, or combinations thereof. Alternatively, the passivation layer may comprise a dielectric layer, such as silicon oxide, silicon nitride, silicon oxynitride, or combinations thereof. The material of the back redistribution layer 324 may be similar to that of the front redistribution layer 302, and will not be described further here.

[0080] like Figure 3 As shown, according to some embodiments, the front redistribution layer 302 includes more conductive and passivation layers than the back redistribution layer 324. The front redistribution layer 302 may be thicker than the back redistribution layer 324, but the invention is not limited thereto. For example, the back redistribution layer 324 may be thicker than or substantially equal to the front redistribution layer 302.

[0081] like Figure 3 As shown, according to some embodiments, the first package structure 300a includes a plurality of conductive terminals 304 disposed below and electrically coupled to the front redistribution layer 302. The conductive terminals 304 may be formed of a conductive material, such as metal. The conductive terminals 304 may include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, or combinations thereof.

[0082] like Figure 3 As shown, according to some embodiments, the first package structure 300a includes a first semiconductor die 312 and a second semiconductor die 306 vertically stacked above the front redistribution layer 302. In some embodiments, the first semiconductor die 312 and the second semiconductor die 306 each independently include a system-on-a-chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, or any combination thereof.

[0083] For example, the first semiconductor die 312 and the second semiconductor die 306 may each independently include a microcontroller unit (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a global positioning system (GPS) device, an acceleration processing unit (APU) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input / output (IO) die, a dynamic random access memory (DRAM) controller, a static random access memory (SRAM), a high bandwidth memory (HBM), or any combination thereof.

[0084] Although Figure 3 The diagram shows two semiconductor dies, a first semiconductor die 312 and a second semiconductor die 306, but one or more semiconductor dies may be present. For example, the first package structure 300a may include three semiconductor dies stacked vertically. Alternatively, the first package structure 300a may include four semiconductor dies, with two semiconductor dies stacked vertically above the first semiconductor die and another semiconductor die disposed above and adjacent to the two semiconductor dies.

[0085] In some embodiments, the first package structure 300a further includes one or more passive components (not shown) adjacent to the first semiconductor die 312 and / or the second semiconductor die 306, such as resistors, capacitors, inductors, or combinations thereof.

[0086] In some embodiments, the second semiconductor die 306 includes a plurality of vias 308 electrically coupled to the front redistribution layer 302. The vias 308 may be formed of a metal, such as copper, tungsten, or a combination thereof. Figure 3 As shown, the via 308 may have substantially vertical sidewalls and may extend from the top surface of the second semiconductor die 306 to the bottom surface of the second semiconductor die 306, but the invention is not limited thereto. The via 308 may have other configurations and other numbers.

[0087] In some embodiments, the first semiconductor die 312 includes a plurality of vias 314 electrically coupled to the back redistribution layer 324. The vias 314 may be formed of a metal, such as copper, tungsten, or a combination thereof. Figure 3 As shown, the via 314 may have substantially vertical sidewalls and may extend from the top surface of the first semiconductor die 312 to the bottom surface of the first semiconductor die 312, but the invention is not limited thereto. The via 314 may have other configurations and numbers.

[0088] like Figure 3 As shown, according to some embodiments, the first package structure 300a includes a capacitor 310 disposed below and electrically coupled to the front redistribution layer 302. The capacitor 310 may be disposed between conductive terminals 314. The capacitor 310 may have multiple terminals 310t and may be electrically coupled to the front redistribution layer 302 through the terminals 310t.

[0089] In some other embodiments, capacitor 310 is a multi-capacitor structure, such as... Figure 1A , Figure 1BThe multi-terminal multi-capacitor structure 110 shown will not be described in detail here. In these embodiments, the capacitor 310 can be electrically coupled to the first semiconductor die 312 through the front redistribution layer 302 and the through-hole 308 in the second semiconductor die 306, and can also be electrically coupled to the second semiconductor die 306 through the front redistribution layer 302.

[0090] like Figure 3 As shown, according to some embodiments, the first package structure 300a includes a molding material (or molding compound) 316 surrounding the first semiconductor die 312. The molding material 316 may cover the top surface (or upper surface) of the second semiconductor die 306 and may abut the sidewalls of the first semiconductor die 312. The molding material 316 may protect the first semiconductor die 312 from environmental influences, thereby preventing damage to the first semiconductor die 312 due to, for example, stress, chemicals and / or moisture.

[0091] The molding material 316 may include non-conductive materials, such as moldable polymers, epoxy resins, resins, or combinations thereof. In some embodiments, the molding material 316 is applied in a liquid or semi-liquid form and then cured by any suitable curing process, including, for example, thermosetting, UV curing, or combinations thereof. The molding material 316 may be shaped or molded using a mold (not shown).

[0092] The molding material 316 can then be partially removed using a planarization process, such as chemical mechanical polishing (CMP), until the top surface of the first semiconductor die 312 is exposed. In some embodiments, the top surface of the molding material 316 and the top surface of the first semiconductor die 312 are substantially coplanar. Figure 3 As shown, the sidewalls of the molding material 316 can be substantially coplanar with the sidewalls of the second semiconductor die 306.

[0093] like Figure 3 As shown, according to some embodiments of the present invention, the first package structure 300a includes a plurality of conductive pillars 318 adjacent to the first semiconductor die 312, the second semiconductor die 306, and the molding material 316. The conductive pillars 318 may be formed of metal, such as copper, tungsten, or combinations thereof. In some embodiments, the conductive pillars 318 are formed by an electroplating process or any other suitable process.

[0094] like Figure 3 As shown, the conductive post 318 may have substantially vertical sidewalls. The conductive post 318 may be disposed between the front redistribution layer 302 and the back redistribution layer 324, and may electrically couple the front redistribution layer 302 to the back redistribution layer 324.

[0095] The configuration of the conductive posts 318 shown in the figure is merely exemplary and is not intended to limit the invention. For example, the number of conductive posts 318 may differ on opposite sides of the first semiconductor die 312 and the second semiconductor die 306. Alternatively, the conductive posts 318 may be disposed on one side of the first semiconductor die 312 and the second semiconductor die 306.

[0096] like Figure 3 As shown, according to some embodiments, the first package structure 300a includes a molding material 322 surrounding a first semiconductor die 312, a second semiconductor die 306, a molding material 316, and conductive pillars 318. The molding material 322 may be adjacent to the sidewalls of the second semiconductor die 306 and the molding material 316, and may cover the top surface of the front redistribution layer 302 and the bottom surface (lower surface) of the back redistribution layer 324.

[0097] like Figure 3 As shown, the molding material 322 can fill the gaps between the conductive posts 318 and between the first semiconductor die 312 and the second semiconductor die 306 and the conductive posts 318. The molding material 322 can protect the semiconductor die 312, the second semiconductor die 306 and the conductive posts 318 from environmental influences, thereby preventing these components from being damaged due to, for example, stress, chemicals and / or moisture.

[0098] In some embodiments, the molding material 322 comprises a non-conductive material, such as a moldable polymer, epoxy resin, resin, or a combination thereof. In some embodiments, the molding material 322 is applied in a liquid or semi-liquid form and then cured by any suitable curing process, such as a thermosetting process, a UV curing process, or a combination thereof. The molding material 322 may be shaped or molded using a mold (not shown).

[0099] The molding material 322 can then be partially removed by a planarization process such as chemical mechanical polishing (CMP) until the top surface of the conductive pillar 318 is exposed. In some embodiments, the top surface of the molding material 322 and the top surface of the conductive pillar 318 are substantially coplanar. Figure 3 As shown, the sidewalls of the molding material 322 can be substantially coplanar with the sidewalls of the front redistribution layer 302 and the back redistribution layer 324. In some other embodiments, the molding material 316 can be omitted, and the molding material 322 can be adjacent to the sidewalls of the first semiconductor die 312.

[0100] like Figure 3 As shown, according to some embodiments, a back redistribution layer 324 is disposed above the first semiconductor die 312. The back redistribution layer 324 may cover the top surface of the first semiconductor die 312, the top surface of the molding material 316, the top surface of the conductive pillar 318, and the top surface of the molding material 322.

[0101] As shown in the figure, refer to Figure 3 According to some embodiments, the first package structure 300a includes a capacitor 320 disposed below the back redistribution layer 324 and surrounded by molding material 322. The capacitor 320 may be disposed between the conductive pillar 318 and the first semiconductor die 312.

[0102] like Figure 3 As shown, capacitor 320 can contact the back redistribution layer 324 and be spaced apart from the front redistribution layer 302 by molding material 322. Capacitor 320 can have multiple terminals 320t and can be electrically coupled to the first semiconductor die 312 through the terminals 320t, the back redistribution layer 324 and the via 314.

[0103] Compared to semiconductor package structures with pad-side capacitance (capacitors located on or near the pads of the die), the semiconductor package structure 300 according to the present invention has a capacitor 320 that does not occupy the space of the conductive terminals 304, which increases design flexibility. The capacitor 320 is disposed within the molding material 322, saving space. By utilizing the gap between the first semiconductor die 312 and the conductive pillars 318 to arrange the capacitor 320, idle space is fully utilized, improving space utilization.

[0104] In some other embodiments, capacitor 320 is a multi-capacitor structure, for example as... Figure 1A , Figure 1B The multi-terminal multi-capacitor structure 110 shown will not be described in detail here. In these embodiments, the capacitor 320 can be electrically coupled to the first semiconductor die 312, and can also be electrically coupled to the second semiconductor die 306 through the terminals 320t in the first semiconductor die 312, the back redistribution layer 324, the via 314, and the via 308 in the second semiconductor die 306.

[0105] In embodiments where capacitor 310 is a multi-capacitor structure electrically coupled to first semiconductor die 312 and second semiconductor die 306, capacitor 320 can be omitted. Similarly, in embodiments where capacitor 320 is a multi-capacitor structure electrically coupled to first semiconductor die 312 and second semiconductor die 306, capacitor 310 can be replaced by conductive terminal 304.

[0106] Alternatively, in some embodiments, at least one of capacitors 310 and 320 is a multi-capacitor structure, and the first package structure 300a may include two or more semiconductor dies that can be electrically coupled to capacitors 310 and 320.

[0107] like Figure 3As shown, according to some embodiments, a second package structure 300b is disposed above a first package structure 300a and electrically coupled to a back redistribution layer 324 via a plurality of conductive terminals 326. The conductive terminals 326 may be formed of a conductive material, such as metal. In some embodiments, the conductive terminals 326 include microbumps, controlled-collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, or combinations thereof.

[0108] like Figure 3 As shown, according to some embodiments, the second package structure 300b includes a substrate 328. The substrate 328 may have a wiring structure therein. In some embodiments, the wiring structure of the substrate 328 includes a conductive layer, conductive vias, conductive pillars, or combinations thereof. The wiring structure of the substrate 328 may be formed of a metal, such as copper, titanium, tungsten, aluminum, or combinations thereof.

[0109] The wiring structure of substrate 328 can be disposed in an inter-metal dielectric (IMD) layer. In some embodiments, the IMD layer can be formed of an organic material, such as a polymer base material, an organic material, such as silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. Any desired semiconductor component can be formed in and on substrate 328. However, for the sake of simplicity, only a flat substrate 328 is shown.

[0110] like Figure 3 As shown, according to some embodiments, the second package structure 300b includes a semiconductor component 330 disposed above a substrate 328. The semiconductor component 330 may include the same or different devices. For example, the semiconductor component 330 may include a memory die such as dynamic random access memory (DRAM). In some embodiments, the second package structure 300b also includes one or more passive elements (not shown), such as resistors, capacitors, inductors, etc., or combinations thereof.

[0111] Figure 4 This is a cross-sectional view of a semiconductor package structure 400 according to some embodiments of the present invention. It should be noted that the semiconductor package structure 400 may include... Figure 3 The semiconductor package structure 300 shown contains the same or similar components, which will not be described further for simplicity. In the following embodiments, the capacitor is disposed above the back redistribution layer 324.

[0112] like Figure 4 As shown, according to some embodiments, the first semiconductor die 312 includes a plurality of vias 402 electrically coupled to the back redistribution layer 324. The vias 402 can be similar to... Figure 3 The through hole 314 shown will not be described in detail here.

[0113] like Figure 4As shown, according to some embodiments, the first package structure 300a includes a capacitor 410 disposed above the back redistribution layer 324. The capacitor 320 may be disposed between the back redistribution layer 324 and the second package structure 300b. Figure 4 As shown, the capacitor 410 may have multiple terminals 410t and can be electrically coupled to the first semiconductor die 312 through the terminals 410t, the back redistribution layer 324 and the through-hole 402 in the first semiconductor die 312.

[0114] In some other embodiments, capacitor 410 is a multi-capacitor structure, such as... Figure 1A , Figure 1B The multi-terminal, multi-capacitor structure 110 shown will not be described in detail here. In these embodiments, the capacitor 410 can be electrically coupled to the first semiconductor die 312, and can also be electrically coupled to the second semiconductor die 306 through the terminal 410t, the back redistribution layer 324, the via 402, and the via 308. The arrangement of the capacitor 410 in this embodiment can form an additional heat dissipation path, helping to dissipate heat from the first semiconductor die 312, the second semiconductor die 306, and the semiconductor component 330. For example, the heat from the first semiconductor die 312 and the second semiconductor die 306 can be transferred to the capacitor 410 through the via 402 and the terminal 410t, and the heat from the semiconductor component 330 can be transferred to the capacitor 410 through the substrate 328, and then the capacitor 410 dissipates the heat to the outside. Therefore, the arrangement of the capacitor 410 in this embodiment also improves the heat dissipation efficiency.

[0115] In embodiments where capacitor 310 is a multi-capacitor structure electrically coupled to the first semiconductor die 312 and the second semiconductor die 306, capacitor 410 can be omitted. Similarly, in embodiments where capacitor 410 is a multi-capacitor structure electrically coupled to the first semiconductor die 312 and the second semiconductor die 306, capacitor 310 can be replaced by conductive terminal 304.

[0116] Alternatively, in some embodiments, at least one of capacitors 310 and 410 is a multi-capacitor structure, and the first package structure 300a may include two or more semiconductor dies that can be electrically coupled to capacitors 310 and 410.

[0117] In some embodiments, capacitors 310 and 320 in semiconductor package structure 300 can be stacked vertically. Similarly, in some embodiments, capacitors 310 and 410 in semiconductor package structure 400 can be stacked vertically. Stacked capacitors can be referred to as a multi-capacitor structure and will be used in conjunction with... Figure 5A and 5B This will be discussed in the relevant description.

[0118] Figure 5A This is a cross-sectional view of a multi-capacitor structure 500a, an exemplary semiconductor package structure according to some embodiments. Figure 5A The multi-capacitor structure 500a can be disposed below the front redistribution layer 302, such as... Figure 3 The location of capacitor 310 is shown, and it can be electrically connected to the front redistribution layer 302 (e.g., Figure 3 (As shown).

[0119] like Figure 5A As shown, according to some embodiments, the multi-capacitor structure 500a includes vertically stacked capacitors 510 and 520. By using stacked capacitors instead of individual capacitors, the space occupied by the capacitors can be reduced, and this space can be used for active circuitry. Furthermore, more conductive terminals 304 can be retained (e.g., ...). Figure 3 (As shown) is used for interconnection. Capacitors (values) can also be added.

[0120] Capacitor 510 may have an active surface 510a and a back surface 510b opposite to the active surface 510a, and capacitor 520 may have an active surface 520a and a back surface 520b opposite to the active surface 520a. In some embodiments, capacitors 510 and 520 are stacked face to back, such as... Figure 5A As shown. That is, the active surface 510a of capacitor 520 is close to (towards) the back surface 520b of capacitor 520.

[0121] like Figure 5A As shown, according to some embodiments, capacitor 520 includes a plurality of through-holes 502 electrically coupled to the front redistribution layer 302 (e.g., Figure 3 (As shown). The capacitor 510 below the capacitor 520 can be electrically coupled to the front redistribution layer 302 through a via 502. The via 502 can be formed of a metal, such as copper, tungsten, or a combination thereof.

[0122] like Figure 5A As shown, the via 502 may have substantially vertical sidewalls and may extend from the active surface 520a of the capacitor 520 to the back surface 520b of the capacitor 520, but the invention is not limited thereto. The via 502 may have other configurations and other numbers.

[0123] Figure 5B This is a cross-sectional view of a multi-capacitor structure 500b, an exemplary semiconductor package structure according to some embodiments. It should be noted that the multi-capacitor structure 500b may include... Figure 5A For simplicity, the components that are the same as or similar to those in the multi-capacitor structure 500a shown will not be described in detail.

[0124] In some embodiments, capacitors 510 and 520 are stacked face-to-face, such as... Figure 5B As shown. That is, the active surface 510a of capacitor 520 is close to (oriented towards) the active surface 520a of capacitor 520. Figure 5B As shown, the multi-capacitor structure 500b may include a plurality of terminals 504 on the back surface 520b of the capacitor 520. The terminals 504 may be disposed on the front redistribution layer 302 (e.g., Figure 3 (As shown) and capacitor 520, and the front redistribution layer 302 can be electrically coupled to capacitor 520. The above... Figure 5A and 5B In this embodiment, the capacitance value is increased by forming a stacked capacitor structure. At the same time, the stacked capacitor structure will save the space of the plane. The above method does not increase the area occupied by the plane, thus saving the space occupied by the plane.

[0125] Figure 6 This is a cross-sectional view of a semiconductor package structure 600 according to some embodiments of the present invention. It should be noted that the semiconductor package structure 600 may include... Figure 3 The semiconductor package structure 300 shown contains the same or similar components, which will not be described in detail for simplicity. In the following embodiments, the capacitor is disposed adjacent to the first semiconductor die 312.

[0126] like Figure 6 As shown, according to some embodiments of the present invention, the semiconductor package structure 600 includes a capacitor 610 disposed above a second semiconductor die 306 and adjacent to a first semiconductor die 312. The capacitor 610 can be electrically coupled to the second semiconductor die 306 through a through-hole 308.

[0127] like Figure 6 As shown, the semiconductor package structure 600 includes a capacitor 620 disposed above the second semiconductor die 306 and adjacent to the first semiconductor die 312, according to some embodiments of the present invention. The semiconductor package structure 600 may include an interconnect structure 602 disposed above the second semiconductor die 306. In some embodiments, the interconnect structure 602 includes a redistribution layer.

[0128] like Figure 6 As shown, interconnect structure 602 may extend between first semiconductor die 312 and second semiconductor die 306, and also between capacitor 620 and second semiconductor die 306. Interconnect structure 602 may be electrically coupled to capacitor 620 connected to first semiconductor die 312. In some embodiments, interconnect structure 602 may be electrically coupled to second semiconductor die 306 via via 308.

[0129] The arrangement of capacitors 310, 610, and 620 shown in the figures is merely exemplary and not intended to limit the invention. For example, a conductive terminal 304 may be used instead of capacitor 310. Alternatively, capacitor 610 or capacitor 620 may be omitted.

[0130] In some other embodiments, capacitor 610 is a multi-capacitor structure, such as... Figure 1A , Figure 1B The multi-terminal, multi-capacitor structure 110 shown will not be described in detail here. In these embodiments, capacitor 610 can be electrically coupled to the second semiconductor die 306, and can also be electrically coupled to the first semiconductor die 312 through via 308 and front redistribution layer 302. In this embodiment, arranging capacitors 610 and 620 on the second semiconductor die 306 and around the first semiconductor die 312 can greatly shorten the connection distance between capacitors 610 and 620 and the second semiconductor die 306 (and / or the first semiconductor die 312), thereby improving signal transmission efficiency. Therefore, the capacitor arrangement in this embodiment not only saves space but also has a shorter signal transmission path, improving the operating efficiency of the semiconductor packaging structure.

[0131] In some other embodiments, capacitor 620 is a multi-capacitor structure, such as... Figure 1A , Figure 1B The multi-terminal multi-capacitor structure 110 shown will not be described in detail here. In these embodiments, the capacitor 620 can be electrically coupled to the first semiconductor die 312, and can also be electrically coupled to the second semiconductor die 306 through the interconnect structure 602 and the via 308.

[0132] Similarly, capacitor 310 can be a multi-capacitor structure, which will not be elaborated further here. In embodiments where at least one of capacitors 310, 610, or 620 is a multi-capacitor structure, the others in capacitors 310, 610, or 620 may be omitted and / or replaced by conductive terminals 304. Furthermore, the first package structure 300a may include two or more semiconductor dies electrically coupled to at least one of capacitors 310, 610, and 620.

[0133] like Figure 6 As shown, molding material 316 may surround the first semiconductor die 312, capacitor 610, and capacitor 620. Molding material 316 may cover the top surfaces of capacitor 610 and capacitor 620. Molding material 316 may protect capacitor 610 and capacitor 620 from environmental influences, thereby preventing these components from being damaged due to, for example, stress, chemicals, and / or moisture.

[0134] Figure 7This is a cross-sectional view of a semiconductor package structure 700 according to some embodiments of the present invention. It should be noted that the semiconductor package structure 700 may include... Figure 3 The semiconductor package structure 300 shown contains the same or similar components, which will not be described again for simplicity. In the following embodiments, the capacitor is disposed below the back redistribution layer 324 and / or above the front redistribution layer 302.

[0135] In some embodiments, the first semiconductor die 312 includes a plurality of vias 702 electrically coupled to the back redistribution layer 324. The vias 702 can be similar to... Figure 3 The through-hole 314 shown is not repeated.

[0136] like Figure 7 As shown, according to some embodiments, the semiconductor package structure 700 includes a capacitor 710 disposed below the back redistribution layer 324 and surrounded by molding material 322. The capacitor 710 may be disposed between the conductive pillar 318 and the first semiconductor die 312.

[0137] like Figure 7 As shown, capacitor 710 can contact the front redistribution layer 302 and the back redistribution layer 324. Capacitor 710 can have multiple terminals 710t and can be electrically coupled to the first semiconductor die 312 through the terminals 710t, the back redistribution layer 324 and the through-hole 702.

[0138] like Figure 7 As shown, according to some embodiments, the semiconductor package structure 700 includes a capacitor 720 disposed above the front redistribution layer 302 and surrounded by molding material 322. The capacitor 720 may be disposed between the conductive pillar 318 and the second semiconductor die 306.

[0139] like Figure 7 As shown, capacitor 720 can be in contact with the front redistribution layer 302 and spaced apart from the back redistribution layer 324 via molding material 322. Capacitor 720 can have multiple terminals 720t and can be electrically coupled to the second semiconductor die 306 via the terminals 720t and the front redistribution layer 302.

[0140] The arrangement of capacitors 310, 710, and 720 shown in the figures is merely exemplary and not intended to limit the invention. For example, a conductive terminal 304 can be used instead of capacitor 310. Alternatively, capacitor 710 or capacitor 720 can be omitted. In this embodiment, this arrangement of capacitor 710 can also form an additional heat dissipation path for heat dissipation through capacitor 710; furthermore, the above arrangement of capacitors 710 and 720 facilitates manufacturing.

[0141] In some other embodiments, capacitor 710 is a multi-capacitor structure, such as... Figure 1A , Figure 1B The multi-terminal multi-capacitor structure 110 shown will not be described in detail here. In these embodiments, the capacitor 710 can be electrically coupled to the first semiconductor die 312, and can also be electrically coupled to the second semiconductor die 306 through the back redistribution layer 324, via 702 and via 308.

[0142] In some other embodiments, capacitor 720 is a multi-capacitor structure, such as... Figure 1A , Figure 1B The multi-terminal multi-capacitor structure 110 shown will not be described in detail here. In these embodiments, the capacitor 720 can be electrically coupled to the second semiconductor die 306, and can also be electrically coupled to the first semiconductor die 312 through the front redistribution layer 302 and the via 308.

[0143] Similarly, capacitor 310 can be a multi-capacitor structure, which will not be elaborated further here. In embodiments where at least one of capacitors 310, 710, or 720 is a multi-capacitor structure, the others of capacitors 310, 710, or 720 may be omitted and / or replaced by conductive terminal 304. Furthermore, the first package structure 300a may include two or more semiconductor dies electrically coupled to at least one of capacitors 310, 710, and 720.

[0144] Figure 8 This is a cross-sectional view of a semiconductor package structure 800 according to some embodiments of the present invention. It should be noted that the semiconductor package structure 800 may include... Figure 3 The semiconductor package structure 300 shown contains the same or similar components, which will not be described further for simplicity. In the following embodiments, the capacitor is disposed above the back redistribution layer.

[0145] like Figure 8 As shown, according to some embodiments, the semiconductor package structure 800 includes a semiconductor die 802 disposed between a front redistribution layer 302 and a back redistribution layer 324. The semiconductor die 802 can be electrically coupled to the front redistribution layer 302. The semiconductor die 802 can be similar to Figure 3 The first semiconductor die 312 or the second semiconductor die 306 shown are not repeated hereafter.

[0146] like Figure 8As shown, according to some embodiments, the semiconductor package structure 800 includes a capacitor 810 disposed above a back redistribution layer 324. The capacitor 810 may be disposed directly above one (or more) of the conductive pillars 322. In some embodiments, the capacitor 810 may be electrically coupled to the semiconductor die 802 through the back redistribution layer 324, the conductive pillars 322, and the front redistribution layer 302.

[0147] In some other embodiments, capacitor 810 is a multi-capacitor structure, such as... Figure 1A , Figure 1B The multi-terminal multi-capacitor structure 110 shown will not be described in detail here. In these embodiments, capacitor 310 can be replaced by conductive terminal 304. Alternatively, the first package structure 300a may include more than one semiconductor die electrically coupled to capacitor 310 and / or capacitor 810.

[0148] Compared to semiconductor package structures with die-side capacitors (e.g., capacitors formed around semiconductor die 802), the semiconductor package structure 800 according to the present invention, having a capacitor 810 disposed above the back redistribution layer 324, can reduce manufacturing complexity and improve reliability.

[0149] Figure 9 This is a cross-sectional view of a semiconductor package structure 900 according to some embodiments of the present invention. It should be noted that the semiconductor package structure 900 may include... Figure 3 The semiconductor package structure 300 shown contains the same or similar components, which will not be described further for simplicity. In the following embodiments, the capacitor is disposed above the interposer.

[0150] like Figure 9 As shown, according to some embodiments, the semiconductor package structure 900 includes a first package structure 900a and a second package structure 900b that are vertically stacked. Figure 9 As shown, according to some embodiments, the first package structure 900a includes a substrate 902. The substrate 902 may have a wiring structure therein. In some embodiments, the wiring structure in the substrate 902 includes a conductive layer, conductive vias, conductive pillars, or combinations thereof. The wiring structure in the substrate 902 may be formed of a metal, such as copper, aluminum, or combinations thereof.

[0151] The wiring structure in substrate 902 may be disposed in an inter-metal dielectric (IMD) layer. In some embodiments, the IMD layer may be formed of an organic material such as a polymer substrate, an organic material such as silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof. Substrate 902 may include an insulating core, such as a glass fiber reinforced resin core, to prevent substrate 902 from warping.

[0152] It should be noted that the configuration of substrate 902 shown in the figure is merely exemplary and is not intended to limit the present invention. Any desired semiconductor component can be formed in and on substrate 902. However, for the sake of simplicity, only a flat substrate 902 is shown.

[0153] like Figure 9 As shown, according to some embodiments, the first package structure 900a includes a plurality of conductive terminals 904 disposed below a substrate 902 and electrically coupled to a wiring structure in the substrate 902. The conductive terminals 904 can be connected to... Figure 3 The conductive terminal 304 shown is similar and will not be described again here.

[0154] like Figure 9 As shown, according to some embodiments, the first package structure 900a includes a semiconductor die 912 disposed above a substrate 902. The semiconductor die 912 may be similar to... Figure 3 The first semiconductor die 312 or the second semiconductor die 306 shown will not be described in detail here.

[0155] The semiconductor die 912 can be electrically coupled to the wiring structure in the substrate 902 through multiple conductive structures 906. For example... Figure 9 As shown, a conductive structure 906 may be disposed between a substrate 902 and a semiconductor die 912. In some embodiments, the conductive structure 906 is formed of a conductive material, such as a metal. The conductive structure 906 may include microbumps, controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, or combinations thereof.

[0156] like Figure 9 As shown, according to some embodiments, the first package structure 900a includes a plurality of bump structures 914 disposed above a substrate 902 and adjacent to a semiconductor die 912. The bump structures 914 can be electrically coupled to wiring structures in the substrate 902. The bump structures 914 can be formed of a conductive material such as metal. In some embodiments, the bump structures 914 include solder balls.

[0157] like Figure 9 As shown, the bump structure 914 can be disposed on the opposite side of the semiconductor die 912 (e.g., on the interposer layer 918). The configuration of the bump structure 914 shown in the figure is merely exemplary and is not intended to limit the invention.

[0158] like Figure 9 As shown, according to some embodiments, the first package structure 900a includes a plurality of conductive pillars 916 directly disposed above the bump structure 914. The conductive pillars 916 can be electrically coupled to wiring structures in the substrate 902 through the bump structure 914. The conductive pillars 916 can be formed of metal, such as copper, tungsten, or combinations thereof.

[0159] like Figure 9 As shown, according to some embodiments, the first package structure 900a includes a molding material 908 surrounding a semiconductor die 912, a bump structure 914, and conductive pillars 916. The molding material 908 may be adjacent to the sidewalls of the semiconductor die 912 and may cover the top surface of the semiconductor die 912 and the top surface of the substrate 902.

[0160] like Figure 9 As shown, the molding material 908 can fill the gaps between the conductive posts 916 and between the semiconductor die 912 and the conductive posts 916. The molding material 908 can protect the semiconductor die 912, the bump structure 914 and the conductive posts 916 from environmental influences, thereby preventing these components from being damaged due to, for example, stress, chemicals and / or moisture.

[0161] In some embodiments, the molding material 908 comprises a non-conductive material, such as a moldable polymer, epoxy resin, resin, or a combination thereof. The molding material 908 may be similar to... Figure 3 The molding material 322 shown will not be described in detail here.

[0162] like Figure 9 As shown, according to some embodiments, the first package structure 900a includes an interposer layer 918 disposed above a molding material 908. The interposer layer 918 may have wiring structures therein. The wiring structures in the interposer layer 918 may be electrically coupled to a substrate 902 via conductive pillars 916 and bump structures 914.

[0163] In some embodiments, the wiring structure in the interposer 918 includes a conductive layer, conductive vias, conductive pillars, or combinations thereof. The wiring structure in the interposer 918 may be formed of a metal, such as copper, aluminum, or combinations thereof.

[0164] The wiring structure in the interposer 918 can be disposed in an intermetallic dielectric (IMD) layer. In some embodiments, the IMD layer can be formed of an organic material such as a polymer substrate, an organic material such as silicon nitride, silicon oxide, silicon oxynitride, or a combination thereof.

[0165] It should be noted that the configuration of the interposer 918 shown in the figure is merely exemplary and is not intended to limit the invention. Any desired semiconductor component can be formed in and on the interposer 918. However, for the sake of simplicity, only a flat interposer 918 is shown.

[0166] like Figure 9As shown, according to some embodiments, the semiconductor package structure 900 includes a capacitor 910 disposed above an interposer layer 918. The capacitor 910 can be electrically coupled to a semiconductor die 912 through wiring structures, conductive pillars 916, bump structures 914 in the interposer layer 918, wiring structures and conductive structures 906 in the substrate 902.

[0167] In some other embodiments, capacitor 910 may be a multi-capacitor structure, such as... Figure 1A , Figure 1B The multi-terminal multi-capacitor structure 110 shown will not be described in detail here. In these embodiments, the first package structure 900a may include more than one semiconductor die electrically coupled to the capacitor 910.

[0168] like Figure 9 As shown, according to some embodiments, a second package structure 900b is disposed above the first package structure 900a and electrically coupled to a wiring structure in the interposer layer 918 via a plurality of conductive terminals 920. The conductive terminals 920 may be similar to... Figure 3 The conductive terminal 326 shown will not be described in detail here.

[0169] like Figure 9 As shown, according to some embodiments, the second package structure 900b includes a substrate 922 and a semiconductor component 924 disposed above the substrate 922. The substrate 922 and the semiconductor component 924 can be respectively coupled to... Figure 3 The substrate 328 and semiconductor component 330 shown are similar and will not be described again here.

[0170] Compared to semiconductor package structures with die-side capacitors, the semiconductor package structure 900 of the present invention, which has a capacitor 910 disposed above an interposer layer 918, can reduce manufacturing complexity.

[0171] Figure 10 This is a cross-sectional view of a semiconductor package structure 1000 according to some embodiments of the present invention. It should be noted that the semiconductor package structure 1000 may include... Figure 9 The semiconductor package structure 900 shown contains the same or similar components, which will not be described further for simplicity. In the following embodiments, the capacitor is disposed on the molding material.

[0172] like Figure 10 As shown, according to some embodiments, the semiconductor package structure 1000 includes a substrate 1002. The substrate 1002 may have wiring structures therein. The substrate 1002 may be coupled with… Figure 9 The substrate 902 shown is similar and will not be described in detail here.

[0173] like Figure 10As shown, according to some embodiments, the semiconductor package structure 1000 includes a plurality of conductive terminals 1004 disposed beneath a substrate 1002 and electrically coupled to wiring structures within the substrate 1002. The conductive terminals 1004 can be connected to... Figure 3 The conductive terminal 304 shown is similar and will not be described again here.

[0174] like Figure 10 As shown, according to some embodiments, the semiconductor package structure 1000 includes a semiconductor die 1006 disposed above a substrate 1002. The semiconductor die 1006 may be similar to... Figure 3 The first semiconductor die 312 or the second semiconductor die 306 shown will not be described in detail here.

[0175] The semiconductor die 1006 can be electrically coupled to the wiring structure in the substrate 1002 through multiple conductive structures 1008. For example... Figure 10 As shown, a conductive structure 1008 may be disposed between a substrate 1002 and a semiconductor die 1006. In some embodiments, the conductive structure 1008 is formed of a conductive material, such as a metal. The conductive structure 1008 may include microbumps, controlled-collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) balls, or combinations thereof.

[0176] like Figure 10 As shown, according to some embodiments, the semiconductor package structure 1000 includes a plurality of bump structures 1014 disposed above a substrate 1002 and adjacent to a semiconductor die 1006. The bump structures 1014 can be electrically coupled to wiring structures in the substrate 1002.

[0177] The bump structure 1014 may be formed of a conductive material such as metal. In some embodiments, the bump structure 1014 includes solder balls. Figure 10 As shown, the bump structure 1014 can be disposed on opposite sides of the semiconductor die 912. The configuration of the bump structure 1014 shown in the figure is merely exemplary and is not intended to limit the invention.

[0178] like Figure 10 As shown, according to some embodiments, the semiconductor package structure 1000 includes a molding material 1012 surrounding a semiconductor die 1006 and a bump structure 1014. Figure 10 As shown, the molding material 1012 can be adjacent to the sidewall of the semiconductor die 1006 and can cover the top surface of the semiconductor die 1006 and the top surface of the substrate 1002.

[0179] The molding material 1012 can protect the semiconductor die 1006 and bump structure 1014 from environmental influences, thereby preventing these components from being damaged due to factors such as stress, chemicals, and / or moisture. The molding material 908 can be similar to... Figure 3The molding material 322 shown will not be described in detail here.

[0180] In some embodiments, the molding material 1012 comprises a non-conductive material, such as a moldable polymer, epoxy resin, resin, or a combination thereof. The molding material 1012 may be similar to... Figure 3 The molding material 322 shown will not be described in detail here.

[0181] like Figure 10 As shown, according to some embodiments, the molding material 1012 has an opening to expose the upper portion of the bump structure 1014. The opening of the molding material 1012 can be formed by laser ablation or any other suitable method. In the laser ablation method, a portion of the molding material 1012 can be removed when irradiated with a laser beam.

[0182] The semiconductor package structure 1000 may include a capacitor 1010 disposed in an opening in the molding material 1012. The capacitor 1010 may be electrically coupled to the semiconductor die 1006 via the bump structure 1014, the wiring structure in the substrate 1002, and the conductive structure 1008. Although not explicitly shown in the figures, it is understood that the capacitor 1010 may be directly or indirectly electrically connected to the bump structure 1014.

[0183] In some other embodiments, capacitor 1010 may be a multi-capacitor structure, such as... Figure 1A , Figure 1B The multi-terminal multi-capacitor structure 110 shown will not be described in detail here. In these embodiments, the semiconductor package structure 1000 may include one or more semiconductor dies electrically coupled to the capacitor 1010.

[0184] Compared with semiconductor package structures having die-side capacitors, the semiconductor package structure 1000 according to the present invention having a capacitor 910 disposed above the molding material 1012 can reduce manufacturing complexity, facilitate manufacturing and forming, and improve production yield.

[0185] In summary, in some embodiments, the semiconductor packaging structure of the present invention employs a multi-terminal, multi-capacitor structure to reduce the space occupied and retain more conductive terminals compared to using separate capacitors for different semiconductor dies. It also improves design flexibility.

[0186] Furthermore, in some embodiments, at least one capacitor is provided without occupying space for conductive terminals, for example, by being positioned above the front redistribution layer. Therefore, more conductive terminals located below the front redistribution layer can be reserved for interconnection, increasing design flexibility.

[0187] Furthermore, in some embodiments, at least one capacitor is disposed on the molding material. Compared to die-side capacitors, capacitors according to these embodiments of the invention can reduce manufacturing complexity and cost. They can also improve the reliability of semiconductor package structures.

[0188] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A semiconductor packaging structure, characterized in that, include: Frontal redistribution layer; The first semiconductor die is disposed above the front redistribution layer; A first capacitor is disposed above the front redistribution layer and electrically coupled to the first semiconductor die; Conductive terminals are disposed below the front redistribution layer and electrically connected to the front redistribution layer; as well as A back redistribution layer is disposed above the first semiconductor die, wherein the first capacitor is disposed above or below the back redistribution layer and electrically coupled to the first semiconductor die through a via in the back redistribution layer and the first semiconductor die; The second semiconductor die is disposed above the front redistribution layer and between the front redistribution layer and the first semiconductor die. as well as The second capacitor is disposed below the front redistribution layer and electrically coupled to the second semiconductor die through the front redistribution layer. A third capacitor is disposed below the second capacitor and electrically connected to the front redistribution layer through a through-hole in the second capacitor.

2. The semiconductor packaging structure as described in claim 1, characterized in that, It also includes a molding material disposed between the front redistribution layer and the back redistribution layer and surrounding the first capacitor and the first semiconductor die.

3. The semiconductor packaging structure as described in claim 2, characterized in that, The first capacitor is in contact with the back redistribution layer and is separated from the front redistribution layer by the molding material.

4. The semiconductor packaging structure as described in claim 2, characterized in that, The first capacitor contacts the front redistribution layer and the back redistribution layer.

5. The semiconductor packaging structure as described in claim 4, characterized in that, Also includes: A fourth capacitor is disposed above the front redistribution layer and electrically coupled to the second semiconductor die through the front redistribution layer.

6. The semiconductor packaging structure as described in claim 1, characterized in that, The first capacitor is disposed above the front redistribution layer and is electrically coupled to the first semiconductor die through a via in the front redistribution layer and the second semiconductor die.

7. The semiconductor packaging structure as described in claim 1, characterized in that, The first semiconductor die and the first capacitor are disposed on the second semiconductor die; It also includes: an interconnect structure disposed above the second semiconductor die and electrically coupled the first capacitor to the first semiconductor die.

8. The semiconductor packaging structure according to claim 7, characterized in that, It also includes a fourth capacitor, which is disposed above the second semiconductor die and electrically coupled to the second semiconductor die through a through-hole in the second semiconductor die.

9. The semiconductor packaging structure as described in claim 1, characterized in that, It also includes a conductive pillar adjacent to the first semiconductor die, wherein the first capacitor is disposed above the back redistribution layer and electrically connected to the first semiconductor die through the back redistribution layer, the conductive pillar and the front redistribution layer.

10. The semiconductor packaging structure as described in claim 1, characterized in that, The first capacitor has a multi-terminal, multi-capacitor structure and is electrically coupled to a second semiconductor die adjacent to the first semiconductor.

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