Extended Drain MOS with Double-Well Isolation

Abstract

An integrated circuit (100) includes an extended drain MOS transistor (105). A substrate (101) of the integrated circuit (100) has a lower layer (103) of a first conductivity type. A drain well (106) of the extended drain MOS transistor (105) has the first conductivity type. The drain well (106) is separated from the lower layer (103) by a drain isolation well (112) of an opposite second conductivity type. A source region (108) of the extended drain MOS transistor (105) is separated from the lower layer (103) by a body well (113) of the second conductivity type. Both the drain isolation well (112) and the body well (113) contact the lower layer (103). An average dopant density of the second conductivity type in the drain isolation well (112) is less than an average dopant density of the second conductivity type in the body well (113).

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits. More particularly, the present disclosure relates to extended drain metal oxide semiconductor (MOS) transistors in integrated circuits. Background Art

[0002] Some integrated circuits include extended-drain metal-oxide-semiconductor (MOS) transistors, in which the drain has the same conductivity type as the underlying substrate. The drain must be isolated from the substrate, which involves increased process complexity, increased component area, or both. Providing isolation without degrading transistor performance and reliability parameters such as on-state current, off-state current, threshold, and hot-carrier reliability has proven challenging. Summary of the Invention

[0003] The present disclosure describes an integrated circuit comprising an extended drain metal oxide semiconductor (MOS) transistor positioned above a lower layer in a substrate of the integrated circuit. The drain well of the extended drain MOS transistor and the lower layer both have a first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second conductivity type opposite to the first conductivity type. The source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. The drain isolation well and the body well both contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a cross section of an example integrated circuit including an extended drain MOS transistor with dual well isolation.

[0005] Figures 2A to 2D is a cross-section of an integrated circuit including an extended drain MOS transistor with dual-well isolation depicted at various stages of an example formation method.

[0006] Figure 3 is a cross section of another example integrated circuit including an extended drain MOS transistor with double well isolation.

[0007] Figures 4A to 4D is a cross-section of an integrated circuit including extended drain MOS transistors with dual-well isolation depicted at various stages of another example formation method.

[0008] Figure 5 is a cross section of yet another example integrated circuit including an extended-drain MOS transistor with double-well isolation.

[0009] Figures 6A to 6D is a cross-section of an integrated circuit including extended drain MOS transistors with dual-well isolation depicted at various stages of yet another example formation method. DETAILED DESCRIPTION

[0010] The present disclosure is described with reference to the accompanying drawings. The drawings are not drawn to scale and are provided for illustration purposes only. Several aspects of the present disclosure are described below with reference to example applications for illustration. It should be understood that many specific details, relationships, and methods are set forth to provide an understanding of the present disclosure. The present disclosure is not limited by the order of the actions or events described, as some actions may occur in a different order and / or simultaneously with other actions or events. In addition, not all described actions or events are required to implement the methods according to the present disclosure.

[0011] Furthermore, while some of the embodiments described herein are shown in two-dimensional views of various regions having depth and width, it should be clearly understood that these regions are merely illustrative of what would actually be a portion of a device having a three-dimensional structure. Thus, when fabricated on an actual device, these regions would have three dimensions, including length, width, and depth. It is not intended to limit the active devices of the present invention to the physical structures shown. These structures are included to demonstrate the utility and application of the present invention to the presently preferred embodiments.

[0012] An integrated circuit has a substrate with a lower layer of semiconductor material having a first conductivity type. The integrated circuit includes an extended drain metal oxide semiconductor (MOS) transistor located above the lower layer. The drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well, which contacts the drain well and contacts the lower layer. The drain isolation well has a second conductivity type opposite to the first conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well. The body well contacts the source region and the lower layer. The body well has a second conductivity type. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.

[0013] Terms such as top, over, above, below, and under may be used in this disclosure. These terms should not be construed as limiting the position or orientation of structures or elements, but rather should be used to provide spatial relationships between structures or elements.

[0014] As used in this disclosure, the term "substantially equal" refers, in one aspect, to quantities that are equal within manufacturing tolerances encountered during integrated circuit fabrication, such as average dopant density. In another aspect, as used in this disclosure, the term "substantially equal" refers to measurements of quantities (such as average dopant density) that are equal within measurement tolerances encountered during measurement of the quantities.

[0015] Figure 11 is a cross-section of an example integrated circuit including an extended drain MOS transistor with double well isolation. Integrated circuit 100 has a substrate 101 having a top surface 102 and including a lower layer 103 of semiconductor material having a first conductivity type. In this example, the first conductivity type is p-type, such as Figure 1 As shown. The substrate 101 may further include a field oxide layer 104 extending to the top surface 102. The field oxide layer 104 may laterally separate components and elements in the integrated circuit 100. For the purposes of this disclosure, the terms "lateral" and "laterally" are understood to refer to directions parallel to the plane of the top surface 102. Similarly, the terms "vertical" and "vertically" are understood to refer to directions perpendicular to the plane of the top surface 102. The terms lateral, laterally, vertical, and vertically are understood similarly in subsequent examples. The field oxide layer 104 may have a shallow trench isolation (STI) structure, wherein the field oxide layer 104 extends below the top surface 102 to a depth of 250 nanometers to 750 nanometers, has substantially straight sidewalls, and does not extend more than 100 nanometers above the top surface 102, as shown. Figure 1 Depicted.

[0016] Integrated circuit 100 includes an extended drain MOS transistor 105 having a first polarity. In this example, the first polarity is p-channel. Extended drain MOS transistor 105 includes a drain well 106 having a first conductivity type located in substrate 101; in this example, drain well 106 is p-type. For example, drain well 106 may have a first conductivity type. 16 cm -3 to 10 18 cm -3 , so that the extended drain MOS transistor 105 can operate at a desired voltage. For the purposes of this disclosure, the terms "dopant concentration of the first conductivity type" and "dopant of the first conductivity type" refer to dopants that provide the first conductivity type. For the case where the first conductivity type is p-type, as in this example, boron, gallium, and indium are dopants of the first conductivity type because they provide p-type conductivity. For the case where the first conductivity type is n-type, phosphorus, arsenic, and antimony are dopants of the first conductivity type because they provide n-type conductivity. The extended drain MOS transistor 105 may optionally include a drain contact region 107 that contacts the drain well 106 and extends to the top surface 102. The drain contact region 107 has the first conductivity type, and the average dopant density of the first conductivity type is, for example, 10 19 cm -3 to 10 21 cm -3 To provide a desired low resistance connection to the drain well 106 .

[0017] Extended drain MOS transistor 105 includes a source region 108 of a first conductivity type located in substrate 101; in this example, source region 108 is p-type. Source region 108 and drain contact region 107 may have substantially equal average densities of dopants of the first conductivity type. Extended drain MOS transistor 105 includes a gate dielectric layer 109 on top surface 102 of substrate 101 and a gate 110 on gate dielectric layer 109. Gate dielectric layer 109 may include silicon dioxide, silicon dioxide nitride, hafnium oxide, zirconium oxide, or other dielectric materials suitable for MOS transistors. Gate dielectric layer 109 may have a thickness suitable for the desired gate-drain potential during operation of integrated circuit 100. For example, extended drain MOS transistor 105 may operate at a gate-drain potential of 8 volts to 100 volts. For example, gate dielectric layer 109 may have a thickness of 3 nanometers to 10 nanometers. The gate 110 may comprise, for example, polysilicon, titanium nitride, tantalum nitride, or metal silicide. The gate 110 extends from the source region 108 to the drain well 106, overlapping a portion of the drain well 106. In this example, the extended drain MOS transistor 105 may comprise an element of a field oxide layer 104a located between the drain contact region 107 and a portion of the drain well 106 overlapping the gate 110. The drain well 106 extends below the element of the field oxide layer 104a, as shown in FIG. Figure 1 This drain configuration can advantageously reduce the area of the extended drain MOS transistor 105 by providing a voltage drop across the portion of the drain well 106 below the elements of the field oxide layer 104a. The extended drain MOS transistor 105 may include gate sidewall spacers 111 on the side surfaces of the gate 110. The gate sidewall spacers 111 may include, for example, silicon nitride, silicon dioxide, or silicon oxynitride.

[0018] The drain well 106 is vertically separated from the lower layer 103 by a drain isolation well 112, which is located in the substrate 101 and has a second conductivity type opposite to the first conductivity type. The drain isolation well 112 contacts the lower layer 103 and the drain well 106. In this example, the drain isolation well 112 is n-type, as shown in FIG. Figure 1 As shown. The drain isolation well 112 may have, for example, 10 15 cm -3 to 10 17 cm -3The average dopant density of the second conductivity type in the drain isolation well 112 is adjusted to provide a desired junction capacitance at the junction between the drain isolation well 112 and the drain well 106, and to provide a desired breakdown potential between the drain isolation well 112 and the drain well 106. For the purposes of this disclosure, the terms "dopant concentration of the second conductivity type" and "dopant of the second conductivity type" refer to dopants that provide the second conductivity type. The dopant concentration of the second conductivity type in the drain isolation well 112 can decrease with the vertical distance below the top surface 102 and can decrease with the lateral distance from the drain contact region 107, which can achieve the desired junction capacitance and the desired breakdown potential by appropriately placing the junction between the drain isolation well 112 and the drain well 106.

[0019] The source region 108 is vertically separated from the lower layer 103 by a body well 113, which is located in the substrate 101 and has the second conductivity type. The body well 113 contacts the lower layer 103 and the source region 108. In this example, the body well 113 is n-type, as shown in FIG. Figure 1 As shown. The body well 113 may have, for example, 10 16 cm -3 to 10 18 cm -3 The average dopant density of the second conductivity type of the drain isolation well 112 is less than the average dopant density of the second conductivity type of the body well 113. In this example, the body well 113 may contact the drain well 106 below the gate 110, as shown in FIG. Figure 1 As shown, this can advantageously reduce the area of the extended drain MOS transistor 105. The body well 113 can optionally extend laterally around the drain well 106, as shown in FIG. Figure 1 The configuration of the extended drain MOS transistor 105 (having a drain well 106 isolated from the underlying layer 103 by a drain isolation well 112, and having a source region 108 isolated from the underlying layer 103 by a body well 113, wherein both the drain isolation well 112 and the body well 113 contact the underlying layer 103) can advantageously reduce the area of the extended drain MOS transistor 105 by eliminating the need for a single isolation structure extending completely below the extended drain MOS transistor 105. The extended drain MOS transistor 105 can optionally include a body contact region 114 contacting the body well 113 and extending to the top surface 102. The body contact region 114 has a second conductivity type, wherein the average dopant density of the second conductivity type is, for example, 10 19 cm -3 to 10 21 cm -3 To provide the desired low resistance connection to the body well 113 .

[0020] Extended drain MOS transistor 105 Figure 1 106 as having an asymmetric configuration, wherein source region 108 is located on one side of drain well 106. In an alternative version of this example, extended drain MOS transistor 105 may have a symmetric configuration, wherein source region 108 is located on opposite sides of drain well 106.

[0021] The integrated circuit 100 may optionally include a first low voltage MOS transistor 115 having a first polarity and a second low voltage MOS transistor 116 having a second polarity opposite to the first polarity. In this example, the first low voltage MOS transistor 115 is p-channel and the second low voltage MOS transistor 116 is n-channel. For the purposes of this disclosure, the term "low voltage" as applied to MOS transistors refers to MOS transistors that operate at a drain-source potential of less than 3 volts. Such transistors are typically used in logic circuits and static random access memory (SRAM) circuits. The first low voltage MOS transistor 115 has a first low voltage gate structure 117 on the top surface 102 of the substrate 101, a first source 118 in the substrate 101, and a first drain 119 in the substrate 101. The first low voltage MOS transistor 115 is disposed in a first well 120. The first well 120 has a second conductivity type, in this example n-type, such as Figure 1 The first well 120 may have an average dopant density of the second conductivity type substantially equal to that of the body well 113 .

[0022] The second low voltage MOS transistor 116 has a second low voltage gate structure 121 on the top surface 102 of the substrate 101, a second source 122 in the substrate 101, and a second drain 123 in the substrate 101. The second low voltage MOS transistor 116 is disposed in a second well 124. The second well 124 has a first conductivity type, which is p-type in this example. Figure 1 As shown. The second well 124 can have an average dopant density of the first conductivity type substantially equal to that of the drain well 106. In the semiconductor industry, a well having the same conductivity type as the substrate is sometimes simply referred to as the substrate, rather than a well at all. However, as used herein, the term "well" is intended to mean either an n-type well or a p-type well, and includes wells that can have the same conductivity type as the substrate.

[0023] The integrated circuit 100 may optionally include a first high voltage MOS transistor 125 having a first polarity (p-channel in this example), and a second high voltage MOS transistor 126 having a second polarity (n-channel in this example). For the purposes of this disclosure, the term "high voltage" as applied to MOS transistors refers to MOS transistors that operate at a drain-source potential of 3 volts to 6 volts. Such transistors are typically used in input / output circuits and analog circuits. The first high voltage MOS transistor 125 has a first high voltage gate structure 127 on the top surface 102 of the substrate 101, a third source 128 in the substrate 101, and a third drain 129 in the substrate 101. The first high voltage MOS transistor 125 is disposed in a third well 130. The third well 130 has a second conductivity type, which in this example is n-type, as shown in FIG. Figure 1 The third well 130 may have an average dopant density of the second conductivity type substantially equal to that of the drain isolation well 112 .

[0024] The second high voltage MOS transistor 126 has a second high voltage gate structure 131 on the top surface 102 of the substrate 101, a fourth source 132 in the substrate 101, and a fourth drain 133 in the substrate 101. The second high voltage MOS transistor 126 is disposed in a fourth well 134. The fourth well 134 has a first conductivity type, which is p-type in this example. Figure 1 shown.

[0025] Integrated circuit 100 may include a dielectric layer 135 above the top surface 102 of substrate 101. Dielectric layer 135 may be a pre-metal dielectric (PMD) layer having one or more sublayers, such as a PMD liner of silicon nitride on top surface 102, a layer of silicon dioxide, phosphosilicate glass (PSG), or borophosphosilicate glass (BPSG), and a capping layer of silicon nitride, silicon oxynitride, silicon carbide, or silicon carbonitride. Integrated circuit 100 may also include contacts 136 extending through dielectric layer 135 to provide electrical connections to extended drain MOS transistor 105, first low voltage MOS transistor 115, second low voltage MOS transistor 116, first high voltage MOS transistor 125, and second high voltage MOS transistor 126. Contact 136 may include a liner of titanium with a tungsten core and titanium nitride or tantalum nitride. Integrated circuit 100 may also include interconnects 137 on dielectric layer 135 to make electrical connections to contacts 136. For example, the interconnects may comprise aluminum or copper.

[0026] Figures 2A to 2D is a cross-section of an integrated circuit including an extended drain MOS transistor with dual well isolation depicted at various stages of an example formation method. Figure 2A, forming the integrated circuit 200 includes obtaining a substrate 201. The substrate 201 can be implemented as a bulk semiconductor wafer, a semiconductor wafer with an epitaxial layer, a silicon-on-insulator (SOI) wafer, or other structures suitable for forming the integrated circuit 200. The substrate 201 has a top surface 202 and includes a lower layer 203 of semiconductor material having a first conductivity type below the top surface 202. In this example, the first conductivity type is p-type, such as Figure 2A shown.

[0027] The substrate 201 includes a region for the extended drain MOS transistor 205, a region for the first low voltage MOS transistor 215, a region for the second low voltage MOS transistor 216, a region for the first high voltage MOS transistor 225, and a region for the second high voltage MOS transistor 226. Figure 1 The terms "low voltage" and "high voltage" are used as described.

[0028] A protective layer 238 may be formed on top surface 202. Protective layer 238 may include silicon dioxide formed by a thermal oxidation process. For example, protective layer 238 may have a thickness of 5 to 25 nanometers. Protective layer 238 is sometimes referred to as a pad layer or pad oxide layer. Protective layer 238 may advantageously reduce contamination of substrate 201 during subsequent manufacturing operations. Other compositions and formation methods of protective layer 238 are within the scope of this example.

[0029] A first implantation mask 239 is formed over the protective layer 238. The first implantation mask 239 is formed in the region for the extended drain MOS transistor 205 to form a drain isolation well 212 (eg, Figure 2B In this example, the protective layer 238 is exposed in a region 240 parallel to the Figure 2A The first implantation mask 239 may optionally expose a third well 230 (e.g., a well 230 formed subsequently) in a region for the first high voltage MOS transistor 225. Figure 2B The first implantation mask 239 may be formed of a photoresist using a photolithography process. Alternatively, the first implantation mask 239 may be formed of a hard mask material such as silicon oxynitride. Other materials and processes for forming the first implantation mask 239 are within the scope of this example.

[0030] In the region exposed by the first implantation mask 239, a first dopant 241 is implanted into the substrate 201 to form a drain isolation implant region 243 in the region for the extended drain MOS transistor 205 and a well implant region 244 in the region for the first high voltage MOS transistor 225. The first dopant 241 is a dopant of the second conductivity type, which in this example is an n-type dopant such as phosphorus. 12 cm -2 to 10 14 cm -2 The first dopant 241 is implanted at a dose of 100 nm to provide a desired average dopant density of the second conductivity type in the subsequently formed drain isolation well 212 and the subsequently formed third well 230. The first dopant 241 may be implanted at an energy sufficient to allow a substantial portion of the first dopant 241 to pass through the protective layer 238 and into the substrate 201. For example, the first dopant 241 may be implanted at an energy of 20 kiloelectronvolts (keV) to 100 keV.

[0031] The first implantation mask 239 is removed after implanting the first dopant 241. The first implantation mask 239 may be removed by a plasma etching process followed by a wet etching clean process.

[0032] refer to Figure 2B , the substrate 201 is heated by a thermal process 245 to diffuse and activate Figure 2A The drain isolation implantation region 243 and the well implantation region 244 Figure 2A The first dopant 241 is diffused to form the drain isolation well 212 and the third well 230. The thermal process 245 may have a thermal profile sufficient to diffuse the first dopant 241 so that the drain isolation well 212 is parallel to the third well 230. Figure 2B The lateral dimension in the direction of the plane is given by Figure 2A The thermal process 245 may heat the substrate 201 to a temperature of 1080° C. to 1120° C. for 300 to 400 minutes. The thermal process 245 may be performed as a furnace treatment using an ambient environment including some oxygen to grow additional silicon dioxide on the top surface 202 of the substrate 201. As a result of the thermal process 245, the density of the first dopant 241 in the drain isolation well 212 at the junction between the drain isolation well 212 and the underlying layer 203 may be lower than the density in the region surrounding the drain isolation implant region 243.

[0033] refer to Figure 2C , forming a field oxide layer 204 extending into the substrate 201. The field oxide layer 204 can be formed by an STI process so that the field oxide layer 204 has a Figure 2CThe STI structure depicted. An example STI process includes forming a chemical mechanical polishing (CMP) stop layer of silicon nitride over substrate 201, etching isolation trenches through the CMP stop layer and into substrate 201, and filling the isolation trenches with silicon dioxide using a plasma enhanced chemical vapor deposition (PECVD) process using tetraethyl orthosilicate (TEOS), a high density plasma (HDP) process, a high aspect ratio process (HARP) using TEOS and ozone, an atmospheric chemical vapor deposition (APCVD) process using silane, or a sub-atmospheric pressure chemical vapor deposition (SACVD) process using dichlorosilane. Excess silicon dioxide is removed from above the CMP stop layer by an oxide CMP process, and the CMP stop layer is subsequently removed, leaving a field oxide layer 204. In this example, elements of field oxide layer 204a can be formed in drain isolation well 212.

[0034] The fourth well 234 may be formed in a region for the second high voltage MOS transistor 226. The fourth well 234 has a first conductivity type, which is a p-type in this example. Figure 2C shown.

[0035] A second implantation mask 246 is formed over the protective layer 238. The second implantation mask 246 exposes the protective layer 238 in the region for the body well 213 to be formed later in the region for the extended drain MOS transistor 205. The second implantation mask 246 may optionally expose a region for the first well 220 to be formed later in the region for the first low voltage MOS transistor 215. For example, the second implantation mask 246 may include a photoresist or hard mask material and may be formed by contacting the second implantation mask 246 with the body well 213. Figure 2A The first implantation mask 239 is formed by a similar process.

[0036] In the areas exposed by the second implantation mask 246, a second dopant 247 is implanted into the substrate 201. The second dopant 247 is a dopant of the second conductivity type, in this example, an n-type dopant, such as phosphorus and arsenic. The second dopant 247 may be implanted in more than one implantation step, with the main step having a dose of 10 12 cm- 2 to 10 14 cm- 2 The phosphorus is implanted at an energy of 400 keV to 600 keV. The additional implantation step of the second dopant 247 may have a lower dose and lower energy to set the threshold potential for the extended drain MOS transistor 205 and the first low voltage MOS transistor 215.

[0037] The second implantation mask 246 is removed after the second dopant 247 is implanted. Figure 2AThe second implantation mask 246 is removed by a process similar to the process of removing the first implantation mask 239 .

[0038] The substrate 201 is then heated to activate the second dopant 247 implanted into the substrate 201 to form the body well 213 and the first well 220. The substrate 201 may be heated by a rapid thermal process to reduce the second dopant 247 and the Figure 2A The substrate 201 may be heated to 1000° C. to 1100° C. for 20 seconds to 60 seconds to prevent undesired diffusion of the first dopant 241 in the drain isolation well 212 .

[0039] refer to Figure 2D In the region for the extended-drain MOS transistor 205, a drain well 206 is formed in the substrate 201, such that the drain well 206 is vertically separated from the underlying layer 203 by a drain isolation well 212. In this example, the drain well 206 is formed so as to extend below the elements of the field oxide layer 204a. The drain well 206 has a first conductivity type; in this example, the drain well 206 is p-type. In the region for the second low-voltage MOS transistor 216, a second well 224 can be formed in the substrate 201. The second well 224 has the first conductivity type and can be formed with a similar distribution of dopants of the first conductivity type as the drain well 206.

[0040] The drain well 206 and the second well 224 can be formed by using an appropriate implantation mask ( Figure 2D The first conductivity type dopant (such as boron) is implanted into the substrate 201 (not shown). The first conductivity type dopant can be implanted in more than one implantation step, with the main step having a dose of 10 12 cm -2 to 10 14 cm -2 The boron is implanted at an energy of 200keV to 400keV. The additional implantation step of the first conductivity type dopant may have a lower dose and lower energy to set the threshold potential for the second low voltage MOS transistor 216. The substrate 201 is then heated to activate the first conductivity type dopant implanted into the substrate 201 to form the drain well 206 and the second well 224. The substrate 201 may be heated by contacting the reference electrode 201. Figure 2C Forming the drain well 206 and the second well 224 may reduce the manufacturing cost of the integrated circuit 200 compared to forming the drain well 206 and the second well 224 separately. In some versions of the example, activating the dopant of the first conductivity type may be combined with activating the dopant of the first conductivity type. Figure 2C The second dopant 247 is added simultaneously.

[0041] Figure 2C The protective layer 238 is then removed. For example, the protective layer 238 can be removed by a wet etching process using a buffered dilute aqueous solution of hydrofluoric acid.

[0042] In the region for the extended drain MOS transistor 205, a gate dielectric layer 209 is formed on the top surface 202 of the substrate 201. The gate dielectric layer 209 can be formed by a thermal oxidation process or by depositing an oxide material, for example, using an atomic layer deposition (ALD) process. A gate 210 of the extended drain MOS transistor 205 is formed on the gate dielectric layer 209. The gate 210 can be formed, for example, by forming a polysilicon layer on the gate dielectric layer 209 and then patterning the polysilicon layer using an etch mask and a reactive ion etching (RIE) process. Gate sidewall spacers 211 can be formed on the side surfaces of the gate 210. The gate sidewall spacers 211 can be formed by forming one or more conformal layers of silicon nitride, silicon dioxide, or silicon oxynitride over the gate 210 and removing the one or more conformal layers from the horizontal surfaces of the gate 210 and the substrate 201 using an anisotropic etching process, thereby leaving the one or more conformal layers on the side surfaces of the gate 210 to provide the gate sidewall spacers 211.

[0043] In the region for the first low-voltage MOS transistor 215, a first low-voltage gate structure 217 is formed on the top surface 202 of the substrate 201. In the region for the second low-voltage MOS transistor 216, a second low-voltage gate structure 221 is formed on the top surface 202 of the substrate 201. In the region for the first high-voltage MOS transistor 225, a first high-voltage gate structure 227 is formed on the top surface 202 of the substrate 201. In the region for the second high-voltage MOS transistor 226, a second high-voltage gate structure 231 is formed on the top surface 202 of the substrate 201. Part or all of the first low-voltage gate structure 217, the second low-voltage gate structure 221, the first high-voltage gate structure 227, and the second high-voltage gate structure 231 may be formed simultaneously with the gate dielectric layer 209, the gate 210, and the gate sidewall spacers 211 of the extended-drain MOS transistor 205.

[0044] A source region 208 is formed in the substrate 201 in contact with the body well 213 adjacent to the gate 210 and positioned opposite the drain well 206. The source region 208 has a first conductivity type; in this example, the source region 208 is p-type. The source region 208 can be formed by implanting a dopant of the first conductivity type, such as boron, in two or more implantation steps. A first portion of the source region 208 can be formed by implanting a first portion of the dopant of the first conductivity type before forming the gate sidewall spacers 211, and a second portion of the source region 208 can be formed by implanting a second portion of the dopant of the first conductivity type after forming the gate sidewall spacers 211. For example, the total dose of the dopant of the first conductivity type can be 1×10 14 cm -2 to 1×10 16 cm -2 The substrate 201 is then heated to activate the first conductivity type dopants implanted into the substrate 201 to form the source regions 208. The substrate 201 may be heated by a spike annealing process to reduce undesirable diffusion of the activated dopants in the substrate 201. For example, the substrate 201 may be heated to 950° C. to 1100° C. for 1 second to 10 seconds.

[0045] A drain contact region 207 may be optionally formed in the substrate 201 , contacting the drain well 206 . The drain contact region 207 has a first conductivity type; in this example, the drain contact region 207 is p-type. The drain contact region 207 may be formed simultaneously with the source region 208 .

[0046] In the region for the first low-voltage MOS transistor 215, a first source 218 and a first drain 219 are formed in the substrate 201 on opposite sides of the first low-voltage gate structure 217. In the region for the first high-voltage MOS transistor 225, a third source 228 and a third drain 229 are formed in the substrate 201 on opposite sides of the first high-voltage gate structure 227. The first source 218, the first drain 219, the third source 228, and the third drain 229 have a first conductivity type; in this example, the first source 218, the first drain 219, the third source 228, and the third drain 229 are p-type. The first source 218, the first drain 219, the third source 228, and the third drain 229 can be formed simultaneously with the source region 208.

[0047] A body contact region 214 may optionally be formed in the substrate 201, contacting the body well 213. The body contact region 214 has a second conductivity type; in this example, the body contact region 214 is n-type. The body contact region 214 may be formed by implanting dopants of the second conductivity type (such as phosphorus, arsenic, and antimony) into the substrate 201, optionally in two or more implantation steps. For example, the total dose of the dopants of the second conductivity type may be 1×10 14 cm -2 to 1×10 16 cm -2 The substrate 201 is then heated to activate the second conductivity type dopants implanted into the substrate 201 to form the body contact region 214. The substrate 201 may be heated by a spike annealing process to reduce undesirable diffusion of the activated dopants in the substrate 201. For example, the substrate 201 may be heated to 950° C. to 1100° C. for 1 second to 10 seconds.

[0048] In the region for the second low-voltage MOS transistor 216, a second source 222 and a second drain 223 are formed in the substrate 201 on opposite sides of the second low-voltage gate structure 221. In the region for the second high-voltage MOS transistor 226, a fourth source 232 and a fourth drain 233 are formed in the substrate 201 on opposite sides of the second high-voltage gate structure 231. The second source 222, the second drain 223, the fourth source 232, and the fourth drain 233 have the second conductivity type; in this example, the second source 222, the second drain 223, the fourth source 232, and the fourth drain 233 are n-type. The second source 222, the second drain 223, the fourth source 232, and the fourth drain 233 can be formed simultaneously with the body contact region 214.

[0049] The integrated circuit 200 may be formed by forming a dielectric layer ( Figure 2D ) to continue, the dielectric layer is similar to Figure 1 The dielectric layer 135. Contacts can be formed through the dielectric layer (not in Figure 2D ), similar to Figure 1 The contact 136 can be formed on the dielectric layer. Figure 2D Not shown), thereby making electrical connections to the contacts, similar to Figure 1 interconnecting member 137.

[0050] Figure 3 is a cross section of another example integrated circuit including an extended drain MOS transistor with double well isolation. Integrated circuit 300 has a substrate 301 having a top surface 302 and including a lower layer 303 of semiconductor material having a first conductivity type. In this example, the first conductivity type is p-type, such as Figure 3 As shown. The substrate 301 may further include a field oxide layer 304 extending to the top surface 302. The field oxide layer 304 may have an STI structure, such as Figure 3 Depicted.

[0051] Integrated circuit 300 includes an extended drain MOS transistor 305 having a first polarity (p-channel in this example). Extended drain MOS transistor 305 includes a drain well 306 having a first conductivity type located in substrate 301; in this example, drain well 306 is p-type. Drain well 306 may have a first conductivity type as described in reference to FIG. Figure 1 The drain well 106 of the extended drain MOS transistor 305 may optionally include a drain contact region 307 that contacts the drain well 306 and extends to the top surface 302. The drain contact region 307 has the first conductivity type and has a Figure 1 The drain contact region 107 discloses an average dopant density of the first conductivity type.

[0052] The extended drain MOS transistor 305 includes a source region 308 of a first conductivity type located in the substrate 301; in this example, the source region 308 is p-type. In this example, the source region 308 is symmetrically arranged on opposite sides of the drain well 306, as shown in FIG. Figure 3 As depicted. The source region 308 and the drain contact region 307 may have similar average densities of dopants of the first conductivity type. The extended drain MOS transistor 305 includes a gate dielectric layer 309 on the top surface 302 of the substrate 301 and a gate 310 on the gate dielectric layer 309. In this example, the gate 310 and the gate dielectric layer 309 are symmetrically arranged on opposite sides of the drain well 306, as shown in FIG. Figure 3 The gate 310 and the gate dielectric layer 309 may include a reference Figure 1 306. The gate 310 extends from the source region 308 toward the drain well 306; in this example, the gate 310 does not overlap a portion of the drain well 306. The extended drain MOS transistor 305 may include gate sidewall spacers 311 on the side surfaces of the gate 310. A silicide blocking layer 348 is disposed above the top surface 302 of the substrate 301 and extends from the gate 310 to the drain contact region 307. The silicide blocking layer 348 may include one or more layers of silicon dioxide, silicon nitride, silicon oxynitride, or other materials suitable for preventing the formation of metal silicide on the top surface 302. In some versions of this example, the silicide blocking layer 348 may appear as an extension of the gate sidewall spacers 311.

[0053] The drain well 306 is vertically separated from the lower layer 303 by a drain isolation well 312, which is located in the substrate 301 and has a second conductivity type opposite to the first conductivity type. In this example, the drain isolation well 312 is n-type, such as Figure 3 As shown. The drain isolation well 312 contacts the lower layer 303 and the drain well 306. The drain isolation well 312 may have, for example, 10 15 cm -3 to 10 17 cm -3 The average dopant density of the second conductivity type is Figure 3 As depicted, drain isolation well 312 can laterally surround drain well 306 and extend completely below drain well 306. In this example, drain isolation well 312 can have two or more regions 312a with a higher dopant density of the second conductivity type laterally adjacent to each other, wherein the drain isolation well between regions 312a has a lower dopant density of the second conductivity type than regions 312a. The higher dopant density regions 312a can provide a more uniform distribution of dopants of the second conductivity type, as shown in FIG. Figure 1 This may advantageously achieve a desired junction capacitance and a desired breakdown potential for the drain well 306 around the lateral perimeter of the drain well 306 , compared to the laterally reduced dopant concentration of the drain isolation well 112 .

[0054] The source region 308 is vertically separated from the lower layer 303 by a body well 313, which is located in the substrate 301 and has a second conductivity type. In this example, the body well 313 is n-type, such as Figure 3 As shown. The body well 313 contacts the lower layer 303 and the source region 308. The body well 313 may have a thickness of, for example, 10 16 cm -3 to 10 18 cm -3 The average dopant density of the second conductivity type of the drain isolation well 312 is less than the average dopant density of the second conductivity type of the body well 313. In this example, the body well 313 can be separated from the drain well 306 below the gate 310 by the drain isolation well 312, as shown in FIG. Figure 3As depicted, this can advantageously enable extended drain MOS transistor 305 to operate at a higher potential than a similar transistor in which the body well contacts the drain well. The construction of extended drain MOS transistor 305 (having a drain well 306 isolated from the lower layer 303 by a drain isolation well 312, and having a source region 308 isolated from the lower layer 303 by a body well 313, wherein both the drain isolation well 312 and the body well 313 contact the lower layer 303) can advantageously reduce the area of the extended drain MOS transistor 305 by eliminating the need for a single isolation structure extending completely below the extended drain MOS transistor 305. The extended drain MOS transistor 305 can optionally include a body contact region 314 that contacts the body well 313 and extends to the top surface 302. The body contact region 314 has a second conductivity type, wherein the average dopant density of the second conductivity type is, for example, 10 19 cm -3 to 10 21 cm -3 , to provide the desired low resistance connection to the body well 313.

[0055] Extended drain MOS transistor 305 Figure 3 306 as having a symmetrical configuration, wherein the source region 308 is located on both sides of the drain well 306. In an alternative version of this example, the extended drain MOS transistor 305 may have an asymmetrical configuration, wherein the source region 308 is located on one side of the drain well 306.

[0056] In this example, metal silicide 349 is disposed on drain contact region 307, source region 308, and body contact region 314. Metal silicide 349 can advantageously provide reduced resistance connections to drain contact region 307, source region 308, and body contact region 314. Due to the presence of silicide barrier layer 348, top surface 302 between drain contact region 307 and gate 310 is free of metal silicide 349. Metal silicide 349 can include, for example, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, or tungsten silicide.

[0057] The integrated circuit 300 may optionally include a first low voltage MOS transistor 315 having a first polarity (p-channel in this example). The first low voltage MOS transistor 315 has a first low voltage gate structure 317 on the top surface 302 of the substrate 301, a first source 318 in the substrate 301, and a first drain 319 in the substrate 301, wherein a metal silicide 349 is formed on the first source 318 and the first drain 319. The first low voltage MOS transistor 315 is disposed in a first well 320 having a second conductivity type, which is n-type in this example, as shown in FIG. Figure 3The first well 320 may have an average dopant density of the second conductivity type substantially equal to that of the body well 313 .

[0058] The integrated circuit 300 may also optionally include a second low-voltage MOS transistor 316 having a second polarity (n-channel in this example). The second low-voltage MOS transistor 316 has a second low-voltage gate structure 321 on the top surface 302 of the substrate 301, a second source 322 in the substrate 301, and a second drain 323 in the substrate 301, wherein a metal silicide 349 is formed on the second source 322 and the second drain 323. The second low-voltage MOS transistor 316 is disposed in a second well 324 having a first conductivity type, which is p-type in this example, as shown in FIG. Figure 3 The second well 324 may have an average dopant density of the first conductivity type substantially equal to that of the drain well 306 .

[0059] The integrated circuit 300 may optionally include a first high voltage MOS transistor 325 having a first polarity (p-channel in this example). The first high voltage MOS transistor 325 has a first high voltage gate structure 327 on the top surface 302 of the substrate 301, a third source 328 in the substrate 301, and a third drain 329 in the substrate 301, wherein a metal silicide 349 is on the third source 328 and the third drain 329. The first high voltage MOS transistor 325 is disposed in a third well 330 having a second conductivity type, which is n-type in this example, as shown in FIG. Figure 3 The third well 330 may have an average dopant density of the second conductivity type substantially equal to that of the drain isolation well 312 .

[0060] The integrated circuit 300 may also optionally include a second high voltage MOS transistor 326 having a second polarity (n-channel in this example). The second high voltage MOS transistor 326 has a second high voltage gate structure 331 on the top surface 302 of the substrate 301, a fourth source 332 in the substrate 301, and a fourth drain 333 in the substrate 301, wherein a metal silicide 349 is on the fourth source 332 and the fourth drain 333. The second high voltage MOS transistor 326 is disposed in a fourth well 334 having a first conductivity type, which is p-type in this example, as shown in FIG. Figure 3 shown.

[0061] Integrated circuit 300 may include a dielectric layer 335 above the top surface 302 of substrate 301. Dielectric layer 335 may behave similarly to reference Figure 1The PMD layer disclosed herein. The integrated circuit 300 may further include a contact 336 extending through the dielectric layer 335 to the metal silicide 349 to provide electrical connections to the extended drain MOS transistor 305, the first low voltage MOS transistor 315, the second low voltage MOS transistor 316, the first high voltage MOS transistor 325, and the second high voltage MOS transistor 326. The contact 336 may have a reference Figure 1 The integrated circuit 300 may further include an interconnect 337 on the dielectric layer 335 to make electrical connections to the contact 336.

[0062] Figures 4A to 4D is a cross-section of an integrated circuit including an extended drain MOS transistor with dual well isolation depicted at various stages of another example formation method. Figure 4A , the formation of the integrated circuit 400 includes obtaining a substrate 401, which can be as described in reference Figure 2A The substrate 401 has a top surface 402 and includes a lower layer 403 of semiconductor material below the top surface 402. The lower layer 403 has a first conductivity type, in this example, a p-type, such as Figure 4A shown.

[0063] The substrate 401 includes a region for an extended drain MOS transistor 405, a region for a first low voltage MOS transistor 415, a region for a second low voltage MOS transistor 416, a region for a first high voltage MOS transistor 425, and a region for a second high voltage MOS transistor 426. Figure 1 The terms "low voltage" and "high voltage" are used as described.

[0064] A protective layer 438 may be formed on the top surface 402. The protective layer 438 may have a Figure 2A The composition and structure of the protective layer 238 are described. A first implantation mask 439 is formed above the protective layer 438. The first implantation mask 439 is formed in the region for extending the drain MOS transistor 405 for the drain isolation well 412 (eg, Figure 4B In this example, the first implantation mask 439 exposes the protective layer 438 in a plurality of sub-regions 450 in the region for the extended drain MOS transistor 405. The sub-regions 450 may be separated from each other or may be formed in a plurality of sub-regions 450. Figure 2A The first implantation mask 439 may optionally expose a third well 430 ( Figure 4B As shown in the area. Figure 2AA first implantation mask 439 is formed as disclosed for the first implantation mask 239 .

[0065] A first dopant 441 is implanted into the substrate 401 in the region exposed by the first implantation mask 439 to form a plurality of drain isolation implant regions 443 in the region for the extended drain MOS transistor 405 and a well implant region 444 in the region for the first high voltage MOS transistor 425. In this example, the drain isolation implant regions 443 correspond to the sub-regions 450 exposed by the first implantation mask 439, as shown in FIG. Figure 4A The first dopant 441 is a dopant of the second conductivity type, in this example an n-type dopant such as phosphorus. 12 cm -2 to 10 14 cm -2 The first dopant 441 is implanted at a dose sufficient to provide a desired average dopant density of the second conductivity type in the subsequently formed drain isolation well 412 and the subsequently formed third well 430. Having multiple drain isolation implant regions 443 can provide a first average dose of the first dopant 441 in the drain isolation implant regions 443, and can provide a second average dose of the first dopant 441 in the well implant regions 444 in the region for the first high voltage MOS transistor 425, wherein the first desired average dose of the first dopant 441 in the drain isolation implant regions 443 is lower than the second average dose of the first dopant 441 in the well implant regions 444. The first dopant 441 can be implanted at an energy sufficient to propagate a substantial portion of the first dopant 441 through the protective layer 438 and into the substrate 401. The first implant mask 439 is removed after implanting the first dopant 441.

[0066] refer to Figure 4B , the substrate 401 is heated by a thermal process 445 to diffuse and activate Figure 4A The drain isolation implantation region 443 and the well implantation region 444 Figure 4A The first dopant 441 is diffused to form the drain isolation well 412 and the third well 430, respectively. The thermal process 445 can have a thermal profile sufficient to allow the first dopant 441 to diffuse sufficiently to form a drain isolation well 412 that is continuous across the drain isolation injection region. Having multiple drain isolation injection regions 443 can cause multiple laterally adjacent regions 412a of a higher dopant density of the second conductivity type in the drain isolation well 412, wherein each region 412a corresponds to the drain isolation injection region 443. For example, the thermal process 445 can heat the substrate 401 to 1080°C to 1120°C for 300 minutes to 400 minutes. The thermal process 445 can be as described in reference Figure 2BThe average density of the first dopant 441 in the drain isolation well 412 may be lower than the average density of the first dopant 441 in the third well 430 .

[0067] refer to Figure 4C , forming a field oxide layer 404 extending into the substrate 401. The field oxide layer 404 can be formed by an STI process so that the field oxide layer 404 has a Figure 4C The fourth well 434 may be formed in the region for the second high voltage MOS transistor 426. The fourth well 434 has a first conductivity type, in this example, a p-type, as shown in FIG. Figure 4C shown.

[0068] A second implantation mask 446 is formed over the protective layer 438. The second implantation mask 446 exposes the protective layer 438 in the region for the body well 413 to be formed later in the region for the extended drain MOS transistor 405. The second implantation mask 446 may optionally expose a region for the first well 420 to be formed later in the region for the first low voltage MOS transistor 415. Figure 4A A second implantation mask 446 is formed by a similar process to the first implantation mask 439. A second dopant 447 is implanted into the substrate 401 in the areas exposed by the second implantation mask 446. In this example, the second dopant 447 is a dopant of the second conductivity type, an n-type dopant such as phosphorus and arsenic. The second dopant 447 may be implanted in more than one implantation step, with the primary step having a dose of 10 12 cm -2 to 10 14 cm -2 The phosphorus is implanted at an energy of 400keV to 600keV. The additional implantation step of the second dopant 447 can have a lower dose and lower energy to set the threshold potential for the extended drain MOS transistor 405 and the first low voltage MOS transistor 415. The second implantation mask 446 is removed after the second dopant 447 is implanted. Figure 4A The second implantation mask 446 is removed by a process similar to the process of removing the first implantation mask 439 .

[0069] The substrate 401 is then heated to activate the second dopant 447 implanted into the substrate 401 to form the body well 413 and the first well 420. The substrate 401 may be heated by a rapid thermal process to reduce the second dopant 447 and Figure 4A The body well 413 has a higher average dopant density of the second conductivity type than the drain isolation well 412.

[0070] refer to Figure 4D In the region for the extended drain MOS transistor 405, a drain well 406 is formed in the substrate 401, such that the drain well 406 is vertically separated from the lower layer 403 by the drain isolation well 412. The drain well 406 has a first conductivity type; in this example, a p-type. In the region for the second low voltage MOS transistor 416, a second well 424 can be formed in the substrate 401. The second well 424 has a first conductivity type and can be formed to have a distribution of dopants of the first conductivity type similar to that of the drain well 406. The drain well 406 and the second well 424 can be as described in reference Figure 2D The drain well 206 and the second well 224 are formed simultaneously as disclosed herein, thereby obtaining similar advantages of reducing manufacturing costs. Figure 4C The protective layer 438 is then removed.

[0071] In the region for the extended drain MOS transistor 405, a gate dielectric layer 409 is formed on the top surface 402 of the substrate 401. A gate 410 of the extended drain MOS transistor 405 is formed on the gate dielectric layer 409. The gate 410 and the gate dielectric layer 409 may be formed as described in reference to FIG. Figure 2D The gate 210 and the gate dielectric layer 209 are formed as disclosed in the prior art. The gate sidewall spacer 411 may be formed on the side surface of the gate 410. The gate sidewall spacer 411 may be formed as disclosed in the prior art. Figure 2D The silicide blocking layer 448 is formed as disclosed above. The silicide blocking layer 448 is formed over the top surface 402 of the substrate 401, extending from the gate 410 to the drain contact region 407. The silicide blocking layer 448 can be formed by forming one or more layers of silicon dioxide, silicon nitride, or silicon nitride over the gate 410 and over the top surface 402 of the substrate 401, and then etching the silicide blocking layer 448 on the etched mask ( Figure 4D Alternatively, the silicide blocking layer 448 may be formed by patterning a conformal layer used to form the gate sidewall spacers 411, such that the silicide blocking layer 448 is implemented as an extension of the gate sidewall spacers 411.

[0072] In the region for the first low-voltage MOS transistor 415, a first low-voltage gate structure 417 is formed on the top surface 402 of the substrate 401. In the region for the second low-voltage MOS transistor 416, a second low-voltage gate structure 421 is formed on the top surface 402 of the substrate 401. In the region for the first high-voltage MOS transistor 425, a first high-voltage gate structure 427 is formed on the top surface 402 of the substrate 401. In the region for the second high-voltage MOS transistor 426, a second high-voltage gate structure 431 is formed on the top surface 402 of the substrate 401. Part or all of the first low-voltage gate structure 417, the second low-voltage gate structure 421, the first high-voltage gate structure 427, and the second high-voltage gate structure 431 may be formed simultaneously with the gate dielectric layer 409, the gate 410, and the gate sidewall spacers 411 of the extended-drain MOS transistor 405.

[0073] The source region 408 is formed in the substrate 401, in contact with the body well 413 adjacent to the gate 410, and is positioned opposite the drain well 406. The source region 408 has a first conductivity type; in this example, the source region 408 is p-type. The source region 408 can be as described in reference Figure 2D 4. A drain contact region 407 may be formed as disclosed above in the substrate 401, contacting the drain well 406. The drain contact region 407 has a first conductivity type; in this example, it is p-type. The drain contact region 407 may be formed simultaneously with the source region 408. A first source 418 and a first drain 419 are formed in the substrate 401 on opposite sides of the first low-voltage gate structure 417 in the region for the first low-voltage MOS transistor 415. A third source 428 and a third drain 429 are formed in the substrate 401 on opposite sides of the first high-voltage gate structure 427 in the region for the first high-voltage MOS transistor 425. The first source 418, the first drain 419, the third source 428, and the third drain 429 have a first conductivity type; in this example, they are p-type. The first source 418 , the first drain 419 , the third source 428 , and the third drain 429 may be formed simultaneously with the source region 408 .

[0074] A body contact region 414 may be optionally formed in the substrate 401, contacting the body well 413. The body contact region 414 has a second conductivity type; in this example, the body contact region 414 is n-type. The body contact region 414 may be as described in reference Figure 2DThe second low-voltage MOS transistor 416 is formed as disclosed in the body contact region 214. A second source 422 and a second drain 423 are formed in the substrate 401 on opposite sides of the second low-voltage gate structure 421 in the region for the second low-voltage MOS transistor 416. A fourth source 432 and a fourth drain 433 are formed in the substrate 401 on opposite sides of the second high-voltage gate structure 431 in the region for the second high-voltage MOS transistor 426. The second source 422, the second drain 423, the fourth source 432, and the fourth drain 433 have the second conductivity type; in this example, the second source 422, the second drain 423, the fourth source 432, and the fourth drain 433 are n-type. The second source 422, the second drain 423, the fourth source 432, and the fourth drain 433 can be formed simultaneously with the body contact region 414.

[0075] Metal silicide 449 is formed on drain contact region 407, source region 408, body contact region 414, first source 418, first drain 419, second source 422, second drain 423, third source 428, third drain 429, fourth source 432, and fourth drain 433. An example process for forming metal silicide 449 may include forming a metal layer ( Figure 4D 432 and the fourth drain 433.

[0076] The integrated circuit 400 may be formed by forming a dielectric layer ( Figure 4D ) to continue, which is similar to Figure 3 The dielectric layer 335. Contacts can be formed through the dielectric layer (not in Figure 4D ), similar to Figure 4D The contact 336 can be formed on the dielectric layer. Figure 4D ), thereby making electrical connections to the contacts, similar to Figure 3 Interconnect 337.

[0077] Figure 55 is a cross-section of yet another example integrated circuit including an extended drain MOS transistor with dual well isolation. Integrated circuit 500 has a substrate 501 having a top surface 502 and including a lower layer 503 of semiconductor material having a first conductivity type. In this example, the first conductivity type is n-type, such as Figure 5 As shown. The substrate 501 may further include a field oxide layer 504 extending to the top surface 502. The field oxide layer 504 may have a local oxidation of silicon (LOCOS) structure, wherein the field oxide layer 504 extends below the top surface 502 to a depth of 250 nanometers to 750 nanometers and extends above the top surface 502 to a height of 150 nanometers to 500 nanometers, with a tapered end, sometimes referred to as a bird's beak, as shown. Figure 5 Depicted.

[0078] Integrated circuit 500 includes an extended drain MOS transistor 505 having a first polarity (n-channel in this example). Extended drain MOS transistor 505 includes a drain well 506 located in substrate 501, which has a first conductivity type, n-type in this example. Drain well 506 may have a first conductivity type, n-type in this example. Figure 1 The average dopant density of the first conductivity type disclosed in the drain well 106 of the extended drain MOS transistor 505 may optionally include a drain contact region 507 that contacts the drain well 506 and extends to the top surface 502 of the substrate 501. The drain contact region 507 has the first conductivity type and may have a configuration similar to that described in reference to FIG. Figure 1 The drain contact region 107 discloses an average dopant density of the first conductivity type.

[0079] The extended drain MOS transistor 505 includes a source region 508 of a first conductivity type located in the substrate 501; in this example, the source region 508 is n-type. The source region 508 and the drain contact region 507 may have similar average densities of dopants of the first conductivity type. The extended drain MOS transistor 505 includes a gate dielectric layer 509 on the top surface 502 of the substrate 501 and a gate 510 on the gate dielectric layer 509. The gate 510 and the gate dielectric layer 509 may be reference Figure 1 The gate 110 and the gate dielectric layer 109 are made of materials disclosed herein. The gate 510 extends from the source region 508 toward the drain well 506; in this example, the gate 510 overlaps a portion of the drain well 506. In this example, the extended drain MOS transistor 505 can include an element of the field oxide layer 504a between the drain contact region 507 and the portion of the drain well 506 that overlaps with the gate 510. The drain well 506 extends below the element of the field oxide layer 504a, as shown in FIG. Figure 5 The extended drain MOS transistor 505 may include gate sidewall spacers 511 on side surfaces of the gate 510 .

[0080] The drain well 506 is vertically separated from the lower layer 503 by a drain isolation well 512, which is located in the substrate 501 and has a second conductivity type opposite to the first conductivity type. In this example, the drain isolation well 512 is p-type, such as Figure 5 As shown. The drain isolation well 512 contacts the lower layer 503 and the drain well 506. The drain isolation well 512 may have, for example, 10 15 cm -3 to 10 17 cm -3 The average dopant density of the second conductivity type is Figure 5 As shown, the drain isolation well 512 can laterally surround the drain well 506 and extend completely below the drain well 506. In this example, the drain isolation well 512 can have two or more vertically adjacent regions 512a of higher dopant density of the second conductivity type. The higher dopant density regions 512a can provide a more uniform vertical distribution of the second conductivity type dopant, which is consistent with the embodiment of the present invention. Figure 1 This may advantageously achieve a desired junction capacitance and a desired breakdown potential of the drain well 506 around the lateral perimeter of the drain well 506 , compared to the vertically reduced dopant concentration of the drain isolation well 112 .

[0081] The source region 508 is vertically separated from the lower layer 503 by a body well 513, which is located in the substrate 501 and has a second conductivity type. In this example, the body well 513 is p-type, such as Figure 5 As shown. The body well 513 contacts the lower layer 503 and the source region 508. The body well 513 may have a thickness of, for example, 10 16 cm -3 to 10 18 cm -3 The average dopant density of the second conductivity type of the drain isolation well 512 is less than the average dopant density of the second conductivity type of the body well 513. In this example, the body well 513 can be separated from the drain well 506 below the gate 510 by the drain isolation well 512, as shown in FIG. Figure 5The configuration of the extended drain MOS transistor 505 (having a drain well 506 isolated from the lower layer 503 by a drain isolation well 512, and having a source region 508 isolated from the lower layer 503 by a body well 513, wherein both the drain isolation well 512 and the body well 513 contact the lower layer 503) can advantageously reduce the area of the extended drain MOS transistor 505 by eliminating the need for a single isolation structure extending completely below the extended drain MOS transistor 505. The extended drain MOS transistor 505 can optionally include a body contact region 514 that contacts the body well 513 and extends to the top surface 502 of the substrate 501. The body contact region 514 has a second conductivity type, wherein the average dopant density of the second conductivity type is, for example, 10 19 cm -3 to 10 21 cm -3 To provide the desired low resistance connection to the body well 513 .

[0082] Extended drain MOS transistor 505 Figure 5 506. In an alternative version of this example, extended drain MOS transistor 505 may have a symmetrical configuration, with source regions 508 located on opposite sides of drain well 506.

[0083] The integrated circuit 500 may optionally include a first low voltage MOS transistor 515 having a first polarity (n-channel in this example). The first low voltage MOS transistor 515 has a first low voltage gate structure 517 on the top surface 502 of the substrate 501, a first source 518 in the substrate 501, and a first drain 519 in the substrate 501. The first low voltage MOS transistor 515 is disposed in a first well 520 and has a second conductivity type, which is p-type in this example, as shown in FIG. Figure 5 The first well 520 may have an average dopant density of the second conductivity type substantially equal to that of the body well 513 .

[0084] The integrated circuit 500 may also optionally include a second low voltage MOS transistor 516 having a second polarity (p-channel in this example). The second low voltage MOS transistor 516 has a second low voltage gate structure 521 on the top surface 502 of the substrate 501, a second source 522 in the substrate 501, and a second drain 523 in the substrate 501. The second low voltage MOS transistor 516 is disposed in a second well 524 and has a first conductivity type, which is n-type in this example. Figure 5 The second well 524 may have an average dopant density of the first conductivity type substantially equal to that of the drain well 506 .

[0085] The integrated circuit 500 may optionally include a first high voltage MOS transistor 525 having a first polarity (n-channel in this example). The first high voltage MOS transistor 525 has a first high voltage gate structure 527 on the top surface 502 of the substrate 501, a third source 528 in the substrate 501, and a third drain 529 in the substrate 501. The first high voltage MOS transistor 525 is disposed in a third well 530, which has a second conductivity type, in this example, p-type, as shown in FIG. Figure 5 The third well 530 may have an average dopant density of the second conductivity type substantially equal to that of the drain isolation well 512 , and may have two or more regions 530 a vertically adjacent to each other having a higher dopant density of the second conductivity type substantially equal to that of the drain isolation well 512 .

[0086] The integrated circuit 500 may also optionally include a second high voltage MOS transistor 526 having a second polarity (p-channel in this example). The second high voltage MOS transistor 526 has a second high voltage gate structure 531 on the top surface 502 of the substrate 501, a fourth source 532 in the substrate 501, and a fourth drain 533 in the substrate 501. The second high voltage MOS transistor 526 is disposed in a fourth well 534, which has a first conductivity type, in this example, n-type, as shown in FIG. Figure 5 shown.

[0087] The integrated circuit 500 may include a dielectric layer 535 above the top surface 502 of the substrate 501. The dielectric layer 535 may be a PMD layer that is substantially equal to the reference Figure 1 The integrated circuit 500 may further include a contact 536 extending through the dielectric layer 535 to provide electrical connections to the extended drain MOS transistor 505, the first low voltage MOS transistor 515, the second low voltage MOS transistor 516, the first high voltage MOS transistor 525, and the second high voltage MOS transistor 526. The contact 536 may have a reference Figure 1 The integrated circuit 500 may further include an interconnect 537 on the dielectric layer 535 to make electrical connections to the contact 536.

[0088] Figures 6A to 6D is a cross-section of an integrated circuit including an extended drain MOS transistor with dual well isolation depicted at various stages of yet another example formation method. Figure 6A , the formation of the integrated circuit 600 includes obtaining a substrate 601, which may be as described in reference Figure 2AThe substrate 601 has a top surface 602 and includes a lower layer 603 of semiconductor material below the top surface 602. The lower layer 603 has a first conductivity type, in this example, n-type, such as Figure 6A As shown. The substrate 601 includes a region for an extended drain MOS transistor 605, a region for a first low voltage MOS transistor 615, a region for a second low voltage MOS transistor 616, a region for a first high voltage MOS transistor 625, and a region for a second high voltage MOS transistor 626. Figure 1 The terms "low voltage" and "high voltage" are used as described.

[0089] A protective layer 638 may be formed on the top surface 602. The protective layer 638 may have a Figure 2A The composition and structure of the protective layer 238 are described. A first implantation mask 639 is formed above the protective layer 638. The first implantation mask 639 is formed in the region for extending the drain MOS transistor 605 for the drain isolation well 612 (eg, Figure 6B The first implantation mask 639 may optionally expose a third well 630 (as shown) for subsequent formation in the region for the first high voltage MOS transistor 625. Figure 6B As shown in the area. Figure 2A A first implantation mask 639 is formed as disclosed for the first implantation mask 239 .

[0090] A first dopant 641 is implanted into the substrate 601 in the region exposed by the first implant mask 639 to form a plurality of drain isolation implant regions 643 vertically arranged in the region for the extended drain MOS transistor 605, and a well implant region 644 vertically arranged in the region for the first high voltage MOS transistor 625. In this example, the drain isolation implant regions 643 correspond to the implantation of the first dopant 641 implanted at different implant energies. The first dopant 641 is a dopant of the second conductivity type, in this example a p-type dopant such as boron. It can be 10 12 cm -2 to 10 14 cm -2 The first dopant 641 is implanted with a total dose of 100 keV to 1000 keV to form a well implant region 644 in a vertically arranged structure. The drain isolation well 612 (e.g., a drain isolation well 612 formed later) may be formed by having multiple drain isolation implant regions 643 in the region for the extended drain MOS transistor 605 and a well implant region 644 in the region for the first high voltage MOS transistor 625. Figure 6B ) and in the subsequently formed third well 630 (as shown Figure 6B After implanting the first dopant 641, the first implant mask 639 is removed.

[0091] refer to Figure 6B , the substrate 601 is heated by a thermal process 645 to diffuse and activate Figure 6A The drain isolation implantation region 643 and the well implantation region 644 Figure 6A The first dopant 641 is diffused to form the drain isolation well 612 and the third well 630, respectively. The thermal process 645 may have a thermal profile sufficient to sufficiently diffuse the first dopant 641 to form a continuous drain isolation well 612 from the drain isolation implant region 643 and a continuous third well 630 from the well implant region 644, as shown in FIG. Figure 6B As shown. Having multiple drain isolation injection regions 643 can cause multiple regions 612a with a higher second conductivity type dopant density vertically adjacent to each other in the drain isolation well 612, wherein each region 612a corresponds to the drain isolation injection region 643. Similarly, having multiple well injection regions 644 can cause multiple regions 630a with a higher second conductivity type dopant density vertically adjacent to each other in the third well 630, wherein each region 630a corresponds to the drain isolation injection region 643. For example, the thermal process 645 can heat the substrate 601 to 1080°C to 1120°C for 100 minutes to 300 minutes. The thermal process 645 can be as described in reference Figure 2B Implemented as disclosed.

[0092] refer to Figure 6C , forming a field oxide layer 604, which extends into the substrate 601. The field oxide layer 604 can be formed by a LOCOS process so that the field oxide layer 604 has Figure 6C The LOCOS structure is depicted. An exemplary LOCOS process includes forming a silicon nitride layer over protective layer 638, patterning the silicon nitride layer to expose protective layer 638 in the area for field oxide layer 604, growing field oxide layer 604 via a thermal oxidation process, and removing the silicon nitride layer. After field oxide layer 604 is formed, protective layer 638 may be augmented by a new protective material layer (such as a new silicon dioxide layer) formed via a thermal oxidation process.

[0093] A fourth well 634 may be formed in the region for the second high voltage MOS transistor 626. The fourth well 634 has a first conductivity type, which is an n-type in this example. Figure 6C shown.

[0094] A second implantation mask 646 is formed over the protective layer 638. The second implantation mask 646 exposes the protective layer 638 in the region for the body well 613 to be formed later in the region for the extended drain MOS transistor 605. The second implantation mask 646 may optionally expose a region for the first well 620 to be formed later in the region for the first low voltage MOS transistor 615. Figure 6A A second implantation mask 646 is formed by a similar process to the first implantation mask 639. A second dopant 647 is implanted into the substrate 601 in the areas exposed by the second implantation mask 646. The second dopant 647 is a dopant of the second conductivity type, in this example a p-type dopant such as boron. The second dopant 647 may be implanted in more than one implantation step, with the primary step having a dose of 10 12 cm -2 to 10 14 cm -2 The phosphorus is implanted at an energy of 400keV to 600keV. The additional implantation step of the second dopant 647 can have a lower dose and lower energy to set the threshold potential for the extended drain MOS transistor 605 and the first low voltage MOS transistor 615. The second implantation mask 646 is removed after the second dopant 647 implantation. Figure 6A The second implantation mask 646 is removed by a process similar to the process of removing the first implantation mask 639 .

[0095] The substrate 601 is then heated to activate the second dopant 647 implanted into the substrate 601 to form the body well 613 and the first well 620. The substrate 601 may be heated by a rapid thermal process to reduce the second dopant 647 and the Figure 6A The body well 613 has a higher average dopant density of the second conductivity type than the drain isolation well 612 .

[0096] refer to Figure 6D In the region for the extended drain MOS transistor 605, a drain well 606 is formed in the substrate 601 so that the drain well 606 is vertically separated from the lower layer 603 by the drain isolation well 612. The drain well 606 may extend partially below the gate 610, as shown in FIG. Figure 6D As depicted, drain well 606 is laterally separated from body well 613 by drain isolation well 612 below gate 610. Drain well 606 of this example is formed so as to extend below elements of field oxide layer 604a. Drain well 606 has a first conductivity type; in this example, n-type.

[0097] In the region for the second low voltage MOS transistor 616, a second well 624 may be formed in the substrate 601. The second well 624 has a first conductivity type and may be formed to have a distribution of dopants of the first conductivity type similar to that of the drain well 606. The drain well 606 and the second well 624 may be formed as described in reference to FIG. Figure 2D The drain well 206 and the second well 224 are formed simultaneously as disclosed herein, thereby obtaining similar advantages of reducing manufacturing costs. Figure 6C The protective layer 638 is then removed.

[0098] In the region for the extended drain MOS transistor 605, a gate dielectric layer 609 is formed on the top surface 602 of the substrate 601. A gate 610 of the extended drain MOS transistor 605 is formed on the gate dielectric layer 609. The gate 610 and the gate dielectric layer 609 may be formed as described in reference to FIG. Figure 2D The gate 210 and gate dielectric layer 209 are formed as disclosed in the prior art. In this example, the gate 610 may extend from the source region 608 to the field oxide layer 604a in the drain well 606. Gate sidewall spacers 611 may be formed on the side surfaces of the gate 610. The gate sidewall spacers 611 may be formed as disclosed in the prior art. Figure 2D The gate sidewall spacers 211 are formed as disclosed.

[0099] In the region for the first low-voltage MOS transistor 615, a first low-voltage gate structure 617 is formed on the top surface 602 of the substrate 601. In the region for the second low-voltage MOS transistor 616, a second low-voltage gate structure 621 is formed on the top surface 602 of the substrate 601. In the region for the first high-voltage MOS transistor 625, a first high-voltage gate structure 627 is formed on the top surface 602 of the substrate 601. In the region for the second high-voltage MOS transistor 626, a second high-voltage gate structure 631 is formed on the top surface 602 of the substrate 601. Part or all of the first low-voltage gate structure 617, the second low-voltage gate structure 621, the first high-voltage gate structure 627, and the second high-voltage gate structure 631 may be formed simultaneously with the gate dielectric layer 609, the gate 610, and the gate sidewall spacers 611 of the extended-drain MOS transistor 605.

[0100] The source region 608 is formed in the substrate 601, in contact with the body well 613 adjacent to the gate 610, and positioned opposite the drain well 606. The source region 608 has a first conductivity type; in this example, the source region 608 is n-type. The source region 608 can be as described in reference Figure 2D606. A drain contact region 607 may optionally be formed in substrate 601, contacting drain well 606. Drain contact region 607 has a first conductivity type; in this example, drain contact region 607 is n-type. Drain contact region 607 may be formed simultaneously with source region 608. A first source 618 and a first drain 619 are formed in substrate 601 on opposite sides of a first low-voltage gate structure 617 in the region for first low-voltage MOS transistor 615. A third source 628 and a third drain 629 are formed in substrate 601 on opposite sides of a first high-voltage gate structure 627 in the region for first high-voltage MOS transistor 625. The first source 618, the first drain 619, the third source 628, and the third drain 629 have a first conductivity type; in this example, the first source 618, the first drain 619, the third source 628, and the third drain 629 are n-type. The first source 618 , the first drain 619 , the third source 628 , and the third drain 629 may be formed simultaneously with the source region 608 .

[0101] A body contact region 614 may be optionally formed in the substrate 601, contacting the body well 613. The body contact region 614 has a second conductivity type; in this example, the body contact region 614 is p-type. The body contact region 614 may be as described in reference Figure 2D The second low-voltage MOS transistor 616 is formed as disclosed in the body contact region 214. A second source 622 and a second drain 623 are formed in the substrate 601 on opposite sides of the second low-voltage gate structure 621 in the region for the second low-voltage MOS transistor 616. A fourth source 632 and a fourth drain 633 are formed in the substrate 601 on opposite sides of the second high-voltage gate structure 631 in the region for the second high-voltage MOS transistor 626. The second source 622, the second drain 623, the fourth source 632, and the fourth drain 633 have the second conductivity type; in this example, the second source 622, the second drain 623, the fourth source 632, and the fourth drain 633 are p-type. The second source 622, the second drain 623, the fourth source 632, and the fourth drain 633 can be formed simultaneously with the body contact region 614.

[0102] The integrated circuit 600 may be formed by forming a dielectric layer ( Figure 6D ) to continue, similar to Figure 5 A dielectric layer 535 may be formed through the dielectric layer. Figure 6D not shown), similar to Figure 5 The contact 536 can be formed on the dielectric layer. Figure 6D Not shown), thereby making electrical connections to the contacts, similar to Figure 5 Interconnect 537.

[0103] Various features of the examples disclosed herein may be combined in other manifestations of the example integrated circuits. Any of the extended drain MOS transistors 105, 305, and 505 may have a symmetrical or asymmetrical construction, and any of the extended drain MOS transistors 105, 305, and 505 may have p-channel polarity or n-channel polarity, with appropriate changes to the first conductivity type and the second conductivity type. Any of the extended drain MOS transistors 105, 305, and 505 may have a field oxide element in the corresponding drain well 106, 306, and 506. Any of the extended drain MOS transistors 105, 305, and 505 may have an STI or LOCOS field oxide. Any of the extended drain MOS transistors 105, 305, and 505 may have a metal silicide and may have a silicide barrier layer. Any of the drain isolation wells 112, 312, and 512 may be provided in accordance with reference to Figure 2A and Figure 2B 、 Figure 4A and Figure 4B 、 Figure 6A and Figure 6B The disclosed example methods are formed.

[0104] Although various embodiments of the present disclosure have been described above, it should be understood that they are presented by way of example only and not limitation. Various modifications may be made to the disclosed embodiments according to the disclosure herein without departing from the spirit or scope of the present disclosure. Therefore, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. Rather, the scope of the present disclosure should be defined in accordance with the appended claims and their equivalents.

Claims

1. An integrated circuit comprising: substrate; a lower layer of semiconductor material in the substrate, the lower layer having a first conductivity type; An extended drain metal oxide semiconductor transistor, i.e., an extended drain MOS transistor, comprises: a drain well in the substrate, the drain well having the first conductivity type; a source region in the substrate, the source region having the first conductivity type; a drain isolation well in the substrate, the drain isolation well having a second conductivity type opposite to the first conductivity type, wherein the drain isolation well separates the drain well from the underlying layer and contacts the drain well and contacts the underlying layer; and A body well in the substrate, the body well having the second conductivity type, wherein the body well separates the source region from the underlying layer, and the body well contacts the source region and contacts the underlying layer, and wherein an average dopant density of dopants of the second conductivity type in the drain isolation well is less than an average dopant density of dopants of the second conductivity type in the body well. 2 . The integrated circuit of claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

3. The integrated circuit of claim 1 , further comprising a MOS transistor in a well in the substrate, the well having the second conductivity type, wherein an average dopant density of dopants of the second conductivity type in the well is equal to an average dopant density of dopants of the second conductivity type in the body well.

4. The integrated circuit of claim 1 , further comprising a MOS transistor in a well in the substrate, the well having the second conductivity type, wherein an average dopant density of dopants of the second conductivity type in the well is equal to an average dopant density of dopants of the second conductivity type in the drain isolation well.

5. The integrated circuit of claim 1 , wherein the drain isolation well has a plurality of regions of higher dopant density of the second conductivity type, the plurality of regions being laterally adjacent to one another, the drain isolation well between the regions of higher dopant density having a lower dopant density of the second conductivity type than the regions of higher dopant density, wherein laterally refers to a direction parallel to the top surface of the substrate.

6. The integrated circuit of claim 1 , wherein the drain isolation well has a plurality of regions of higher dopant density of the second conductivity type, the plurality of regions being vertically adjacent to one another and separated by regions of lower dopant density of the second conductivity type, wherein vertical refers to a direction perpendicular to a top surface of the substrate.

7. The integrated circuit of claim 1, wherein the drain well extends beneath elements of a field oxide layer.

8. The integrated circuit of claim 1 , further comprising a metal silicide on the source region and a drain contact region, the drain contact region contacting the drain well, wherein a top surface of the substrate between the gate of the extended drain MOS transistor and the drain contact region is free of the metal silicide.

9. The integrated circuit of claim 1, wherein the drain well contacts the body well below the gate of the extended drain MOS transistor.

10. The integrated circuit of claim 1, wherein the drain well is separated from the body well by the drain isolation well below the gate of the extended drain MOS transistor.

11. The integrated circuit of claim 1 , further comprising a MOS transistor in a well in the substrate, the well having the first conductivity type, wherein an average dopant density of dopants of the first conductivity type in the well is equal to an average dopant density of dopants of the first conductivity type in the drain well.

12. A method of forming an integrated circuit, comprising: Obtaining a substrate, the substrate comprising a lower layer of semiconductor material, the lower layer having a first conductivity type; forming a drain isolation well in the substrate, the drain isolation well having a second conductivity type opposite to the first conductivity type, wherein the drain isolation well contacts the underlying layer; forming a body well in the substrate, the body well having the second conductivity type, wherein the body well contacts the underlying layer, and wherein an average dopant density of dopants of the second conductivity type in the drain isolation well is less than an average dopant density of dopants of the second conductivity type in the body well; forming a drain well in the substrate, the drain well having the first conductivity type, wherein the drain well contacts the drain isolation well and is separated from the underlying layer by the drain isolation well; as well as A source region is formed in the substrate, the source region having the first conductivity type, wherein the source region contacts the body well and is separated from the underlying layer by the body well.

13. The method according to claim 12, wherein forming the drain isolation well comprises: forming an implantation mask, the implantation mask exposing a region having a lateral dimension in one direction that is less than half of a lateral dimension of the drain isolation well in the same direction, wherein lateral refers to a direction parallel to a top surface of the substrate; implanting a dopant of the second conductivity type into the substrate at locations exposed by the implantation mask; removing the implantation mask; as well as The substrate is heated to diffuse and activate the dopants in the substrate.

14. The method according to claim 12, wherein forming the drain isolation well comprises: forming an implantation mask that exposes a plurality of subregions in a region for an extended drain MOS transistor; implanting a dopant of the second conductivity type into the substrate at a location exposed by the implantation mask to form a drain isolation implantation region, the drain isolation implantation region corresponding to the sub-region; removing the implantation mask; as well as The substrate is heated to diffuse and activate the dopants in the substrate so that the drain isolation well is continuous across the drain isolation implant region.

15. The method according to claim 12, wherein forming the drain isolation well comprises: implanting a dopant of the second conductivity type into the substrate at multiple doses at different energies; as well as The substrate is heated to diffuse and activate the dopants in the substrate. The method of claim 12 , wherein the first conductivity type is p-type and the second conductivity type is n-type.

17. The method according to claim 12, wherein forming the drain isolation well comprises: forming an implantation mask that exposes a region for an extended drain MOS transistor and an area for a well in the region for the MOS transistor; implanting a dopant of the second conductivity type into the substrate at locations exposed by the implantation mask to form a drain isolation implant region in the region for the extended drain MOS transistor and a well implant region in the region for the MOS transistor; removing the implantation mask; as well as The substrate is heated to diffuse and activate the dopants in the substrate to simultaneously form the drain isolation implant region and the well.

18. The method of claim 12, wherein forming the body well comprises: implanting a dopant of the second conductivity type into the substrate in a region for an extended drain MOS transistor and in a region for a well in a region for a MOS transistor; as well as The substrate is heated to diffuse and activate the dopants in the substrate to simultaneously form a body implant region and the well.

19. The method of claim 12, comprising forming an element of a field oxide layer in the substrate, wherein the drain well extends below the element of the field oxide layer.

20. The method of claim 12, comprising: forming a drain contact region in the substrate in the drain well; forming a silicide blocking layer over the substrate between the gate of the extended drain MOS transistor and the drain contact region; as well as A metal silicide is formed on the drain contact region, and the substrate between the gate and the drain contact region does not contain the metal silicide.

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