Motor control device, motor system, and motor control method

Abstract

The present invention provides a motor control device. A PWM signal generating unit of the motor control device (100-1) divides the on-time of any one of a first PWM signal, a second PWM signal and a third PWM signal, and allocates the divided on-time to the on-time less than the threshold value when there is an on-time greater than a threshold value in one of an up-counting period and a down-counting period of a carrier and there is an on-time less than the threshold value in the other of the up-counting period and the down-counting period.

Description

Technical Field

[0001] The present invention relates to a motor control device, a motor system and a motor control method. Background Art

[0002] Patent document 1 discloses a technique for detecting the current of each phase U, V, and W for controlling a motor by using a shunt resistor inserted into the DC portion of an inverter circuit. In order to detect all currents of the three phases in this manner, it is necessary to generate a three-phase PWM signal pattern in such a manner that currents of two or more phases can be detected within one cycle of a PWM (Pulse Width Modulation) carrier.

[0003] <Prior Art Literature>

[0004] <Patent Documents>

[0005] Patent Document 1: Japanese Patent Application Publication No. 2015-84632 Summary of the invention

[0006] <Problems to be Solved by the Invention>

[0007] However, in the conventional technology, there are cases where the phase currents of at least two phases cannot be detected with high accuracy within one cycle of the carrier.

[0008] The present invention is made in view of the above, and its object is to provide a motor control device that can detect phase currents of at least two phases with high accuracy within one cycle of a carrier.

[0009] <Methods used to solve the problem>

[0010] The motor control device of the embodiment of the present invention includes: an inverter unit that drives the motor based on a first PWM signal, a second PWM signal, and a third PWM signal; a current detector that outputs a detection signal corresponding to the current value of the current flowing through the DC side of the inverter unit; a current detection unit that detects the phase current flowing through each phase of the motor by obtaining the detection signal; a duty ratio setting unit that sets the duty ratio of the first PWM signal, the second PWM signal, and the third PWM signal based on the detection value of the phase current of each phase; and a PWM signal generating unit that sets the duty ratio of the first PWM signal, the second PWM signal, and the third PWM signal. The first PWM signal, the second PWM signal and the third PWM signal are generated by comparing a set value of the ratio with the level of a carrier whose level increases and decreases periodically. When there is a power-on time greater than a threshold value in one of an up-count period and a down-count period of the carrier and there is a power-on time less than the threshold value in the other of the up-count period and the down-count period, the PWM signal generating unit divides the on time of any one of the first PWM signal, the second PWM signal and the third PWM signal and allocates the divided on time to the power-on time less than the threshold value.

[0011] <Effects of the Invention>

[0012] The motor control device of the present invention has the effect of being able to detect phase currents of at least two phases with high accuracy within one cycle of a carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a diagram showing a configuration example of a motor system 1 - 1 according to Embodiment 1 of the present invention.

[0014] Figure 2 It is shown Figure 1 The diagram shows an example of the configuration of the carrier generator 37, the PWM signal generator 32, etc.

[0015] Figure 3 This is a diagram for explaining the principle of generating a triangular wave carrier of each phase.

[0016] Figure 4 The diagram shows waveforms of a plurality of PWM signals U, V, and W, a waveform of a carrier wave C per cycle of these PWM signals, and waveforms of duty ratios Udu, Vdu, and Wdu of each phase.

[0017] Figure 5 This is the first diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention.

[0018] Figure 6This is a second diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention.

[0019] Figure 7 1 is a flowchart showing the operation of the motor control device 100 - 1 .

[0020] Figure 8 : is a flowchart showing an example of the first current detection process.

[0021] Fig. 9 : is a flowchart showing an example of the second current detection process.

[0022] Fig. 10A This is a first flowchart for explaining the operation of the pulse phase adjustment process.

[0023] Fig. 10B This is a second flowchart for explaining the operation of the pulse phase adjustment process.

[0024] Fig. 10C This is a third flowchart for explaining the operation of the pulse phase adjustment process. DETAILED DESCRIPTION

[0025] Hereinafter, a motor control device, a motor system, and a motor control method according to embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0026] [Implementation Method 1]

[0027] Figure 1 It is a diagram showing a configuration example of a motor system 1 - 1 according to Embodiment 1 of the present invention. Figure 2 It is shown Figure 1 The diagram shows an example of the configuration of the carrier generator 37, the PWM signal generator 32, etc. Figure 1 The motor system 1-1 shown controls the rotation of the motor 4. The device on which the motor system 1-1 is mounted is, for example, a copy machine, a personal computer, a refrigerator, etc., but the device is not limited thereto. The motor system 1-1 includes at least the motor 4 and the motor control device 100-1.

[0028] The motor 4 has a plurality of windings. The motor 4 has, for example, a three-phase winding including a U-phase winding, a V-phase winding, and a W-phase winding. As a specific example of the motor 4, a three-phase brushless motor or the like can be cited.

[0029] The motor control device 100-1 drives the motor through an inverter, which converts direct current into three-phase alternating current by controlling the on / off (ON, OFF) of a plurality of switching elements connected in a three-phase bridge according to an energization pattern of a PWM signal including three phases. The motor control device 100-1 includes an inverter 23, a current detection unit 27, a current detection timing adjustment unit 34, a drive circuit 33, an energization pattern generation unit 35, a carrier generation unit 37, and a clock pulse generation unit 36.

[0030] The inverter 23, which is an inverter unit, is a circuit that converts the DC supplied from the DC power supply 21 into a three-phase AC by switching a plurality of switching elements, and causes the three-phase AC driving current to flow through the motor 4, thereby rotating the rotor of the motor 4. The inverter 23 drives the motor 4 based on a plurality of energization patterns generated by the energization pattern generation unit 35 (more specifically, a three-phase PWM signal generated by the PWM signal generation unit 32 in the energization pattern generation unit 35).

[0031] The inverter 23 has a plurality of switching elements 25U+, 25V+, 25W+, 25U-, 25V-, and 25W- connected in a three-phase bridge. The switching elements 25U+, 25V+, and 25W+ are high-side switching elements (upper bridge arms) connected to the positive side of the DC power supply 21 via the positive bus 22a, respectively. The switching elements 25U-, 25V-, and 25W- are low-side switching elements (lower bridge arms) connected to the negative side (specifically, the ground side) of the DC power supply 21, respectively. The plurality of switching elements 25U+, 25V+, 25W+, 25U-, 25V-, and 25W- are turned on or off according to corresponding drive signals among the plurality of drive signals supplied from the drive circuit 33 based on the PWM signal included in the above-mentioned power-on mode. Hereinafter, when no particular distinction is made, the plurality of switching elements 25U+, 25V+, 25W+, 25U-, 25V-, and 25W- may be referred to simply as switching elements.

[0032] The connection point of the switching element 25U+ and the switching element 25U- is connected to one end of the U-phase winding of the motor 4. The connection point of the switching element 25V+ and the switching element 25V- is connected to one end of the V-phase winding of the motor 4. The connection point of the switching element 25W+ and the switching element 25W- is connected to one end of the W-phase winding of the motor 4. The other ends of the U-phase winding, the V-phase winding, and the W-phase winding are connected to each other.

[0033] Specific examples of the switching element include N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), IGBT (Insulated Gate Bipolar Transistor), etc. However, the switching element is not limited to these.

[0034] The current detector 24 s outputs a detection signal Sd corresponding to the current value of the current flowing through the DC side of the inverter 23 . Figure 1 The current detector 24 shown generates a detection signal Sd corresponding to the current value of the current flowing through the negative bus 22b. The current detector 24 is, for example, a current detection element configured on the negative bus 22b, and more specifically, it is a shunt resistor inserted into the negative bus 22b. The current detection element such as the shunt resistor generates a voltage signal corresponding to the current value of the current flowing through itself as the detection signal Sd. It should be noted that the current detector 24 can be an element that outputs a detection signal corresponding to the current value of the current flowing through the positive bus 22a, and it can be a sensor such as a CT (Current Transformer).

[0035] The current detection unit 27 acquires the detection signal Sd based on the multiple energization patterns (more specifically, the three-phase PWM signals) generated by the energization pattern generation unit 35, thereby detecting the phase currents Iu, Iv, and Iw flowing through the U, V, and W phases of the motor 4. More specifically, the current detection unit 27 acquires the detection signal Sd at an acquisition timing synchronized with the multiple energization patterns (more specifically, the three-phase PWM signals), thereby detecting the phase currents Iu, Iv, and Iw flowing through the U, V, and W phases of the motor 4. The acquisition timing of the detection signal Sd is set by the current detection timing adjustment unit 34.

[0036] For example, the current detection unit 27 introduces the detection signal Sd of the analog voltage generated by the current detector 24 into an AD (Analog to Digital) converter at the acquisition timing set by the current detection timing adjustment unit 34. The AD converter is provided in the current detection unit 27. In addition, the current detection unit 27 detects the phase currents Iu, Iv, and Iw of the U, V, and W phases of the motor 4 by performing AD conversion on the imported analog detection signal Sd to make it a digital detection signal Sd, and digitally processes the digital detection signal Sd after the AD conversion. The detection values ​​of the phase currents Iu, Iv, and Iw of each phase detected by the current detection unit 27 are supplied to the power-on pattern generation unit 35. The clock pulse generation unit 36 ​​generates a clock pulse of a predetermined frequency through a built-in oscillation circuit, and outputs the generated clock pulse to the carrier generation unit 37. It should be noted that the clock pulse generation unit 36 ​​starts to operate at the same time as the power supply of the motor control device 100-1 is turned on.

[0037] The energizing pattern generation unit 35 includes a duty ratio setting unit 31 and a PWM signal generation unit 32. The energizing pattern generation unit 35 generates a pattern for energizing the inverter 23 (energizing pattern of the inverter 23) based on the detection values ​​of the phase currents Iu, Iv, and Iw of the motor 4 detected by the current detection unit 27. The energizing pattern of the inverter 23 can be said to be a pattern for energizing the motor 4 (energizing pattern of the motor 4). The energizing pattern of the inverter 23 includes, for example, a three-phase PWM signal for energizing the inverter 23 in a manner that the motor 4 rotates.

[0038] In addition, when the energization pattern generation unit 35 generates the energization pattern of the inverter 23 by vector control, it has a vector control unit 30 in addition to the duty ratio setting unit 31 and the PWM signal generation unit 32. It should be noted that although the energization pattern of the inverter is generated by vector control in this embodiment, it is not limited to this, and the phase voltage of each phase can also be obtained by VF control or the like.

[0039] After the rotation speed command ωref of the motor 4 is given from the outside, the vector control unit 30 generates a torque current command Iqref and an excitation current command Idref based on the difference between the measured value or estimated value of the rotation speed of the motor 4 and the rotation speed command ωref. The vector control unit 30 calculates the torque current Iq and the excitation current Id based on the phase currents Iu, Iv, and Iw of the U, V, and W phases of the motor 4 by vector control calculation using the rotor position θ. The vector control unit 30 generates a voltage command Vq by, for example, performing a PI control calculation on the difference between the torque current command Iqref and the torque current Iq. The vector control unit 30 generates a voltage command Vd by, for example, performing a PI control calculation on the difference between the excitation current command Idref and the excitation current Id. The vector control unit 30 converts the voltage commands Vq and Vd into phase voltage commands Vu*, Vv*, and Vw* of the U, V, and W phases using the above-mentioned rotor position θ. The phase voltage commands Vu*, Vv*, and Vw* of the respective phases are supplied to the duty ratio setting unit 31 .

[0040] The duty ratio setting unit 31 sets the duty ratios Udu, Vdu, and Wdu for generating three-phase PWM signals (set values ​​of the duty ratios of the phases) based on the input phase voltage commands Vu*, Vv*, and Vw* of the phases.

[0041] A specific example of the method for setting the duty ratio Udu, Vdu, and Wdu of each phase is described. As shown in the following formulas (1) to (3), the duty ratio Udu, Vdu, and Wdu of each phase are set based on the modulation rates modU, modV, and modW. The duty ratios Udu, Vdu, and Wdu of each phase obtained based on the following formulas (1) to (3) are, for example, sinusoidal waveforms with phases that differ by 120 degrees. It should be noted that examples of the waveforms of the duty ratios Udu, Vdu, and Wud of each phase will be described later.

[0042] Udu = modU × (carrier upper limit value) (1)

[0043] Vdu=modV×(carrier upper limit value)···(2)

[0044] Wdu=modW×(carrier upper limit value)···(3)

[0045] The PWM signal generating unit 32 generates a power-on pattern including a 3-phase PWM signal by comparing the duty ratios Udu, Vdu, and Wdu of each phase set by the duty ratio setting unit 31 with the level of the carrier C. The carrier C is a carrier signal whose level increases and decreases periodically. The PWM signal generating unit 32 compares each set value of the duty ratio of each phase with the level of the carrier C. Based on the comparison result, the PWM signal generating unit 32 sets the level of the PWM signal to a high level during a period when the set value of the duty ratio of the PWM signal is greater than the level of the carrier C. On the other hand, based on the comparison result, the PWM signal generating unit 32 sets the level of the PWM signal to a low level during a period when the set value of the duty ratio of the PWM signal is less than the level of the carrier C. The PWM signal generating unit 32 also generates a PWM signal for driving the lower bridge arm by inverting the 3-phase PWM signal for driving the upper bridge arm, and outputs the generated power-on pattern including the PWM signal to the driving circuit 33 after adding a dead time as needed.

[0046] The drive circuit 33 outputs a drive signal for switching the six switching elements 25U+, 25V+, 25W+, 25U-, 25V-, and 25W- included in the inverter 23 according to the power-on pattern including the PWM signal given. As a result, a three-phase AC drive current is supplied to the motor 4, and the rotor of the motor 4 rotates.

[0047] The current detection timing adjustment unit 34 determines the acquisition timing for the current detection unit 27 to detect the phase currents of two phases (two phases) among the phase currents of three phases (three phases) within one cycle of the carrier C based on the carrier C supplied from the PWM signal generation unit 32 and the PWM signal generated by the PWM signal generation unit 32.

[0048] It should be noted that the functions of the current detection unit 27, the energization pattern generation unit 35, and the current detection timing adjustment unit 34 are implemented by the CPU (Central Processing Unit) operating a program stored in a storage device (not shown) in a readable manner. For example, these functions are implemented by the cooperation of hardware and software in a microcomputer including a CPU.

[0049] Next, use Figure 2 The carrier generation unit 37 and the PWM signal generation unit 32 will be described in detail.

[0050] The carrier generation unit 37 includes an up-down counter 12 , a comparator 13 , a comparator 14 , and a flip-flop 15 .

[0051] since Figure 1 The clock pulse, count start signal, and count initial value signal outputted from the clock pulse generating section 36 are inputted into the up-down counter 12 .

[0052] After receiving the count start signal, the up-down counter 12 starts counting the clock pulses, and outputs a triangular wave carrier, namely, carrier C, through cumulative addition operation (adding 1 for each input clock pulse) or cumulative subtraction operation (subtracting 1 for each input clock pulse) of the count value.

[0053] In addition, an initial value of the count is set in the up-down counter 12, and the initial value is set by the above-mentioned count initial value signal.

[0054] The comparator 13 compares the count value of the up-down counter 12 with a predetermined upper limit value, and outputs a detection signal INT1 when detecting that the count value reaches the upper limit value.

[0055] The comparator 14 compares the count value of the up-down counter 12 with a predetermined lower limit value, and outputs a detection signal INT2 when detecting that the count value reaches the lower limit value.

[0056] The flip-flop 15 outputs a low-level “L” signal to the up-down counter 12 through the output from the comparator 13 , and outputs a high-level “H” signal to the up-down counter 12 through the output from the comparator 14 .

[0057] The up-down counter 12 performs cumulative addition operation on the count value of the clock pulse after the "H" signal is input from the trigger 15, and performs cumulative subtraction operation on the count value of the clock pulse after the "L" signal is input. Therefore, the "H" signal from the trigger 15 is an addition operation instruction for cumulative addition operation, and the "L" signal is a subtraction operation instruction for cumulative subtraction operation.

[0058] An initial command value signal is given to the flip-flop 15. Whether the initial state of the flip-flop 15 is "H" or "L" is set by the initial command value signal.

[0059] The detection output of the comparator 13, that is, the signal detecting that the count value has reached the upper limit value, is given to the flip-flop 15 as described above, and is output as the detection signal INT1.

[0060] Furthermore, the detection output of the comparator 14 of each phase, that is, the signal detecting that the count value has reached the lower limit value, is given to the flip-flop 15 as described above and is output as the detection signal INT2.

[0061] The PWM signal generating unit 32 includes three comparators 16 , 17 , and 18 , a PWM circuit 108 , and an interrupt controller 109 .

[0062] The comparator 16 compares the duty cycle Udu of the U phase with the carrier C, and outputs the comparison result as a pulse. Specifically, the comparator 16 compares the value of the duty cycle Udu with the amplitude of the carrier C, and outputs an "H" signal in a range where the amplitude of the carrier C is greater than the duty cycle Udu, and outputs an "L" signal in a range where the amplitude of the carrier C is less than the duty cycle Udu.

[0063] The comparator 17 compares the duty cycle Vdu of the V phase with the carrier C, and outputs the comparison result as a pulse. Specifically, the comparator 17 compares the value of the duty cycle Vdu with the amplitude of the carrier C, and outputs an "H" signal in a section where the amplitude of the carrier C is greater than the duty cycle Vdu, and outputs an "L" signal in a section where the amplitude of the carrier C is less than the duty cycle Vdu.

[0064] The comparator 18 compares the duty cycle Wdu of the W phase with the carrier C, and outputs the comparison result as a pulse. Specifically, the comparator 18 compares the value of the duty cycle Wdu with the amplitude of the carrier C, and outputs an "H" signal in a section where the amplitude of the carrier C is greater than the duty cycle Wdu, and outputs an "L" signal in a section where the amplitude of the carrier C is less than the duty cycle Wdu.

[0065] The PWM circuit 108 outputs six PWM signals having on-off intervals corresponding to the changes in the voltage commands of each phase based on the outputs from the comparators 16, 17, and 18. The six PWM signals include a PWM signal for driving the switch element of the upper bridge arm of the U phase, a PWM signal for driving the switch element of the lower bridge arm of the U phase, a PWM signal for driving the switch element of the upper bridge arm of the V phase, a PWM signal for driving the switch element of the lower bridge arm of the V phase, a PWM signal for driving the switch element of the upper bridge arm of the W phase, and a PWM signal for driving the switch element of the lower bridge arm of the W phase. The six PWM signals are given to the gates of the switch elements of the inverter 23. Under the action of the six PWM signals, the on-off actions of the switch elements are performed. As a result, the voltages of the U phase, the V phase, and the W phase are output from the inverter 23 and applied to the motor 4. It should be noted that, as for the specific power supply method, although the triangle wave comparison method is used in Implementation 1, it is not limited to the triangle wave comparison method, and other methods such as the space vector method can be used to output the voltage of each phase.

[0066] In addition, the PWM circuit 108 generates an interrupt signal at the timing of the rise of the PWM signal, for example, and inputs it to the interrupt controller 109. The interrupt controller 109 receives the interrupt signal from the PWM circuit 108 and gives an A / D conversion instruction to the current detection unit 27. As a result, the current detection unit 27 performs A / D conversion of the detection signal Sd at the timing of the interrupt signal generation.

[0067] Next, use Figure 2 as well as Figure 3 , the principle of generating a triangular wave carrier of each phase is explained. Figure 3 This is a diagram for explaining the principle of generating a triangular wave carrier of each phase. Figure 3 The waveform of carrier C is shown in FIG.

[0068] exist Figure 2 In the embodiment, after the count start signal is input to the up-down counter 12, the up-down counter 12 starts counting the clock pulses from the clock pulse generating unit 36. As described above, an initial value is set in the up-down counter 12, and the initial value is set to 0, for example. Therefore, the up-down counter 12 starts counting from 0. In addition, the output of the trigger 15 that instructs the up-down counter 12 to perform cumulative addition and cumulative subtraction operations is set to "H" in the initial state. The initial state is the output state of the trigger 15 at the moment when the initial instruction value signal is given. Therefore, if the up-down counter 12 starts counting, the cumulative addition operation of the count value is performed. As a result of the above, if Figure 3 As shown, the output of the up-down counter 12 increases with time from the lower limit value (initial value), that is, 0, toward the upper limit value T as indicated by arrow a1.

[0069] And, if the count value reaches the upper limit value T, the comparator 13 detects it and gives the detection signal INT1 to the trigger 15. The trigger 15 is inverted based on the signal, thereby outputting "L". Therefore, the operation of the up-down counter 12 is changed from cumulative addition operation to cumulative subtraction operation, such as Figure 3 As shown, the output decreases with time from the upper limit value T toward the lower limit value 0 as shown by arrow b1.

[0070] And, if the count value reaches the lower limit value 0, the comparator 14 detects it and gives the detection signal INT2 to the trigger 15. The trigger 15 is inverted based on the signal, and outputs "H". Therefore, the action of the up-down counter 12 is changed to cumulative addition operation again, and its output increases from the lower limit value 0 to the upper limit value T as shown by the arrow c1.

[0071] By repeating such cumulative addition and cumulative subtraction operations, the output of the self-up / down counter 12 is Figure 3 The carrier C of the triangle wave shown.

[0072] It should be noted that, in Embodiment 1, although the carrier C is generated from the valley (lower limit), the carrier C may also be generated from the mountain (upper limit). In this case, the initial value of the carrier C is T (upper limit), and the initial command value is "L", which is phase-shifted by 1 / 2 cycle compared to the carrier generated from the valley.

[0073] It should be noted that, in the first embodiment, the carrier wave C is output as a triangular wave, but it may be output as a sawtooth wave or the like using an output comparator.

[0074] Figure 4 The diagram shows waveforms of a plurality of PWM signals U, V, and W, a waveform of a carrier wave C per cycle of these PWM signals, and waveforms of duty ratios Udu, Vdu, and Wdu of each phase.

[0075] like Figure 4 As shown, a plurality of PWM signals U to W are generated in such a manner that the high level and the low level are inverted at the timing consistent with the carrier C at the duty ratios Udu, Vdu, and Wdu of each phase.

[0076] The PWM signal U is a PWM signal for driving the two switching elements of the upper and lower bridge arms constituting the U phase. Figure 4 In the figure, the PWM signal U is expressed as "U-phase PWM signal (U)". When the PWM signal U is at a low level, the switch element of the lower bridge arm of the U phase is turned on (the switch element of the upper bridge arm of the U phase is turned off), and when the PWM signal U is at a high level, the switch element of the lower bridge arm of the U phase is turned off (the switch element of the upper bridge arm of the U phase is turned on). In response to the change in the level of the PWM signal U, the two switch elements constituting the upper and lower bridge arms of the U phase are turned on and off complementarily.

[0077] The PWM signal V is a PWM signal for driving the two switching elements of the upper and lower bridge arms constituting the V phase. Figure 4 In the figure, the PWM signal V is expressed as "V-phase PWM signal (V)". When the PWM signal V is at a low level, the switch element of the lower bridge arm of the V phase is turned on (the switch element of the upper bridge arm of the V phase is turned off), and when the PWM signal V is at a high level, the switch element of the lower bridge arm of the V phase is turned off (the switch element of the upper bridge arm of the V phase is turned on). In response to the change in the level of the PWM signal V, the two switch elements constituting the upper and lower bridge arms of the V phase are turned on and off complementarily.

[0078] The PWM signal W is a PWM signal for driving the two switching elements of the upper and lower bridge arms constituting the W phase. Figure 4 In the figure, the PWM signal W is expressed as "W-phase PWM signal (W)". When the PWM signal W is at a low level, the switch element of the lower bridge arm of the W phase is turned on (the switch element of the upper bridge arm of the W phase is turned off), and when the PWM signal W is at a high level, the switch element of the lower bridge arm of the W phase is turned off (the switch element of the upper bridge arm of the W phase is turned on). With respect to the change in the level of the PWM signal W, the two switch elements constituting the upper and lower bridge arms of the W phase are turned on and off complementarily.

[0079] It should be noted that the timing of the multiple PWM signals U~W changing from low level to high level is slightly later than the timing when the duty ratios Udu, Vdu, and Wdu of each phase are consistent with the carrier C. This is because a dead time is required to prevent short circuits between the upper and lower bridge arms. Figure 4 In the description, the dead time is omitted for convenience of explanation. Hereinafter, when the plurality of PWM signals U to W are not distinguished from each other, they are sometimes referred to as "PWM signals".

[0080] like Figure 4 As shown, in one cycle Tpwm of each of the plurality of PWM signals U to W, the change points (t1 to t6) of each of the plurality of PWM signals U to W are defined as follows.

[0081] The change point t1 is the timing when the lower bridge arm of the W phase changes from being connected to being disconnected (the timing when the upper bridge arm of the W phase changes from being disconnected to being connected). The change point t2 is the timing when the lower bridge arm of the V phase changes from being connected to being disconnected (the timing when the upper bridge arm of the V phase changes from being disconnected to being connected). The change point t3 is the timing when the lower bridge arm of the U phase changes from being connected to being disconnected (the timing when the upper bridge arm of the U phase changes from being disconnected to being connected). The change point t4 is the timing when the lower bridge arm of the U phase changes from being disconnected to being connected (the timing when the upper bridge arm of the U phase changes from being connected to being disconnected). The change point t5 is the timing when the lower bridge arm of the V phase changes from being disconnected to being connected (the timing when the upper bridge arm of the V phase changes from being connected to being disconnected). The change point t6 is the timing when the lower bridge arm of the W phase changes from being disconnected to being connected (the timing when the upper bridge arm of the W phase changes from being connected to being disconnected).

[0082] In the present embodiment, the period from t2 to t3 is defined as the first current detection timing Tm1 and the period from t5 to t6 is defined as the second current detection timing Tm2, ​​but the periods of the first current detection timing Tm1 and the second current detection timing Tm2 are not limited thereto.

[0083] When the inverter 23 is outputting PWM modulated three-phase AC, the current detection unit 27 can detect the current of a specific phase according to the power-on pattern of the switch elements 25U+, 25V+, and 25W+ on the upper bridge arm side. Alternatively, when the inverter 23 is outputting PWM modulated three-phase AC, the current detection unit 27 can detect the current of a specific phase according to the power-on pattern of the switch elements 25U-, 25V-, and 25W on the lower bridge arm side.

[0084] For example Figure 4As shown, during the power-on time T21, the voltage value of the voltage generated at both ends of the current detector 24 corresponds to the current value of the positive phase current Iu+. The power-on time T21 is the time from t2 to t3. The power-on time T21 corresponds to the period when the switch element of the lower bridge arm of the U phase is turned on, the switch element of the lower bridge arm of the V phase is turned off, and the switch element of the lower bridge arm of the W phase is turned off. Therefore, the current detection unit 27 can detect the current value of the positive phase current Iu+ by obtaining the detection signal Sd at the first current detection timing Tm1 during the power-on time T21.

[0085] The current detection timing adjustment unit 34 sets the first current detection timing Tm1 when a predetermined delay time td has elapsed since one phase of the PWM signal transitions to a logic level different from the other two phases (for example, the timing when the PWM signal of the U phase transitions from a high level that is the same as the V phase and the W phase to a low level: t4). At this time, the current detection timing adjustment unit 34 sets the first current detection timing Tm1 within the power-on time T21.

[0086] The delay time td is expressed by the following equation (4): Tdead is the dead time. Tring is the time required for the damped oscillation generated when the PWM signal changes to converge (damped oscillation convergence time).

[0087] td=Tdead+Tring…(4)

[0088] In addition, for example Figure 4 As shown, during the power-on time T22, the voltage value of the voltage generated at both ends of the current detector 24 corresponds to the current value of the negative phase current Iw-. The power-on time T22 is the time from t5 to t6. The power-on time T22 corresponds to the period when the switch element of the lower bridge arm of the U phase is turned on, the switch element of the lower bridge arm of the V phase is turned on, and the switch element of the lower bridge arm of the W phase is turned off. Therefore, the current detection unit 27 can detect the current value of the negative phase current Iw- by acquiring the detection signal Sd at the second current detection timing Tm2 within the power-on time T21.

[0089] The current detection timing adjustment unit 34 sets the second current detection timing Tm2 when a predetermined delay time td has elapsed since one phase of the PWM signal transitions to a logic level different from the other two phases (for example, the timing at which the PWM signal of the V phase transitions from a high level that is the same as the W phase to a low level that is the same as the U phase, so that the W phase is at a logic level different from the U phase and the V phase: t5). At this time, the current detection timing adjustment unit 34 sets the second current detection timing Tm2 within the energization time T22.

[0090] Similarly, the current detection unit 27 can also detect the current values ​​of other phase currents.

[0091] In this way, if the phase currents of two phases among the phase currents Iu, Iv, and Iw are detected and stored in sequence according to the energization pattern of the PWM signal including the three phases, the currents of the three phases can be detected in time division. Since the sum of the phase currents of the three phases is zero, the current detection unit 27 can detect the phase current of the remaining one phase as long as it can detect the phase currents of two phases among the three phases in the case of three-phase modulation.

[0092] Here, when the magnitude relationship of the duty ratios Udu, Vdu, and Wdu changes, the on-duty ratios of the first PWM signal, the second PWM signal, and the third PWM signal change. A specific example of the case where the magnitude relationship of the duty ratios Udu, Vdu, and Wdu changes will be described later. The first PWM signal is, for example, a PWM signal for driving the lower bridge arm switching element of the U phase. The second PWM signal is, for example, a PWM signal for driving the lower bridge arm switching element of the V phase. The third PWM signal is, for example, a PWM signal for driving the lower bridge arm switching element of the W phase.

[0093] The motor control device 100-1 of embodiment 1 is configured as follows: even if there is a power-on time greater than a threshold value in one of the carrier's increment count period and decrement count period due to a change in the magnitude relationship of the duty cycles Udu, Vdu, and Wdu, and there is a power-on time less than the threshold value in the other of the increment count period and the decrement count period, the on time of any one of the first PWM signal, the second PWM signal, and the third PWM signal is divided and allocated to the power-on time less than the threshold value.

[0094] Figure 5 This is the first diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention. Figure 6 This is a second diagram for explaining the operation of pulse phase adjustment according to the first embodiment of the present invention.

[0095] like Figure 5 As shown in FIG. 1 , if the on-period of the PWM signal of the U phase changes due to the change in the duty ratio Vdu, even in this case, since the on-time T22 is ensured, the current detection timing adjustment unit 34 sets the second current detection timing Tm2 in the on-time T22 during the count-down period. However, if the on-time T21 becomes shorter, for example, if it becomes shorter than the delay time td, the on-time T21 during the count-up period cannot be ensured.

[0096] The motor control device 100-1 of this embodiment is constructed as follows: even if the duty cycle Vdu and the like change and the power-on time T21 or the power-on time T22 cannot be ensured during the up-count period or the down-count period, the power-on time can be ensured by dividing the PWM signal (pulse phase adjustment).

[0097] Figure 6 The method of implementing pulse segmentation is shown in Figure 6 In the present invention, (1) the high level period of the V-phase PWM signal is divided into the first signal Sig1 and the second signal Sig2, and (2) the second signal Sig2 is moved to the leading phase side, thereby ensuring the power-on time T21.

[0098] Next, the operation of the motor control device 100 - 1 will be described. Figure 7 is a flowchart showing the operation of the motor control device 100-1. In this embodiment, at each timing of the phase ta at the bottom of the carrier C, a Figure 7 PWM counter interrupt processing is shown.

[0099] In step S10, the PWM signal generating unit 32 performs a pulse phase adjustment process. The pulse phase adjustment process will be described in detail later.

[0100] In step S11, the current detection unit 27 detects the phase currents Iu, Iv, and Iw of the U, V, and W phases. The current detection unit 27 obtains the current detection interrupt processing of the detection signal Sd (for example, the interrupt processing of performing AD conversion on the detection signal Sd) and Figure 7 The treatments shown are separated (see Figure 8 , 9 ), is executed twice within one cycle Tpwm of carrier C.

[0101] Figure 8 1 is a flowchart showing an example of the first current detection process. If the count value of the up-down counter 12 matches the value corresponding to the time when the delay time td has passed since t2, the current detection timing adjustment unit 34 sets (asserts) the setting register of the first current detection timing Tm1. If the setting register of the first current detection timing Tm1 is set, the current detection unit 27 obtains the detection signal Sd through the AD converter (step S41), and stores the obtained value of the detection signal Sd in the first acquisition register.

[0102] Fig. 9 1 is a flowchart showing an example of the second current detection process. If the count value of the up-down counter 12 matches the value corresponding to the time when the delay time td has passed since t5, the current detection timing adjustment unit 34 sets the setting register of the second current detection timing Tm2. If the setting register of the second current detection timing Tm2 is set, the current detection unit 27 obtains the detection signal Sd through the AD converter (step S51), and stores the obtained value of the detection signal Sd in the second acquisition register.

[0103] The current detection unit 27 detects the three-phase currents Iu, Iv, and Iw based on the set values ​​of the detection signal Sd stored in the first acquisition register and the second acquisition register.

[0104] The vector control unit 30 performs current control such as PI control based on the current calculation values ​​of the three-phase currents Iu, Iv, and Iw detected by the current detection unit 27 (step S13), and calculates the phase voltage commands Vu*, Vv*, and Vw* (control amounts) of each phase (step S14).

[0105] In step S15, the duty ratio setting unit 31 sets the duty ratio of each phase based on the phase voltage commands Vu*, Vv*, and Vw* of each phase calculated in step S14. In step S16, the PWM signal generating unit 32 determines which of the plurality of energizing modes is used to control the energization of the inverter 23 based on the duty ratio of each phase set by the duty ratio setting unit 31.

[0106] Next, the operation of the pulse phase adjustment process will be described. Fig. 10 is a flowchart for describing the operation of the pulse phase adjustment process.

[0107] The PWM signal generating unit 32 is provided with the following first to sixth energizing modes. The first to sixth energizing modes are provided by using the reference phase tb (refer to Figure 4 ) as the center and extending on both sides of the phase delay side and the phase advance side. For example, in the first power-on mode, the on-width is small, medium, and large in the order of U phase, V phase, and W phase (the on-width of W phase>the on-width of V phase>the on-width of U phase). In the second to sixth power-on modes, the on-width is small, large, medium, medium, medium, medium, large, and medium, small, medium, and small, respectively, in the order of U phase, V phase, and W phase.

[0108] When the first energization pattern is satisfied (step S111 , Yes), the PWM signal generating unit 32 determines whether T21≧td and T22≧td (step S112 ).

[0109] When T21≧td and T22≧td (step S112 , Yes), the PWM signal generating unit 32 sets Tm1 to T21 and sets Tm2 to T22 (step S113 ).

[0110] When T21≧td and T22≧td are not satisfied (step S112 , No), the PWM signal generating unit 32 performs the process of step S114 .

[0111] When T21 ≥ td and T22 < td (step S114, Yes), the PWM signal generation unit 32 performs the pulse division in step S115, sets Tm1 in T21, and sets Tm2 in T22 (step S116).

[0112] When it is not the case that T21 ≥ td and T22 < td (step S114, No), the PWM signal generation unit 32 determines that T21 < td and T22 ≥ td, performs the pulse division in step S117, sets Tm1 in T21, and sets Tm2 in T22 (step S118).

[0113] When the first energization mode is not satisfied (step S111, No), the PWM signal generation unit 32 performs the process in step S121.

[0114] When the second energization mode is satisfied (step S121, Yes), the PWM signal generation unit 32 determines whether T21 ≥ td and T22 ≥ td (step S122).

[0115] When T21 ≥ td and T22 ≥ td (step S122, Yes), the PWM signal generation unit 32 sets Tm1 in T21 and sets Tm2 in T22 (step S123).

[0116] When it is not the case that T21 ≥ td and T22 ≥ td (step S122, No), the PWM signal generation unit 32 performs the process in step S124.

[0117] When T21 ≥ td and T22 < td (step S124, Yes), the PWM signal generation unit 32 performs the pulse division in step S125, sets Tm1 in T21, and sets Tm2 in T22 (step S126).

[0118] When it is not the case that T21 ≥ td and T22 < td (step S124, No), the PWM signal generation unit 32 determines that T21 < td and T22 ≥ td, performs the pulse division in step S127, sets Tm1 in T21, and sets Tm2 in T22 (step S128).

[0119] When the second energization mode is not satisfied (step S121, No), the PWM signal generation unit 32 performs the process in step S131.

[0120] When the third energization mode is satisfied (step S131, Yes), the PWM signal generation unit 32 determines whether T21 ≥ td and T22 ≥ td (step S132).

[0121] When T21 ≥ td and T22 ≥ td (step S132, Yes), the PWM signal generation unit 32 sets Tm1 in T21 and sets Tm2 in T22 (step S133).

[0122] When it is not the case that T21 ≥ td and T22 ≥ td (step S132, No), the PWM signal generation unit 32 performs the process of step S134.

[0123] When T21 ≥ td and T22 < td (step S134, Yes), the PWM signal generation unit 32 performs the pulse division of step S135, sets Tm1 in T21, and sets Tm2 in T22 (step S136).

[0124] When it is not the case that T21 ≥ td and T22 < td (step S134, No), the PWM signal generation unit 32 determines that T21 < td and T22 ≥ td, performs the pulse division of step S137, sets Tm1 in T21, and sets Tm2 in T22 (step S138).

[0125] When the third energization mode is not satisfied (step S1311, No), the PWM signal generation unit 32 performs the process of step S141.

[0126] When the fourth energization mode is satisfied (step S141, Yes), the PWM signal generation unit 32 determines whether T21 ≥ td and T22 ≥ td (step S142).

[0127] When T21 ≥ td and T22 ≥ td (step S142, Yes), the PWM signal generation unit 32 sets Tm1 in T21 and sets Tm2 in T22 (step S143).

[0128] When it is not the case that T21 ≥ td and T22 ≥ td (step S142, No), the PWM signal generation unit 32 performs the process of step S144.

[0129] When T21 ≥ td and T22 < td (step S144, Yes), the PWM signal generation unit 32 performs the pulse division of step S145, sets Tm1 in T21, and sets Tm2 in T22 (step S146).

[0130] When it is not the case that T21 ≥ td and T22 < td (step S144, No), the PWM signal generation unit 32 determines that T21 < td and T22 ≥ td, performs the pulse division of step S147, sets Tm1 in T21, and sets Tm2 in T22 (step S148).

[0131] When the fourth energization mode is not satisfied (step S1411, No), the PWM signal generation unit 32 performs the process of step S151.

[0132] When the fifth energization mode is satisfied (step S151, Yes), the PWM signal generation unit 32 determines whether T21 ≥ td and T22 ≥ td (step S152).

[0133] When T21 ≥ td and T22 ≥ td (step S152, Yes), the PWM signal generation unit 32 sets Tm1 in T21 and sets Tm2 in T22 (step S153).

[0134] When it is not the case that T21 ≥ td and T22 ≥ td (step S152, No), the PWM signal generation unit 32 performs the process of step S154.

[0135] When T21 ≥ td and T22 < td (step S154, Yes), the PWM signal generation unit 32 performs the pulse division of step S155, sets Tm1 in T21, and sets Tm2 in T22 (step S156).

[0136] When it is not the case that T21 ≥ td and T22 < td (step S154, No), the PWM signal generation unit 32 determines that T21 < td and T22 ≥ td, performs the pulse division of step S157, sets Tm1 in T21, and sets Tm2 in T22 (step S158).

[0137] When the fifth energization mode is not satisfied (step S151, No), the PWM signal generation unit 32 determines that the sixth energization mode is satisfied and performs the process of step S162.

[0138] In step S162, the PWM signal generation unit 32 determines whether T21 ≥ td and T22 ≥ td.

[0139] When T21 ≥ td and T22 ≥ td (step S162, Yes), the PWM signal generation unit 32 sets Tm1 in T21 and sets Tm2 in T22 (step S163).

[0140] When it is not the case that T21 ≥ td and T22 ≥ td (step S162, No), the PWM signal generation unit 32 performs the process of step S164.

[0141] When T21 ≥ td and T22 < td (step S164, Yes), the PWM signal generation unit 32 performs the pulse division of step S165, sets Tm1 in T21, and sets Tm2 in T22 (step S166).

[0142] When it is not the case that T21 ≥ td and T22 < td (step S164, No), the PWM signal generation unit 32 determines that T21 < td and T22 ≥ td, performs pulse division in step S167, sets Tm1 in T21, and sets Tm2 in T22 (step S168).

[0143] It should be noted that the PWM signal generation unit 32 of the present embodiment uses a common carrier C for each phase to generate the PWM signals of each phase. That is, the present embodiment is not a method of generating carriers C corresponding to each phase separately. Moreover, in the present embodiment, since a triangular wave symmetric about the phase tb is set as the carrier C, the circuit configuration for generating the waveforms of the PWM signals of each phase can be simplified. For the up-down counter 12, it counts down until the phase ta, counts up from the phase ta to the phase tb, and counts down from the phase tb. In this way, the count-up period and the count-down period are repeated.

[0144] It should be noted that in the present embodiment, the case where the first PWM signal is the PWM signal of the U phase, the second PWM signal is the PWM signal of the V phase, and the third PWM signal is the PWM signal of the W phase has been described, but the types of the first PWM signal, the second PWM signal, and the third PWM signal are not limited thereto.

[0145] As described above, the motor control device 100-1 of Embodiment 1 includes: an inverter that drives a motor based on the first PWM signal, the second PWM signal, and the third PWM signal; a current detector that outputs a detection signal corresponding to the current value of the current flowing through the DC side of the inverter; a current detection unit that detects the phase currents of each phase flowing through the motor by obtaining the detection signal; a duty ratio setting unit that sets the duty ratios of the first PWM signal, the second PWM signal, and the third PWM signal based on the detection values of the phase currents of each phase; and a PWM signal generation unit that compares the set value of the duty ratio with the level of a carrier whose level increases and decreases periodically to generate the first PWM signal, the second PWM signal, and the third PWM signal. When there is a conduction time equal to or greater than a threshold value in one of the count-up period and the count-down period of the carrier, and there is a conduction time less than the threshold value in the other of the count-up period and the count-down period, the PWM signal generation unit divides the on-time of any one of the first PWM signal, the second PWM signal, and the third PWM signal, and distributes the divided on-time to the conduction time less than the threshold value.

[0146] In this way, by dividing the on-time of any one of the first PWM signal, the second PWM signal, and the third PWM signal and allocating the divided on-time to the on-time less than the threshold, the on-times T11 and T21 can be ensured, making it possible to detect the phase current with high precision.

[0147] In addition, the energization time T11 for detecting the phase current of one of the two phases and the energization time T21 for detecting the phase current of the other phase are divided into the first half cycle period and the second half half cycle period of one cycle of the carrier C. Therefore, compared with the case where there are two acquisition timings during the half cycle period of the carrier C, the time interval between the acquisition timing A and the acquisition timing B (the time interval of the interrupt processing) can be left with a margin. With this margin, even if a CPU with low processing power is used, it is possible to suppress the acquisition timing delay.

[0148] The motor control device, the motor system, and the motor control method are described above by using the embodiments, but the present invention is not limited to the above embodiments. Various modifications and improvements such as combination and replacement with part or all of other embodiments are possible within the scope of the present invention.

[0149] This international application claims the benefit of priority based on Japanese Patent Application No. 2019-057289 filed on March 25, 2019, and the entire contents of Japanese Patent Application No. 2019-057289 are cited in this international application.

[0150] Description of Reference Numerals

[0151] 1-1 Motor system, 4 Motor, 12 Up / down counter, 13 Comparator, 14 Comparator, 15 Flip-flop, 16 Comparator, 17 Comparator, 18 Comparator, 21 DC power supply, 22a Positive bus, 22b Negative bus, 23 Inverter, 24 Current detector, 25U Switching element, 25V Switching element, 25W Switching element, 27 Current detection unit, 27A Current detection unit, 30 Vector control unit, 31 Duty ratio setting unit, 32 PWM signal generation unit, 33 Drive circuit, 34 Current detection timing adjustment unit, 35 Power-on pattern generation unit, 36 Clock pulse generation unit, 37 Carrier generation unit, 100-1 Motor control device, 108 PWM circuit, 109 Interrupt controller

Claims

1. A motor control device, comprising: an inverter unit that drives the motor based on the first PWM signal, the second PWM signal, and the third PWM signal; a current detector that outputs a detection signal corresponding to a current value of a current flowing through the DC side of the inverter section; a current detection unit that detects a phase current flowing through each phase of the motor by acquiring the detection signal; a duty ratio setting unit that sets the duty ratios of the first PWM signal, the second PWM signal, and the third PWM signal based on the detected values ​​of the phase currents of the respective phases; as well as a PWM signal generating unit that generates the first PWM signal, the second PWM signal, and the third PWM signal by comparing the set value of the duty ratio with the level of a carrier wave whose level increases and decreases periodically, The PWM signal generating unit divides the on-time of any one of the first PWM signal, the second PWM signal, and the third PWM signal, and allocates the divided on-time to the second PWM signal that is smaller than the threshold value, when there is a first on-time that is greater than a threshold value in one of an up-count period and a down-count period of the carrier, and there is a second on-time that is smaller than the threshold value in the other of the up-count period and the down-count period. The on-time of any one of the PWM signals is adjusted so that the second energization time increases in accordance with the divided on-time, and the on-times of the remaining two PWM signals are not adjusted.

2. A motor system comprising: The motor control device according to claim 1; and The above motor.

3. A motor control method, which is performed in a motor control device for controlling a motor, the motor control method comprising: an output step of outputting a detection signal corresponding to a current value of a current flowing through a DC side of an inverter section that drives the motor based on the first PWM signal, the second PWM signal, and the third PWM signal, using a current detector; a detection step of detecting the phase current flowing through each phase of the motor by acquiring the detection signal; a setting step of setting the duty ratios of the first PWM signal, the second PWM signal, and the third PWM signal based on the detected values ​​of the phase currents of the phases; A generating step, which generates the first PWM signal, the second PWM signal and the third PWM signal by comparing the set value of the duty ratio with the level of the carrier whose level increases and decreases periodically; as well as an allocating step, in which, when a first on-time greater than a threshold value exists in one of an up-count period and a down-count period of the carrier and a second on-time less than the threshold value exists in the other of the up-count period and the down-count period, the on-time of any one of the first PWM signal, the second PWM signal and the third PWM signal is divided, and the divided on-time is allocated to the second on-time less than the threshold value, The on-time of any one of the PWM signals is adjusted so that the second energization time increases in accordance with the divided on-time, and the on-times of the remaining two PWM signals are not adjusted.

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