Semiconductor device

Abstract

The present disclosure relates to a semiconductor device. The semiconductor device performs software lockstep. The semiconductor device includes a first circuit group including a first intellectual property (IP) to be operated in a first address space, a first bus, and a first memory; a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory; a third bus connectable to a third memory; and a transfer control circuit coupled with the first bus to the third bus. When software lockstep is performed, the second circuit group converts an access address from the second IP to the second memory so that an address allocated to the second memory in the second address space is the same as an address allocated to the first memory in the first address space.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] The semiconductor devices installed in autonomous vehicles need to be highly reliable. However, due to cosmic rays or physical degradation, these devices may perform unintentional operations. This means that failures can occur within the semiconductor devices. Since it is impossible to prevent all failures from occurring in semiconductor devices, it is necessary to detect any failures that have occurred.

[0003] One technique used to detect faults occurring in semiconductor devices is called lockstepping. In this technique, two circuit blocks that perform the same function are used, and each circuit block operates at a specific timing. After processing both circuit blocks, the results are compared.

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2020-4108

[0006] Patent Document 1 discloses a semiconductor device for performing Software Lockstep (SWLS). The semiconductor device disclosed in Patent Document 1 includes CPU 10, CPU 20, CPU 230, and memory 260. During SWLS operation, each of CPU 10 and CPU 20 reads a program and data for SWLS stored in memory. Each of CPU 10 and CPU 20 executes the program for SWLS to write the execution result into memory 260. CPU 230 reads the execution results of CPU 10 and CPU 20 from memory 260 and compares them. Summary of the Invention

[0007] The semiconductor device for performing SWLS disclosed in Patent Document 1 allows CPU 10 and CPU 20 to perform different processes. Therefore, when SWLS operations and non-SWLS operations are mixed, the semiconductor device performing SWLS has the advantage of being able to effectively utilize hardware resources (CPU 10 and CPU 20).

[0008] However, during SWLS operation, each of CPUs 10 and 20 reads the SWLS program and data from memory 260 and writes the execution results into memory 260. Furthermore, CPU 230 reads the execution results of CPU 10 and CPU 20 from memory 260. That is, during SWLS operation, the following problem exists: the bus bandwidth required to access memory 260 increases.

[0009] Other objects and new features will be apparent from the description and accompanying drawings in this specification.

[0010] A semiconductor device according to one embodiment performs a software lockstep (SWLS). The semiconductor device includes: a first circuit group including a first intellectual property (IP) to be operated in a first address space, a first bus, and a first memory coupled to the first IP via the first bus; a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory coupled to the second IP via the second bus; a third bus connectable to a third memory; and transfer control circuitry coupled to the first bus and the third bus, the transfer control circuitry including a comparator. When the SWLS is executed, the transfer control circuitry transfers a program for the SWLS from the third memory to the first memory and the second memory. The first IP executes a program for the SWLS stored in the first memory to store a first execution result in the first memory. The second IP executes a program for the SWLS stored in the second memory to store a second execution result in the second memory. The transfer control circuitry reads the first execution result and the second execution result from the first memory and the second memory, and uses the comparator to compare the first execution result with the second execution result. The second circuit group translates the access address from the second IP to the second memory, such that the address allocated to the second memory in the second address space is the same as the address allocated to the first memory in the first address space.

[0011] According to one embodiment, the bus bandwidth required to access memory during SWLS operation can be reduced. Attached Figure Description

[0012] Figure 1 This is a block diagram illustrating an example configuration of a semiconductor device according to the first embodiment.

[0013] Figure 2 This is a flowchart illustrating an example of software lockstep (SWLS) operation of a semiconductor device according to a first embodiment.

[0014] Figure 3 This is a flowchart illustrating an example of SWLS operation of a modified semiconductor device according to the first embodiment.

[0015] Figure 4 This is a block diagram illustrating an example configuration of a semiconductor device according to a second embodiment.

[0016] Figure 5 This is a block diagram illustrating an example configuration of a semiconductor device according to a third embodiment. Detailed Implementation

[0017] In the following description, embodiments will be illustrated in detail with reference to the accompanying drawings. In the specification and drawings, identical or corresponding components are denoted by the same reference numerals, and repeated descriptions are omitted. In the drawings, configurations may be omitted or simplified for ease of description.

[0018] First Embodiment

[0019] Figure 1 This is a block diagram illustrating an example configuration of the semiconductor device 1 according to the first embodiment. Figure 1 As shown, the semiconductor device 1 includes a central processing unit (CPU) 11, a first circuit group 12, a second circuit group 13, a third bus 14, and a transmission control circuit 15. The first circuit group 12 includes a first intellectual property (IP) 121, a first bus 122, and a first memory 123. The second circuit group 13 includes a second IP 131, a second bus 132, and a second memory 133.

[0020] In the first embodiment, the first circuit group 12 and the second circuit group 13 perform Software Lockstep (SWLS). In SWLS, the same program for SWLS is executed by the first IP 121 and the second IP 131, and the execution results of the first IP 121 and the second IP 131 are compared. That is, SWLS refers to a process in which a fault occurring in a semiconductor device is detected by executing a program with the same result by multiple IPs and confirming that the execution results of the multiple IPs are the same.

[0021] Additionally, in the first embodiment, operations performed when the first circuit group 12 and the second circuit group 13 are executing a series of processes related to SWLS are referred to as SWLS operations. On the other hand, operations performed when the first circuit group 12 and the second circuit group 13 are not executing a series of processes related to SWLS are referred to as non-SWLS operations.

[0022] The first memory 123 and the second memory 133 are memories such as, for example, static random access memory (SRAM). In the first embodiment, the first memory 123 and the second memory 133 are described as being provided in a configuration independent of the first IP 121 and the second IP 131, respectively, but this disclosure is not limited thereto. That is, the first memory 123 and the second memory 133 may be built into the first IP 121 and the second IP 131, respectively.

[0023] Furthermore, semiconductor device 1 is connected to a third memory 2. Specifically, third memory 2 is connected to a third bus 14 in semiconductor device 1. Third memory 2 is a memory such as, for example, double data rate synchronous dynamic random access memory (DDR-SDRAM). In the first embodiment, third memory 2 is described as being external to semiconductor device 1, but this disclosure is not limited thereto. That is, third memory 2 may be internal to semiconductor device 1.

[0024] CPU 11 is connected to first IP 121, second IP 131, second bus 132, and transmission control circuitry 15. During SWLS operation, CPU 11 controls the operation of first IP 121, second IP 131, and transmission control circuitry 15.

[0025] CPU 11 performs the following settings to cause the transfer control circuit 15 to transfer program and data for SWLS from third memory 2 to first memory 123 and second memory 133. For example, this is performed by storing the address of third memory 2 in a register in the transfer control circuit 15 for storing the transfer source address, and storing the addresses of first memory 123 and second memory 133 in a register in the transfer control circuit 15 for storing the transfer destination address. Then, CPU 11 sends an activation request to the transfer control circuit 15 to cause the transfer control circuit 15 to begin transferring program and data for SWLS.

[0026] Furthermore, after the CPU 11 detects that the transmission control circuit 15 has completed the transmission of the program and data for SWLS, the CPU 11 sends an activation request to each of the first IP 121 and the second IP 131. The activation request is used to cause each of the first IP 121 and the second IP 131 to execute the program and data for SWLS. The execution result of the program for SWLS executed by the first IP 121 is stored in the first memory 123 as a first execution result. The execution result of the program for SWLS executed by the second IP 131 is stored in the second memory 133 as a second execution result.

[0027] Furthermore, after the CPU 11 detects that the first IP 121 and the second IP 131 have completed the execution of the program for SWLS, the CPU 11 sends an activation signal to the transmission control circuit 15. The activation signal is used to enable the transmission control circuit 15 to read the first execution result stored in the first memory 123 and the second execution result stored in the second memory 133 and compare them.

[0028] Additionally, the CPU 11 sets a first or second value in the operation mode setting register 134 included in the second bus 132, the first value indicating that SWLS is to be executed, and the second value indicating that SWLS will not be executed. Details of the operation mode setting register 134 will be described later.

[0029] The first IP address 121 is connected to the CPU 11 and the first bus 122. The first bus 122 is connected to the first memory 123. The first IP address 121 operates in a first address space. In the first address space, a predetermined address is assigned to the first memory 123. The first IP address 121 uses the address assigned to the first memory 123 in the first address space to access the first memory 123.

[0030] Furthermore, the first IP 121, under the control of the CPU 11, reads and executes the SWLS-specific program stored in the first memory 123. At this time, the first IP 121 reads the SWLS-specific data stored in the first memory 123 and, according to the address written in the SWLS-specific program, writes the data generated by executing the SWLS-specific program into the first memory 123. The data generated by executing the SWLS-specific program includes the execution result of the SWLS-specific program by the first IP 121, i.e., the first execution result.

[0031] The second IP 131 is connected to the CPU 11 and the second bus 132. Furthermore, the second bus 132 is connected to the second memory 133. The second IP 131 operates in a second address space. In the second address space, predetermined addresses are assigned to the second memory 133. The second IP 131 uses the addresses assigned to the second memory 133 in the second address space to access the second memory 133.

[0032] Furthermore, the second IP 131, under the control of the CPU 11, reads and executes the SWLS-specific program stored in the second memory 133. At this time, the second IP 131 reads the SWLS-specific data stored in the second memory 133 and, according to the address written in the SWLS-specific program, writes the data generated by executing the SWLS-specific program into the second memory 123. The data generated by executing the SWLS-specific program includes the execution result of the SWLS-specific program by the second IP 131, i.e., the second execution result.

[0033] The second bus 132 also includes an operation mode setting register 134 and an address translation circuit 135. A first value indicating whether SWLS should be executed or a second value indicating whether SWLS should not be executed is set in the operation mode setting register 134. As described above, the first and second values ​​are set by the CPU 11.

[0034] Address translation circuit 135 determines whether to translate the access address from second IP 131 to second memory 133 based on the value set in operation mode setting register 134. More specifically, when the first value is set in operation mode setting register 134, address translation circuit 135 translates the access address from second IP 131 to second memory 133, such that the address allocated to second memory 133 in the second address space is the same as the address allocated to first memory 123 in the first address space. On the other hand, when the second value is set in operation mode setting register 134, address translation circuit 135 does not translate the access address from second IP 131 to second memory 133.

[0035] A program for SWLS is written for execution by the first IP 121. That is, the address used for data access written in the SWLS-specific program corresponds to the address allocated to the first memory 123 in the first address space. During SWLS operation, the first IP 121 needs to access the first memory 123 based on the address written in the SWLS-specific program, and the second IP 131 needs to access the second memory 133. However, during SWLS operation, since the first IP 121 and the second IP 131 execute the same SWLS-specific program written for the first IP 121, the second IP 131 cannot access the second memory 133 based on the address written in the SWLS-specific program.

[0036] In the first embodiment, when the first circuit group 12 and the second circuit group 13 execute SWLS, the CPU 11 sets a first value indicating that SWLS to be executed in the operation mode setting register 134. When the first value is set in the operation mode setting register 134, the address translation circuit 135 translates the access address from the second IP 131 to the second memory 133, such that the address allocated to the second memory 133 in the second address space is the same as the address allocated to the first memory 123 in the first address space. As a result, even if the second IP 131 executes a program for SWLS written for the first IP 121, the second IP 131 can properly access the second memory 133.

[0037] As described above, in SWLS operation, the second circuit group 13 translates the access address from the second IP 131 to the second memory 133, such that the address allocated to the second memory 133 in the second address space is the same as the address allocated to the first memory 123 in the first address space. Therefore, even if the same program for SWLS is executed, the first circuit group 12 and the second circuit group 13 can properly execute SWLS.

[0038] On the other hand, in non-SWLS operation, the second circuit group 13 does not translate the access address from the second IP 131 to the second memory 133. Therefore, the second IP 131 in non-SWLS operation can properly access the second memory 133. That is, even when SWLS operation and non-SWLS operation are mixed, the semiconductor device 1 will operate appropriately.

[0039] like Figure 1 As shown, semiconductor device 1 includes paths connecting the first bus 122 and the second bus 132 without passing through transmission control circuitry 15. Therefore, in non-SWLS operation, using these paths, the first IP 121 can access the second memory 133 in addition to accessing the first memory 123, and the second IP 131 can access the first memory 123 in addition to accessing the second memory 133. Additionally, semiconductor device 1 includes paths connecting the first bus 122 and the third bus 14 without passing through transmission control circuitry 15, and paths connecting the second bus 132 and the third bus 14 without passing through transmission control circuitry 15. Therefore, in non-SWLS operation, each of the first IP 121 and the second IP 131 can use these paths to access the third memory 2.

[0040] The transmission control circuit 15 is connected to the CPU 11, the first bus 122, the second bus 132, and the third bus 14. During SWLS operation, the transmission control circuit 15 transmits the program and data for SWLS, reads the first execution result and the second execution result, and compares them.

[0041] The transmission control circuit 15 transmits programs and data for SWLS based on the control of the CPU 11. The transmission control circuit 15 reads the programs and data for SWLS stored in the third memory 2 via the third bus 14. The transmission control circuit 15 transmits the read programs and data for SWLS to the first memory 123 and the second memory 133 via the first bus 122 and the second bus 132. In this case, considering that during SWLS operation, the access address is translated from the second IP 131 to the second memory 123, the transmission control circuit 15 transmits programs and data for SWLS such that the arrangement to the first memory 123 is the same as the arrangement to the second memory.

[0042] Furthermore, the transmission control circuit 15 reads the first execution result stored in the first memory 123 and the second execution result stored in the second memory 133 based on the control of the CPU 11. At this time, the first execution result and the second execution result are read via the first bus 122 and the second bus 132. The transmission control circuit 15 includes a comparator 151 and uses the comparator 151 to compare the first execution result and the second execution result.

[0043] Subsequently, the transmission control circuit 15 stores the first execution result in the third memory 2 via the third bus 14. Furthermore, when the first execution result and the second execution result are inconsistent, the transmission control circuit 15 transmits an interrupt signal to notify the CPU 11 that the first execution result and the second execution result are inconsistent.

[0044] Next, the SWLS operation of the semiconductor device 1 according to the first embodiment will be described. Figure 2 This is a flowchart illustrating an example of SWLS operation of semiconductor device 1 according to the first embodiment. Figure 2 The flowchart includes four processing steps S201-S204. First, in step S201, the process of setting the address for the SWLS operation is performed. In the address setting process, CPU 11 sets a first value indicating that SWLS is to be executed in the operation mode setting register 134. By setting the first value, a translation of the access address from the second IP 131 to the second memory 133 is performed.

[0045] Next, in step S202, the process of transferring the program and data for SWLS is performed. During this process, the CPU 11 sets the transfer control circuit 15 to transfer the program and data for SWLS from the third memory 2 to the first memory 123 and the second memory 133, and then activates the transfer control circuit 15 to begin the transfer. The activated transfer control circuit 15 reads the program and data for SWLS stored in the third memory 2 via the third bus 14. The transfer control circuit 15 then transfers the read program and data for SWLS to the first memory 123 and the second memory 133 via the first bus 122 and the second bus 132.

[0046] At this time, the transmission control circuit 15 transmits the program and data for SWLS to the first memory 123 and the second memory 133 in a single read process. That is, the bus bandwidth required to access the third memory 3 can be reduced compared to the case where transmissions from the third memory 2 to the first memory 123 and from the third memory 2 to the second memory 133 are performed separately. Additionally, in the first embodiment, since the address translation circuit 135 performs the access address translation, the first IP 121 and the second IP 131 can execute the same program for SWLS. As a result, the transmission of the program for SWLS can be performed in a single transmission process.

[0047] Next, in step S203, the following process is performed: Execute the program for SWLS. During the execution of the program for SWLS, CPU 11 detects that the transmission of the program and data for SWLS has been completed via the transmission control circuit 15. For example, the transmission control circuit 15 sends a signal to CPU 11 to indicate that the transmission is complete, and CPU 11 receives the signal, thereby detecting that the transmission processing of the transmission control circuit 15 has been completed. After CPU 11 detects that the transmission control circuit 15 has completed the transmission of the program and data for SWLS, CPU 11 activates the first IP 121 and the second IP 131 to cause the first IP 121 and the second IP 131 to execute the program for SWLS.

[0048] The activated first IP address 121 reads and executes the SWLS-specific program stored in the first memory 123. At this time, the first IP address 121 accesses the first memory 123 using the address allocated to the first memory 123 in the first address space. The first IP address 121 stores the execution result of the SWLS-specific program in the first memory 123 as a first execution result.

[0049] Furthermore, the activated second IP 131 reads and executes the SWLS-specific program stored in the second memory 133. At this time, the second IP 131 accesses the second memory 133 using the address allocated to the second memory 133 in the second address space. The second IP 131 stores the execution result of the SWLS-specific program in the second memory 133 as a second execution result.

[0050] The first address space in which the first IP 121 operates is different from the second address space in which the second IP 131 operates. That is, the address allocated to the first memory 123 in the first address space is different from the address allocated to the second memory 133 in the second address space. In SWLS operation, the first IP 121 and the second IP 131 execute the same program for SWLS. Therefore, in SWLS operation, the second circuit group 13 translates the access address from the second IP 131 to the second memory 133, such that the address allocated to the second memory 133 in the second address space is the same as the address allocated to the first memory 123 in the first address space.

[0051] Specifically, the address translation circuit 135 confirms the value set in the operation mode setting register 134. During SWLS operation, since a first value indicating that SWLS is to be executed is set in step S201, the address translation circuit 135 translates the access address from the second IP 131 to the second memory 133, making the address allocated to the second memory 133 in the second address space the same as the address allocated to the first memory 123 in the first address space. As a result, even if the second IP 131 executes a SWLS-specific program written for the first IP 121, the second IP 131 can still appropriately implement the SWLS operation.

[0052] Finally, in step S204, a process for comparing the execution results is performed. In this process, the CPU 11 detects that the first IP 121 and the second IP 131 have completed the execution of the program for SWLS. For example, each of the first IP 121 and the second IP 131 sends a signal to the CPU 11 to notify that the execution of the program for SWLS has been completed, and the CPU 11 receives signals from both the first IP 121 and the second IP 131, thereby detecting that the first IP 121 and the second IP 131 have completed the execution of the program for SWLS. After the CPU 11 detects that the first IP 121 and the second IP 131 have completed the execution of the program for SWLS, the CPU 11 activates the transmission control circuit 15, causing the transmission control circuit 15 to read the first execution result stored in the first memory 123 and the second execution result stored in the second memory 133 and compare them.

[0053] The activated transmission control circuit 15 reads a first execution result from the first memory 123 via the first bus 122. Furthermore, the transmission control circuit 15 reads a second execution result from the second memory 133 via the second bus 132. The transmission control circuit 15 uses a comparator 151 to compare the first and second execution results. The transmission control circuit 15 stores the first execution result in the third memory 2 via the third bus 14. When comparing two execution results, the transmission control circuit 15 stores only one execution result in the third memory, thus not increasing the bus bandwidth required to access the third memory 2. Additionally, when the first and second execution results are inconsistent, the transmission control circuit 15 sends an interrupt signal to the CPU 11 to notify that the first and second execution results are inconsistent.

[0054] When step S204 is completed, the series of SWLS operations are finished. Afterwards, when semiconductor device 1 switches from SWLS operation to non-SWLS operation, CPU 11 sets a second value indicating that SWLS is not executed in operation mode setting register 134.

[0055] As described above, according to the first embodiment, since the transmission control circuit 15 can transmit programs and data for SWLS by performing a single read process from the third memory 2, in other words, by performing a single transmission process from the third memory 2 to the first memory 123 and the second memory 133, the bus bandwidth required to access the third memory 2 can be reduced.

[0056] Furthermore, in the first embodiment, when SWLS is executed, the second circuit group 13 translates the access address from the second IP 131 to the second memory 133, such that the address allocated to the second memory 133 in the second address space is the same as the address allocated to the first memory 123 in the first address space. As a result, even if the second IP 131 executes a program written for SWLS for the first IP 121, the second IP 131 can still properly access the second memory 133.

[0057] exist Figure 1 In the diagram, the first circuit group 12 and the second circuit group 13 are shown to have the same configuration, which includes IP, bus, and memory. However, the first circuit group 12 and the second circuit group 13 do not necessarily have to have the same configuration. That is, the first circuit group 12 and the second circuit group 13 can have asymmetrical configurations as long as they can perform SWLS.

[0058] exist Figure 1 In the diagram, each of the first circuit group 12 and the second circuit group 13 is shown as having a configuration with one IP address, but each of the first circuit group 12 and the second circuit group 13 may have multiple IP addresses. In this case, since SWLS operation and non-SWLS operation can be mixed for each IP address, the address translation circuit 135 can translate the access address for each IP address.

[0059] exist Figure 1 In the diagram, the operation mode setting register 134 and the address translation circuit 135 are shown as a configuration included in the second bus 132, but this disclosure is not limited thereto. That is, the operation mode setting register 134 and the address translation circuit 135 only need to be included in the second circuit group 13, and do not necessarily need to be included in the second bus 132. For example, the second IP 131 may include the operation mode setting register 134 and the address translation circuit 135.

[0060] exist Figure 1In the diagram, the operation mode setting register 134 and address translation circuit 135 are shown as a configuration included in the second bus 132 on the second circuit group 13 side, but they can be included in the first bus 122 on the first circuit group 12 side. In this case, the program for SWLS can be written to correspond to the address allocated to the second memory 133 in the second address space.

[0061] exist Figure 2 In this context, although the process of setting addresses for SWLS operations is described as being performed before the process of transmitting SWLS programs and data, the order of the process of setting addresses for SWLS operations and the process of transmitting SWLS programs and data can be interchanged.

[0062] CPU 11 can be configured to be accessed by the second memory 133 during both SWLS and non-SWLS operations. In this case, regardless of the value set in the operation mode setting register 134, the address translation circuit 135 will not translate the access address from CPU 11 to the second memory 133.

[0063] Modifications to the first embodiment

[0064] Next, modifications to the first embodiment will be described. In the first embodiment, although the first IP 121 and the second IP 131 are described as executing the same program for SWLS, the first IP 121 and the second IP 131 may also execute different programs for SWLS. In the modifications to the first embodiment, the configuration and operation of the semiconductor device 1 when different programs for SWLS are executed will be described.

[0065] First IP 121 executes a first program for SWLS. The first program for SWLS is written to correspond to the address allocated to first memory 123 in the first address space. Second IP 131 executes a second program for SWLS. The second program for SWLS is written to correspond to the address allocated to second memory 133 in the second address space. Although the first program for SWLS and the second program for SWLS differ in the descriptions relating to SWLS below, the execution result of the first program for SWLS and the execution result of the second program for SWLS are the same: the address used to access first memory 123 and the address used to access second memory 133.

[0066] Furthermore, since the second IP 131 executes the second program of the SWLS to be written by the second IP 131, the operation mode setting register 134 and the address translation circuit 135 are not required. Therefore, the modified semiconductor device 1 according to the first embodiment does not include the operation mode setting register 134 and the address translation circuit 135. That is, in the modification of the first embodiment, during SWLS operation, the second circuit group 13 does not translate the access address from the second IP 131 to the second memory 133.

[0067] Figure 3 This is a flowchart illustrating an example of SWLS operation of a modified semiconductor device 1 according to the first embodiment. In the processes of steps S202a and S202b, Figure 3 Flowcharts and Figure 2 The flowcharts are different. Additionally, in Figures 2 to 3 In the flowchart, steps S203 and S204 are processed in the same way.

[0068] exist Figure 3 In step S202a, the process of transmitting data for SWLS is performed. During this process, the transmission control circuit 15 reads the data for SWLS stored in the third memory 2 via the third bus 14. The transmission control circuit 15 then transmits the read data for SWLS to the first memory 123 and the second memory 133 via the first bus 122 and the second bus 132. Figure 3 Step S202 processing and Figure 2 The difference in step S202 is that only the data for SWLS is transmitted, not the program for SWLS.

[0069] exist Figure 3 In step S202b, the process of transferring the program for SWLS is performed. In this process, the transfer control circuit 15 reads the first program for SWLS stored in the third memory 2 via the third bus 14, and transfers the read first program for SWLS to the first memory 123 via the first bus 122. Additionally, the transfer control circuit 15 reads the second program for SWLS stored in the third memory 2 via the third bus 14, and transfers the read second program for SWLS to the second memory 133 via the first bus 132.

[0070] According to the modification of the first embodiment, since the transmission control circuit 15 can transfer data for SWLS from the third memory 2 to the first memory 123 and the second memory 133 in one transmission process, the bus bandwidth required to access the third memory 2 can be reduced.

[0071] In the above description, the transmission control circuit 15 executes the transmission processing of the first program and the second program for SWLS in step S202b, but the first IP 121 and the second IP 131 can also perform transmission processing. In this case, after the CPU 11 detects that the transmission control circuit 15 has completed the transmission of data for SWLS, the CPU 11 activates the first IP 121 to start transmitting the first program for SWLS, and activates the second IP 131 to start transmitting the second program for SWLS.

[0072] The activated first IP 121 transfers the first program for SWLS from the third memory 2 to the first memory 123 via the path connecting the first bus 122 and the third bus 14. Furthermore, the activated second IP 131 transfers the second program for SWLS from the third memory 2 to the second memory 133 via the path connecting the second bus 132 and the third bus 14.

[0073] Second Embodiment

[0074] Next, a second embodiment will be described. The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment in that it can communicate with each other between the first IP and the transmission control circuit, and between the second IP and the transmission control circuit. Figure 4 This is a block diagram illustrating an example configuration of the semiconductor device 1a according to the second embodiment. Figure 4 As shown, Figure 1 The first circuit group 12, the first IP 121, the second circuit group 13, the second IP 131 and the transmission control circuit 15 are respectively changed to the first circuit group 12a, the first IP 121a, the second circuit group 13a, the second IP 131a and the transmission control circuit 15a.

[0075] Transmission control circuit 15a is connected to first IP 121a and second IP 131a. After transmission control circuit 15a has completed the transmission processing of program and data for SWLS, transmission control circuit 15a transmits an activation request to first IP 121a to execute the SWLS program, and transmits an activation request to second IP 131a to execute the SWLS program. These activation requests are executed, for example, by transmitting a signal from transmission control circuit 15a to first IP 121a to indicate that transmission processing is complete, and transmitting a signal from transmission control circuit 15a to second IP 131a to indicate that transmission processing is complete. Upon receiving the activation request, each of first IP 121a and second IP 131a executes the SWLS program.

[0076] After the first IP 121a and the second IP 131a have completed the execution of the program for SWLS, each of the first IP 121a and the second IP 131a sends an activation request to the transmission control circuit 15a to read the first execution result stored in the first memory 123 and the second execution result stored in the second memory 133 and compare them. These activation requests are executed, for example, by sending a signal from the first IP 121a to the transmission control circuit 15a to indicate that the execution process is complete, and by sending a signal from the second IP 131a to the transmission control circuit 15a to indicate that the execution process is complete. Upon receiving the activation request from the first IP 121a and the activation from the second IP 131a, the transmission control circuit 15a compares the first execution result with the second execution result.

[0077] As described above, according to the second embodiment, without using the CPU 11, the transmission control circuit 15a can transmit an activation request for executing a program for SWLS to the first IP 121a, and an activation request for executing a program for SWLS to the second IP 131a. Furthermore, without using the CPU 11, each of the first IP 121a and the second IP 131a can transmit an activation request for reading and comparing a first execution result to the transmission control circuit 15a. As a result, compared to the semiconductor device 1 according to the first embodiment, the semiconductor device 1a according to the second embodiment can significantly reduce the burden of interrupt handling on the CPU 11. Specifically, as the number of IPs included in the first circuit group 12a and the second circuit group 13a increases, the effect of reducing the load on the CPU 11 becomes more significant.

[0078] The activation request may include processing for register settings of the transmission control circuit 15a, the first IP 121a, or the second IP 131a. Additionally, even if the transmission control circuit 15a, the first IP 121a, and the second IP 131a receive the activation request while performing other processing, the activation request may be queued and the queued activation request may be processed later.

[0079] Third Embodiment

[0080] Next, a third embodiment will be described. The semiconductor device according to the third embodiment differs from the semiconductor devices according to the first and second embodiments in that the transmission control circuit includes a protection circuit. Figure 5This is a block diagram illustrating an example configuration of the semiconductor device 1b according to a third embodiment. Figure 5 As shown, semiconductor device 1b includes protection circuitry 16 on the path connecting the first bus 122 and the second bus 132.

[0081] The first IP 121 accesses the second memory 133 included in the second circuit group 13 via a path connecting the first bus 122 and the second bus 132. Additionally, the second IP 131 accesses the first memory 123 included in the first circuit group 12 via a path connecting the first bus 122 and the second bus 132. Therefore, the first IP 121 and the second IP 131 can increase the usable memory capacity.

[0082] Protection circuit 16 controls the permission or prohibition of the following accesses: access from first IP 121 to second memory 133 and access from second IP 131 to first memory 123. Specifically, when SWLS is executed, protection circuit 16 prohibits first IP 121 from accessing second memory 133 via the path connecting first bus 122 and second bus 132, and prohibits second IP 131 from accessing first memory 123 via the path connecting first bus 122 and second bus 132. On the other hand, when SWLS is not executed, protection circuit 16 allows first IP 121 to access second memory 133 via the path connecting first bus 122 and second bus 132, and allows second IP 131 to access first memory via the path connecting first bus 122 and second bus 132.

[0083] As described above, according to the third embodiment, the protection circuit 16 monitors access from one circuit group to another, such as access from the first IP 121 to the second memory 133 and access from the second IP 131 to the first memory 123, and prohibits such access during SWLS operation. Thus, for example, the problem of undetected failures can be avoided where, during SWLS operation, the first IP 121 stores the same data in both the first memory 123 and the second memory 133.

[0084] Protection circuit 16 can determine whether SWLS is being executed based on the value set in the operation mode setting register 134. Protection circuit 16 can also be configured to receive information from CPU 11 directly regarding whether SWLS is being executed.

[0085] Furthermore, in semiconductor device 1b, the first IP 121 can access the second memory 133 via the third bus 14 without using the path connecting the first bus 122 and the second bus 132, and the second IP 131 can access the first memory 123. However, access via the third bus 14 is not preferred because it increases contention for accessing the third bus 14.

[0086] Although the inventions made by the inventors have been specifically described based on the embodiments, it is understood that the invention is not limited to the above embodiments and various changes can be made without departing from the scope of the invention.

Claims

1. A semiconductor device that performs a software lockstep (SWLS), comprising: a first circuit group including a first intellectual property (IP) to be operated in a first address space, a first bus, and a first memory coupled to the first IP via the first bus; a second circuit group including a second IP to be operated in a second address space, a second bus, and a second memory coupled to the second IP via the second bus; a third bus connectable with a third memory; and a transfer control circuit coupled to the first bus to the third bus and including a comparator, wherein when the SWLS is performed, the transfer control circuit is configured to transfer a program for the SWLS from the third memory to the first memory and the second memory, the first IP is configured to execute the program for the SWLS stored in the first memory to store a first execution result in the first memory, the second IP is configured to execute the program for the SWLS stored in the second memory to store a second execution result in the second memory; the transfer control circuit is configured to read the first execution result and the second execution result from the first memory and the second memory, and compare the first execution result with the second execution result using the comparator, and the second circuit group is configured to convert an access address from the second IP to the second memory so that an address assigned to the second memory in the second address space is the same as an address assigned to the first memory in the first address space, wherein the second bus includes: an address conversion circuit configured to convert the access address from the second IP to the second memory; and an operation mode setting register configured to set either a first value indicating that the SWLS is to be performed, or a second value indicating that the SWLS is not to be performed, wherein when the first value is set in the operation mode setting register, the address conversion circuit is configured to convert the access address from the second IP to the second memory so that the address assigned to the second memory in the second address space is the same as the address assigned to the first memory in the first address space.

2. The semiconductor device according to claim 1, wherein when the second value is set in the operation mode setting register, the address conversion circuit is configured not to convert the access address from the second IP to the second memory.

3. The semiconductor device according to claim 1, further comprising a central processing unit (CPU) coupled to the second bus, and wherein the address conversion circuit is configured not to convert an access address from the CPU to the second memory regardless of a value set in the operation mode setting register. ​ ​ 4. The semiconductor device of claim 1, wherein when the SWLS is executed, the transfer control circuit is configured to transfer data for the SWLS from the third memory to the first memory and the second memory.

5. The semiconductor device of claim 1, further comprising a central processing unit (CPU) coupled to the transfer control circuit, and wherein the transfer control circuit is configured to: store the first execution result in the third memory; and transmit an interrupt signal to the CPU when the first execution result is inconsistent with the second execution result, the interrupt signal notifying that the first execution result is inconsistent with the second execution result.

6. The semiconductor device of claim 1, further comprising a central processing unit (CPU) coupled to the first IP, the second IP, and the transfer control circuit, and wherein the CPU is configured to activate the first IP and the second IP to cause the first IP and the second IP to execute the program for the SWLS after the CPU detects that the transfer of the program for the SWLS by the transfer control circuit has completed.

7. The semiconductor device of claim 1, further comprising a central processing unit (CPU) coupled to the first IP, the second IP, and the transfer control circuit, and wherein the CPU is configured to activate the transfer control circuit to cause the transfer control circuit to compare the first execution result with the second execution result after the CPU detects that the execution of the program for the SWLS by the first IP and the second IP has completed.

8. The semiconductor device of claim 1, wherein the transfer control circuit is configured to transmit a first signal to the first IP and the second IP, the first signal indicating that the transfer of the program for the SWLS has completed, and wherein the first IP and the second IP are configured to execute the program for the SWLS after receiving the first signal.

9. The semiconductor device of claim 1, wherein each of the first IP and the second IP is configured to transmit a second signal to the transfer control circuit, the second signal indicating that the execution of the program for the SWLS has completed, and wherein the transfer control circuit is configured to compare the first execution result with the second execution result after receiving the second signal from the first IP and the second signal from the second IP.

10. The semiconductor device of claim 1, further comprising a protection circuit on a path that couples the first bus and the second bus without passing through the transfer control circuit, and wherein the protection circuit is configured to: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ when the SWLS is executed, the first IP is prohibited from accessing the second memory via the path coupling the first bus and the second bus, and the second IP is prohibited from accessing the first memory via the path coupling the first bus and the second bus, and when the SWLS is not executed, the first IP is allowed to access the second memory via the path coupling the first bus and the second bus, and the second IP is allowed to access the first memory via the path coupling the first bus and the second bus.

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