A cascading method for PCIe signal processing cards

Abstract

The present invention discloses a cascading method of a PCIe signal processing card, wherein a plurality of identical PCIe signal processing cards are cascaded through an inter-board data high-speed cascading channel, wherein one PCIe signal processing card is connected to an FMC daughter card as a main card, and the rest are co-processing cards, and each PCIe signal processing card is connected to a host computer through a PCIe slot; the FMC daughter card sends the collected raw data to the main card for slicing and encapsulation, and the encapsulation header contains the board ID of the corresponding PCIe signal processing card; the main card transmits all data to the co-processing card through an inter-board data high-speed cascading channel, and each co-processing card processes data matching its own board ID, and transmits the processing result data to the host computer, and the host computer reorganizes the data. The present invention solves the problem of being limited by FPGA resources during hardware acceleration, and realizes a cascade channel with elastic expansion; it is suitable for acquisition scenarios and transmission scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing, in particular to a cascading method of PCIe signal processing cards. Background Art

[0002] PCIe-based signal processing cards usually use FPGA to implement hardware acceleration of signal processing. The application scenario is mainly to insert it into the PCIe slot of a PC or server, and after the external medium-frequency signal is processed by hardware, the data results are transmitted to the host computer CPU for further processing. For example, in a specific FPGA device, hardware DDC or FFT operations of multiple channels are implemented. However, due to the following two limitations, the acceleration capability of a single PCIe card has reached its ceiling: (1) Limited by FPGA resources. When the logic resources in the FPGA are used up, it is impossible to implement hardware acceleration of more channels, and a larger FPGA device can only be replaced. (2) Limited by the connection bandwidth of PCIe. The bandwidth of a single card PCIe3.0 X8 or X16 has a maximum limit, and some FPGAs or host computers do not support PCIe4.0. When more hardware channels need to communicate with the host computer, there is always a bandwidth bottleneck. Summary of the invention

[0003] The purpose of the present invention is to provide a cascading method for PCIe signal processing cards, which is used to solve the problem of being limited by FPGA resources when using FPGA to implement PCIe signal processing hardware acceleration in the prior art, and further solve the problem that the acceleration capability of a single PCIe card is limited due to the connection bandwidth limitation of PCIe.

[0004] The present invention solves the above problems through the following technical solutions:

[0005] A cascading method for PCIe signal processing cards, comprising:

[0006] Step S110, cascading multiple identical PCIe signal processing cards through an inter-board data high-speed cascade channel, wherein one PCIe signal processing card is connected to the FMC daughter card as a main card, and the remaining PCIe signal processing cards are used as co-processing cards, and each PCIe signal processing card is connected to the host computer through a PCIe slot;

[0007] Step S120, the FMC daughter card sends the collected raw data to the main card, and the main card slices and encapsulates the raw data to obtain encapsulated data, where the encapsulation header of the encapsulated data contains the board ID of the corresponding PCIe signal processing card;

[0008] Step S130, the main card transmits all data to the co-processing card through the inter-board data high-speed cascade channel, each co-processing card processes all original data and transmits the processing result data to the host computer, and the host computer reorganizes the received processing result data.

[0009] Each PCIe signal processing card communicates with the host computer. In a computer system, each PCIe signal processing card occupies a PCIe slot. In the acquisition scenario, when solving the problem of insufficient FPGA hardware resources of the PCIe signal processing card, the main card needs to transmit all the original data, and the downstream cascade board uses all the original data to perform hardware accelerated calculations. Each PCIe signal processing card uses all the original data and performs independent hardware accelerated calculations according to the configuration of the card. Multiple PCIe signal processing cards process in parallel and transmit the processing result data independently to the host computer.

[0010] A cascading method for PCIe signal processing cards, comprising:

[0011] Step S210, cascading multiple identical PCIe signal processing cards through an inter-board data high-speed cascade channel, wherein one PCIe signal processing card is connected to the FMC daughter card as a main card, and the remaining PCIe signal processing cards are used as co-processing cards, and each PCIe signal processing card is connected to the host computer through a PCIe slot;

[0012] Step S220, the FMC daughter card sends the collected raw data to the main card, and the main card slices and encapsulates the raw data to obtain encapsulated data, wherein the encapsulation header of the encapsulated data contains information such as the board ID and data block sequence number of the corresponding PCIe signal processing card;

[0013] Step S230: the master card extracts the data corresponding to its own board ID from the encapsulated data, and then sends the remaining data to the next-level co-processing card through the inter-board data high-speed cascade channel. Similarly, the co-processing card extracts the data corresponding to its own board ID and sends the other data to the next-level co-processing card through the inter-board data high-speed cascade channel, and so on, until each co-processing card receives the data corresponding to its own board ID.

[0014] Each PCIe signal processing card uploads the data corresponding to its own card ID to the host computer through the PCIe slot, and the host computer reorganizes all received data according to information such as the card ID and data block sequence number.

[0015] It is used in acquisition scenarios to solve the problem of insufficient PCIe transmission bandwidth with the host computer. In this case, the main card can transmit only part of the data. The main card takes out the data corresponding to its own board ID from the packaged data, and uploads the data matching its own board ID to the host computer through the PCIe slot. Therefore, this part of the data does not need to be passed to the downstream cascaded PCIe signal processing card, and only the remaining data is sent to the next-level co-processing card through the inter-board data high-speed cascade channel; similarly, after the co-processing card takes out the data corresponding to its own board ID, it also uploads it to the host computer through the PCIe slot, and sends other data to its next-level co-processing card through the inter-board data high-speed cascade channel, and so on, until each co-processing card receives the data corresponding to its own board ID and uploads it to the host computer independently, and the host computer reorganizes all the received data according to information such as the board ID and data block sequence number.

[0016] In the acquisition scenario, the FMC daughter card is an AD chip or at least contains an AD chip.

[0017] A cascading method for PCIe signal processing cards, comprising:

[0018] Step S310, cascading multiple identical PCIe signal processing cards through the inter-board data high-speed cascade channel, wherein one PCIe signal processing card is connected to the FMC daughter card as the main card, and the remaining PCIe signal processing cards are used as co-processing cards, and each PCIe signal processing card is connected to the host computer through a PCIe slot;

[0019] Step S320: The host computer slices and encapsulates the modulated data to obtain encapsulated data, wherein the encapsulation header of the encapsulated data contains information such as the board ID and data block sequence number of the corresponding PCIe signal processing card;

[0020] Step S330: The host computer sends all packaged data to each PCIe signal processing card through the PCIe slot. The FPGA on each PCIe signal processing card processes the data according to its own settings, and segments and packages the modulation result data according to its position in the stacking scenario. Each co-processing card sends the data to the main card, which reassembles the data according to information such as the board ID and data block sequence number and then transmits it.

[0021] It is used to solve the problem of insufficient FPGA hardware resources of PCIe signal processing cards in the transmission scenario. In this case, the host computer needs to send out the modulated data, and the modulation function needs to be implemented on the FPGA. At this time, different hardware acceleration channels are required to process different modulation parameters. Therefore, the host computer sends all the data to each PCIe signal processing card through the PCIe slot. The FPGA on each PCIe signal processing card processes the received data according to its own settings (each acceleration channel may have different parameter settings), and slices and encapsulates the modulation result data according to its position in the cascade stacking scenario. The encapsulated data also contains information such as the board ID and serial number. On the high-speed cascade channel between boards, the sliced ​​data of multiple PCIe signal processing cards may be interleaved and transmitted at the same time. After receiving this data, the main card classifies and reorganizes the data transmitted by each PCIe signal processing card, and obtains the complete modulated data from multiple processing cards after reorganization, and then transmits it through the FMC daughter card.

[0022] A cascading method for PCIe signal processing cards, comprising:

[0023] Step S410, cascading multiple identical PCIe signal processing cards through the inter-board data high-speed cascade channel, wherein one PCIe signal processing card is connected to the FMC daughter card as the main card, and the remaining PCIe signal processing cards are used as co-processing cards, and each PCIe signal processing card is connected to the host computer through a PCIe slot;

[0024] Step S420: The host computer slices and encapsulates the modulated data to obtain encapsulated data, wherein the encapsulation header of the encapsulated data contains the board ID of the corresponding PCIe signal processing card;

[0025] Step S430: The host computer distributes the encapsulated data to the corresponding PCIe signal processing card through the PCIe slot according to the board ID and serial number information contained in the encapsulation header of the encapsulated data. Each co-processing card transmits the received data to the main card through the inter-board data high-speed cascade channel. The main card reassembles the data and then transmits it.

[0026] When the host computer needs to send the modulated data to the PCIe card for transmission, but the data volume is very large and the bandwidth of the PCIe channel of a single PCIe card is insufficient, the data needs to be sliced ​​and encapsulated in the header. The header contains the ID of each processing card and the serial number of the data block, such as Figure 3 .Each data fragment can only be sent from the CPU to the plug-in card corresponding to the ID through PCIe, and then transmitted to the main card through the high-speed cascade channel between boards. The main card sorts according to the ID and serial number in the header, completes the reorganization of the data fragments, and finally transmits it through DA.

[0027] Applied to the transmission scenario, it solves the problem of insufficient PCIe transmission bandwidth with the host computer. The host computer needs to send modulated data out, but the PCIe transmission bandwidth of a single PCIe signal processing card is not high enough and cannot be transmitted. In this case, the co-processing card is used to share the transmission. At this time, the host computer will slice the data. Similarly, each piece of data has board ID, serial number and other information. The corresponding slice is sent to the corresponding PCIe signal processing card through the corresponding PCIe slot. After these cards receive the data, they transmit the data to the main card through the high-speed cascade channel between boards. The main card reorganizes the data according to the board ID, serial number, etc.

[0028] In the transmission scenario, the FMC daughter card is a DA chip or at least includes a DA chip.

[0029] When we increase the device scale or PCIe transmission bandwidth, there will be waste when so many resources or bandwidth are not needed in some scenarios. The present invention adds the card ID of the PCIe signal processing card in the package header, and determines how many cards are needed for the usage scenario according to the number of FPGA acceleration channels or PCIe bandwidth, and then cascades several cards, and the entire cascade channel is elastically expandable.

[0030] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0031] (1) The present invention solves the problem of being limited by FPGA resources when using FPGA to implement PCIe signal processing hardware acceleration in the prior art. When more hardware acceleration channels are needed, it is only necessary to select the number of processing cards through the board ID of the packaging header; and elastically expandable cascade channels are realized; it is suitable for acquisition scenarios and transmission scenarios.

[0032] (2) The present invention solves the problem that the acceleration capability of a single PCIe card is limited by the connection bandwidth of PCIe. Each processing card only processes the database matching its own board ID and independently uploads it to the main card or host computer, thus breaking through the bottleneck of the limited acceleration capability of a single PCIe card. It also realizes a cascade channel with elastic expansion. It is suitable for acquisition scenarios and transmission scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a principle block diagram of a first embodiment of the present invention;

[0034] Figure 2 It is a principle block diagram of a first embodiment of the present invention;

[0035] Figure 3 Flowchart for implementing hardware acceleration for an acquisition scenario. DETAILED DESCRIPTION

[0036] The present invention is further described in detail below in conjunction with examples, but the embodiments of the present invention are not limited thereto.

[0037] Embodiment 1:

[0038] Combined with Figure 1 and Figure 3 As shown, a cascading method of PCIe signal processing cards includes:

[0039] Step S110, cascading multiple identical PCIe signal processing cards through an inter-board data high-speed cascade channel, wherein one PCIe signal processing card is connected to the FMC daughter card as a main card, and the remaining PCIe signal processing cards are used as co-processing cards, and each PCIe signal processing card is connected to the host computer through a PCIe slot;

[0040] Step S120, the FMC daughter card sends the collected raw data to the main card, and the main card slices and encapsulates the raw data to obtain encapsulated data. The encapsulation header of the encapsulated data contains information such as the board ID and serial number of the corresponding PCIe signal processing card. The data format of the encapsulation header is shown in the following table:

[0041]

[0042] Step S130, the main card transmits all data to the co-processing card through the inter-board data high-speed cascade channel. Each co-processing card processes all original data and performs independent calculations, and transmits the processing result data to the host computer, which reorganizes the received processing result data.

[0043] Each PCIe signal processing card communicates with the host computer. In a computer system, each PCIe signal processing card occupies a PCIe slot. In the acquisition scenario, when solving the problem of insufficient FPGA hardware resources of the PCIe signal processing card, the main card needs to transmit all the original data, and the downstream cascaded board card uses all the original data to perform hardware accelerated calculations. Each PCIe signal processing card only processes hardware acceleration tasks related to its own board configuration information (each project or application has its own calculation method, such as completing FFT, DDC, etc. in the field of digital signal processing. The parameters of each FFT or DDC channel are different, and the calculation results are also different). Multiple PCIe signal processing cards process in parallel and transmit the processing result data independently to the host computer. For hardware acceleration scenarios, the work completed by each card is independent. For example, the main card completes FFT channels 1-16, the first co-processing card completes channels 17-32, the second draft co-processing card completes channels 33-48, ... The work completed by the FPGA of each card is independent. Because these tasks consume a lot of hardware resources, a single card may not be able to handle so many channels, so the work is distributed to multiple cards. Because each card works independently and the results are complete, the calculation results transmitted to the host computer are also independent.

[0044] Embodiment 2:

[0045] A cascading method for PCIe signal processing cards, comprising:

[0046] Step S210, cascading multiple identical PCIe signal processing cards through an inter-board data high-speed cascade channel, wherein one PCIe signal processing card is connected to the FMC daughter card as a main card, and the remaining PCIe signal processing cards are used as co-processing cards, and each PCIe signal processing card is connected to the host computer through a PCIe slot;

[0047] Step S220, the FMC daughter card sends the collected raw data to the main card, and the main card slices and encapsulates the raw data to obtain encapsulated data, wherein the encapsulation header of the encapsulated data contains information such as the board ID and data block sequence number of the corresponding PCIe signal processing card;

[0048] Step S230: the master card extracts the data corresponding to its own board ID from the encapsulated data, and then sends the remaining data to the next-level co-processing card through the inter-board data high-speed cascade channel. Similarly, the co-processing card extracts the data corresponding to its own board ID and sends the other data to the next-level co-processing card through the inter-board data high-speed cascade channel, and so on, until each co-processing card receives the data corresponding to its own board ID.

[0049] Each PCIe signal processing card uploads the data corresponding to its own card ID to the host computer through the PCIe slot, and the host computer reassembles all received data according to the card ID and data block sequence number.

[0050] It is used in acquisition scenarios to solve the problem of insufficient PCIe transmission bandwidth with the host computer. In this case, the main card can transmit only part of the data. The main card takes out the data corresponding to its own board ID from the packaged data, and uploads the data matching its own board ID to the host computer through the PCIe slot. Therefore, this part of the data does not need to be passed to the downstream cascaded PCIe co-processing card. Therefore, only the remaining data is sent to the next-level co-processing card through the inter-board data high-speed cascade channel; similarly, after the co-processing card takes out the data corresponding to its own board ID, it also uploads it to the host computer through the PCIe slot, and sends other data to its next-level co-processing card through the inter-board data high-speed cascade channel, and so on, until each co-processing card receives the data corresponding to its own board ID and uploads it to the host computer independently, and the host computer reorganizes all the received data.

[0051] In the data collection scenario, the FMC daughter card is an AD chip (analog-to-digital chip) or at least contains an AD chip.

[0052] Embodiment 3:

[0053] Combined with Figure 2 As shown, a cascading method of PCIe signal processing cards includes:

[0054] Step S310, cascading multiple identical PCIe signal processing cards through the inter-board data high-speed cascade channel, wherein one PCIe signal processing card is connected to the FMC daughter card as the main card, and the remaining PCIe signal processing cards are used as co-processing cards, and each PCIe signal processing card is connected to the host computer through a PCIe slot;

[0055] Step S320: The host computer slices and encapsulates the modulated data to obtain encapsulated data, wherein the encapsulation header of the encapsulated data contains information such as the board ID and data block sequence number of the corresponding PCIe signal processing card;

[0056] Step S330: The host computer sends all packaged data to each PCIe signal processing card through the PCIe slot. The FPGA on each PCIe signal processing card processes the data according to its own settings, and slices and packages the modulation result data according to its position in the stacking scenario. Each co-processing card sends the data to the main card, which reassembles the data and transmits it.

[0057] It is used to solve the problem of insufficient FPGA hardware resources of PCIe signal processing cards in the transmission scenario. In this case, the host computer needs to send out the modulated data, and the modulation function needs to be implemented on the FPGA. At this time, different hardware acceleration channels are required to process different modulation parameters. Therefore, the host computer sends all the data to each PCIe signal processing card through the PCIe slot. The FPGA on each PCIe signal processing card processes the received data according to its own settings (each acceleration channel may have different parameter settings), and slices and encapsulates the modulation result data according to its position in the cascade stacking scenario. The encapsulated data also contains information such as the board ID and serial number. On the high-speed cascade channel between boards, the sliced ​​data of multiple PCIe signal processing cards may be interleaved and transmitted at the same time. After receiving this data, the main card classifies and reorganizes the data transmitted by each PCIe signal processing card, and obtains the complete modulated data from multiple processing cards after reorganization, and then transmits it through the FMC daughter card.

[0058] Embodiment 4:

[0059] A cascading method for PCIe signal processing cards, comprising:

[0060] Step S410, cascading multiple identical PCIe signal processing cards through the inter-board data high-speed cascade channel, wherein one PCIe signal processing card is connected to the FMC daughter card as the main card, and the remaining PCIe signal processing cards are used as co-processing cards, and each PCIe signal processing card is connected to the host computer through a PCIe slot;

[0061] Step S420: The host computer slices and encapsulates the modulated data to obtain encapsulated data, wherein the encapsulation header of the encapsulated data contains information such as the board ID and data block sequence number of the corresponding PCIe signal processing card;

[0062] Step S430: The host computer distributes the encapsulated data to the corresponding PCIe signal processing card through the PCIe slot according to the board ID contained in the encapsulation header of the encapsulated data. Each co-processing card transmits the received data to the main card through the inter-board data high-speed cascade channel. The main card reassembles the data and then transmits it.

[0063] When the host computer needs to send the modulated data to the PCIe card for transmission, but the data volume is very large and the bandwidth of the PCIe channel of a single PCIe card is insufficient, the data needs to be sliced ​​and encapsulated in a header. The header contains information such as the ID of each processing card and the serial number of the data block, such as Figure 3.Each data fragment can only be sent from the CPU to the plug-in card corresponding to the ID through PCIe, and then transmitted to the main card through the high-speed cascade channel between boards. The main card sorts according to the ID and serial number in the header, completes the reorganization of the data fragments, and finally transmits it through DA.

[0064] Applied to the transmission scenario, it solves the problem of insufficient PCIe transmission bandwidth with the host computer. The host computer needs to send modulated data out, but the PCIe transmission bandwidth of a single PCIe signal processing card is not high enough and cannot be transmitted. In this case, the co-processing card is used to share the transmission. At this time, the host computer will slice the data. Similarly, each piece of data has board ID, serial number and other information. The corresponding slice is sent to the corresponding PCIe signal processing card through the corresponding PCIe slot. After these cards receive the data, they transmit the data to the main card through the high-speed cascade channel between boards. The main card reorganizes the data according to the board ID, serial number, etc.

[0065] For scenarios that require PCIe transmission bandwidth, if the host computer CPU completes the modulation of the signal channel through software, it only needs to solve the transmission problem. Since the PCIe bandwidth of a single card or several cards is insufficient and cannot transmit so much data, more co-processing cards are needed. The host computer needs to slice and encapsulate the data, and identify which card processes the data. Then, the data is transmitted to the corresponding PCIe signal processing card through the corresponding PCIe slot, and the PCIe signal processing card transmits the data to the main card through the inter-board high-speed cascade channel. Since the inter-board high-speed cascade channel may transmit the sliced ​​data of many boards at the same time, all the data is intertwined, and the order of reaching the main card may also be out of order, which requires the main card to reorganize the data gathered from each card.

[0066] In the transmission scenario, the FMC daughter card is a DA chip (analog-to-digital chip) or at least includes a DA chip.

[0067] Collection and transmission are two independent scenarios, which are inverse processes of each other. When the FMC daughter card includes both AD chip and DA chip, collection and transmission exist in the same product. You only need to select the data flow direction according to the scenario.

[0068] Although the present invention is described herein with reference to the illustrative embodiments of the present invention, the above embodiments are only preferred embodiments of the present invention, and the embodiments of the present invention are not limited to the above embodiments. It should be understood that those skilled in the art can design many other modifications and embodiments, which will fall within the scope and spirit of the principles disclosed in this application.

Claims

1. A cascading method for PCIe signal processing cards, characterized in that: include: Step S110, cascading multiple identical PCIe signal processing cards through the inter-board data high-speed cascade channel, wherein one PCIe signal processing card is connected to the FMC daughter card as the main card, and the remaining PCIe signal processing cards are used as co-processing cards, that is, the inter-board data high-speed cascade channel of the main card is connected to the inter-board data high-speed cascade channel of the first co-processing card, and the inter-board data high-speed cascade channel of the first co-processing card is connected to the inter-board data high-speed cascade channel of the second co-processing card, and so on, each PCIe signal processing card is connected to the host computer through the PCIe slot; In the collection scenario: When the FPGA hardware resources of the main card are insufficient, the FMC daughter card sends the collected raw data to the main card, and the main card transmits all the data to the co-processing card through the inter-board data high-speed cascade channel. Each co-processing card uses all the raw data and performs independent hardware accelerated calculations according to its own configuration, and transmits the processing result data to the host computer, which reorganizes the received processing result data. When the PCIe transmission bandwidth between the main card and the host computer is insufficient, the FMC daughter card sends the collected raw data to the main card, which slices and encapsulates the raw data to obtain encapsulated data. The encapsulation header of the encapsulated data contains the board ID and data block sequence number of the corresponding PCIe signal processing card; the main card takes out the data corresponding to its own board ID from the encapsulated data, and then sends the remaining data to the next-level co-processing card through the inter-board data high-speed cascade channel. Similarly, the co-processing card takes out the data corresponding to its own board ID and sends the other data to the next-level co-processing card through the inter-board data high-speed cascade channel, and so on, until each co-processing card receives the data corresponding to its own board ID; each PCIe signal processing card uploads the data corresponding to its own board ID to the host computer through the PCIe slot, and the host computer reorganizes all received data according to the board ID and data block sequence number.

2. A cascading method for PCIe signal processing cards according to claim 1, characterized in that: The FMC daughter card is an AD chip.

3. A cascading method for PCIe signal processing cards according to claim 1, characterized in that: In the launch scenario: When the FPGA hardware resources of the PCIe signal processing card are insufficient, the host computer sends all packaged data to each PCIe signal processing card through the PCIe slot. The FPGA on each PCIe signal processing card processes the data according to its own settings and slices and packages the modulation result data according to its position in the stacking scenario. Each co-processing card sends the data to the main card, which reassembles the data and transmits it. When the PCIe transmission bandwidth with the host computer is insufficient, the host computer will slice and encapsulate the modulated data to obtain encapsulated data. The encapsulation header of the encapsulated data contains the board ID and data block sequence number of the corresponding PCIe signal processing card. The host computer distributes the encapsulated data to the corresponding PCIe signal processing card through the PCIe slot according to the board ID contained in the encapsulation header of the encapsulated data. Each co-processing card transmits the received data to the main card through the inter-board data high-speed cascade channel. The main card reassembles the data according to the board ID and data block sequence number and then transmits it.

4. A cascading method for PCIe signal processing cards according to claim 3, characterized in that: The FMC daughter card is a DA chip.

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