A three-dimensional heterogeneous integrated programmable chip structure

Abstract

This application relates to the field of integrated chip technology, and more particularly to a three-dimensional heterogeneous integrated programmable chip structure. In this programmable chip structure, a first chip has a first metal layer; a first three-dimensional heterogeneous integration bonding point is provided on the three-dimensional heterogeneous integration surface on one side of the first chip between the first chip and a second chip; the first three-dimensional heterogeneous integration bonding point is interconnected with the first metal layer; a second chip has a second metal layer; a second three-dimensional heterogeneous integration bonding point is provided on the three-dimensional heterogeneous integration surface on one side of the second chip between the first chip and the second chip; the second three-dimensional heterogeneous integration bonding point is interconnected with the second metal layer; the first three-dimensional heterogeneous integration bonding point and the second three-dimensional heterogeneous integration bonding point are in contact and interconnected to form a three-dimensional heterogeneous integrated structure. The embodiments of this application utilize three-dimensional heterogeneous integration technology and semiconductor metal processing technology to achieve inter-chip stacking interconnection, thereby reducing the power consumption of the programmable chip structure while improving its access bandwidth.

Description

Technical Field

[0001] This application relates to the field of integrated chip technology, and in particular to a three-dimensional heterogeneous integrated programmable chip structure. Background Technology

[0002] Existing packaging technologies such as SIP (System In a Package) and MCM (Multichip Module) require bonding the chip and other circuits to a substrate or silicon interposer, interconnecting them through through silicon vias (TSVs) to form a 2.5D package, enabling large-scale interconnection between the chip and other circuits.

[0003] Programmable chip structures such as FPGA (Field Programmable Gate Array) chips or chips containing eFPGA (Embedded Field Programmable Gate Array) modules have the advantages of abundant wiring resources, reprogrammability, high integration, and low investment, and have been widely used in the field of digital circuit design. Currently, the scale of FPGAs has evolved from tens of thousands of logic cells (LEs) to millions of logic cells. However, the interconnection between FPGAs and other circuits is limited by existing packaging, with the interconnection scale remaining at the thousand-level. This significantly restricts the access bandwidth and power consumption of FPGA chips or chips containing eFPGA modules in high-capacity storage applications.

[0004] Therefore, improving the access bandwidth of programmable chip structures and reducing their power consumption are urgent technical problems that need to be solved. Summary of the Invention

[0005] This application provides a three-dimensional heterogeneous integrated programmable chip structure to improve the access bandwidth of the programmable chip structure and reduce its operating power consumption.

[0006] To achieve the above objectives, this application provides the following solutions:

[0007] In a first aspect, embodiments of this application provide a three-dimensional heterogeneous integrated programmable chip structure, the programmable chip structure comprising: the chips in the multilayer chip include one or more of the following: FPGA chip, chip containing eFPGA module, and memory chip;

[0008] The multilayer chip has an adjacent first chip and a second chip.

[0009] The first chip has a first metal layer; a first three-dimensional heterogeneous integration bonding point is provided on the three-dimensional heterogeneous integration surface on one side of the first chip between the first chip and the second chip; the first three-dimensional heterogeneous integration bonding point is interconnected with the first metal layer;

[0010] The second chip has a second metal layer; a second three-dimensional heterogeneous integration bonding point is provided on the three-dimensional heterogeneous integration surface on one side of the second chip between the first chip and the second chip; the second three-dimensional heterogeneous integration bonding point is interconnected with the second metal layer;

[0011] The first three-dimensional heterogeneous integration bonding point and the second three-dimensional heterogeneous integration bonding point are in contact and interconnected to form a three-dimensional heterogeneous integration structure.

[0012] In one possible embodiment, the first metal layer in the first chip is provided with a first dielectric layer and a first three-dimensional heterogeneous integration bonding layer; wherein, the first three-dimensional heterogeneous integration bonding point is located on the surface of the first three-dimensional heterogeneous integration bonding layer;

[0013] The second chip has a second dielectric layer and a second three-dimensional heterogeneous integration bonding layer on the second metal layer; wherein the second three-dimensional heterogeneous integration bonding point is located on the surface of the second three-dimensional heterogeneous integration bonding layer.

[0014] In one possible embodiment, the third chip in the multilayer chip is disposed above the first chip and adjacent to the first chip;

[0015] The first chip also includes a third metal layer; a third dielectric layer and a third three-dimensional heterogeneous integration bonding layer are also provided on the bottom surface of the substrate of the first chip; the surface of the third three-dimensional heterogeneous integration bonding layer is provided with third three-dimensional heterogeneous integration bonding points; the third metal layer interconnects the third three-dimensional heterogeneous integration bonding points and the first metal layer respectively;

[0016] The third chip has a fourth metal layer; a fourth three-dimensional heterogeneous integration bonding point is provided on the three-dimensional heterogeneous integration surface on one side of the third chip between the first chip and the third chip; the fourth three-dimensional heterogeneous integration bonding point is interconnected with the fourth metal layer;

[0017] The third three-dimensional heterogeneous integration bonding point is in contact with and interconnected with the fourth three-dimensional heterogeneous integration bonding point.

[0018] In one possible embodiment, the first three-dimensional heterogeneous integration bonding point is disposed on the three-dimensional heterogeneous integration surface on the bottom surface of the substrate of the first chip.

[0019] The second chip has a second dielectric layer and a second three-dimensional heterogeneous integration bonding layer on the second metal layer; wherein the second three-dimensional heterogeneous integration bonding point is located on the surface of the second three-dimensional heterogeneous integration bonding layer.

[0020] In one possible embodiment, the first three-dimensional heterogeneous integration bonding point is disposed on the three-dimensional heterogeneous integration surface on the bottom surface of the substrate of the first chip.

[0021] The second three-dimensional heterogeneous integration bonding point is disposed on the three-dimensional heterogeneous integration surface on the bottom surface of the substrate of the second chip.

[0022] In one possible embodiment, the third chip in the multilayer chip is disposed above the first chip and adjacent to the first chip;

[0023] The first chip also includes a third metal layer; the third metal layer further includes a third dielectric layer and a third three-dimensional heterogeneous integration bonding layer along a direction away from the substrate of the first chip; the surface of the third three-dimensional heterogeneous integration bonding layer is provided with third three-dimensional heterogeneous integration bonding points; the third metal layer interconnects the third three-dimensional heterogeneous integration bonding points and the first metal layer respectively;

[0024] The third chip has a fourth metal layer; a fourth three-dimensional heterogeneous integration bonding point is provided on the three-dimensional heterogeneous integration surface on one side of the third chip between the first chip and the third chip; the fourth three-dimensional heterogeneous integration bonding point is interconnected with the fourth metal layer;

[0025] The third three-dimensional heterogeneous integration bonding point is in contact with and interconnected with the fourth three-dimensional heterogeneous integration bonding point.

[0026] In one possible embodiment, the first chip has a first signal output terminal; the second chip has a first signal input terminal;

[0027] The common ground terminal of the first chip is interconnected with the common ground terminal of the second chip through the three-dimensional heterogeneous integration structure to form the common ground terminal of the multilayer chip;

[0028] The first signal output terminal is interconnected with the first signal input terminal through the three-dimensional heterogeneous integrated structure.

[0029] In one possible embodiment, the first chip includes a first level conversion circuit and a second level conversion circuit;

[0030] In the first chip, the first signal output terminal is interconnected with the input terminal of the second level conversion circuit via the first level conversion circuit; the output terminal of the second level conversion circuit is interconnected with the first signal input terminal via the three-dimensional heterogeneous integrated structure.

[0031] The first reference voltage terminal of the first level conversion circuit is interconnected with the core voltage terminal of the first chip; the second reference voltage terminal of the first level conversion circuit is interconnected with the common ground terminal of the multilayer chip.

[0032] The first reference voltage terminal of the second level conversion circuit is interconnected with the core voltage terminal of the second chip via the three-dimensional heterogeneous integrated structure; the second reference voltage terminal of the second level conversion circuit is interconnected with the common ground terminal of the multilayer chip.

[0033] In one possible embodiment, the second chip includes a first level conversion circuit and a second level conversion circuit;

[0034] The first signal output terminal is interconnected with the input terminal of the first level conversion circuit via the three-dimensional heterogeneous integrated structure; the output terminal of the first level conversion circuit is interconnected with the first signal input terminal via the second level conversion circuit.

[0035] The first reference voltage terminal of the first level conversion circuit is interconnected with the core voltage terminal of the first chip via the three-dimensional heterogeneous integrated structure; the second reference voltage terminal of the first level conversion circuit is interconnected with the common ground terminal of the multilayer chip via the three-dimensional heterogeneous integrated structure.

[0036] The first reference voltage terminal of the second level conversion circuit is interconnected with the core voltage terminal of the second chip; the second reference voltage terminal of the second level conversion circuit is interconnected with the common ground terminal of the multilayer chip.

[0037] In one possible embodiment, the multilayer chip includes an adjacent fourth chip and a fifth chip;

[0038] The fourth chip has a first metal network and a second metal network; the fifth chip has a third metal network;

[0039] A fifth three-dimensional heterogeneous integration bonding point and a sixth three-dimensional heterogeneous integration bonding point are disposed on the three-dimensional heterogeneous integration surface on one side of the fourth chip between the fourth chip and the fifth chip; wherein, the fifth three-dimensional heterogeneous integration bonding point interconnects the first metal network; and the sixth three-dimensional heterogeneous integration bonding point interconnects the second metal network;

[0040] A seventh three-dimensional heterogeneous integration bonding point and an eighth three-dimensional heterogeneous integration bonding point are disposed on the three-dimensional heterogeneous integration surface on one side of the fifth chip between the fourth chip and the fifth chip; wherein, the seventh three-dimensional heterogeneous integration bonding point and the eighth three-dimensional heterogeneous integration bonding point are interconnected with the third metal network; the seventh three-dimensional heterogeneous integration bonding point contacts and interconnects the fifth three-dimensional heterogeneous integration bonding point; and the eighth three-dimensional heterogeneous integration bonding point contacts and interconnects the sixth three-dimensional heterogeneous integration bonding point.

[0041] In one possible embodiment, the FPGA chip includes an FPGA die and / or an FPGA wafer;

[0042] The chip containing the eFPGA module includes a die containing the eFPGA module and / or a wafer containing the eFPGA module.

[0043] The memory chip includes memory chips and / or memory wafers.

[0044] Compared with the prior art, this application has the following advantages and beneficial effects:

[0045] In this application's programmable chip structure, multiple chips are stacked and connected to form a multi-layer chip. Adjacent first and second chips are connected by three-dimensional heterogeneous integration bonding to achieve interconnection between the first and second chips. This application utilizes three-dimensional heterogeneous integration technology and semiconductor metal processing technology to achieve stacked interconnection between chips. This ensures that the physical and electrical parameters of the interconnects between chips conform to the characteristics of semiconductor processing technology, reducing the use of vias, interconnects, and I / O structures, and increasing the interconnection density and interconnection speed between chips. At the same time, the three-dimensional heterogeneous integration interconnection technology does not use traditional I / O structures and has a shorter interconnection distance, reducing the communication power consumption between chips. This improves the integration density and interconnection frequency of the integrated chip and reduces interconnection power consumption, thereby reducing the operating power consumption of the programmable chip structure while increasing its access bandwidth. Attached Figure Description

[0046] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This application provides a schematic diagram of a three-dimensional heterogeneous integrated programmable chip structure.

[0048] Figure 2 A schematic diagram of the first type of stacked interconnection structure of a dual-layer chip provided in this application embodiment;

[0049] Figure 3 This is a schematic diagram of the stacked connection structure of the second type of dual-layer chip provided in the embodiments of this application;

[0050] Figure 4 A schematic diagram of the stacked connection structure of the third type of dual-layer chip provided in the embodiments of this application;

[0051] Figure 5A schematic diagram of a stacked interconnection structure of a three-layer chip provided in an embodiment of this application;

[0052] Figure 6 A schematic diagram of the connection of the logic level conversion circuit when the logic level conversion circuit is set in the first chip, provided for an embodiment of this application;

[0053] Figure 7 This is a connection diagram of a level conversion circuit provided in an embodiment of this application;

[0054] Figure 8 A schematic diagram of the logic level conversion circuit connection when the logic level conversion circuit is set in the second chip, provided for an embodiment of this application;

[0055] Figure 9 This is a schematic diagram of a metal layer wiring scheme for a stacked chip structure provided in an embodiment of this application. Detailed Implementation

[0056] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0057] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0058] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0059] like Figure 1 The diagram shown is a schematic diagram of a three-dimensional heterogeneous integrated programmable chip structure provided in an embodiment of this application. The programmable chip structure includes: a multilayer chip 100 stacked and connected.

[0060] For example, a multilayer chip includes at least one of multilayer dies or multilayer wafers. It is readily understood that the chip mentioned in the embodiments of the present invention can be a product existing in the form of a wafer or a die. A chip can be at least one of a die (or chip) and a wafer, but is not limited thereto, and can be any substitution that can be conceived by those skilled in the art. Here, a wafer refers to a silicon wafer used to fabricate silicon semiconductor circuits, and a chip or die refers to a silicon wafer after the aforementioned wafer with semiconductor circuits fabricated has been diced. Specific embodiments of the present invention are described using a chip as an example.

[0061] The multi-layer chip 100 includes at least two chips, any one of which is an FPGA (Field Programmable Gate Array) chip or a chip containing an eFPGA (Embedded Field Programmable Gate Array) module.

[0062] Of course, each chip can be any one or any combination of computing and storage units such as FPGA chip, chip containing eFPGA module (which also includes chips that use FPGA as an embedded module, hereinafter collectively referred to as FPGA chip), memory chip, central processing unit (CPU), digital signal processing (DSP), graphics processing unit (GPU), and intellectual property core module (IP core).

[0063] Memory chips can employ a variety of memory technologies, including but not limited to any one or any combination of Random Access Memory (RAM), Flash memory, Resistive RAM (RRAM or ReRAM), Magnetoresistive RAM (MRAM), Ferroelectric RAM (FeRAM), Ox RAM, Bridge RAM (CBRAM), Phase Change Memory (PCM), Spin-Torque-MRAM (STT-MRAM), or Electrically Erasable Memory (EEPROM).

[0064] Specifically, FPGA chips include FPGA chips and / or FPGA wafers; chips containing eFPGA modules include chips containing eFPGA modules and / or wafers containing eFPGA modules; memory chips include memory chips and / or memory wafers.

[0065] Specifically, an FPGA chip may include the logic circuit, power supply circuit, level conversion circuit, and signal processing circuit of an FPGA; a chip containing an eFPGA module may include the logic circuit, power supply circuit, level conversion circuit, and signal processing circuit of an eFPGA; and a memory chip may include a memory array, a memory controller, a power supply circuit, and a level conversion circuit.

[0066] Each chip can be made using the same process structure and / or type of chip, or it can be made using different process structures and / or types of chips; there are no restrictions here.

[0067] In this embodiment, multiple chips are stacked sequentially to improve overall integration and / or achieve specific functions. The total number of chips is the number of layers in a 100-layer multi-chip stack; however, no limit is placed on the number of layers in a 100-layer multi-chip stack.

[0068] The multilayer chip 100 includes a first chip 210 and a second chip 220 arranged adjacent to each other. The first chip 210 can be any chip in the multilayer chip 100, and the second chip 220 is any chip in the multilayer chip 100 that is adjacent to the first chip 210. In this embodiment, "adjacent" of the first chip 210 and the second chip 220 can be understood as the first chip 210 and the second chip 220 being "stacked and / or interconnected".

[0069] In this embodiment, the first chip 210 and the second chip 220 are arranged in a group. Of course, if the multi-layer chip contains two groups of first chips 210 and second chips 220, the first chip 210 in the first group can be the second chip 220 in the second group.

[0070] The first chip 210 has a first metal layer 211. The material of the first metal layer 211 can be copper, aluminum, or gold, and there is no limitation. The relevant circuits in the first chip 210 can be connected in the first metal layer 211.

[0071] A first three-dimensional heterogeneous integration bonding point 212 is provided on one side of the three-dimensional heterogeneous integration surface of the first chip 210 between the first chip 210 and the second chip 220; the first three-dimensional heterogeneous integration bonding point 212 is interconnected with the first metal layer 211.

[0072] The first three-dimensional heterogeneous integration bonding point 212 contains several interconnect bonding points, and the collection of these interconnect bonding points is used together to realize the cross-chip interconnection function of signals.

[0073] The second chip 220 has a second metal layer 221, which can be made of copper, aluminum, or gold, and there is no limitation on the material. The relevant circuits in the first chip 210 can be connected to the second metal layer 221.

[0074] A second three-dimensional heterogeneous integration bonding point 222 is provided on the three-dimensional heterogeneous integration surface on one side of the second chip 220 between the first chip 210 and the second chip 220; the second three-dimensional heterogeneous integration bonding point 222 is interconnected with the second metal layer 221.

[0075] The second three-dimensional heterogeneous integration bonding point 222 contains several interconnect bonding points, and the collection of these interconnect bonding points is used together to realize the cross-chip interconnection function of signals.

[0076] The first three-dimensional heterogeneous integration bonding point 212 and the second three-dimensional heterogeneous integration bonding point 222 are in contact and interconnected to form a three-dimensional heterogeneous integration structure.

[0077] Specifically, the interconnection points in the first three-dimensional heterogeneous integration bonding point 212 can be interconnected with the corresponding interconnection points in the second three-dimensional heterogeneous integration bonding point 222, thereby achieving contact and interconnection between the first three-dimensional heterogeneous integration bonding point 212 and the second three-dimensional heterogeneous integration bonding point 222.

[0078] Of course, multiple sets of first chips 210 and second chips 220 can exist in the multilayer chip 100 to realize a stacked chip structure of three or more layers.

[0079] This embodiment utilizes three-dimensional heterogeneous integration technology to achieve stacked interconnection between chips through semiconductor metal processing technology. This ensures that the physical and electrical parameters of the interconnects between chips follow the characteristics of semiconductor processing technology, reducing the use of vias, interconnects, and I / O structures, thereby increasing the interconnection density and speed between chips. At the same time, the three-dimensional heterogeneous integration interconnection technology does not use traditional I / O structures and has shorter interconnection distances, reducing the interconnection power consumption between chips. It also improves the integration level of the integrated chip, thereby reducing the operating power consumption of the programmable chip structure while increasing its access bandwidth.

[0080] Here, this embodiment takes a group of first chips 210 and second chips 220 in the multilayer chip 100 as an example to provide three stacked connection structures of dual-layer chips. In practical applications, these three stacked connection structures of dual-layer chips can be combined to construct the multilayer chip 100.

[0081] In this embodiment, the first chip 210 can be an FPGA chip, and the second chip 220 can be a memory chip. Through three-dimensional heterogeneous integration interconnection technology, a high-density metal layer is established between the FPGA chip and the memory chip for direct cross-chip interconnection, establishing high-bandwidth cross-chip memory access between the FPGA chip and the memory chip. Compared with the prior art where the FPGA chip interconnects external memory chips through IO interfaces and / or IO circuits, memory access between the FPGA chip and the memory chip is realized within the three-dimensional heterogeneous integrated programmable chip structure. This reduces the IO interface overhead of the FPGA chip for interconnecting external memory chips, significantly increases memory access bandwidth, reduces memory access power consumption, and improves memory access capacity.

[0082] like Figure 2 The above is a schematic diagram of the first type of stacked interconnect structure of a dual-layer chip provided in this application embodiment. This stacked interconnect structure belongs to a face-to-face (F2F) interconnect structure, wherein:

[0083] The first chip 210 has a first dielectric layer 213 and a first three-dimensional heterogeneous integration bonding layer 214 on the first metal layer 211; wherein, the first three-dimensional heterogeneous integration bonding point 212 is located on the surface of the first three-dimensional heterogeneous integration bonding layer 214.

[0084] The second chip 220 has a second dielectric layer 223 and a second three-dimensional heterogeneous integration bonding layer 224 on the second metal layer 221; wherein, the second three-dimensional heterogeneous integration bonding point 222 is located on the surface of the second three-dimensional heterogeneous integration bonding layer 224.

[0085] Since the stacked interconnect structure is a face-to-face interconnect structure, the first metal layer 211 can be the top metal layer of the first chip 210, and the second metal layer 221 can be the top metal layer of the second chip 220.

[0086] Preparation process flow:

[0087] 1. A first metal layer 211 is prepared on the side of the first chip 210 away from its substrate, and a second metal layer 221 is prepared on the side of the second chip 220 away from its substrate.

[0088] The three-dimensional integration process of the first chip 210 and the second chip 220 can be flexibly selected. For example, the three-dimensional integrated FPGA chip can use copper metal interconnect technology, and the three-dimensional integrated memory chip can use copper or aluminum metal interconnect technology.

[0089] 2. Using a back end of line (BEOL) process, a first dielectric layer 213 and a first three-dimensional heterogeneous integration bonding layer 214 are prepared on the first metal layer 211, and a first three-dimensional heterogeneous integration bonding point 212 is prepared on the first three-dimensional heterogeneous integration bonding layer 214; using a back end of line process, a second dielectric layer 223 and a second three-dimensional heterogeneous integration bonding layer 224 are prepared on the second metal layer 221, and a second three-dimensional heterogeneous integration bonding point 222 is prepared on the second three-dimensional heterogeneous integration bonding layer 224.

[0090] Specifically, the first three-dimensional heterogeneous integration bonding point 212 can be a copper-processed three-dimensional heterogeneous integration bonding point and interconnected with the first metal layer 211 through inter-metal vias; the second three-dimensional heterogeneous integration bonding point 222 can be a copper-processed three-dimensional heterogeneous integration bonding point and interconnected with the second metal layer 221 through inter-metal vias.

[0091] 3. Align and bond the three-dimensional heterogeneous integration bonding layers of the first chip 210 and the second chip 220 to achieve three-dimensional heterogeneous bonding interconnection between the first chip 210 and the second chip 220.

[0092] like Figure 3 The above is a schematic diagram of the second type of stacked interconnect structure of a dual-layer chip provided in this application embodiment. This stacked interconnect structure belongs to a face-to-back (F2B) interconnect structure. Figure 3 Viewed from bottom to top, this is a face-to-back interconnect structure or a back-to-face (B2F) interconnect structure. Figure 3 Viewed from top to bottom, this is a back-to-back interconnect structure, in which:

[0093] The first three-dimensional heterogeneous integration bonding point 212 is disposed on the three-dimensional heterogeneous integration surface on the bottom surface of the substrate of the first chip 210.

[0094] Specifically, a dielectric layer is disposed on the bottom surface of the substrate of the first chip 210, and a three-dimensional heterogeneous integration bonding layer is disposed on the dielectric layer, and the first three-dimensional heterogeneous integration bonding point 212 is disposed on the three-dimensional heterogeneous integration bonding layer.

[0095] The second chip 220 has a second dielectric layer 223 and a second three-dimensional heterogeneous integration bonding layer 224 on the second metal layer 221; wherein, the second three-dimensional heterogeneous integration bonding point 222 is located on the surface of the second three-dimensional heterogeneous integration bonding layer 224.

[0096] Since the stacked interconnect structure is a face-to-back interconnect structure, the first metal layer 211 can be an internal metal layer of the first chip 210, and the second metal layer 221 can be an internal metal layer of the second chip 220.

[0097] Preparation process flow:

[0098] 1. The first metal layer 211 is the internal metal layer of the first chip 210, and the second metal layer 221 is prepared on the side of the second chip 220 away from its substrate.

[0099] The three-dimensional integration process of the first chip 210 and the second chip 220 can be flexibly selected. For example, the three-dimensional integrated FPGA chip can use copper metal interconnect technology, and the three-dimensional integrated memory chip can use copper or aluminum metal interconnect technology.

[0100] 2. Using a back-end of line (BEOL) process, a TSV (Through Silicon Via) technology is used to create and insulate a hole on the thinned substrate 202 of the first chip 210. Then, a first three-dimensional heterogeneous integration bonding point 212 is prepared through the TSV hole and interconnected with the first metal layer 211. Using a back-end process, a second dielectric layer 223 and a second three-dimensional heterogeneous integration bonding layer 224 are prepared on the second metal layer 221, and a second three-dimensional heterogeneous integration bonding point 222 is prepared on the second three-dimensional heterogeneous integration bonding layer 224.

[0101] Specifically, the first three-dimensional heterogeneous integration bonding point 212 can be a copper-processed three-dimensional heterogeneous integration bonding point and interconnected with the first metal layer 211 through a TSV via; the second three-dimensional heterogeneous integration bonding point 222 can be a copper-processed three-dimensional heterogeneous integration bonding point and interconnected with the second metal layer 221 through an inter-metal via.

[0102] 3. Align and bond the three-dimensional heterogeneous integration bonding layers of the first chip 210 and the second chip 220 to achieve three-dimensional heterogeneous bonding interconnection between the first chip 210 and the second chip 220.

[0103] like Figure 4 The above is a schematic diagram of the third type of stacked interconnect structure for a dual-layer chip provided in this application embodiment. This stacked interconnect structure belongs to a back-to-back (B2B) interconnect structure, wherein:

[0104] The first three-dimensional heterogeneous integration bonding point 212 is disposed on the three-dimensional heterogeneous integration surface on the bottom surface of the substrate of the first chip 210.

[0105] Specifically, a dielectric layer is disposed on the bottom surface of the substrate of the first chip 210, and a three-dimensional heterogeneous integration bonding layer is disposed on the dielectric layer, and the first three-dimensional heterogeneous integration bonding point 212 is disposed on the three-dimensional heterogeneous integration bonding layer.

[0106] The second three-dimensional heterogeneous integration bonding point 222 is disposed on the three-dimensional heterogeneous integration surface on the bottom surface of the substrate of the second chip 220.

[0107] Specifically, a dielectric layer is disposed on the bottom surface of the substrate of the second chip 220, and a three-dimensional heterogeneous integration bonding layer is disposed on the dielectric layer, and the second three-dimensional heterogeneous integration bonding point 222 is disposed on the three-dimensional heterogeneous integration bonding layer.

[0108] Since the stacked interconnect structure is a back-to-back interconnect structure, the first metal layer 211 can be the internal metal layer of the first chip 210, and the second metal layer 221 can be the internal metal layer of the second chip 220.

[0109] Preparation process flow:

[0110] 1. The first metal layer 211 is the inner metal layer of the first chip 210 that is close to its substrate, and the second metal layer 221 is the inner metal layer of the second chip 220 that is close to its substrate.

[0111] The three-dimensional integration process of the first chip 210 and the second chip 220 can be flexibly selected. For example, the three-dimensional integrated FPGA chip can use copper metal interconnect technology, and the three-dimensional integrated memory chip can use copper or aluminum metal interconnect technology.

[0112] 2. In the subsequent process, TSV technology is used to open and insulate the substrate of the first chip 210. Then, the first three-dimensional heterogeneous integration bonding point 212 is prepared through the TSV hole and interconnected with the first metal layer 211. In the subsequent process, TSV technology is used to open and insulate the substrate of the second chip 220. Then, the second three-dimensional heterogeneous integration bonding point 222 is prepared through the TSV hole and interconnected with the first metal layer 211.

[0113] Specifically, the first three-dimensional heterogeneous integration bonding point 212 can be a copper-processed three-dimensional heterogeneous integration bonding point and interconnected with the first metal layer 211 through a TSV via; the second three-dimensional heterogeneous integration bonding point 222 can be a copper-processed three-dimensional heterogeneous integration bonding point and interconnected with the second metal layer 221 through a TSV via.

[0114] 3. Align and bond the three-dimensional heterogeneous integration bonding layers of the first chip 210 and the second chip 220 to achieve three-dimensional heterogeneous bonding interconnection between the first chip 210 and the second chip 220.

[0115] In practical applications, face-to-face (F2F) interconnects usually have the best performance when used independently. Face-to-back (F2B), back-to-face (B2F), and back-to-back (B2B) interconnects are also effective methods and are the basic fabrication methods for constructing three-dimensional heterogeneous integrated programmable chip structures with more than two layers.

[0116] In this embodiment, the first chip 210 and the second chip 220 are arranged in groups. The multilayer chip 100 may contain multiple groups of first chips 210 and second chips 220, and the first chip 210 in one group may be the second chip 220 in another group.

[0117] Each group of first chip 210 and second chip 220 can adopt any one of the three double-layer chip stacking connection structures described above to realize a stacking connection structure of three-layer chips or more.

[0118] This embodiment takes the stacked connection structure of the third chip 230 on a two-layer chip with face-to-face (F2F) interconnection composed of the first chip 210 and the second chip 220 as an example to illustrate the specific structure and preparation method of the stacked connection structure of the three-layer chip.

[0119] like Figure 5 The above is a schematic diagram of a three-layer chip stacked connection structure provided in an embodiment of this application. In this stacked connection structure, the first chip 210 is located between the third chip 230 and the second chip 220. The first chip 210 and the second chip 220 first form a two-layer chip structure, and then the third chip 230 is stacked on the two-layer chip structure to form a three-layer chip structure.

[0120] In this stacked interconnect structure, the first chip 210 and the second chip 220 are first constructed as the face-to-face interconnect structure described above, and on this basis:

[0121] The first chip 210 also includes a third metal layer 215; a third dielectric layer 216 and a third three-dimensional heterogeneous integration bonding layer 217 are also provided on the bottom surface of the substrate of the first chip 210; a third three-dimensional heterogeneous integration bonding point 218 is provided on the surface of the third three-dimensional heterogeneous integration bonding layer 217; the third metal layer 215 interconnects the third three-dimensional heterogeneous integration bonding point 218 and the first metal layer 211 respectively;

[0122] The third chip 230 has a fourth metal layer 231; a fourth three-dimensional heterogeneous integration bonding point 232 is provided on the three-dimensional heterogeneous integration surface on one side of the third chip 230 between the first chip 210 and the third chip 230; the fourth three-dimensional heterogeneous integration bonding point 232 is interconnected with the fourth metal layer 231.

[0123] The third three-dimensional heterogeneous integration bonding point 218 and the fourth three-dimensional heterogeneous integration bonding point 232 are interconnected by three-dimensional heterogeneous integration bonding.

[0124] In this stacked connection structure, the combination of the first chip 210 and the second chip 220 corresponds to Figure 2The face-to-face interconnect structure, viewed as a whole, forms a face-to-back (viewed from top to bottom) interconnect between the third chip 230, the first chip 210, and the second chip 220; wherein, the third chip 230 can be understood as corresponding to Figure 3 The combination of the second chip 220, the first chip 210, and the second chip 220 can be understood as corresponding... Figure 3 The first chip 210. In addition, the third chip 230, along with the first chip 210, can employ... Figure 5 The back-to-back interconnect shown above can also be used. Figure 4 The back-to-back interconnect structure shown.

[0125] If the third chip 230 and the first chip 210 adopt the above-mentioned... Figure 4 In the back-to-back interconnect structure shown, the third metal layer 231 can be the internal metal layer of the third chip 230, and the third metal layer 215 is the internal metal layer of the first chip 210.

[0126] Here, we take the third chip 230 and the first chip 210 using the face-to-back interconnect structure described above as an example to illustrate its fabrication process:

[0127] 1. Using the above-described scheme, a stacked interconnect structure containing a face-to-face (F2F) interconnect of a first chip 210 and a second chip 220 is fabricated, and this combination is regarded as a whole.

[0128] 2. A third metal layer 231 is prepared on the side of the third chip 230 away from its substrate.

[0129] The 3D integration process of the third chip 230 can be flexibly selected. For example, the 3D integrated FPGA chip can use copper metal interconnect technology, and the 3D integrated memory chip can use copper or aluminum metal interconnect technology.

[0130] 3. Using a subsequent process, a corresponding dielectric layer and a corresponding three-dimensional heterogeneous integration bonding layer are prepared on the third metal layer, and a fourth three-dimensional heterogeneous integration bonding point 232 is prepared on the corresponding three-dimensional heterogeneous integration bonding layer; the substrate of the first chip 210 is thinned, and a third dielectric layer 216 is prepared on the substrate; in the subsequent process, TSV technology is used to open and insulate the thinned substrate of the first chip 210, and then a third three-dimensional heterogeneous integration bonding layer 217 is prepared through the TSV hole to form the interconnection between the third three-dimensional heterogeneous integration bonding point 218 and the third metal layer 215.

[0131] 4. Flip the third chip 230 and align it with the dual-layer chip structure for three-dimensional heterogeneous bonding interconnection. Align and bond the lower layer of the third chip 230 with the upper layer of the first chip 210 to achieve three-dimensional heterogeneous bonding interconnection between the third chip 230 and the first chip 210, ultimately realizing three-dimensional heterogeneous bonding interconnection between the first chip 210, the second chip 220, and the third chip 230.

[0132] Of course, based on the above scheme, chips can be stacked on the three-layer chip structure to form a multi-layer chip 100 with four or more layers, which will not be elaborated here.

[0133] Of course, the face-to-back (F2B) interconnect structure and back-to-back (B2B) interconnect structure mentioned above can also be constructed in this way to build a stacked interconnect structure of three-layer chips.

[0134] Specifically:

[0135] The first chip also includes a third metal layer 215; the third metal layer 215 also includes a third dielectric layer 216 and a third three-dimensional heterogeneous integration bonding layer 217 along the direction away from the substrate of the first chip; the surface of the third three-dimensional heterogeneous integration bonding layer 217 is provided with a third three-dimensional heterogeneous integration bonding point 218; the third metal layer 215 interconnects the third three-dimensional heterogeneous integration bonding point 218 and the first metal layer 211 respectively;

[0136] The third chip 230 has a fourth metal layer 231; a fourth three-dimensional heterogeneous integration bonding point 232 is provided on the three-dimensional heterogeneous integration surface on one side of the third chip 230 between the first chip 210 and the third chip 230; the fourth three-dimensional heterogeneous integration bonding point 232 is interconnected with the fourth metal layer 231.

[0137] The third three-dimensional heterogeneous integration bonding point 218 and the fourth three-dimensional heterogeneous integration bonding point 232 are in contact and interconnected.

[0138] Its preparation process and Figure 5 The fabrication process of the stacked interconnection structure of the three-layer chip shown is similar and will not be described in detail here.

[0139] In practical applications, any one of the three stacked connection structures of the two-layer chips described above can be flexibly adopted between any two adjacent layers of the multilayer chip 100 according to design requirements, thereby completing the design and fabrication of the multilayer chip 100 and meeting the fabrication requirements of different chips in different scenarios.

[0140] In a multi-layer chip 100, at least one FPGA chip and at least one memory chip are incorporated. Through three-dimensional heterogeneous integration, a high-density three-dimensional heterogeneous interconnect from the FPGA chip to the memory chip is formed. The memory chip is an independent chip supporting large-capacity storage. Simultaneously, the physical and electrical parameters of the interconnects between the chips follow semiconductor manufacturing process characteristics, forming a high-bandwidth (typically several thousand to several million bits total memory access width) and low-power memory access data channel from the FPGA chip to the memory chip. This overcomes the memory wall of limited bandwidth (typically tens of bits) for memory access between the FPGA chip and external large-capacity external memory in existing technologies.

[0141] In the aforementioned multilayer chip 100, adjacent chips are interconnected via three-dimensional heterogeneous integration, establishing high-density metal layer interconnections layer by layer within the chip. The constituent chips in the multilayer chip 100 are designed and packaged within the same three-dimensional chip, eliminating the need for functions such as driving, external level boost (output), external level buck (input), tri-state controller, ESD protection, and surge protection circuits provided by existing I / O circuits. Instead of interconnecting through existing I / O interfaces and / or I / O circuits, high-density metal layer interconnections are directly established across chips. This reduces the use of FPGA chip I / O structures, increases the interconnection density and speed between FPGA chips and memory chips, and simultaneously reduces communication power consumption between chips due to the absence of traditional I / O structures and shorter interconnection distances. This further improves the integration level of the multilayer chip and the interconnection frequency between FPGA chips and memory chips, while reducing interconnection power consumption. Consequently, the programmable routing network of widely interconnected programmable resources on the FPGA chip extends across chips to the large-capacity memory array on the memory chip, forming a wide interconnection. This enables programmable resources to access the three-dimensional heterogeneous integrated memory array on the memory chip in a high-bandwidth, programmable manner. This multi-layered chip combines the large capacity of external memory with the key advantages of BRAM (Browser RAM) interconnected via a programmable routing network (existing technology, small capacity) on FPGA chips, offering wide bit width and high bandwidth. It fundamentally overcomes the bottlenecks in I / O quantity, memory access bandwidth, and memory access power consumption of existing FPGA chips when expanding large-scale memory.

[0142] If the core operating voltages of the first chip 210 and the second chip 220 are the same, then the first signal output terminal in the first chip 210 can be directly interconnected with the first signal input terminal in the second chip 220 through a three-dimensional heterogeneous integration structure composed of the first three-dimensional heterogeneous integration bonding point 212 and the second three-dimensional heterogeneous integration bonding point 222; the common ground terminal of the first chip is interconnected with the common ground terminal of the second chip through the three-dimensional heterogeneous integration structure to form the common ground terminal VSS terminal of the multilayer chip. Thus, through three-dimensional heterogeneous integration, a metal layer interconnection is established between the first chip 210 and the second chip 220.

[0143] If the core operating voltages of the first chip 210 and the second chip 220 are different, then the signal interconnection between the first signal output terminal and the second signal output terminal needs to be converted by logic level.

[0144] In practical applications, the logic level conversion circuit can be set on the first chip 210 or the second chip 220.

[0145] like Figure 6 The diagram shown is a schematic diagram of the connection of the logic level conversion circuit when the logic level conversion circuit is set in the first chip 210 according to this embodiment. The active area of ​​the first chip 210 is provided with a first level conversion circuit and a second level conversion circuit.

[0146] Both the first level conversion circuit and the second level conversion circuit belong to the same type of level conversion circuit, such as... Figure 7 The diagram shows a connection schematic of a level conversion circuit provided in this embodiment. PMOS1 and NMOS1 constitute a first level conversion circuit, and PMOS2 and NMOS2 constitute a second level conversion circuit. The input terminals of the first level conversion circuit are connected to the gates of PMOS1 and NMOS1, respectively, and the output terminals of the second level conversion circuit are connected to the second path terminal of PMOS2 and the first path terminal of NMOS2, respectively. The second path terminal of PMOS1, the first path terminal of NMOS1, and the gates of PMOS2 and NMOS2 are interconnected and regarded as the output terminal of the first level conversion circuit and / or the input terminal of the second level conversion circuit. The first path terminal of PMOS1 is connected to the core voltage terminal (VINT_210) of the first chip 210, and the second path terminal of NMOS1 is connected to the common ground terminal (VSS) of the multilayer chip 100. The first path terminal of PMOS2 is connected to the core voltage terminal (VINT_220) of the second chip 220, and the second path terminal of NMOS2 is connected to the common ground terminal (VSS) of the multilayer chip 100.

[0147] Of course, other level conversion circuits can be used for the first and second level conversion circuits, and this is not a limitation here.

[0148] In the first chip 210, the first signal output terminal is interconnected with the input terminal of the second level conversion circuit via a first level conversion circuit; the output terminal of the second level conversion circuit is interconnected with the first signal input terminal via a three-dimensional heterogeneous integrated structure.

[0149] The first reference voltage terminal of the first level conversion circuit is interconnected with the core voltage terminal (VINT_210) of the first chip 210; the second reference voltage terminal of the first level conversion circuit is interconnected with the common ground terminal (VSS) of the multilayer chip 100.

[0150] The first reference voltage terminal of the second level conversion circuit is interconnected with the core voltage terminal (VINT_220) of the second chip 220 via a three-dimensional heterogeneous integrated structure; the second reference voltage terminal of the second level conversion circuit is interconnected with the common ground terminal (VSS) of the multilayer chip 100.

[0151] Of course, depending on actual needs, you can choose to set all, partially, or not set buffers between the first signal output terminal, the input terminal of the first level conversion circuit, the output terminal of the first level conversion circuit, the input terminal of the second level conversion circuit, the output terminal of the second level conversion circuit, and the first signal input terminal.

[0152] In the above logic level conversion circuit, the core voltage terminal (VINT_220) and common ground terminal (VSS) of the second chip 220 are connected to the first chip 210 through three-dimensional heterogeneous integration, providing a voltage reference for the second level conversion circuit. By utilizing the three-dimensional heterogeneous integration structure between the first chip 210 and the second chip 220, signal interconnection between the first chip 210 and the second chip 220 can be realized. The interconnection signal between the first chip 210 and the second chip 220 is connected to the second chip 220 across chips through the first level conversion circuit and the second level conversion circuit, and enters the level interconnection range of the second chip 220.

[0153] like Figure 8 The diagram shown is a schematic diagram of the logic level conversion circuit when the logic level conversion circuit is set in the second chip 220 according to this embodiment. The second chip 220 is provided with a first level conversion circuit and a second level conversion circuit.

[0154] The first signal output terminal is interconnected with the input terminal of the first level conversion circuit via a three-dimensional heterogeneous integrated structure; the output terminal of the first level conversion circuit is interconnected with the first signal input terminal via a second level conversion circuit.

[0155] The first reference voltage terminal of the first level conversion circuit is interconnected with the core voltage terminal (VINT_210) of the first chip 210 via a three-dimensional heterogeneous integrated structure; the second reference voltage terminal of the first level conversion circuit is interconnected with the common ground terminal (VSS) of the multilayer chip 100 via a three-dimensional heterogeneous integrated structure.

[0156] The first reference voltage terminal of the second level conversion circuit is interconnected with the core voltage terminal (VINT_220) of the second chip 220 through three-dimensional heterogeneous integration; the second reference voltage terminal of the second level conversion circuit is interconnected with the common ground terminal (VSS) of the multilayer chip 100 through three-dimensional heterogeneous integration.

[0157] Of course, depending on actual needs, you can choose to set all, partially, or not set buffers between the first signal output terminal, the input terminal of the first level conversion circuit, the output terminal of the first level conversion circuit, the input terminal of the second level conversion circuit, the output terminal of the second level conversion circuit, and the first signal input terminal.

[0158] In the above logic level conversion circuit, the core voltage terminal (VINT_210) and common ground terminal (VSS) of the first chip 210 are connected to the second chip 220 to provide a voltage reference for the first level conversion circuit. By utilizing the three-dimensional heterogeneous integration structure between the first chip 210 and the second chip 220, signal interconnection between the first chip 210 and the second chip 220 can be realized. The interconnection signal between the first chip 210 and the second chip 220 is connected across chips to the second chip 220 through the first level conversion circuit and the second level conversion circuit, and enters the level interconnection range of the second chip 220.

[0159] In this embodiment, the operating voltage of two adjacent chip cores is determined, and they are connected end-to-end directly or by a logic level conversion circuit. This eliminates the need for traditional IO protection and IO voltage selection circuits, further increasing the interconnection density and speed between chips and improving the integration level of the integrated chip.

[0160] Here, this embodiment also provides a new metal layer wiring scheme for the multilayer chip 100 to achieve different functions in different scenarios, such as... Figure 9 The diagram shown is a structural schematic of a metal layer wiring scheme for a multilayer chip provided in an embodiment of this application.

[0161] In this embodiment, the multilayer chip 100 is further provided with an adjacent fourth chip 240 and a fifth chip 250.

[0162] The fourth chip 240 and the fifth chip 250 can be the first chip 210 and the second chip 220 mentioned above, or other adjacent chips in the multilayer chip 100, and there are no specific restrictions.

[0163] The fourth chip 240 has a first metal network (i.e., metal layer network) 241 and a second metal network 242. The first metal network 241 and the second metal network 242 can be located in the same top metal layer or inner metal layer in the fourth chip 240, and the first metal network 241 and the second metal network 242 need to be interconnected.

[0164] The fifth chip 250 has a third metal network 251; the third metal network 251 may be located in the internal metal layer of the fifth chip 250.

[0165] For example, when the metal layer resources in the fourth chip 240 are insufficient to complete the first metal network 241 and the second metal network 242 in the fourth chip 240; or when the interconnection of the first metal network 241 and the second metal network 242 in the fourth chip 240 is omitted, and beneficial effects such as recycling critical wiring resources in the fourth chip 240 are produced, the present invention does not limit this, and the interconnection of the first metal network 241 and the second metal network 242 in the fourth chip 240 can be achieved by means of three-dimensional heterogeneous integration interconnection through the third metal network 251 in the fifth chip 250.

[0166] A fifth three-dimensional heterogeneous integration bonding point 243 and a sixth three-dimensional heterogeneous integration bonding point 244 are provided on the three-dimensional heterogeneous integration surface on one side of the fourth chip 240 between the fourth chip 240 and the fifth chip 250; wherein, the fifth three-dimensional heterogeneous integration bonding point 243 is interconnected with the first metal network 241; and the sixth three-dimensional heterogeneous integration bonding point 244 is interconnected with the second metal network 242.

[0167] A seventh three-dimensional heterogeneous integration bonding point 252 and an eighth three-dimensional heterogeneous integration bonding point 253 are disposed on the three-dimensional heterogeneous integration surface on one side of the fifth chip 250 between the fourth chip 240 and the fifth chip 250; wherein, the seventh three-dimensional heterogeneous integration bonding point 252 and the eighth three-dimensional heterogeneous integration bonding point 253 are interconnected with the third metal network 251; the seventh three-dimensional heterogeneous integration bonding point 252 is interconnected with the fifth three-dimensional heterogeneous integration bonding point 243; and the eighth three-dimensional heterogeneous integration bonding point 253 is interconnected with the sixth three-dimensional heterogeneous integration bonding point 244.

[0168] Here, we take a face-to-face interconnect structure similar to the one mentioned above as an example to illustrate its fabrication process:

[0169] 1. A first metal network 241 and a second metal network 243 are fabricated on the side of the fourth chip 240 away from its substrate, and a third metal network 251 is fabricated on the side of the fifth chip 250 away from its substrate.

[0170] The three-dimensional integration process of the fourth chip 240 and the fifth chip 250 can be flexibly selected. For example, the three-dimensional integrated FPGA chip can use copper metal interconnect technology, and the three-dimensional integrated memory chip can use copper or aluminum metal interconnect technology.

[0171] 2. Using a subsequent process, a dielectric layer and a three-dimensional heterogeneous integration bonding layer are fabricated on the top metal layer of the fourth chip 240, and a fifth three-dimensional heterogeneous integration bonding point 243 and a sixth three-dimensional heterogeneous integration bonding point 244 are fabricated on the three-dimensional heterogeneous integration bonding layer; using a subsequent process, a dielectric layer and a three-dimensional heterogeneous integration bonding layer are fabricated on the third metal network 251 of the fifth chip 250, and a seventh three-dimensional heterogeneous integration bonding point 252 and an eighth three-dimensional heterogeneous integration bonding point 253 are fabricated on the three-dimensional heterogeneous integration bonding layer. Specifically, the fifth three-dimensional heterogeneous integration bonding point 243 can be a copper-processed three-dimensional heterogeneous integration bonding point, and interconnected with the first metal network 241 through inter-metal vias; the sixth three-dimensional heterogeneous integration bonding point 244 can be a copper-processed three-dimensional heterogeneous integration bonding point, and interconnected with the second metal network 242 through inter-metal vias; both the fifth three-dimensional heterogeneous integration bonding point 252 and the sixth three-dimensional heterogeneous integration bonding point 253 can be copper-processed three-dimensional heterogeneous integration bonding points, and interconnected with the third metal network 251 through inter-metal vias.

[0172] After this step is completed, the seventh three-dimensional heterogeneous integration bonding point 252 and the eighth three-dimensional heterogeneous integration bonding point 253 are both interconnected with the third metal network 251; the seventh three-dimensional heterogeneous integration bonding point 252 is interconnected with the fifth three-dimensional heterogeneous integration bonding point 243, and then interconnected with the first metal network 241; the eighth three-dimensional heterogeneous integration bonding point 253 is interconnected with the sixth three-dimensional heterogeneous integration bonding point 244, and then interconnected with the second metal network 242.

[0173] 3. The three-dimensional heterogeneous integration bonding layers of the fourth chip 240 and the fifth chip 250 are aligned and bonded to achieve three-dimensional heterogeneous bonding interconnection between the fourth chip 240 and the fifth chip 250. Furthermore, the third metal network 251 in the fifth chip 250 is interconnected with the first metal network 241 and the second metal network 242 in the fourth chip 240 via the three-dimensional heterogeneous integration interconnection. Of course, while a face-to-face (F2F) interconnection structure is used here to achieve the interconnection between the first metal network 241 and the second metal network 242 in the fourth chip 240 and the fifth chip 250, a structure similar to the face-to-back (F2B), back-to-face (B2F), or back-to-back (B2B) interconnection structures described above can also be used to achieve the interconnection between the first metal network 241 and the second metal network 242 in the fourth chip 240 and the fifth chip 250. The specific process will not be elaborated here.

[0174] The above-mentioned interconnection structure between the fourth chip 240 and the fifth chip 250 introduces the fifth chip 250, which is adjacent to the fourth chip 240. A third metal network 251 is fabricated in the fifth chip 250. Through three-dimensional heterogeneous integration technology, the first metal network 241 and the second metal network 242 are interconnected in the fifth chip 250.

[0175] This novel conductive connection structure with a metal layer offers the following advantages:

[0176] 1. This metal layer conductive connection structure is implemented across dies (chips). Although it is functionally equivalent to a metal connection structure completed within a single die, and this metal layer conductive connection structure requires the use of a three-dimensional heterogeneous integration bonding structure, resulting in additional process overhead, this overhead is not generated independently by this requirement. Rather, it is an additional benefit generated in the process of combining the advantages of three-dimensional heterogeneous integration, and it helps to reduce the number of metal layers per die. Overall, it can still reduce the process cost of multi-layer chips by 100%.

[0177] 2. If the process of the fourth chip 240 is more advanced than that of the fifth chip 250, the conductive connection structure of the metal layer can be replaced by the fifth metal layer 251 of the fifth chip 250 with a lower process, which can effectively reduce the process cost.

[0178] 3. If the process of the fifth chip 250 is more advanced than that of the fourth chip 240, the conductive connection structure of the metal layer can be replaced by the fifth metal layer 251 of the fifth chip 250 with a higher process, which helps to supplement the metal connection density in the fifth chip 250 with a lower process and improve the overall integration of the multilayer chip 100.

[0179] 4. If the metal connection density of the fourth chip 240 is higher than that of the fifth chip 250, the conductive connection structure of the metal layer can be replaced by the fifth metal layer 251 in the fifth chip 250, which helps to reduce the metal connection density of the fourth chip 240, increase the metal connection density in the fifth chip 250, and optimize the overall metal connection density of the multilayer chip 100.

[0180] 5. If the metal connection density of the fourth chip 240 and the metal connection density of the fifth chip 250 are both low, the metal layer conductive connection structure can be replaced by the fifth metal layer 251 in the fifth chip 250, which can reduce one metal layer and help reduce the overall cost.

[0181] The above structure may include one or more of the following combinations:

[0182] 1. A multilayer chip includes at least one of a multilayer die or a multilayer wafer;

[0183] 2. The programmable chip structure may also include at least one of a programmable die or a programmable wafer;

[0184] 3. The memory chip includes at least one of the following: memory die or memory wafer;

[0185] 4. The stored FPGA chips include at least one of FPGA chips or FPGA wafers;

[0186] 5. The chip containing the eFPGA module includes at least one of the following: a die containing the eFPGA module or a wafer containing the eFPGA module.

[0187] 6. The first chip includes at least one of a first die or a first wafer;

[0188] 7. The second chip includes at least one of a second die or a second wafer;

[0189] 8. The third chip includes at least one of a third die or a third wafer;

[0190] 9. The fourth chip includes at least one of a fourth die or a fourth wafer;

[0191] 10. The fifth chip includes at least one of a fifth die or a fifth wafer.

[0192] If the programmable chip structure adopts a wafer structure, when fabricating the wafer structure, it can also be fabricated in units of wafers according to the process flow of the multilayer chip 100 mentioned above, and three-dimensional heterogeneous integration can be performed.

[0193] When fabricating this wafer structure, it is also possible to follow the process flow of the multilayer chip 100 described above, and partially fabricate on a wafer-by-wafer basis, and perform three-dimensional heterogeneous integration. Specifically, there are two methods: first, perform three-dimensional heterogeneous integration on some wafer layers to form an intermediate product, and then perform the above iteration on the remaining wafer layers and the intermediate product until the fabrication is completed; or first, perform three-dimensional heterogeneous integration on some wafer layers to form an intermediate product, and then cut the intermediate product into dies, and perform die-to-die three-dimensional heterogeneous integration with other functional dies to complete the fabrication.

[0194] The technical solutions described in the embodiments of this application have at least the following technical effects or advantages:

[0195] In the programmable chip structure of this application embodiment, multiple chips are stacked and connected to form a multi-layer chip. Adjacent first and second chips are connected by three-dimensional heterogeneous integration bonding to achieve interconnection between the first and second chips. This application utilizes three-dimensional heterogeneous integration technology and semiconductor metal processing technology to achieve stacked interconnection between chips. This ensures that the physical and electrical parameters of the interconnects between chips follow the characteristics of semiconductor processing technology, reducing the use of vias, interconnects, and I / O structures, and increasing the interconnection density and interconnection speed between chips. At the same time, the three-dimensional heterogeneous integration interconnection technology does not use traditional I / O structures and has a shorter interconnection distance, reducing the communication power consumption between chips. This improves the integration level and interconnection frequency of the integrated chip and reduces interconnection power consumption, thereby increasing the access bandwidth of the programmable chip structure while reducing its operating power consumption.

[0196] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0197] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0198] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A three-dimensional heterogeneous integrated programmable chip structure, characterized in that, The programmable chip structure includes: a multi-layer chip stacked together; the chip in the multi-layer chip includes one or more of the following: an FPGA chip, a chip containing an eFPGA module, and a memory chip; The multilayer chip has an adjacent first chip and a second chip. The first chip has a first metal layer; a first three-dimensional heterogeneous integration bonding point is provided on the three-dimensional heterogeneous integration surface on one side of the first chip between the first chip and the second chip; the first three-dimensional heterogeneous integration bonding point is interconnected with the first metal layer; The second chip has a second metal layer; a second three-dimensional heterogeneous integration bonding point is provided on the three-dimensional heterogeneous integration surface on one side of the second chip between the first chip and the second chip; the second three-dimensional heterogeneous integration bonding point is interconnected with the second metal layer; The first three-dimensional heterogeneous integration bonding point and the second three-dimensional heterogeneous integration bonding point are in contact and interconnected to form a three-dimensional heterogeneous integration structure; The first chip has a first dielectric layer and a first three-dimensional heterogeneous integration bonding layer on the first metal layer; wherein the first three-dimensional heterogeneous integration bonding point is located on the surface of the first three-dimensional heterogeneous integration bonding layer; The second chip has a second dielectric layer and a second three-dimensional heterogeneous integration bonding layer on the second metal layer; wherein the second three-dimensional heterogeneous integration bonding point is located on the surface of the second three-dimensional heterogeneous integration bonding layer; The first three-dimensional heterogeneous integration bonding point includes a number of interconnection bonding points, and the collection of these interconnection bonding points is used together to realize the cross-chip interconnection function of signals; the second three-dimensional heterogeneous integration bonding point includes a number of interconnection bonding points, and the collection of these interconnection bonding points is used together to realize the cross-chip interconnection function of signals. The first chip has a first signal output terminal; the second chip has a first signal input terminal; The common ground terminal of the first chip is interconnected with the common ground terminal of the second chip through the three-dimensional heterogeneous integration structure to form the common ground terminal of the multilayer chip; The first signal output terminal is interconnected with the first signal input terminal through the three-dimensional heterogeneous integrated structure.

2. The programmable chip structure according to claim 1, characterized in that, In the multi-layer chip, the third chip is disposed above the first chip and adjacent to the first chip; The first chip also includes a third metal layer; a third dielectric layer and a third three-dimensional heterogeneous integration bonding layer are also provided on the bottom surface of the substrate of the first chip; the surface of the third three-dimensional heterogeneous integration bonding layer is provided with third three-dimensional heterogeneous integration bonding points; the third metal layer interconnects the third three-dimensional heterogeneous integration bonding points and the first metal layer respectively; The third chip has a fourth metal layer; a fourth three-dimensional heterogeneous integration bonding point is provided on the three-dimensional heterogeneous integration surface on one side of the third chip between the first chip and the third chip; the fourth three-dimensional heterogeneous integration bonding point is interconnected with the fourth metal layer; The third three-dimensional heterogeneous integration bonding point is in contact with and interconnected with the fourth three-dimensional heterogeneous integration bonding point.

3. The programmable chip structure according to claim 1, characterized in that, The first three-dimensional heterogeneous integration bonding point is disposed on the three-dimensional heterogeneous integration surface on the bottom surface of the substrate of the first chip; The second chip has a second dielectric layer and a second three-dimensional heterogeneous integration bonding layer on the second metal layer; wherein the second three-dimensional heterogeneous integration bonding point is located on the surface of the second three-dimensional heterogeneous integration bonding layer.

4. The programmable chip structure according to claim 1, characterized in that, The first three-dimensional heterogeneous integration bonding point is disposed on the three-dimensional heterogeneous integration surface on the bottom surface of the substrate of the first chip; The second three-dimensional heterogeneous integration bonding point is disposed on the three-dimensional heterogeneous integration surface on the bottom surface of the substrate of the second chip.

5. The programmable chip structure according to claim 3 or 4, characterized in that, In the multi-layer chip, the third chip is disposed above the first chip and adjacent to the first chip; The first chip also includes a third metal layer; the third metal layer further includes a third dielectric layer and a third three-dimensional heterogeneous integration bonding layer along a direction away from the substrate of the first chip; the surface of the third three-dimensional heterogeneous integration bonding layer is provided with third three-dimensional heterogeneous integration bonding points; the third metal layer interconnects the third three-dimensional heterogeneous integration bonding points and the first metal layer respectively; The third chip has a fourth metal layer; a fourth three-dimensional heterogeneous integration bonding point is provided on the three-dimensional heterogeneous integration surface on one side of the third chip between the first chip and the third chip; the fourth three-dimensional heterogeneous integration bonding point is interconnected with the fourth metal layer; The third three-dimensional heterogeneous integration bonding point is in contact with and interconnected with the fourth three-dimensional heterogeneous integration bonding point.

6. The programmable chip structure according to claim 1, characterized in that, The first chip includes a first level conversion circuit and a second level conversion circuit; In the first chip, the first signal output terminal is interconnected with the input terminal of the second level conversion circuit via the first level conversion circuit; the output terminal of the second level conversion circuit is interconnected with the first signal input terminal via the three-dimensional heterogeneous integrated structure. The first reference voltage terminal of the first level conversion circuit is interconnected with the core voltage terminal of the first chip; the second reference voltage terminal of the first level conversion circuit is interconnected with the common ground terminal of the multilayer chip. The first reference voltage terminal of the second level conversion circuit is interconnected with the core voltage terminal of the second chip via the three-dimensional heterogeneous integrated structure; the second reference voltage terminal of the second level conversion circuit is interconnected with the common ground terminal of the multilayer chip.

7. The programmable chip structure according to claim 1, characterized in that, The second chip includes a first level conversion circuit and a second level conversion circuit; The first signal output terminal is interconnected with the input terminal of the first level conversion circuit via the three-dimensional heterogeneous integrated structure; the output terminal of the first level conversion circuit is interconnected with the first signal input terminal via the second level conversion circuit. The first reference voltage terminal of the first level conversion circuit is interconnected with the core voltage terminal of the first chip via the three-dimensional heterogeneous integrated structure; the second reference voltage terminal of the first level conversion circuit is interconnected with the common ground terminal of the multilayer chip via the three-dimensional heterogeneous integrated structure. The first reference voltage terminal of the second level conversion circuit is interconnected with the core voltage terminal of the second chip; the second reference voltage terminal of the second level conversion circuit is interconnected with the common ground terminal of the multilayer chip.

8. The programmable chip structure according to any one of claims 1 to 4, characterized in that, The multilayer chip includes an adjacent fourth chip and a fifth chip; The fourth chip has a first metal network and a second metal network; the fifth chip has a third metal network; A fifth three-dimensional heterogeneous integration bonding point and a sixth three-dimensional heterogeneous integration bonding point are disposed on the three-dimensional heterogeneous integration surface on one side of the fourth chip between the fourth chip and the fifth chip; wherein, the fifth three-dimensional heterogeneous integration bonding point interconnects the first metal network; and the sixth three-dimensional heterogeneous integration bonding point interconnects the second metal network; A seventh three-dimensional heterogeneous integration bonding point and an eighth three-dimensional heterogeneous integration bonding point are disposed on the three-dimensional heterogeneous integration surface on one side of the fifth chip between the fourth chip and the fifth chip; wherein, the seventh three-dimensional heterogeneous integration bonding point and the eighth three-dimensional heterogeneous integration bonding point are interconnected with the third metal network; the seventh three-dimensional heterogeneous integration bonding point is interconnected with the fifth three-dimensional heterogeneous integration bonding point; and the eighth three-dimensional heterogeneous integration bonding point is interconnected with the sixth three-dimensional heterogeneous integration bonding point.

9. The programmable chip structure according to claim 1, characterized in that, The FPGA chip includes FPGA chips and / or FPGA wafers; The chip containing the eFPGA module includes a die containing the eFPGA module and / or a wafer containing the eFPGA module. The memory chip includes memory chips and / or memory wafers.

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