A three-dimensional heterogeneous integrated programmable chip structure and electronic device

Abstract

The present application relates to the technical field of integrated chip, and especially relates to a three-dimensional heterogeneous integrated programmable chip structure and electronic equipment. In the programmable chip structure, at least two chips are connected in a stack; in the stack structure between the outermost chip and a target chip, two adjacent chips are connected through a three-dimensional heterogeneous integrated bonding structure; if a third chip is adjacent to the first chip on the side far from the second chip, the metal layer close to the second chip is connected to the metal layer close to the third chip in the first chip; a target lead-out structure corresponding to the target chip is arranged on the interface of the outermost chip; and the target lead-out structure is connected to the metal layer close to the second chip in the outermost chip. The present application uses three-dimensional heterogeneous integration technology, reduces the use of holes, interconnection lines and IO structures, increases the interconnection density and speed between chips, and improves the integration of integrated chips.

Description

Technical Field

[0001] This invention relates to the field of integrated chip technology, and more particularly to a three-dimensional heterogeneous integrated programmable chip structure and electronic device. Background Technology

[0002] Existing packaging technologies such as SIP (System In a Package) and MCM (Multichip Module) require bonding the chip and other circuits to a substrate or silicon interposer, and interconnecting them through through silicon vias (TSVs) to form a 2.5D package, enabling large-scale interconnection between the chip and other circuits.

[0003] However, 2.5D packaging inevitably uses vias, interconnects, and I / O (Input-Output) structures to achieve signal interconnection between chips. Therefore, compared to on-chip integration (where interconnect distances are typically on the order of ten micrometers), 2.5D packaging has the following disadvantages:

[0004] 1. The interconnect density of 2.5D packages is significantly lower (interconnect spacing is typically in the thousands of micrometers).

[0005] 2. In 2.5D packaging, the physical distribution parameters of the interconnects between chips are relatively large, and the signal interconnection frequency and power consumption are significantly inferior to those of on-chip integration.

[0006] 3. In 2.5D packaging, additional I / O overhead is required, which further widens the gap in power consumption and bandwidth between 2.5D packaging and on-chip integration.

[0007] It is evident that the aforementioned shortcomings of 2.5D packaging have become a performance bottleneck for high-speed, large-scale programmable digital computing / processing systems.

[0008] Therefore, how to improve the integration level of integrated chips is a technical problem that urgently needs to be solved. Summary of the Invention

[0009] This invention provides a three-dimensional heterogeneous integrated programmable chip structure and electronic device to improve the integration level of integrated chips.

[0010] To achieve the above objectives, the present invention provides the following solution:

[0011] In a first aspect, embodiments of the present invention provide 1. a three-dimensional heterogeneous integrated programmable chip structure, the programmable chip structure comprising: at least two chips; any one of the at least two chips is an FPGA chip and / or a chip containing an eFPGA module;

[0012] The at least two chips are stacked and connected;

[0013] In the stacked chip structure between the outermost chip and the target chip, the metal layer of the first chip near the second chip and the metal layer of the second chip near the first chip are interconnected through a three-dimensional heterogeneous integration bonding structure; wherein, the outermost chip includes the uppermost chip of the programmable chip structure and / or the lowermost chip of the programmable chip structure; if the first chip is also adjacent to a third chip on the side away from the second chip, then the metal layer near the second chip interconnects the metal layer of the first chip near the third chip;

[0014] The outermost chip has an outermost interface; the outermost interface has a target lead-out structure corresponding to the target chip; the target lead-out structure interconnects the metal layer of the outermost chip that is close to the second outermost chip.

[0015] In one possible embodiment, the target lead-out structure includes a layered PAD structure, a bump structure, or a bonding structure to lead out a metal layer in the target chip.

[0016] In one possible embodiment, the three-dimensional heterogeneous integrated bonding structure includes:

[0017] The first three-dimensional heterogeneous integration bonding point is located on the three-dimensional heterogeneous integration surface on one side of the first chip between the first chip and the second chip, and is interconnected with the metal layer near the second chip.

[0018] The second three-dimensional heterogeneous integration bonding point is located on the three-dimensional heterogeneous integration surface on one side of the second chip between the second chip and the first chip, and interconnects the metal layer close to the first chip and the first three-dimensional heterogeneous integration bonding point to realize the interconnection of the metal layers of the first chip and the second chip.

[0019] In one possible embodiment, the target chip includes a first target chip; the target lead-out structure includes a first target lead-out structure corresponding to the first target chip; wherein the first target lead-out structure is disposed in an interconnect first through-silicon via on the outermost interface;

[0020] The first target chip includes a first target test circuit and a first functional circuit;

[0021] The external lead-out terminal of the first functional circuit is interconnected with the first target lead-out structure through the first target test circuit and each three-dimensional heterogeneous integrated bonding structure in the first stacked chip structure; wherein, the first stacked chip structure is the part of the stacked chip structure from the outermost chip to the first target chip.

[0022] In one possible embodiment, a second through-silicon via (TSV) is further formed on the outermost interface; the second TSV is provided with an interconnecting second target lead-out structure; and the outermost chip is provided with a second target test circuit and a second functional circuit.

[0023] The external leads of the second functional circuit are interconnected with the second target lead structure through the second target test circuit.

[0024] In one possible embodiment, the target chip includes one or more second target chips; the target lead-out structure includes a first general lead-out structure corresponding to each second target chip; wherein the first general lead-out structure is disposed in an interconnect third through-silicon via on the outermost interface;

[0025] The outermost chip is provided with a multiplexing test circuit and a third functional circuit; the second target chip is provided with a fourth functional circuit;

[0026] The external leads of the third functional circuit are interconnected with the first general lead structure through the multiplexing test circuit;

[0027] The external leads of the fourth functional circuit are interconnected with the first general lead structure through the three-dimensional heterogeneous integrated bonding structures in the second stacked chip structure and the multiplexing test circuit; wherein, the second stacked chip structure is the part of the stacked chip structure from the outermost chip to the second target chip.

[0028] In one possible embodiment, the target chip further includes a third target chip; the target lead-out structure further includes a third target lead-out structure corresponding to the third target chip; wherein the third target lead-out structure is disposed in an interconnect fourth through-silicon via on the outermost interface;

[0029] The second target chip includes a third target testing circuit and a fourth functional circuit;

[0030] The external lead-out terminal of the fourth functional circuit is interconnected with the third target lead-out structure through the third target test circuit and each three-dimensional heterogeneous integrated bonding structure in the third stacked chip structure; wherein, the third stacked chip structure is the part of the stacked chip structure from the outermost chip to the third target chip.

[0031] In one possible embodiment, the target chip includes a fourth target chip and a fifth target chip; the target lead-out structure includes a fourth target lead-out structure corresponding to the fourth target chip, and a fifth target lead-out structure corresponding to the fifth target chip; wherein the fourth target lead-out structure is disposed in a fifth interconnect via on the outermost interface, and the fifth target lead-out structure is disposed in a sixth interconnect via on the outermost interface; the fifth target chip is a redundant spare chip of the fourth target chip;

[0032] The fourth target chip is provided with a first target repair circuit and a fifth functional circuit; the fifth target chip is provided with a second target repair circuit and a sixth functional circuit;

[0033] The external lead-out terminal of the fifth functional circuit is interconnected with the fourth target lead-out structure through the first target repair circuit and each three-dimensional heterogeneous integrated bonding structure in the fourth stacked chip structure; wherein, the fourth stacked chip structure is the part of the stacked chip structure from the outermost chip to the fourth target chip;

[0034] The external lead-out terminal of the sixth functional circuit is interconnected with the fifth target lead-out structure through the second target repair circuit and each three-dimensional heterogeneous integrated bonding structure in the fifth stacked chip structure; wherein, the fifth stacked chip structure is the part of the stacked chip structure from the outermost chip to the fifth target chip.

[0035] In one possible embodiment, the target chip includes: one or more sixth target chips, and one or more seventh target chips; the target lead-out structure includes a second general lead-out structure corresponding to each sixth target chip; a second general lead-out structure corresponding to each seventh target chip; wherein the second general lead-out structure is disposed in an interconnect seventh through-silicon via on the outermost interface; the seventh target chip and the sixth target chip are redundant backup chips, and / or, the seventh target chip and the outermost chip are redundant backup chips;

[0036] The outermost chip is provided with a reuse and repair circuit and a seventh functional circuit; the sixth target chip is provided with an eighth functional circuit; the seventh target chip is provided with a ninth functional circuit;

[0037] The external lead-out terminals of the seventh functional circuit are interconnected with the second general lead-out structure through the multiplexing and repair circuit;

[0038] The external lead-out terminals of the eighth functional circuit are interconnected with the second general lead-out structure through the three-dimensional heterogeneous integrated bonding structures in the sixth stacked chip structure and the multiplexing repair circuit; wherein, the sixth stacked chip structure is the part of the stacked chip structure from the outermost chip to the sixth target chip;

[0039] The external lead-out terminals of the ninth functional circuit are interconnected with the second general lead-out structure through the three-dimensional heterogeneous integrated bonding structures in the seventh stacked chip structure and the multiplexing repair circuit; wherein, the seventh stacked chip structure is the part of the stacked chip structure from the outermost chip to the seventh target chip.

[0040] In one possible embodiment, the target chip further includes an eighth target chip; the target lead-out structure further includes a sixth target lead-out structure corresponding to the eighth target chip; wherein the sixth target lead-out structure is disposed in an eighth interconnect silicon via on the outermost interface; the eighth target chip and the sixth target chip are redundant backup chips for each other, the eighth target chip and the seventh target chip are redundant backup chips for each other, and / or, the eighth target chip and the outermost chip are redundant backup chips for each other;

[0041] The eighth target chip is equipped with a second target repair circuit and a tenth functional circuit;

[0042] The external lead-out terminal of the tenth functional circuit is interconnected with the sixth target lead-out structure through the second target repair circuit and each three-dimensional heterogeneous integrated bonding structure in the eighth stacked chip structure; wherein, the eighth stacked chip structure is the part of the stacked chip structure from the outermost chip to the eighth target chip.

[0043] In one possible embodiment, the chip is an FPGA chip, a chip containing an eFPGA module, or a memory chip.

[0044] In a second aspect, embodiments of the present invention provide an electronic device, including a processor, wherein any computing core in the processor includes a programmable chip structure as described in any one of claims 1 to 11.

[0045] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0046] In this invention, multiple chips are stacked together to form a stacked chip structure. Adjacent chips are interconnected by corresponding three-dimensional heterogeneous integration bonding structures. Simultaneously, the outermost chip's outermost interface has a target lead-out structure corresponding to the target chip, enabling the outward lead-out of signals related to the target chip. This invention utilizes three-dimensional heterogeneous integration technology and semiconductor metal processing techniques to achieve stacked interconnection between chips. This ensures that the physical and electrical parameters of the interconnects conform to semiconductor process characteristics, reducing the use of vias, interconnects, and I / O structures, increasing interconnection density and speed, and improving the integration level of the integrated chip. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A schematic diagram of a three-dimensional heterogeneous integrated programmable chip structure provided in an embodiment of the present invention;

[0049] Figure 2 This is a schematic diagram of a programmable chip structure including a three-layer chip structure, provided by an embodiment of the present invention.

[0050] Figure 3 This is a schematic diagram of a programmable chip structure including a three-layer chip structure, provided by an embodiment of the present invention.

[0051] Figure 4 This is a schematic diagram of a programmable chip structure including a two-layer chip structure provided by an embodiment of the present invention;

[0052] Figure 5 This is a schematic diagram of a programmable chip structure comprising a two-layer chip structure, provided as an embodiment of the present invention.

[0053] Explanation of reference numerals in the attached figures: 100 is the programmable chip structure, 110 is the outermost interface, 120 is the target lead-out structure, 121 is the first target lead-out structure, 122 is the second target lead-out structure, 123 is the first general-purpose lead-out structure, 131 is the first through-silicon via (TSV), 132 is the second TSV, 133 is the third TSV, 200 is the chip, 210 is the first chip, 220 is the second chip, 300 is the three-dimensional heterogeneous integration bonding structure, 301 is the first three-dimensional heterogeneous integration bonding point, and 302 is the second three-dimensional heterogeneous integration bonding point. Detailed Implementation

[0054] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0055] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0056] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0057] In this embodiment, the term "input interconnect terminal" is used, which can be understood as an interconnect terminal, or an interconnect terminal, or a terminal that has both input and output functions.

[0058] like Figure 1 The diagram shown is a schematic diagram of a three-dimensional heterogeneous integrated programmable chip structure provided in an embodiment of the present invention. The programmable chip structure 100 includes at least two chips 200.

[0059] Of the two chips 200, at least one chip 200 is an FPGA (Field Programmable Gate Array) chip and / or a chip containing an eFPGA (Embedded Field Programmable Gate Array) module, thereby forming a programmable chip structure.

[0060] In practical applications, each chip 200 can be any of the following: FPGA chip, chip containing eFPGA module, and memory chip.

[0061] The memory chip can be any one or a combination of several of the following memory arrays: Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Flash Memory, RRAM or ReRAM, MRAM, FeRAM, OxRAM, CBRAM, PCM, STT-MRAM, and EEPROM.

[0062] In this embodiment, at least two chips 200 are stacked and connected. Each chip 200 may have a stacked functional layer and a substrate. The functional layer may also have an active layer and functional circuits such as ASICs that implement computing and / or processing functions. The functional circuits of different chips in the programmable chip structure need to communicate and cooperate to realize the specific computing and / or processing functions of the programmable chip structure. Therefore, each chip also has a metal layer (e.g., an internal metal layer).

[0063] When two adjacent chips are stacked together, they can be connected in a face-to-face (F2F) manner, where the two chips are stacked with their near top metal surfaces in contact and aligned. They can also be connected in a back-to-back (B2B) manner, where the substrates of the two chips are stacked with their near top metal surfaces in contact and aligned. Alternatively, they can be connected in a face-to-back (F2B) or back-to-face (B2F) manner, where the near top metal surface of one chip is in contact and aligned with the substrate of another chip. There are no specific restrictions on the method.

[0064] When two adjacent chips are stacked together, a three-dimensional heterogeneous interconnect is achieved within the three-dimensional programmable chip. This eliminates the need for functions provided by existing I / O circuits, such as driving, external level boost (output), external level buck (input), tri-state controllers, ESD protection, and surge protection circuits. It also bypasses existing I / O interfaces and / or I / O circuits, directly establishing a high-density metal layer interconnect across chips. This three-dimensional heterogeneous interconnect, achieved through semiconductor metal processing technology, allows the physical and electrical parameters of the interconnects to conform to semiconductor process characteristics. This reduces the use of vias, interconnects, and I / O structures, increasing interconnect density and speed. Simultaneously, because it avoids traditional I / O structures and has shorter interconnect distances, it reduces communication power consumption between chips. This, in turn, improves the integration density and interconnect frequency of the integrated chip while reducing interconnect power consumption. This allows for the extensive interconnection of programmable resources on FPGA chips and / or chips containing eFPGA modules via a programmable routing network, extending across the chip to a large-capacity memory array on the memory chip. This extensive interconnection enables high-bandwidth, programmable access to the large-capacity memory array on the memory chip through three-dimensional heterogeneous integration. The three-dimensional integrated chip simultaneously possesses the large capacity of external memory and the key advantages of large bit width and high bandwidth, similar to BRAM (existing technology, small capacity) memory cells interconnected via a programmable routing network on FPGA chips and / or chips containing eFPGA modules. This fundamentally overcomes the bottlenecks in I / O quantity, memory access bandwidth, and memory access power consumption when extending large-scale memory using existing FPGA chips and / or chips containing eFPGA modules.

[0065] In this embodiment, the topmost chip and / or the bottommost chip of the programmable chip structure 100 are referred to as the outermost chip. The target chip can be any chip in the programmable chip structure 100 other than the outermost chip. In practical applications, it is necessary to bring out the relevant signals of the target chip. The following is a specific solution in this embodiment:

[0066] In the stacked chip structure between the outermost chip and the target chip, the metal layer of the first chip 210 near the second chip 220 and the metal layer of the second chip 220 near the first chip 210 are interconnected through a three-dimensional heterogeneous integration bonding structure 300.

[0067] In this embodiment, a three-dimensional heterogeneous integration bonding structure 300 is provided between two adjacent chips in the stacked chip structure 100. The two adjacent chips are interconnected through the corresponding three-dimensional heterogeneous integration bonding structure 300. In this way, the functional circuits in the two chips can be interconnected through the three-dimensional heterogeneous integration bonding structure 300, and the metal layers in the first chip 210 and the second chip 220 can be directly interconnected.

[0068] Direct interconnection of metal layers avoids the need for high-density three-dimensional heterogeneous integration through existing I / O interfaces and / or I / O circuits. In practical applications, the number of interconnects can reach thousands to millions; the interconnect spacing can reach 1 to 10 micrometers, which is not limited in this application.

[0069] The first chip 210 and the second chip 220 are directly interconnected across the chip metal layer without any I / O circuit for level conversion. When the core voltages of the first chip 210 and the second chip 220 are different, level conversion is still required for the interconnection.

[0070] If the side of the first chip 210 furthest from the second chip 220 is adjacent to the third chip, meaning that the stacked chip structure between the outermost chip and the target chip is at least a three-layer structure, then the metal layer in the first chip 210 closest to the second chip 220 interconnects the metal layer in the first chip 210 closest to the third chip.

[0071] In this case, a new pair of adjacent chips are formed between the third chip and the first chip 210. The third chip can be understood as the new first chip 210 in this pair of adjacent chips, and the first chip 210 can be understood as the new second chip 220 in this pair of adjacent chips.

[0072] Based on this, the outermost chip has an outermost interface; the outermost interface has a target lead-out structure corresponding to the target chip; the target lead-out structure interconnects the metal layer in the outermost chip that is close to the second outermost chip.

[0073] In practical applications, the target lead-out structure may include a layered PAD structure, a bump structure, or a bonding structure to lead out the metal layer in the target chip.

[0074] If the outermost interface is set on the substrate of the outermost chip, then a through-silicon via (TSV) process is required to create an opening in the substrate of the outermost chip to achieve interconnection between the target lead-out structure and the metal layer in the outermost chip that is close to the next outermost chip.

[0075] In the above structure, the metal layer of the outermost chip closest to the second outermost chip can interconnect the metal layer of the target chip through various three-dimensional heterogeneous integration bonding structures 300; wherein, the outermost chip and the second outermost chip are arranged adjacent to each other; finally, the metal layer of the outermost chip closest to the second outermost chip can lead out the signal of the metal layer interconnecting the target chip through the target lead-out structure.

[0076] In practical applications, the three-dimensional heterogeneous integrated bonding structure 300 may include:

[0077] The first three-dimensional heterogeneous integration bonding point 301 is located on the end face of the first chip 210 that contacts the second chip 220 in two adjacent chips, and is interconnected with the metal layer 211 of the first chip 210 that is close to the second chip 220.

[0078] The second three-dimensional heterogeneous integration bonding point 302 is located on the end face of the second chip 220 that contacts the first chip 210 in two adjacent chips. It is interconnected with the metal layer 221 of the second chip 220 that is close to the first chip 210, and is in contact with and interconnected with the first three-dimensional heterogeneous integration bonding point 301.

[0079] The first three-dimensional heterogeneous integration bonding point 301 and the second three-dimensional heterogeneous integration bonding point 302 can be implemented using hybrid bonding technology to achieve three-dimensional heterogeneous integration interconnection. The first three-dimensional heterogeneous integration bonding point 301 can contain a number of interconnection points, and the collection of these interconnection points is used together to realize the cross-chip interconnection function of signals; similarly, the second three-dimensional heterogeneous integration bonding point 302 can also contain a number of interconnection points, and the collection of these interconnection points is used together to realize the cross-chip interconnection function of signals.

[0080] In this embodiment, multiple chips are stacked together to form a stacked chip structure. Adjacent chips are connected by corresponding three-dimensional heterogeneous integration bonding structures 300 to achieve interconnection between adjacent chips. Simultaneously, a target lead-out structure corresponding to the target chip is provided on the outermost interface of the outermost chip to allow the outward lead-out of signals related to the target chip. This embodiment utilizes three-dimensional heterogeneous integration technology and semiconductor metal processing technology to achieve stacked interconnection between chips. This ensures that the physical and electrical parameters of the interconnects between chips conform to the characteristics of semiconductor processing technology, reducing the use of vias, interconnects, and I / O structures, increasing the interconnection density and speed between chips, and improving the integration level of the integrated chip.

[0081] This provides Figure 2 To illustrate the programmable chip structure in this embodiment, such as Figure 2 The diagram shows a schematic of a programmable chip structure with a three-layer chip structure provided by an embodiment of the present invention. In this programmable chip structure, the outermost chip and the second outermost chip are stacked and connected in an F2B manner, and the second outermost chip and the third chip are stacked and connected in an F2F manner. The second outermost chip is the target chip, and its active layer A network needs to be brought out from the outermost interface on the outermost chip.

[0082] Specifically, the A network in the outermost chip can be a PAD signal or a Bump signal within the chip. Using existing technology, the A network can be connected to the inner metal layer of the outermost chip through internal metal lines and holes.

[0083] The substrate of the outermost chip is thinned, and through-silicon vias are fabricated on the substrate. A three-dimensional heterogeneous integration bonding structure 300 using copper process is used to achieve three-dimensional heterogeneous integration bonding with the outermost chip. In this way, the A network can be connected to the internal metal layer of the outermost chip through the three-dimensional heterogeneous integration bonding structure 300.

[0084] In the outermost chip, using existing technology, the internal metal layers of the outermost chip that are far from the second outermost chip are interconnected with the internal metal layers that are close to the second outermost chip through the internal metal lines and holes of the outermost chip, thereby connecting the A network to the metal layer close to the outermost interface.

[0085] The substrate of the outermost chip is the outermost interface of this programmable chip structure. Through-silicon vias (TSVs) are disposed on it, interconnecting the target lead-out structure. Using existing technology, the internal metal layer near the substrate can be connected to the target lead-out structure through internal metal lines and vias of the outermost chip. This achieves the goal of connecting the A-network to the target lead-out structure at the outermost interface, optimizing the unified lead-out of the PAD / Bump signals from the three-dimensional heterogeneous integrated target chip through the outermost interface. A TSV can be a collection of several TSVs used together to achieve cross-chip signal interconnection.

[0086] This provides Figure 3 To illustrate the programmable chip structure in this embodiment, such as Figure 3 The diagram shows a schematic of a programmable chip structure comprising a three-layer chip structure according to an embodiment of the present invention. In this programmable chip structure, the first chip 210 is the outermost chip, the second chip 220 is the next outermost chip, and the third chip 230 is the third layer chip. The first chip 210 and the second chip 220 are stacked and connected in an F2B manner, and the second chip 220 and the third layer chip 230 are stacked and connected in an F2F manner. The third layer chip 230 is the target chip, and its B network needs to be brought out from the outermost interface on the outermost chip.

[0087] Specifically, the B network in the third-layer chip 230 can be a PBD lead-out signal or a Bump lead-out signal within the chip. Using existing technology, the B network can be connected to the internal metal layer of the third-layer chip through internal metal lines and holes.

[0088] A three-dimensional heterogeneous integration bonding interface is provided on the upper surface of the third-layer chip 230 and the second chip 220. The three-dimensional heterogeneous integration bonding structure 300 of copper process is used to realize the three-dimensional heterogeneous integration bonding between the third-layer chip and the second chip 220. In this way, the B network can be connected to the internal metal layer of the second chip 220 through the three-dimensional heterogeneous integration bonding structure 300.

[0089] Using existing technology, the internal metal layer of the second chip 220 can be connected to the internal metal layer of the second chip 220 through internal metal lines and holes, thereby connecting the B network to the internal metal layer of the second chip 220.

[0090] The substrate of the second chip 220 is thinned and has through-silicon vias fabricated on it. It is then bonded to the first chip 210 via a three-dimensional heterogeneous integration bonding structure 300 using copper technology. In this way, the B network can be connected to the inner metal layer of the outermost chip through the three-dimensional heterogeneous integration bonding structure 300.

[0091] In the outermost chip, using existing technology, the internal metal layer of the outermost chip, which is far from the second outermost chip, is interconnected with the internal metal layer of the second outermost chip through the internal metal lines and holes, thereby connecting the B network to the metal layer close to the outermost interface.

[0092] The substrate of the outermost chip is the outermost interface of this programmable chip structure. Through-silicon vias (TSVs) are disposed on it, interconnecting the target lead-out structure. Using existing technology, the internal metal layer near the substrate can be connected to the target lead-out structure through internal metal lines and vias of the outermost chip. This achieves the goal of connecting the B network to the target lead-out structure at the outermost interface, optimizing the unified lead-out of the PBD / Bump signals from the three-dimensional heterogeneous integrated target chip through the outermost interface. A TSV can be a collection of several TSVs used together to achieve cross-chip signal interconnection.

[0093] exist Figure 2 and Figure 3 In the example below, similar schemes can be used in the networks of other chip layers to achieve signal extraction.

[0094] In practical applications, the FPGA chips in the programmable chip structure 100 are arrays composed of FPGA modules (such as any combination of at least one programmable module, such as programmable logic module, embedded memory unit, embedded multiplication unit and / or user module), the chips containing eFPGA modules are arrays composed of eFPGA modules (such as any combination of at least one programmable module, such as programmable logic module, embedded memory unit, embedded multiplication unit and / or user module), and the memory chips are arrays composed of memory modules (such as any combination of at least one memory, such as static random access memory, dynamic random access memory, flash memory, ferroelectric memory, phase change memory, magnetic memory and / or rheostat memory). They all have testing requirements, which means that all or some of the chips need to bring out test PAD / Bump signals. Therefore, in practical applications, test circuits need to be designed for all or some of the chips.

[0095] Unlike the single-chip testing requirements of existing technologies, this embodiment provides a multi-chip stacked architecture with three-dimensional heterogeneous integrated interconnects, establishing high-density connections between the metal layers within the chip and sharing the outermost interface (bonding interface, PAD / Bump lead-out interface) of a three-dimensional heterogeneous integrated device. By utilizing these connections, the test reuse of FPGA chips, chips containing eFPGA modules, and memory chips can be achieved, achieving optimal results.

[0096] Based on the above programmable chip structure, this embodiment provides two different external test circuit lead-out schemes: an independent external test circuit lead-out scheme and a multiplexed external test circuit lead-out scheme.

[0097] Independent test circuit external lead-out solution

[0098] In this embodiment, the target chip in the stacked chip structure 100 includes one or more first target chips, and correspondingly, the target lead-out structure includes a first target lead-out structure 121 that is configured one-to-one with the first target chip; wherein, the first target lead-out structure 121 is configured to interconnect the first through silicon via 131 on the outermost interface.

[0099] The first target chip includes a first target test circuit and a first functional circuit; the external lead-out terminal of the first functional circuit is interconnected with the first target lead-out structure 121 through the first target test circuit and each three-dimensional heterogeneous integrated bonding structure 300 in the first stacked chip structure; wherein, the first stacked chip structure is the part of the stacked chip structure from the outermost chip to the first target chip.

[0100] In this embodiment, the first target test circuit can receive test instructions from the first target lead-out structure 121, thereby realizing the test of the first functional circuit in the first target chip.

[0101] In this embodiment, a second through-silicon via 132 is also provided on the outermost interface; the second through-silicon via 132 interconnects the second target lead-out structure 122; the outermost chip is provided with a second target test circuit and a second functional circuit; the external lead-out terminal of the second functional circuit is interconnected with the second target lead-out structure 122 through the second target test circuit.

[0102] In this way, the second target test circuit can receive test commands from the second target lead-out structure 122, thereby realizing the test of the second functional circuit in the second target chip.

[0103] like Figure 4The diagram shown is a schematic diagram of a programmable chip structure with a two-layer chip structure provided by an embodiment of the present invention. The second outermost chip is a first target chip, which includes a first functional circuit interconnected with a first target test circuit and a three-dimensional heterogeneous integration bonding structure 300 and its corresponding first target lead-out structure 121. The second functional circuit in the outermost chip is interconnected with its corresponding second target lead-out structure 122.

[0104] External lead-out scheme for reused test circuit

[0105] In this embodiment, the target chip in the stacked chip structure 100 includes one or more second target chips; the target lead-out structure includes a first general lead-out structure 123 corresponding to each second target chip; wherein, the first general lead-out structure 123 is disposed on the outermost interface to interconnect a third through-silicon via 133.

[0106] The outermost chip contains a multiplexing test circuit and a third functional circuit; the second target chip contains a fourth functional circuit; the external leads of the third functional circuit are interconnected with the first general-purpose lead structure 123 through the multiplexing test circuit; the external leads of the fourth functional circuit are interconnected with the first general-purpose lead structure 123 through each three-dimensional heterogeneous integrated bonding structure 300 in the second stacked chip structure and the multiplexing test circuit; wherein, the second stacked chip structure is the part of the stacked chip structure from the outermost chip to the second target chip.

[0107] In this embodiment, since the multiplexed test circuit interconnects the third functional circuit and the fourth functional circuit respectively, it is possible to perform functional tests on different chips using only one multiplexed test circuit.

[0108] like Figure 5 The diagram shows a schematic of a programmable chip structure with a two-layer chip structure provided by an embodiment of the present invention. The second outermost chip is a second target chip. The fourth functional circuit in the chip is interconnected with the interconnection terminal of its corresponding multiplexing test circuit via a three-dimensional heterogeneous integration bonding structure 300. The third functional circuit in the outermost chip is interconnected with the interconnection terminal of its corresponding multiplexing test circuit. The interconnection terminal of the multiplexing test circuit is connected to the first general-purpose lead-out structure 123.

[0109] Of course, based on the above-mentioned external lead-out scheme for reused test circuits, the above-mentioned external lead-out scheme for independent test circuits can also be combined to construct programmable chip structures more flexibly. Specifically:

[0110] Based on the above-mentioned external lead-out scheme for the multiplexing test circuit, the target chip also includes a third target chip; the target lead-out structure also includes a third target lead-out structure corresponding to the third target chip; wherein, the third target lead-out structure is disposed on the outermost interface to interconnect a fourth through-silicon via; the second target chip is provided with a third target test circuit and a fourth functional circuit; the external lead-out terminal of the fourth functional circuit is interconnected with the third target lead-out structure through the third target test circuit and each three-dimensional heterogeneous integrated bonding structure 300 in the third stacked chip structure; wherein, the third stacked chip structure is the part of the stacked chip structure from the outermost chip to the third target chip.

[0111] In this way, the fourth functional circuit in the third chip can be interconnected with the third target lead-out structure through the third target test circuit and each three-dimensional heterogeneous integrated bonding structure 300, thereby mixing the above-mentioned multiplexed test circuit external lead-out scheme and the above-mentioned test circuit external lead-out scheme to flexibly construct a programmable chip structure.

[0112] In practical applications, when testing determines that one or more chips have failed, the failed chips need to be repaired to improve the yield of the programmable chip structure. Based on the above programmable chip structure, this embodiment also provides two different repair and transfer schemes for failed chips: independent repair and transfer scheme and reuse repair and transfer scheme.

[0113] Independent repair and transfer solution

[0114] Based on any of the above programmable chip structures, the target chip in this embodiment includes a fourth target chip and a fifth target chip; the target lead-out structure includes a fourth target lead-out structure corresponding to the fourth target chip, and a fifth target lead-out structure corresponding to the fifth target chip; wherein, the fourth target lead-out structure is provided to interconnect a fifth through-silicon via on the outermost interface, and the fifth target lead-out structure is provided to interconnect a sixth through-silicon via on the outermost interface; the fifth target chip is a redundant spare chip of the fourth target chip.

[0115] The fourth target chip includes a first target repair circuit and a fifth functional circuit; the fifth target chip includes a second target repair circuit and a sixth functional circuit; the external leads of the fifth functional circuit are interconnected with the fourth target lead structure through the first target repair circuit and each of the three-dimensional heterogeneous integrated bonding structures 300 in the fourth stacked chip structure; wherein, the fourth stacked chip structure is the portion of the stacked chip structure from the outermost chip to the fourth target chip; the external leads of the sixth functional circuit are interconnected with the fifth target lead structure through the second target repair circuit and each of the three-dimensional heterogeneous integrated bonding structures 300 in the fifth stacked chip structure; wherein, the fifth stacked chip structure is the portion of the stacked chip structure from the outermost chip to the fifth target chip.

[0116] In this way, when the fifth functional circuit has a problem that causes the fourth target chip to fail, a bypass command can be sent from the fourth target lead-out structure to the fourth target chip to cut off the fourth target chip, and a cut-in command can be sent from the fifth target lead-out structure to the fifth target chip to cut in the fifth target chip, thereby realizing the repair and transfer of the failed chip.

[0117] Reuse Repair Transfer Solution

[0118] Based on any of the above-mentioned programmable chip structures, the target chip in this embodiment includes: one or more sixth target chips, and one or more seventh target chips; the target lead-out structure includes a second general lead-out structure corresponding to each sixth target chip; a second general lead-out structure corresponding to each seventh target chip; wherein the second general lead-out structure is disposed on the outermost interface to interconnect seventh through-silicon vias; the seventh target chip and the sixth target chip are redundant spare chips, and / or, the seventh target chip and the outermost chip are redundant spare chips.

[0119] The outermost chip contains a multiplexing and repair circuit and a seventh functional circuit; the sixth target chip contains an eighth functional circuit; and the seventh target chip contains a ninth functional circuit.

[0120] The external leads of the seventh functional circuit are interconnected with the second general-purpose lead structure through the multiplexing repair circuit.

[0121] The external leads of the eighth functional circuit are interconnected with the second general lead structure through the three-dimensional heterogeneous integrated bonding structures 300 and the multiplexing repair circuit in the sixth stacked chip structure; wherein, the sixth stacked chip structure is the part from the outermost chip to the sixth target chip in the stacked chip structure.

[0122] The external leads of the ninth functional circuit are interconnected with the second general lead structure through the three-dimensional heterogeneous integrated bonding structures 300 and the multiplexing repair circuit in the seventh stacked chip structure; wherein, the seventh stacked chip structure is the part from the outermost chip to the seventh target chip in the stacked chip structure.

[0123] Thus, the above-mentioned reuse repair transfer scheme can achieve failure repair between the seventh target chip and the sixth target chip, as well as failure repair between the seventh target chip and the outermost chip, using only a second general lead-out structure and a reuse repair circuit.

[0124] Of course, based on the above-mentioned reuse repair and transfer scheme, the above-mentioned independent repair and transfer scheme can also be used in combination to build programmable chip structures more flexibly. Specifically:

[0125] Based on the above reuse, repair and transfer scheme, the target chip also includes an eighth target chip; the target lead-out structure also includes a sixth target lead-out structure corresponding to the eighth target chip; wherein, the sixth target lead-out structure is disposed on the outermost interface to interconnect the eighth through-silicon via; the eighth target chip and the sixth target chip are redundant backup chips for each other, the eighth target chip and the seventh target chip are redundant backup chips for each other, and / or, the eighth target chip and the outermost chip are redundant backup chips for each other.

[0126] The eighth target chip contains a second target repair circuit and a tenth function circuit.

[0127] The external lead-out terminal of the tenth functional circuit is interconnected with the sixth target lead-out structure through the second target repair circuit and each three-dimensional heterogeneous integrated bonding structure 300 in the eighth stacked chip structure; wherein, the eighth stacked chip structure is the part from the outermost chip to the eighth target chip in the stacked chip structure.

[0128] Thus, based on the above-mentioned reuse and repair transfer scheme, when the sixth target chip, the seventh target chip and / or the outermost chip fail, the sixth target introduction structure can also issue a cut-in command to the eighth target chip, thereby realizing the repair transfer of the failed chip. This enables the reuse of repair circuits between any combination of chips in a multi-layer three-dimensional heterogeneous integrated device, transferring the repair circuit functions of different chips and concentrating or distributing them on other chips.

[0129] Based on the same inventive concept as the method, embodiments of the present invention also provide an electronic device, which has a processor internally, and the processor has one or more computing cores, any computing core including any of the programmable chip structures described above.

[0130] The technical solutions in the above embodiments of the present invention have at least the following technical effects or advantages:

[0131] In this embodiment of the invention, multiple chips are stacked together to form a stacked chip structure. Adjacent chips are connected by corresponding three-dimensional heterogeneous integration bonding structures to achieve interconnection between them. Simultaneously, a target lead-out structure corresponding to the target chip is provided on the outermost interface of the outermost chip to allow the outward lead-out of signals related to the target chip. This embodiment of the invention utilizes three-dimensional heterogeneous integration technology and semiconductor metal processing technology to achieve stacked interconnection between chips. This ensures that the physical and electrical parameters of the interconnects between chips conform to the characteristics of semiconductor processing technology, reducing the use of vias, interconnects, and I / O structures, increasing the interconnection density and speed between chips, and improving the integration level of the integrated chip.

[0132] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0133] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0134] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A three-dimensional heterogeneous integrated programmable chip structure, characterized in that, The programmable chip structure includes: at least two chips; any one of the at least two chips is an FPGA chip and / or a chip containing an eFPGA module; The at least two chips are stacked and connected; each of the chip stacks is provided with a functional layer and a substrate; In the stacked chip structure between the outermost chip and the target chip, the metal layer of the first chip near the second chip and the metal layer of the second chip near the first chip are interconnected through a three-dimensional heterogeneous integration bonding structure; wherein, the outermost chip includes the uppermost chip of the programmable chip structure and / or the lowermost chip of the programmable chip structure; if the first chip is also adjacent to a third chip on the side away from the second chip, then the metal layer near the second chip interconnects the metal layer of the first chip near the third chip; The outermost chip has an outermost interface; the outermost interface has a target lead-out structure corresponding to the target chip; the target lead-out structure interconnects the metal layer of the outermost chip that is close to the next outermost chip; The target chip includes a first target chip; the target lead-out structure includes a first target lead-out structure corresponding to the first target chip; wherein, the first target lead-out structure is disposed on the outermost interface to interconnect a first through-silicon via; The first target chip includes a first target test circuit and a first functional circuit; The external lead-out terminals of the first functional circuit are interconnected with the first target lead-out structure through the first target test circuit and each three-dimensional heterogeneous integrated bonding structure in the first stacked chip structure; wherein, the first stacked chip structure is the portion of the stacked chip structure from the outermost chip to the first target chip; A second through-silicon via is also provided on the outermost interface; the second through-silicon via interconnects a second target lead-out structure; the outermost chip is provided with a second target test circuit and a second functional circuit; The external leads of the second functional circuit are interconnected with the second target lead structure through the second target test circuit.

2. The programmable chip structure according to claim 1, characterized in that, The target lead-out structure includes a layered PAD structure, a bump structure, or a bonding structure, to lead out the metal layer in the target chip.

3. The programmable chip structure according to claim 2, characterized in that, The three-dimensional heterogeneous integrated bonding structure includes: The first three-dimensional heterogeneous integration bonding point is located on the three-dimensional heterogeneous integration surface on one side of the first chip between the first chip and the second chip, and is interconnected with the metal layer near the second chip. The second three-dimensional heterogeneous integration bonding point is located on the three-dimensional heterogeneous integration surface on one side of the second chip between the second chip and the first chip, and interconnects the metal layer close to the first chip and the first three-dimensional heterogeneous integration bonding point to realize the interconnection of the metal layers of the first chip and the second chip.

4. The programmable chip structure according to any one of claims 1 to 3, characterized in that, The target chip includes one or more second target chips; the target lead-out structure includes a first general lead-out structure corresponding to each second target chip; wherein the first general lead-out structure is disposed on the outermost interface to interconnect a third through-silicon via; The outermost chip is provided with a multiplexing test circuit and a third functional circuit; the second target chip is provided with a fourth functional circuit; The external leads of the third functional circuit are interconnected with the first general lead structure through the multiplexing test circuit; The external leads of the fourth functional circuit are interconnected with the first general lead structure through the three-dimensional heterogeneous integrated bonding structures in the second stacked chip structure and the multiplexing test circuit; wherein, the second stacked chip structure is the part of the stacked chip structure from the outermost chip to the second target chip.

5. The programmable chip structure according to claim 4, characterized in that, The target chip further includes a third target chip; the target lead-out structure further includes a third target lead-out structure corresponding to the third target chip; wherein, the third target lead-out structure is disposed on the outermost interface interconnect fourth through-silicon via; The second target chip includes a third target testing circuit and a fourth functional circuit; The external lead-out terminal of the fourth functional circuit is interconnected with the third target lead-out structure through the third target test circuit and each three-dimensional heterogeneous integrated bonding structure in the third stacked chip structure; wherein, the third stacked chip structure is the part of the stacked chip structure from the outermost chip to the third target chip.

6. The programmable chip structure according to any one of claims 1 to 3, characterized in that, The target chip includes a fourth target chip and a fifth target chip; the target lead-out structure includes a fourth target lead-out structure corresponding to the fourth target chip, and a fifth target lead-out structure corresponding to the fifth target chip; wherein, the fourth target lead-out structure is disposed on the outermost interface to interconnect a fifth through-silicon via, and the fifth target lead-out structure is disposed on the outermost interface to interconnect a sixth through-silicon via; the fifth target chip is a redundant spare chip of the fourth target chip; The fourth target chip is provided with a first target repair circuit and a fifth functional circuit; the fifth target chip is provided with a second target repair circuit and a sixth functional circuit; The external lead-out terminal of the fifth functional circuit is interconnected with the fourth target lead-out structure through the first target repair circuit and each three-dimensional heterogeneous integrated bonding structure in the fourth stacked chip structure; wherein, the fourth stacked chip structure is the part of the stacked chip structure from the outermost chip to the fourth target chip; The external lead-out terminal of the sixth functional circuit is interconnected with the fifth target lead-out structure through the second target repair circuit and each three-dimensional heterogeneous integrated bonding structure in the fifth stacked chip structure; wherein, the fifth stacked chip structure is the part of the stacked chip structure from the outermost chip to the fifth target chip.

7. The programmable chip structure according to any one of claims 1 to 3, characterized in that, The target chip includes: one or more sixth target chips, and one or more seventh target chips; the target lead-out structure includes a second general lead-out structure corresponding to each sixth target chip; a second general lead-out structure corresponding to each seventh target chip; wherein the second general lead-out structure is disposed on the outermost interface to interconnect seventh through-silicon vias; the seventh target chip and the sixth target chip are redundant backup chips for each other, and / or the seventh target chip and the outermost chip are redundant backup chips for each other; The outermost chip is provided with a reuse and repair circuit and a seventh functional circuit; the sixth target chip is provided with an eighth functional circuit; the seventh target chip is provided with a ninth functional circuit; The external lead-out terminals of the seventh functional circuit are interconnected with the second general lead-out structure through the multiplexing and repair circuit; The external lead-out terminals of the eighth functional circuit are interconnected with the second general lead-out structure through the three-dimensional heterogeneous integrated bonding structures in the sixth stacked chip structure and the multiplexing repair circuit; wherein, the sixth stacked chip structure is the part of the stacked chip structure from the outermost chip to the sixth target chip; The external lead-out terminals of the ninth functional circuit are interconnected with the second general lead-out structure through the three-dimensional heterogeneous integrated bonding structures in the seventh stacked chip structure and the multiplexing repair circuit; wherein, the seventh stacked chip structure is the part of the stacked chip structure from the outermost chip to the seventh target chip.

8. The programmable chip structure according to claim 7, characterized in that, The target chip further includes an eighth target chip; the target lead-out structure further includes a sixth target lead-out structure corresponding to the eighth target chip; wherein, the sixth target lead-out structure is disposed on the outermost interface to interconnect an eighth through-silicon via; the eighth target chip and the sixth target chip are redundant backup chips for each other, the eighth target chip and the seventh target chip are redundant backup chips for each other, and / or, the eighth target chip and the outermost chip are redundant backup chips for each other; The eighth target chip is equipped with a second target repair circuit and a tenth functional circuit; The external lead-out terminal of the tenth functional circuit is interconnected with the sixth target lead-out structure through the second target repair circuit and each three-dimensional heterogeneous integrated bonding structure in the eighth stacked chip structure; wherein, the eighth stacked chip structure is the part of the stacked chip structure from the outermost chip to the eighth target chip.

9. The programmable chip structure according to any one of claims 1 to 3, characterized in that, The chip is an FPGA chip, a chip containing an eFPGA module, or a memory chip.

10. An electronic device, comprising a processor, characterized in that, Any computing core in the processor includes the programmable chip structure as described in any one of claims 1 to 9.

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