Memory device and method of forming a three-dimensional (3D) memory device

Abstract

A method of forming a three-dimensional (3D) memory device includes: forming a layer stack above a substrate, the layer stack having alternating layers of a first conductive material and a first dielectric material; forming a trench extending vertically through the layer stack from an upper surface of the layer stack away from the substrate to a lower surface of the layer stack facing the substrate; lining the sidewalls and bottom of the trench with a memory film; forming a channel material above the memory film, the channel material comprising an amorphous material; after forming the channel material, filling the trench with a second dielectric material; forming a memory cell isolation region in the second dielectric material; forming a source line (SL) and a bit line (BL) extending vertically in the second dielectric material on opposite sides of the memory cell isolation region; and after forming the SL and the BL, crystallizing a first portion of the channel material. Embodiments of the present application also relate to memory devices.

Description

Technical Field

[0001] Embodiments of the present application relate to memory devices and methods of forming three-dimensional (3D) memory devices. Background Art

[0002] Semiconductor memory is used in integrated circuits for electronic applications including, for example, radios, televisions, cell phones, and personal computer devices. Semiconductor memory includes two main categories. One is volatile memory and the other is non-volatile memory. Volatile memory includes random access memory (RAM), which can also be divided into two subcategories, static random access memory (SRAM) and dynamic random access memory (DRAM). Both SRAM and DRAM are volatile because they lose the stored information when power is lost.

[0003] On the other hand, non-volatile memory can retain data on it without power. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). The advantages of FeRAM include fast read / write speeds and small size. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a three-dimensional (3D) memory device, the method comprising: forming a layer stack above a substrate, the layer stack comprising alternating layers of a first conductive material and a first dielectric material; forming a groove, the groove extending vertically from an upper surface of the layer stack away from the substrate through the layer stack to a lower surface of the layer stack facing the substrate; lining the sidewalls and bottom of the groove with a memory film; forming a channel material above the memory film, the channel material comprising an amorphous material; after forming the channel material, filling the trench with a second dielectric material; forming a memory cell isolation region in the second dielectric material; forming a source line (SL) and a bit line (BL) extending vertically in the second dielectric material on opposite sides of the memory cell isolation region; and after forming the source line and the bit line, crystallizing a first portion of the channel material.

[0005] Other embodiments of the present application provide a method for forming a three-dimensional (3D) memory device, the method comprising: forming a layer stack above a substrate, the layer stack comprising a first conductive material layer interlaced with a first dielectric material layer; forming a groove through the layer stack; conformally forming a memory film in the groove; conformally forming a channel material in the groove above the memory film, the channel material comprising an amorphous material; after conformally forming the channel material, filling the trench with a second dielectric material; forming a source line (SL) and a bit line (BL) in the second dielectric material, the source line and the bit line extending through the layer stack in a vertical direction perpendicular to a main upper surface of the substrate; and after forming the source line and the bit line, converting a first portion of the channel material into a crystalline material by performing a thermal process.

[0006] Still other embodiments of the present application provide a memory device, comprising: a layer stack located above a substrate, the layer stack comprising alternating layers of word lines and a first dielectric material; a second dielectric material embedded in the layer stack and extending vertically in the layer stack in a direction perpendicular to a main upper surface of the substrate; a source line (SL) and a bit line (BL) located in the second dielectric material and extending vertically through the layer stack; a memory film located between the layer stack and the second dielectric material; and a channel layer comprising a channel material, wherein a first portion of the channel layer is disposed between the memory film and the source line or between the memory film and the bit line, wherein a second portion of the channel layer is disposed between the memory film and the second dielectric material, wherein the first portion of the channel layer comprises a crystalline material of the channel material, and the second portion of the channel layer comprises an amorphous material of the channel material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the size of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A cross-sectional view of a semiconductor device having an integrated memory device in an embodiment is shown.

[0009] Figure 2 A perspective view showing a portion of a storage device in an embodiment.

[0010] Figure 3-Figure 8 , Fig. 9A , Fig. 9B and Figures 10A-10J Various views of a three-dimensional (3D) memory device at various stages of fabrication in an embodiment are shown.

[0011] Fig.11 A flow chart illustrating a method of forming a three-dimensional (3D) memory device in some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides a variety of different embodiments or examples to implement different features of the present invention. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are only examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component are not in direct contact.

[0013] In addition, for ease of description, spatial relationship terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spatial relationship terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein may be interpreted accordingly. Throughout the discussion herein, unless otherwise stated, the same or similar figure numbers in different figures refer to the same or similar elements formed by the same or similar processes using the same or similar materials.

[0014] In some embodiments, a method of forming a three-dimensional (3D) memory device includes: forming a trench extending through a layer stack including alternating layers of a first conductive material and a first dielectric material; lining the sidewalls and bottom of the trench with a memory film; conformally forming a channel material over the memory film, the channel material including an amorphous material; and filling the trench with a second dielectric material after forming the channel material. The method also includes: forming a memory cell isolation region in the second dielectric material; forming a source line (SL) and a bit line (BL) in the second dielectric material on opposite sides of the memory cell isolation region; and after forming the SL and the BL, crystallizing a first portion of the channel material. In some embodiments, a thermal treatment is performed to crystallize a first portion of the channel material in contact with the SL and the BL. The crystallized first portion of the channel material has a lower resistance, thereby reducing the contact resistance between the gate of a thin film transistor (TFT) of the memory cell and the channel material and improving the driving capability of the TFT.

[0015] In an embodiment, Figure 1A cross-sectional view of a semiconductor device 100 having an integrated memory device 123 (e.g., 123A and 123B) is shown. In the illustrated embodiment, the semiconductor device 100 is a fin field effect transistor (FinFET) device having a three-dimensional (3D) memory device 123 integrated in a back-end of line (BEOL) process of semiconductor manufacturing. Note that FinFET is used here as a non-limiting example. The 3D memory device 123 (which may also be referred to as memory device 123) may be integrated in any suitable device, such as a semiconductor device having a planar transistor or a gate-all-around (GAA) transistor. To avoid confusion, in Figure 1 Details of the memory device 123 are not shown in FIG. 1 , but are shown in subsequent figures below.

[0016] like Figure 1 As shown, semiconductor device 100 includes different regions for forming different types of circuits. For example, semiconductor device 100 may include a first region 110 for forming a logic circuit, and may include a second region 120 for forming, for example, a peripheral circuit, an input / output (I / O) circuit, an electrostatic discharge (ESD) circuit, and / or an analog circuit. Other regions for forming other types of circuits are possible and are fully intended to be included within the scope of the present disclosure.

[0017] Semiconductor device 100 includes substrate 101. Substrate 101 may be a bulk substrate, such as a doped or undoped silicon substrate, or an active layer of a semiconductor on insulator (SOI) substrate. Substrate 101 may include: other semiconductor materials such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates may also be used.

[0018] In the front-end of the line (FEOL) process of semiconductor manufacturing, electrical components such as transistors, resistors, capacitors, inductors, diodes, etc. are formed in or on the substrate 101. Figure 1In the example of , semiconductor fins 103 (also referred to as fins) are formed to protrude above the substrate 101. Isolation regions 105, such as shallow trench isolation (STI) regions, are formed between or around the semiconductor fins 103. A gate electrode 109 is formed above the semiconductor fins 103. Gate spacers 111 are formed along the sidewalls of the gate electrode 109. Source / drain regions 107, such as epitaxial source / drain regions, are formed on opposite sides of the gate electrode 109. Contacts 113, such as gate contacts and source / drain contacts, are formed above and electrically coupled to corresponding underlying conductive features (e.g., the gate electrode 109 or the source / drain region 107). One or more dielectric layers 117, such as an interlayer dielectric (ILD) layer, are formed above the substrate 101 and around the semiconductor fins 103 and the gate electrode 109. Other conductive features, such as interconnect structures including conductive lines 115 and vias 114, may also be formed in one or more dielectric layers 117. Figure 1 The FinFET in the embodiment can be formed by any suitable method known or used in the art, which will not be described in detail here. For the convenience of discussion in this article, the substrate 101, the electrical components (e.g., FinFET) formed in or on the substrate 101, the contact 113, the conductive components 115 / 114, and the one or more dielectric layers 117 are collectively referred to as the substrate 50.

[0019] Still reference Figure 1 , a dielectric layer 119, which may be an etch stop layer (ESL), may be formed over one or more dielectric layers 117. In an embodiment, dielectric layer 119 is formed of silicon nitride using plasma enhanced physical vapor deposition (PECVD), but other dielectric materials, such as nitrides, carbides, combinations thereof, and the like, and alternative techniques for forming dielectric layer 119, such as low pressure chemical vapor deposition (LPCVD), PVD, and the like, may be used instead. In some embodiments, dielectric layer 119 is omitted. Next, dielectric layer 121 is formed over dielectric layer 119. Dielectric layer 121 may be any suitable dielectric material, such as silicon oxide, silicon nitride, and the like, formed by a suitable method such as PVD, CVD, and the like. One or more memory devices 123A, each including a plurality of memory cells, are formed in dielectric layer 121 and coupled to conductive features (e.g., vias 124 and conductive lines 125) in dielectric layer 121. This will be discussed in detail below. Figure 1 1. An embodiment of the memory device 123A or 123B (eg, the 3D memory device 200) in FIG.

[0020] Figure 1 Also shown is a second layer of memory device 123B formed over memory device 123A. Memory devices 123A and 123B may have the same or similar structures and may be collectively referred to as memory devices 123. Figure 1The example of shows two layers of memory devices 123 as a non-limiting example. Other numbers of layers of memory devices 123, such as one, three or more layers, are also possible and are fully intended to be included within the scope of the present disclosure. One or more layers of memory devices 123 are formed in the memory region 130 of the semiconductor device 100 and can be formed in the back-end process (BEOL) of semiconductor manufacturing. The memory device 123 can be formed at any suitable location within the semiconductor device 100 in the BEOL process, such as above the first region 110 (e.g., directly above), above the second region 120, or above multiple regions.

[0021] Still reference Figure 1 After forming the memory region 130, an interconnect structure 140 is formed over the memory region 130, which includes a dielectric layer 121 and conductive features (e.g., vias 124 and conductive lines 125) located in the dielectric layer 121. The interconnect structure 140 can electrically connect electrical components formed in / on the substrate 101 to form a functional circuit. The interconnect structure 140 can also electrically couple the memory device 123 to components formed in / on the substrate 101, and / or couple the memory device 123 to conductive pads formed over the interconnect structure 140 to connect to an external circuit or external device. The formation of the interconnect structure is known in the art, so the details are not repeated here.

[0022] In some embodiments, the memory device 123 is electrically coupled to an electrical component (e.g., a transistor) formed on the substrate 50, for example, through a via 124 and a conductive line 125, and is controlled or accessed (e.g., written or read) by the functional circuit of the semiconductor device 100. Additionally or alternatively, in some embodiments, the memory device 123 is electrically coupled to a conductive pad formed above the top metal layer of the interconnect structure 140, in which case the memory device 123 can be directly controlled or accessed by an external circuit (e.g., another semiconductor device) without involving the functional circuit of the semiconductor device 100. Although in Figure 1 In the example of FIG. 1 , an additional metal layer (e.g., interconnect structure 140) is formed above memory device 123, but memory device 123 may be formed in a top (e.g., topmost) metal layer of semiconductor device 100, and these and other variations are fully intended to be included within the scope of the present disclosure.

[0023] Figure 2 A perspective view showing a portion of a three-dimensional (3D) memory device 200 in an embodiment. Figure 2 The 3D memory device 200 can be used as Figure 1For ease of discussion, in the discussion herein, a 3D memory device may be referred to as a memory device. In some embodiments, the memory device 200 is a three-dimensional memory device having a ferroelectric material. Note that for simplicity, not all components of the 3D memory device 200 are shown in the figure.

[0024] like Figure 2 As shown, the memory device 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns in the same horizontal plane (e.g., a plane parallel to the main upper surface of the substrate 50). The memory cells 202 may also be stacked vertically to form a three-dimensional memory array, thereby increasing the integration density of the memory cells.

[0025] In some embodiments, the memory device 200 is a nonvolatile memory device, such as a NOR memory device, etc. Each memory cell 202 of the memory device 200 may include a transistor 201 (e.g., a thin film transistor (TFT)) having an insulating memory film 211 (e.g., a ferroelectric film) as a gate dielectric. In some embodiments, the gate of each transistor 201 is electrically coupled to and / or includes a portion of a corresponding word line 203 (e.g., conductive line 203), a first source / drain region of each transistor 201 is electrically coupled to and / or includes a portion of a corresponding bit line (BL) 219D (e.g., conductive line 219D), and a second source / drain region of each transistor 201 is electrically coupled to and / or includes a portion of a corresponding source line (SL) 219S (e.g., conductive line 219S). Memory cells 202 in the same horizontal row of memory device 200 may share a common word line 203, while memory cells 202 in the same vertical column of memory device 200 may share a common source line 219S and a common bit line 219D. Bit line 219D and source line 219S may be collectively referred to as source / drain region 219 of transistor 201.

[0026] The memory device 200 includes a plurality of word lines (WL) 203 interleaved with a plurality of dielectric layers 205. In other words, the memory device 200 includes alternating layers of WL 203 and dielectric layers 205. The WL 203 is parallel to the major surface ( Figure 2 Not shown, see Figure 1 ). The memory device 200 may have a stepped region 250 and a memory array region 260. In the stepped region 250, the WL 203 and the dielectric layer 205 may have a stepped configuration such that the lower WL 203 is longer than and extends laterally beyond the end point of the upper WL 203. For example, in Figure 2, multiple stacked layers of WL 203 are shown, where the topmost WL 203 is the shortest and the bottommost WL 203 is the longest. The respective lengths of WL 203 can increase in a direction toward the substrate below. In this way, a portion of each WL 203 in the stepped region 250 can be easily accessed from above the memory device 200, and a conductive contact can be formed over and electrically coupled to the exposed portion of each WL 203. Memory cells 202 are formed in the memory array region 260.

[0027] The memory device 200 further includes a plurality of bit lines (BL) 219D and source lines (SL) 219S. The BL 219D and the SL 219S may extend in a direction perpendicular to the WL 203. A dielectric material 215 is disposed between and isolates adjacent BLs 219D and SLs 219S.

[0028] The paired BL 219D and SL 219S and the intersecting WL 203 define the boundaries of each memory cell 202, and the dielectric material 217 is disposed between and isolates adjacent memory cells 202. Therefore, the dielectric material 217 may also be referred to as a memory cell isolation region or a dielectric plug. In some embodiments, the SL 219S is electrically coupled to electrical ground. Although Figure 2 A particular arrangement of the BL 219D relative to the SL 219S is shown, but it should be understood that in other embodiments, the arrangement of the BL 219D and the SL 219S may be reversed.

[0029] like Figure 2 As shown, the memory device 200 may further include a channel material 213, such as an oxide semiconductor (OS) layer. With the understanding that any suitable channel material may be used as the channel material 213, the channel material 213 may be referred to herein as the OS layer 213. The channel material 213 may provide a channel region for the transistor 201 of the memory cell 202. For example, when an appropriate voltage (e.g., higher than the corresponding threshold voltage (V th ), a region of the OS layer 213 in the transistor 201 may allow current to flow from the BL 219D to the SL 219S (eg, in the direction indicated by the arrow 208).

[0030] The memory film 211 is disposed between the BL 219D / SL 219S and the OS layer 213, and the memory film 211 may be used as a gate dielectric of the transistor 201. In some embodiments, the memory film 211 includes a ferroelectric material such as hafnium oxide, zirconium oxide, silicon-doped hafnium oxide, etc. Therefore, the memory film 211 may also be referred to as a ferroelectric film 211, and the memory device 200 may also be referred to as a ferroelectric random access memory (FeRAM) device 200 or a 3D FeRAM device 200. Alternatively, the memory film 211 may be a multilayer structure including a SiO2 layer and a SiO2 layer between two SiO2 layers. x SiN between layers x layers (called ONO structures), different ferroelectric materials, different types of memory layers (e.g., capable of storing bits), etc.

[0031] In some embodiments where the memory film 211 includes a ferroelectric material, the memory film 211 can be polarized in one of two different directions, and the polarization direction of the memory film 211 can be changed by applying an appropriate voltage difference across the memory film 211 and generating an appropriate electric field. The polarization can be relatively local (e.g., typically contained within each boundary of the memory cell 202), and a continuous region of the memory film 211 can extend across multiple memory cells 202. Depending on the polarization direction of a particular region of the memory film 211, the threshold voltage of the corresponding transistor 201 changes, and a digital value (e.g., 0 or 1) can be stored. For example, when a region of the memory film 211 has a first polarization direction, the corresponding transistor 201 can have a relatively low threshold voltage, and when a region of the memory film 211 has a second polarization direction, the corresponding transistor 201 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less prone to error) to read the digital value stored in the corresponding memory cell 202.

[0032] In such an embodiment, in order to perform a write operation on the memory cell 202, a write voltage is applied to a portion of the memory film 211 corresponding to the memory cell 202. For example, the write voltage may be applied by applying a first voltage to the corresponding WL 203 and a second voltage to the corresponding BL 219D and SL 219S, wherein the difference between the first voltage and the second voltage is equal to the write voltage. By applying the write voltage to a portion of the memory film 211, the polarization direction of the region of the memory film 211 may be changed. As a result, the corresponding threshold voltage of the corresponding transistor 201 may be switched from a low threshold voltage to a high threshold voltage, or vice versa, and the threshold voltage of the transistor 201 is used to indicate a digital value (e.g., 0 or 1) stored in the memory cell 202.

[0033] In such an embodiment, to perform a read operation on the memory cell 202, a read voltage (a voltage between the low threshold voltage and the high threshold voltage) is applied to the WL 203 of the memory cell 202. Depending on the polarization direction of the corresponding region of the memory film 211, the transistor 201 of the memory cell 202 may be turned on or off. As a result, when a voltage is applied across the BL 219D and the SL 219S, there may or may not be a current between the BL 219D and the SL 219S (see, for example, Figure 2 208 in the memory cell), the current can be detected to determine the digital value stored in the memory cell 202.

[0034] Figure 3-Figure 8 , Fig. 9A , Fig. 9B and Figures 10A-10J Various views (eg, perspective views, cross-sectional views) of a three-dimensional (3D) memory device 200 are shown at various stages of fabrication in an embodiment. Figure 3-Figure 8 , Fig. 9A , Fig. 9B and Figures 10A-10J of processing to form Figure 2 3D memory device 200 .

[0035] refer to Figure 3 , a layer stack 204 (also referred to as a multilayer stack) is formed above the substrate 50. Note that Figure 3 The substrate 50 is shown in the figure to show the position of the 3D memory device 200 relative to the substrate 50, and the substrate 50 may not be considered as a part of the 3D memory device 200. In addition, not all components of the 3D memory device 200 are shown. For example, in Figure 3 The dielectric layer 119 above the substrate 50 is not shown in FIG. Figure 1 ). For simplicity, the substrate 50 is not shown in subsequent figures.

[0036] In some embodiments, the layer stack 204 includes alternating conductive layers 203 (eg, conductive) and dielectric layers 205. The conductive layers 203 are patterned in a subsequent step to form WL 203 (eg, see Figure 2 ). The conductive layer 203 may include a conductive material such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, molybdenum, aluminum, combinations thereof, and the like, and the dielectric layer 205 may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, and the like. The conductive layer 203 and the dielectric layer 205 may each be formed using, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), and the like. Although Figure 3A particular number of conductive layers 203 and dielectric layers 205 are shown, but other embodiments may include different numbers of conductive layers 203 and dielectric layers 205 .

[0037] Next, in Figure 4 In the embodiment of the present invention, a hard mask layer 207 is formed over the layer stack 204, and a photoresist 209 is formed over the hard mask layer 207. The hard mask layer 207 may include, for example, silicon nitride, silicon oxynitride, etc., which may be deposited by CVD, PVD, ALD, PECVD, etc. For example, the photoresist 209 may be formed by using a spin coating technique.

[0038] Next, the photoresist 209 is patterned using acceptable photolithography and etching techniques. For example, the photoresist 209 can be exposed to light to be patterned. After the exposure process, the photoresist 209 can be developed to remove the exposed or unexposed portions of the photoresist, depending on whether a negative or positive photoresist is used, thereby forming a patterned photoresist 209 having grooves 212, wherein the positions of the grooves 212 correspond to the grooves 206 formed in the layer stack 204 (see FIG. Figure 5 )’s location.

[0039] Next, in Figure 5 In the embodiment of the present invention, the pattern of the patterned photoresist 209 is transferred to the hard mask layer 207 using an acceptable etching process, such as by wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), etc. or a combination thereof. The etching can be anisotropic. The patterned photoresist 209 can then be removed, for example, by an ashing process.

[0040] Next, the pattern of the hard mask layer 207 is transferred to the layer stack 204 using one or more acceptable etching processes, such as wet etching, dry etching, RIE, NBE, etc. or a combination thereof. The etching process can be anisotropic. After the etching process, trenches 206 are formed, which extend through the layer stack 204. The trenches 206 separate the layer stack 204 into a plurality of individual fin structures, such as Figure 5 Using an appropriate removal process, hard mask layer 207 is removed after forming trench 206. In some embodiments, hard mask layer 207 is removed after filling trench 206 (e.g., with ferroelectric material 211, channel material 213, and dielectric material 215) using a planarization process such as chemical mechanical planarization (CMP).

[0041] Next, in Figure 6 In the process, a memory film 211 is formed (eg, conformally) to line the sidewalls and bottom of the trench 206 , a channel material 213 is formed (eg, conformally) over the memory film 211 , and a dielectric material 215 is formed over the channel material 213 to fill the trench 206 .

[0042] In some embodiments, the memory film 211 is formed of a ferroelectric material, such as hafnium zirconium oxide (HfZrO); zirconium oxide (HfZrO); hafnium oxide (HfO) doped with lanthanum (La), silicon (Si), aluminum (Al), etc.; undoped hafnium oxide (HfO); etc. In some embodiments, the memory film 211 has a multilayer structure including a silicon nitride layer between two silicon oxide layers (referred to as an ONO structure). In the discussion herein, the memory film 211 may be referred to as a ferroelectric film 211 or a ferroelectric material 211, with the understanding that any suitable memory material (e.g., capable of storing bits) may be used as the memory film 211. The material of the memory film 211 may be formed by a suitable deposition process such as ALD, CVD, PVD, PECVD, etc.

[0043] like Figure 6 As shown, a channel material 213 is formed (e.g., conformally) in the trench 206 above the ferroelectric film 211. The channel material 213 is formed of a suitable semiconductor material for providing a channel region for the transistor 201 of the memory cell 202, such as polysilicon, amorphous silicon, or an oxide semiconductor (OS) material, such as indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), indium tungsten oxide (IWO), etc. The channel material 213 can be formed by an acceptable deposition process such as ALD, CVD, PVD, PECVD, etc.

[0044] Next, a dielectric material 215 is formed in the trench 206 to fill the trench 206. Suitable dielectric materials include oxides, such as silicon oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, etc. The dielectric material 215 may be formed by an acceptable deposition process, such as ALD, CVD, PVD, PECVD, etc. A planarization process, such as CMP, may then be performed to remove excess portions of the ferroelectric film 211, the channel material 213, and the dielectric material 215 from the top surface of the layer stack 204. The planarization process may also remove the hard mask layer 207 from the top surface of the layer stack 204, as described above.

[0045] Next, in Figure 7, an opening 216 is formed in the groove 206 by removing a portion of the channel material 213 and a portion of the dielectric material 215. Each opening 216 in the corresponding groove 206 extends horizontally between the opposite inner sidewalls of the ferroelectric film 211 facing the corresponding groove 206, and extends vertically from the upper surface of the layer stack 204 to the upper surface of the ferroelectric film 211 at the bottom of the groove 206. In other words, each opening 216 exposes the inner sidewall of the ferroelectric film 211 facing the corresponding groove 206. In addition, in the illustrated embodiment, each opening 216 exposes the upper surface of the ferroelectric film 211 below (e.g., below and in physical contact with) the dielectric material 215, and does not extend through the ferroelectric film 211. For example, the openings 216 can be formed by an anisotropic etching process using a patterned mask layer having a pattern (e.g., an opening) at a location corresponding to the location of the opening 216.

[0046] Next, in Figure 8 In the embodiment of the present invention, a dielectric material is formed in the opening 216 to form an isolation region 217. The dielectric material used to form the isolation region 217 may be any suitable dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc. or a combination thereof, and may be formed by PVD, CVD, ALD, PECVD, etc. In some embodiments, the dielectric material used to form the isolation region 217 is different from the dielectric material 215 to provide etching selectivity in subsequent processing. A planarization process such as CMP may be performed to remove excess portions of the dielectric material from the upper surface of the layer stack 204. As will be discussed in more detail below, the isolation region 217 laterally electrically isolates adjacent memory cells 202 in the same trench, and may therefore also be referred to as a memory cell isolation region or a dielectric plug.

[0047] Next, in Fig. 9A In the embodiment, a bit line (BL) 219D and a source line (SL) 219S are formed in the dielectric material 215 on opposite sides of the isolation region 217. In some embodiments, to form the BL 219D and the SL 219S, Figure 8 A patterned mask layer is formed over the structure of , wherein a pattern (eg, an opening) of the patterned mask layer exposes region 218 (see Figure 8 ), wherein each region 218 includes a portion of the isolation region 217 and a portion of the insulating material 215 located on the opposite side of the isolation region 217. To avoid confusion, Figure 8 Only one of the regions 218 is shown. Note that two opposing sides 218S1 and 218S2 of the region 218 are aligned with (eg, overlap) two corresponding inner sidewalls of the channel material 213 .

[0048] Still reference Fig. 9ANext, an anisotropic etching process is performed to selectively remove portions of dielectric material 215 exposed by patterned mask layer (e.g., within region 218) using, for example, an etchant that is selective to dielectric material 215 (e.g., has a higher etching rate). The opening formed by the selective etching may extend vertically through layer stack 204, such that SL 219S and BL 219D formed in the opening extend through layer stack 204. A conductive material, such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, molybdenum, aluminum, combinations thereof, or multiple layers are formed to fill the opening using a suitable formation method, such as PVD, CVD, ALD, PECVD, etc. A planarization process, such as CMP, may then be performed to remove excess portions of the conductive material from the upper surface of layer stack 204, and the remaining portions of the conductive material in the opening form SL 219S and BL 219D.

[0049] Fig. 9A The dashed boxes in the figure show some memory cells 202 of the memory device 200. Note that, in order to avoid confusion, not all memory cells 202 of the memory device 200 are marked by dashed boxes. Each memory cell 202 includes portions of the following structures / layers / materials within its boundaries: WL 203, bit line 219D, source line 219S, memory film 211 (e.g., ferroelectric film), channel material 213, and dielectric material 215. As described above, the WL 203 of the memory cell 202 serves as the gate (also called gate electrode) of the transistor 201 of the memory cell 202, while the SL 219S / BL 219D serves as the source / drain region of the transistor 201. As shown in FIG. Fig. 9A As shown, each isolation region 217 isolates two laterally adjacent memory cells 202 formed in the same trench.

[0050] Fig. 9B Show Fig. 9A A top view of the memory cell 202 in FIG. Fig. 9B As shown, memory film 211 is disposed between and in contact with WL 203 and channel material 213. SL 219S and BL 219D are in contact (eg, in physical contact) with channel material 213. Dielectric material 215 is laterally disposed between SL 219S and BL 219D.

[0051] In some embodiments, the channel material 213 is or includes indium zinc composite oxide (In x Zn y M z O), where x, y and z are values ​​between zero and one (0≤x, y, z≤1), and M represents a suitable material such as Ti, Ta, Al, Ga, Mg or Si. x Zn yM z When the element M in O is replaced by Ti, Ta, Al, Ga, Mg or Si, indium zinc composite oxide can refer to a variety of different materials. x Zn y M z In the embodiment where the element M in the indium zinc oxide is a metal (such as Ti, Ta, Al, Ga or Mg), the indium zinc composite oxide may also be referred to as indium zinc metal oxide. In the discussion herein, indium zinc composite oxide may be used interchangeably with indium zinc metal oxide. In the embodiment shown, the deposited channel material 213 is an amorphous material (e.g., an amorphous indium zinc metal oxide material).

[0052] Next, in Fig. 10A In the embodiment of the present invention, a thermal treatment 220 (also referred to as a thermal process) is performed to form a crystalline material 223, such as a crystalline indium zinc metal oxide material, between the BL 219D / SL 219S and the ferroelectric film 211 of each memory cell 202. For example, the thermal process 220 may be performed at a temperature between about 300° C. and about 400° C. for a duration of less than about 48 hours, such as about 1 hour.

[0053] In one embodiment, Fig. 10B After heat treatment 220 Fig. 9A Memory cell 202. In the illustrated embodiment, SL 219S / BL 219D is composed of The metal material represented by 213 is distinguished from the element M in the channel material 213, which is an amorphous indium zinc composite oxide (In x Zn y M z O). Metal materials of SL 219S / BL 219D It may be, for example, W, Ti or Ta. During the heat treatment 220, the metal material of SL 219S / BL 219D The thermal treatment 220 diffuses into the channel material 213 to cause crystallization of the channel material 213, thereby transforming the first portion of the channel material 213 (e.g., the portion in contact with the SL 219S / BL 219D) into a crystalline material 223A, such as a crystalline indium zinc composite oxide (e.g., a crystalline indium zinc metal oxide). Therefore, it is said that the thermal treatment 220 crystallizes the first portion of the channel material 213, and the crystalline material 223A may also be referred to as the crystallized first portion 223A of the channel material 213.

[0054] In addition, metal materials reacts with the channel material 213 to form a metal oxide (eg, tungsten oxide, titanium oxide, or tantalum oxide). In some embodiments, the metal material The chemical reaction with the channel material 213 is described by the following chemical equation:

[0055]

[0056] In some embodiments, wherein the material InO x The indium zinc composite oxide from the channel material 213 is composed of InO x , ZnO and MO. As shown in the above chemical equation, InO x Loss of oxygen atoms to produce InO x-1 and oxygen vacancies V o , InO x Lost oxygen atoms and metal materials Combine to form metal oxide Therefore, after the thermal treatment 220, the crystallized first portion 223A of the channel material 213 also includes the metal oxide In some embodiments, the InO in the channel material 213 x The reduction of contributes to higher conductivity of the crystalline portion of the channel material 213 and contributes to higher carrier generation. In some embodiments, the carrier concentration in the crystalline portion of the channel material 213 (e.g., 223A or 223B) exceeds 10E18 / cm 3 .

[0057] Still reference Fig. 10B During the thermal treatment 220, the channel material 213 also diffuses into the SL 219S / BL 219D and is covered by the metal material Inducing crystallization, thereby forming a crystalline material 223B in the region of the SL 219S / BL 219D adjacent to the channel material 213. In addition, the metal material in the SL 219S / BL 219D The diffused channel material 213 (eg, InO x ) to form a metal oxide in the crystalline material 223B Similar to the discussion above regarding crystalline material 223A. Thus, crystalline materials 223A and 223B have the same or similar chemical composition (eg, including crystalline indium zinc metal oxide and metal oxide). ), and in some embodiments may be collectively referred to as crystalline material 223.

[0058] like Fig. 10BAs shown, the crystalline material 223 includes a first region (eg, 223A) in the channel material 213 and a second region (eg, 223B) in the SL 219S / BL 219D. (or channel material 213) diffusion, metal oxide The concentration of the metal oxide (or crystalline indium zinc metal oxide) may show a gradient in the crystalline material 223. In some embodiments, the metal oxide in the crystalline material 223 The concentration of the crystalline indium zinc metal oxide decreases along a first direction from the SL 219S / BL 219D toward the channel material 213 (e.g., from the region 223B toward the corresponding region 223A). In addition, the concentration of the crystalline indium zinc metal oxide in the crystalline material 223 decreases along a second direction from the channel material 213 toward the SL 219S / BL 219D (e.g., from the region 223A toward the corresponding region 223B). In other words, in some embodiments, the metal oxide The concentration gradient of the crystalline indium zinc metal oxide varies in the opposite direction.

[0059] exist Fig. 10B In the embodiment, the second portion of the channel material 213 disposed laterally between the SL 219S and the BL 219D is still an amorphous material (eg, amorphous indium zinc metal oxide) because the metal material in the SL 219S / BL 219D is does not diffuse into (e.g., reach) those areas. Fig. 10B In the example of FIG. 1 , the third portion of the channel material 213 disposed between the ferroelectric film 211 and the crystallized first portion 223A of the channel material 213 is still an amorphous material (eg, amorphous indium zinc metal oxide). There was no spread to those areas.

[0060] Fig. 10B The shapes and sizes of the crystalline material 223 in are non-limiting examples. Other shapes and / or sizes are possible and are fully intended to be included within the scope of the present disclosure. Additional examples of shapes and sizes of the crystalline material 223 are provided in Figure 10C-10G For example, depending on factors such as the thickness of the channel material 213 or the duration / temperature of the heat treatment 220, the crystallized first portion 223A of the channel material 213 may extend to (eg, physically contact) the ferroelectric film 221, such as Fig. 10C As shown. Fig. 10B and Fig. 10C medium, metal The diffusion occurs in the vertical direction. In some embodiments, for example Figure 10D-10G As shown, metal As a result, the first region 223A of the crystalline material 223 is wider than the second region 223B of the crystalline material 223, so that the distance between the opposite side walls 223AS of the first region 223A is smaller than the distance between the opposite side walls 223BS of the second region 223B. Specifically, Fig. 10D and Fig. 10E The examples in are similar to Fig. 10B and Fig. 10C example, but due to the metal The first region 223A has a wider first region due to the lateral diffusion. Fig.10F and Figure 10G The examples in are similar to Fig. 10D and Fig. 10E , but with an inclined sidewall 223AS of the first region 223A. In other words, Fig.10F and Figure 10G Each of the first regions 223A has a width that decreases as the first region 223A extends toward the ferroelectric film 221. As yet another example, each individual region of the crystalline material 223 may have a rounded shape (eg, an elliptical shape or a circular shape) or an irregular shape.

[0061] Fig. 10H , Fig.10I and Fig.10J Shown separately Fig. 10A 1 is a cross-sectional view of the memory device 200 along sections AA, BB, and CC. The sections AA, BB, and CC are all taken along a plane perpendicular to the main upper surface of the substrate 50.

[0062] exist Fig. 10H and Fig.10I In the embodiment, the ferroelectric film 211 has a U-shaped cross section. The channel material 213 is Fig.10I It has a U-shaped cross section. Fig.10J In the embodiment of the present invention, the bottom of the ferroelectric film 211 is removed by an etching process to form openings for the SL 219S and the BL 219D. In other words, the SL 219S and the BL 219D extend through the layer stack 204, which allows easy electrical connection to underlying electrical components (e.g., transistors) formed in the substrate 50. Fig.10J In the embodiment, due to the anisotropic etching, the sidewalls of the channel material 213 are vertically aligned with the corresponding sidewalls of the ferroelectric film 211. Fig.10J Also shown is the crystallized material 223 formed by the thermal treatment 220 .

[0063] Can be Figures 10A-10J After the processing of the memory device 200, additional processing is performed to complete the memory device 200. For example, the stepped region 250 can be formed by multiple etching steps (see Figure 2), and contact plugs may be formed to be electrically coupled to WL 203, BL 219D, and SL 219S. Any suitable formation method for forming the stepped region 250 and the contact plugs may be used.

[0064] In an embodiment, to form the stepped region 250 (see Figure 2 ), a patterned photoresist having a first width (e.g., along the longitudinal direction of WL 205) is formed over the topmost dielectric layer 203, and a first anisotropic etching process is performed to pattern the topmost dielectric layer 203 and expose the topmost WL 205. In other words, the first anisotropic etching process stops when the upper surface of the topmost WL 205 is exposed. Next, the width of the patterned photoresist is reduced (e.g., by a photoresist trimming process), and a second anisotropic etching process is performed to etch exposed portions of the underlying layers (e.g., the topmost WL 305 and the topmost dielectric layer 203). The second anisotropic etching process stops when the upper surface of the next-top dielectric layer 203 is exposed. The above process is repeated, wherein for each additional anisotropic etching process, the width of the patterned photoresist is reduced until the exposed portion of the topmost WL 205 is exposed. Figure 2 The upper surface of the lowermost dielectric layer 203 in the dielectric layer 204 is formed. The patterned photoresist may then be removed, for example, by an ashing or stripping process.

[0065] Embodiments can achieve advantages. In a typical memory device, the interface between the gate (e.g., WL 203) and the channel material (e.g., OS layer 213) can form a Schottky barrier, which can hinder the transmission of electrons, thereby increasing the energy required to overcome the barrier. With the continuous reduction of component sizes in advanced semiconductor manufacturing nodes, the contact resistance between the gate and the channel material is another problem that affects the driving ability of the transistor 201 of the memory cell 202. In addition, it is difficult to find a channel material that achieves a good compromise between conductor-like performance and insulator-like performance. The structures, materials, and formation methods disclosed herein help to reduce or alleviate the above-mentioned problems. For example, the heat treatment 220 reduces the InO in the channel material 213. x The concentration of the channel material 213 is reduced, and a portion of the channel material 213 is converted into a crystalline material 223, which has a lower resistance than the amorphous channel material 213 and a higher carrier concentration, thereby reducing the contact resistance between the gate and the channel material and improving the driving capability of the transistor 201 of the memory cell 202. The metal oxide in the crystalline material 223 The resistance of the channel material is further reduced, thereby further improving the contact resistance and driving capability of the transistor 201 .

[0066] The disclosed embodiments also advantageously mitigate short channel effects. As device components continue to shrink in advanced manufacturing nodes, short channel effects become a factor that limits the performance of the resulting semiconductor devices. The embodiments disclosed herein help reduce or mitigate short channel effects. For example, Fig. 10B Arrow 222 in FIG. 2 shows an example path of current flowing between BL 219D and SL 219S (e.g., between source / drain regions) of transistor 201 of memory cell 202. Note that due to the lower contact resistance of crystalline material 223, current flows through the path indicated by arrow 222 (which is a longer path) rather than the direct, shorter path between the source / drain regions in the case where crystalline material 223 is not formed. Therefore, the longer current path indicated by arrow 222 helps to mitigate short channel effects.

[0067] In some embodiments, Fig.11 A method 1000 of forming a three-dimensional (3D) memory device is shown. It should be understood that Fig.11 The illustrated embodiments are merely examples of many possible embodiments. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, the embodiments may be added, removed, replaced, rearranged, or repeated. Fig.11 The individual steps shown in .

[0068] refer to Fig.11 At box 1010, a layer stack is formed over a substrate, the layer stack comprising alternating layers of a first conductive material and a first dielectric material. At box 1020, a trench is formed, the trench extending vertically through the layer stack from an upper surface of the layer stack away from the substrate to a lower surface of the layer stack facing the substrate. At box 1030, the sidewalls and bottom of the trench are lined with a memory film. At box 1040, a channel material is formed over the memory film, the channel material comprising an amorphous material. At box 1050, after forming the channel material, the trench is filled with a second dielectric material. At box 1060, a memory cell isolation region is formed in the second dielectric material. At box 1070, a source line (SL) and a bit line (BL) extending vertically in the second dielectric material are formed on opposite sides of the memory cell isolation region. At box 1080, after forming the SL and BL, a first portion of the channel material is crystallized.

[0069] According to an embodiment, a method of forming a three-dimensional (3D) memory device includes: forming a layer stack above a substrate, the layer stack including alternating layers of a first conductive material and a first dielectric material; forming a trench extending vertically through the layer stack from an upper surface of the layer stack away from the substrate to a lower surface of the layer stack facing the substrate; lining the sidewalls and bottom of the trench with a memory film; forming a channel material above the memory film, the channel material including an amorphous material; after forming the channel material, filling the trench with a second dielectric material; forming a memory cell isolation region in the second dielectric material; forming a source line (SL) and a bit line (BL) extending vertically in the second dielectric material on opposite sides of the memory cell isolation region; and after forming the SL and the BL, crystallizing a first portion of the channel material. In an embodiment, crystallizing the first portion of the channel material includes transforming the first portion of the channel material from an amorphous material to a crystalline material, wherein the first portion of the channel material contacts the SL or the BL. In an embodiment, crystallizing the first portion of the channel material includes performing a thermal process. In an embodiment, the thermal process is performed at a temperature between about 300° C. and about 400° C. In an embodiment, after the thermal process, a second portion of the channel material laterally disposed between the SL and the BL remains as an amorphous material. In an embodiment, the channel material includes an indium zinc composite oxide (In x Zn y M z O), wherein x, y and z have values ​​between zero and one, and M is Ti, Ta, Al, Ga, Si or Mg. In an embodiment, after the thermal process, the crystallized first portion of the channel material extends from the SL or BL to the memory film. In an embodiment, after the thermal process, a third portion of the channel material disposed between the crystallized first portion of the channel material and the memory film remains as an amorphous material. In an embodiment, the BL and the SL include a second conductive material, wherein the thermal process is performed to form an oxide of the second conductive material in the crystallized first portion of the channel material. In an embodiment, performing the thermal process also forms an oxide of the second conductive material in the BL and the SL. In an embodiment, the channel material is diffused into the BL and the SL by the thermal process to form a crystallized channel material in the BL and the SL.

[0070] According to an embodiment, a method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including a first conductive material layer interlaced with a first dielectric material layer; forming a trench through the layer stack; conformally forming a memory film in the trench; conformally forming a channel material in the trench over the memory film, the channel material including an amorphous material; after conformally forming the channel material, filling the trench with a second dielectric material; forming a source line (SL) and a bit line (BL) in the second dielectric material, the SL and the BL extending through the layer stack in a vertical direction perpendicular to a main upper surface of the substrate; and after forming the SL and the BL, converting a first portion of the channel material into a crystalline material by performing a thermal process. In an embodiment, the first portion of the channel material physically contacts the SL or the BL. In an embodiment, the second conductive material of the SL and the BL diffuses into the first portion of the channel material by a thermal process to induce crystallization of the first portion of the channel material, wherein the channel material diffuses into the SL and the BL by the thermal process and forms a crystallized channel material in the SL and the BL. In an embodiment, the thermal process forms an oxide of the second conductive material in the first portion of the channel material and in first regions of the SL and BL that are in contact with the channel material. In an embodiment, the first portion of the channel material physically contacts the memory film.

[0071] According to an embodiment, a memory device includes: a layer stack located above a substrate, the layer stack including alternating layers of word lines and a first dielectric material; a second dielectric material embedded in the layer stack and extending vertically in the layer stack in a direction perpendicular to the main upper surface of the substrate; a source line (SL) and a bit line (BL) located in the second dielectric material and extending vertically through the layer stack; a memory film located between the layer stack and the second dielectric material; and a channel layer including a channel material, wherein a first portion of the channel layer is disposed between the memory film and the SL or between the memory film and the BL, wherein a second portion of the channel layer is disposed between the memory film and the second dielectric material, wherein the first portion of the channel layer includes a crystalline material of the channel material, and the second portion of the channel layer includes an amorphous material of the channel material. In an embodiment, a third portion of the channel layer is disposed between the memory film and the first portion of the channel layer, wherein the third portion of the channel layer includes an amorphous material of the channel material. In an embodiment, the first portion of the channel layer physically contacts the memory film. In an embodiment, the BL and the SL include a conductive material, wherein the first portion of the channel layer includes an oxide of the conductive material.

[0072] The components of several embodiments are discussed above so that those skilled in the art can better understand the various embodiments of the present invention. It should be understood by those skilled in the art that the present invention can be easily used as a basis to design or change other processing and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced in the present invention. It should also be appreciated by those skilled in the art that these equivalent structures do not deviate from the spirit and scope of the present invention, and that various changes, substitutions and modifications may be made without departing from the spirit and scope of the present invention.

Claims

1. A method of forming a three-dimensional (3D) memory device, the method comprising: forming a layer stack over the substrate, the layer stack comprising alternating layers of a first conductive material and a first dielectric material; forming a groove extending vertically through the layer stack from an upper surface of the layer stack facing away from the substrate to a lower surface of the layer stack facing the substrate, wherein the groove separates the layer stack into a plurality of fin-shaped structures; lining the sidewalls and bottom of the trench with a memory film; forming a channel material over the memory film, the channel material comprising an amorphous material; After forming the channel material, filling the trench with a second dielectric material; forming a memory cell isolation region in the second dielectric material, comprising: forming an opening between the second dielectric material between the first fin-shaped structure and the second fin-shaped structure, the opening vertically extending through the second dielectric material and the channel material, the opening exposing a first sidewall of the memory film extending along a first sidewall of the first fin-shaped structure, and exposing a second sidewall of the memory film extending along a second sidewall of the second fin-shaped structure; and filling the opening with a third dielectric material, wherein the third dielectric material contacts and extends along the first sidewall of the memory film and the second sidewall of the memory film; forming a source line (SL) and a bit line (BL) extending vertically in the second dielectric material on opposite sides of the memory cell isolation region; and After forming the source line and the bit line, a first portion of the channel material is crystallized, wherein the first portion of the channel material contacts the source line and the bit line.

2. The method according to claim 1, wherein: Crystallizing the first portion of the channel material includes transforming the first portion of the channel material from an amorphous material to a crystalline material.

3. The method according to claim 2, wherein: Crystallizing the first portion of the channel material includes performing a thermal process.

4. The method according to claim 3, wherein: The thermal process is performed at a temperature between 300°C and 400°C.

5. The method according to claim 3, wherein: After the thermal process, a second portion of the channel material laterally disposed between the source line and the bit line remains as an amorphous material.

6. The method according to claim 5, wherein: The channel material includes indium zinc composite oxide In x Zn y M z O, wherein x, y and z have values ​​between zero and one, and M is Ti, Ta, Al, Ga, Si or Mg.

7. The method according to claim 5, wherein: After the thermal process, a crystallized first portion of the channel material extends from the source line or the bit line toward the memory film.

8. The method according to claim 5, wherein: After the thermal process, a third portion of the channel material disposed between the crystallized first portion of the channel material and the memory film remains as an amorphous material.

9. The method according to claim 6, wherein: The bit line and the source line are formed of a metal material, wherein performing the thermal process forms an oxide of the metal material in a crystallized first portion of the channel material.

10. The method according to claim 9, wherein: Performing the thermal process also forms an oxide of the metal material in the bit line and the source line.

11. The method according to claim 10, wherein: The channel material is diffused into the bit line and the source line by the thermal process to form a crystallized channel material in the bit line and the source line.

12. A method of forming a three-dimensional (3D) memory device, the method comprising: forming a layer stack over the substrate, the layer stack comprising a first layer of conductive material interleaved with a first layer of dielectric material; forming a groove through the layer stack; conformally forming a memory film in the trench; conformally forming a channel material in the trench over the memory film, the channel material comprising an amorphous material; filling the trench with a second dielectric material after conformally forming the trench material; forming a source line (SL) and a bit line (BL) in the second dielectric material using a metal material, the source line and the bit line extending through the layer stack in a vertical direction perpendicular to the main upper surface of the substrate; as well as After forming the source line and the bit line, converting a first portion of the channel material into a crystalline material by performing a thermal process, wherein a first portion of the channel material physically contacts the source line and the bit line, a second portion of the channel material physically contacts the memory film and includes a portion between the first portion of the channel material and a portion between the first portion of the channel material and the memory film, and the second portion of the channel material includes the amorphous material.

13. The method according to claim 12, wherein: The channel material includes indium zinc composite oxide InxZnyMzO, where x, y and z have values ​​between zero and one, and M is Ti, Ta, Al, Ga, Si or Mg.

14. The method according to claim 13, wherein: The metal material of the source line and the bit line diffuses into the first portion of the channel material by the thermal process to cause crystallization of the first portion of the channel material, wherein the channel material diffuses into the source line and the bit line by the thermal process and forms crystallized channel material in the source line and the bit line.

15. The method according to claim 14, wherein: The thermal process forms an oxide of the metallic material in a first portion of the channel material and in first regions of the source line and the bit line that are in contact with the channel material.

16. The method according to claim 13, wherein: The thermal process is performed at a temperature between 300°C and 400°C.

17. A storage device comprising: a layer stack over the substrate, the layer stack comprising alternating layers of word lines and a first dielectric material; a second dielectric material embedded in the layer stack and extending vertically in the layer stack in a direction perpendicular to the main upper surface of the substrate; a source line (SL) and a bit line (BL) located in the second dielectric material and extending vertically through the layer stack, wherein the bit line and the source line are formed of a metal material; a memory film located between the layer stack and the second dielectric material; and a channel layer including a channel material, wherein a first portion of the channel layer is disposed between the memory film and the source line and between the memory film and the bit line and physically contacts the source line and the bit line, wherein a second portion of the channel layer is disposed between the memory film and the second dielectric material, wherein the first portion of the channel layer includes a crystalline material of the channel material, and the second portion of the channel layer includes an amorphous material of the channel material, The third portion of the channel layer is disposed between the memory film and the first portion of the channel layer, wherein the third portion of the channel layer includes an amorphous material of the channel material.

18. The memory device according to claim 17, wherein: The channel material includes indium zinc composite oxide InxZnyMzO, where x, y and z have values ​​between zero and one, and M is Ti, Ta, Al, Ga, Si or Mg.

19. The memory device according to claim 18, wherein: The crystalline material of the channel material includes a crystalline indium zinc composite oxide.

20. The memory device according to claim 17, wherein: The first portion of the channel layer includes an oxide of the metal material.

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