Shift register, gate drive circuit and display panel

Abstract

The present disclosure provides a shift register, a gate drive circuit, and a display panel, belonging to the field of display technology. The shift register of the present disclosure includes: an input subcircuit, an output subcircuit, a pull-up reset subcircuit, an output reset subcircuit, a first auxiliary subcircuit, and at least one second auxiliary subcircuit; wherein the pull-up reset subcircuit includes a first transistor; the first auxiliary subcircuit is configured to respond to a first control signal and, when the first transistor is turned off, pull down the potential of the second electrode of the first transistor to a first potential; the second auxiliary subcircuit is configured to respond to a second control signal and, when the first transistor is turned on, write the non-operating level signal into the second electrode of the first transistor to reset the potential of the pull-up node.

Description

Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a shift register, a gate driving circuit, and a display panel. Background Art

[0002] GOA (Gate Driver on Array) technology can integrate the gate drive circuit on the array substrate of the display panel, replacing the driver chip made by an external silicon wafer. It can save the Gate IC (Gate Integrated Circuit) part and fan-out wiring space to simplify the structure of the display product. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a shift register, a gate drive circuit and a display panel.

[0004] In a first aspect, an embodiment of the present disclosure provides a shift register comprising: an input subcircuit, an output subcircuit, a pull-up reset subcircuit, an output reset subcircuit, a first auxiliary subcircuit, and at least one second auxiliary subcircuit; wherein,

[0005] The input sub-circuit is configured to respond to an input signal and precharge a pull-up node; the pull-up node is a connection node between the input sub-circuit, the output sub-circuit and the pull-up reset sub-circuit;

[0006] The output sub-circuit is configured to output the clock signal through the signal output terminal under the control of the potential of the pull-up node;

[0007] The output reset subcircuit is configured to reset the output of the signal output terminal through a non-working level signal under the control of the output reset signal;

[0008] The pull-up reset subcircuit comprises a first transistor; a first electrode of the first transistor is connected to the pull-up node, a second electrode is connected to the first auxiliary subcircuit and the second auxiliary subcircuit, and a control electrode is connected to the pull-up reset signal terminal;

[0009] The first auxiliary sub-circuit is configured to respond to a first control signal and pull down the potential of the second electrode of the first transistor to a first potential when the first transistor is turned off;

[0010] The second auxiliary sub-circuit is configured to respond to a second control signal and, when the first transistor is turned on, write the non-operating level signal into the second electrode of the first transistor to reset the potential of the pull-up node.

[0011] The potential of the pull-up node serves as the first control signal, and the pull-up reset signal provided by the pull-up reset signal terminal serves as the second control signal;

[0012] The control end of the first auxiliary sub-circuit is connected to the pull-up node, the first end is connected to the second electrode of the first transistor, and the second end is connected to the first potential signal end;

[0013] The control end of the second auxiliary sub-circuit is connected to the pull-up reset signal end, the first end is connected to the second electrode of the first transistor, and the second end is connected to the non-working level end.

[0014] Wherein, the first auxiliary sub-circuit includes a fifteenth transistor; the second auxiliary sub-circuit includes a seventeenth transistor;

[0015] The first electrode of the fifteenth transistor is connected to the second electrode of the first transistor and the first electrode of the seventeenth transistor, the second electrode is connected to the first potential signal terminal, and the control electrode is connected to the pull-up node;

[0016] The second electrode of the seventeenth transistor is connected to the non-working level end, and the control electrode is connected to the pull-up reset signal end.

[0017] The shift register further comprises: at least one pull-down control subcircuit and at least one pull-down subcircuit; one pull-down control subcircuit is electrically connected to one pull-down subcircuit, and a connection node between the two is a pull-down node;

[0018] The pull-down control subcircuit is configured to respond to a first power supply voltage and control the potential of the pull-down node connected thereto through the first power supply voltage;

[0019] The pull-down sub-circuit is configured to respond to the potential of the pull-up node and pull down the potential of the pull-down node connected thereto through the non-operating level signal.

[0020] Wherein, any of the pull-down control sub-circuits includes: a fifth transistor and a ninth transistor; any of the pull-down sub-circuits includes: a sixth transistor and an eighth transistor;

[0021] The first electrode of the fifth transistor is connected to the first electrode of the ninth transistor and the first power supply voltage terminal, the second electrode is connected to one of the pull-down nodes, the control electrode is connected to the second electrode of the ninth transistor, and the first electrode of the ninth transistor is connected to the control electrode;

[0022] The first electrode of the sixth transistor is connected to the pull-down node, the second electrode is connected to the non-working level end, and the control electrode is connected to the pull-up node;

[0023] The first electrode of the eighth transistor is connected to the second electrode of the ninth transistor in the pull-down control subcircuit connected to the pull-down subcircuit, the second electrode is connected to the non-working level end, and the control electrode is connected to the pull-up node.

[0024] Wherein, the shift register further includes: at least one first noise reduction sub-circuit and at least one second noise reduction sub-circuit;

[0025] a first noise reduction sub-circuit, configured to be controlled by the potential of one of the pull-down nodes and to reduce the potential of the pull-up node by using the non-working level signal, wherein different first noise reduction sub-circuits are controlled by different pull-down nodes;

[0026] A second noise reduction sub-circuit is configured to be controlled by the potential of a pull-down node and to reduce the noise of the output of the signal output end through the non-working level signal, and different second noise reduction sub-circuits are controlled by different pull-down nodes.

[0027] Wherein, any of the first noise reduction sub-circuits includes a tenth transistor;

[0028] The first electrode of the tenth transistor is connected to the pull-up node, the second electrode is connected to the non-working level end, and the control electrode is connected to the pull-down node;

[0029] Any of the second noise reduction sub-circuits includes an eleventh transistor;

[0030] The first electrode of the eleventh transistor is connected to the pull-up node, the second electrode is connected to the non-working level end, and the control electrode is connected to the signal output end.

[0031] There are multiple second auxiliary sub-circuits; the potential of the pull-up node serves as the first control signal, and the potential of one pull-down node serves as the second control signal of one second auxiliary sub-circuit;

[0032] The control end of the first auxiliary sub-circuit is connected to the pull-up node, the first end is connected to the second electrode of the first transistor, and the second end is connected to the first potential signal end;

[0033] A control terminal of the second auxiliary sub-circuit is connected to one of the pull-down nodes, a first terminal is connected to the second electrode of the first transistor, and a second terminal is connected to the non-working level terminal.

[0034] Wherein, the first auxiliary sub-circuit includes a fifteenth transistor; any of the second auxiliary sub-circuits includes a seventeenth transistor;

[0035] The first electrode of the fifteenth transistor is connected to the second electrode of the first transistor and the first electrode of the seventeenth transistor, the second electrode is connected to the first potential signal terminal, and the control electrode is connected to the pull-up node;

[0036] The second electrode of any one of the seventeenth transistors is connected to the non-working level end; the control electrode of one of the seventeenth transistors is connected to one of the pull-down nodes.

[0037] There are multiple second auxiliary sub-circuits; the potential of the pull-up node serves as the first control signal, and the potential of one pull-down node serves as the second control signal of one second auxiliary sub-circuit;

[0038] The control end of the first auxiliary sub-circuit is connected to the pull-up node, the first end is connected to the second electrode of the tenth transistor, and the second end is connected to the first potential signal end;

[0039] A control terminal of the second auxiliary sub-circuit is connected to one of the pull-down nodes, a first terminal is connected to the second electrode of the first transistor, and a second terminal is connected to the non-working level terminal.

[0040] Wherein, the first auxiliary sub-circuit includes a fifteenth transistor; any of the second auxiliary sub-circuits includes a seventeenth transistor;

[0041] The first electrode of the fifteenth transistor is connected to the second electrode of the tenth transistor and the first electrode of the seventeenth transistor, the second electrode is connected to the first potential signal terminal, and the control electrode is connected to the pull-up node;

[0042] The second electrode of any one of the seventeenth transistors is connected to the non-working level end; the control electrode of one of the seventeenth transistors is connected to one of the pull-down nodes.

[0043] Wherein, the shift register further includes a third auxiliary subcircuit and at least one fourth auxiliary subcircuit;

[0044] The third auxiliary sub-circuit is configured to write a non-operating level signal into a first electrode of an eighth transistor and a pull-down node under the control of the potential of the pull-up node;

[0045] One of the fourth auxiliary sub-circuits is configured to pull down the potentials of the second electrodes of the sixth transistor and the eighth transistor to the first potential when the sixth transistor and the eighth transistor in one of the pull-down sub-circuits are turned off.

[0046] Wherein, the third auxiliary sub-circuit includes an eighteenth transistor; any of the fourth auxiliary sub-circuits includes a nineteenth transistor;

[0047] The first electrode of the eighteenth transistor is connected to the first electrode of the nineteenth transistor, the second electrode is connected to the non-working level end, and the control electrode is connected to the pull-up node;

[0048] The first electrode of the nineteenth transistor is connected to the second electrode of the sixth transistor and the second electrode of the eighth transistor in the pull-down sub-circuit, the second electrode is connected to the first potential signal terminal, and the control electrode is connected to the pull-down node.

[0049] Wherein, the shift register further includes a fifth auxiliary subcircuit and at least one sixth auxiliary subcircuit;

[0050] The fifth auxiliary sub-circuit is configured to write the first potential into the first electrode of the eleventh transistor under the control of the potential of the pull-up node and when the eleventh transistor is turned off;

[0051] The sixth auxiliary sub-circuit is configured to pull down the potential of the signal output terminal through the non-working level signal when the eleventh transistor is turned on.

[0052] Wherein, the fifth auxiliary sub-circuit includes a twentieth transistor; any of the sixth auxiliary sub-circuits includes a twenty-first transistor;

[0053] The first electrode of the 20th transistor is connected to the second electrode of the 11th transistor, the second electrode is connected to the first potential signal terminal, and the control electrode is connected to the pull-up node;

[0054] A first electrode of the twenty-first transistor is connected to the first electrode of the twentieth transistor, a second electrode is connected to the non-working level end, and a control electrode is connected to the pull-down node.

[0055] The shift register further includes at least one seventh auxiliary sub-circuit; one of the seventh auxiliary sub-circuits is configured to pull down the potential of one of the pull-down nodes through a non-working level signal under the control of an input signal.

[0056] Wherein, any of the seventh auxiliary sub-circuits includes a sixteenth transistor;

[0057] A first electrode of the sixteenth transistor is connected to one of the pull-down nodes, a second electrode is connected to the non-working level end, and a control electrode is connected to the signal input end.

[0058] The shift register further includes: a frame reset subcircuit configured to reset the potential of the pull-up node through a non-working level signal in response to a frame reset signal.

[0059] Wherein, the frame reset sub-circuit includes a seventh transistor,

[0060] The first electrode of the seventh transistor is connected to the pull-up node, the second electrode is connected to the non-working level end, and the control electrode is connected to the frame reset signal end.

[0061] Wherein, the input sub-circuit includes a second transistor;

[0062] The first electrode and the control electrode of the second transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node.

[0063] Wherein, the output sub-circuit includes a third transistor and a storage capacitor;

[0064] The first electrode of the third transistor is connected to the clock signal terminal, the second electrode is connected to the signal output terminal, and the control electrode is connected to the pull-up node;

[0065] A first end of the storage capacitor is connected to the pull-up node, and a second end is connected to the signal output end.

[0066] In a second aspect, an embodiment of the present disclosure further provides a gate drive circuit, which includes a plurality of cascaded shift registers; the shift register includes any of the above-mentioned shift registers.

[0067] In a third aspect, an embodiment of the present disclosure provides a display panel comprising the above-mentioned gate driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 A schematic diagram of an exemplary shift register.

[0069] Figure 2 is a schematic diagram of an exemplary gate drive circuit.

[0070] Figure 3 FIG. 4 is a schematic diagram of another exemplary shift register.

[0071] Figure 4 Schematic diagram of a shift register according to an embodiment of the present disclosure.

[0072] Figure 5 This is the characteristic curve of the gate-source voltage and leakage current of the a-si thin film transistor.

[0073] Figure 6 Schematic diagram of another shift register according to an embodiment of the present disclosure.

[0074] Figure 7 Schematic diagram of another shift register according to an embodiment of the present disclosure.

[0075] Figure 8 Schematic diagram of another shift register according to an embodiment of the present disclosure.

[0076] Figure 9 Schematic diagram of another shift register according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0077] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0078] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0079] It should be noted that the transistors used in the embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present invention, in order to distinguish the source and drain of the transistor, one of the poles is called the first pole, the other pole is called the second pole, and the gate is called the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are explained with N-type transistors. When an N-type transistor is used, the first pole is the source of the N-type transistor, and the second pole is the drain of the N-type transistor. When the gate input is a high level, the source and drain are turned on, and the P-type is the opposite. It can be imagined that the use of P-type transistors is something that a person skilled in the art can easily think of without creative work, and therefore it is also within the scope of protection of the embodiments of the present invention.

[0080] Among them, since the transistor used in the embodiment of the present invention is an N-type transistor, the working level signal in the embodiment of the present invention refers to a high level signal, and the non-working level signal is a low level signal; the corresponding working level end is a high level signal end, and the non-working level end is a low level signal end.

[0081] Typically, a display panel includes multiple gate lines and multiple data lines. The gate lines and data lines intersect to define multiple pixel regions, each of which is provided with pixel cells. The structure of the display panel is described below using the example of the direction in which each gate line extends as a row direction and the direction in which each data line extends as a column direction. When the display panel is driven to display, gate scan signals are written to the gate lines row by row, and data voltage signals are written to the data lines simultaneously, so that the pixel cells in the display panel are illuminated row by row, depending on the image to be displayed.

[0082] Among them, the gate scan signal is provided by the gate drive circuit, and the data voltage signal is provided by the source drive circuit; in the related technology, the gate drive circuit can be integrated into the gate drive chip, and the source drive circuit can be integrated into the source drive chip; and currently, in order to reduce the number of chips and achieve a narrow frame or no frame, a technology for integrating the gate drive circuit on an array substrate (Gate On Array; GOA) is provided; wherein, the gate drive circuit includes a plurality of cascaded shift registers integrated on the array substrate, each shift register is connected to a gate line one-to-one, and is used to provide a gate scan signal to the gate line connected thereto.

[0083] In order to make it clearer how the shift register outputs the gate scanning signal, a specific example of the shift register is used for explanation below.

[0084] In one example, if Figure 1 The circuit diagram of the shift register shown in the figure; the shift register includes an input sub-circuit 1, an output sub-circuit 2, a pull-up reset sub-circuit 3, and an output reset sub-circuit 4; wherein, the input sub-circuit 1 responds to the input signal input by the signal input terminal INPUT, and charges the pull-up node PU through the input signal; the output sub-circuit 2 responds to the potential of the pull-up node PU, and outputs the clock signal input by the clock signal terminal through the signal output terminal OUTPUT; the pull-up reset sub-circuit 3 responds to the pull-up reset signal output by the pull-up reset signal terminal RST_PU, and resets the pull-up node PU through a low-level signal; the output reset sub-circuit 4 responds to the output reset signal written by the output reset signal terminal RST_OUTPUT, and resets the output of the signal output terminal OUTPUT through a low-level signal.

[0085] Specifically, such as Figure 1As shown, the input sub-circuit 1 includes a second transistor M2; the pull-up reset sub-circuit 3 includes a first transistor M1; the output sub-circuit 2 includes a third transistor M3 and a storage capacitor C; the output reset sub-circuit 4 includes a fourth transistor M4; wherein, the gate and source of M2 are connected to the signal input terminal INPUT, and the drain of M2 is connected to the pull-up node PU; the gate of M1 is connected to the pull-up reset signal terminal RST_PU, the source of M1 is connected to the pull-up node PU, and the drain of M1 is connected to the low-level signal terminal; the gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal CLK, and the drain of M3 is connected to the signal output terminal OUTPUT; the first end of C is connected to the pull-up node PU, and the second end of C is connected to the signal output terminal OUTPUT; the gate of M4 is connected to the output reset signal terminal RST_OUTPUT, the source of M4 is connected to the signal output terminal OUTPUT, and the drain of M4 is connected to the low-level signal terminal.

[0086] Pre-charge stage: A high-level signal is written to the signal input terminal INPUT, M1 is turned on, the PU point is pulled high by the high-level signal, and C is charged.

[0087] Output stage: Since the PU point is pulled high in the input stage, M3 is turned on, and the high-level signal input by the clock signal terminal CLK is output to the gate line connected to the shift register through the signal output terminal OUTPUT.

[0088] In the reset stage, a high-level signal is input to the output reset signal terminal RST_OUTPUT, M4 is turned on, and the output of the signal output terminal OUTPUT is pulled low by the low-level signal input via the low-level signal terminal; a high-level signal is input to the pull-up reset signal terminal RST_PU, M1 is turned on, and the low-level signal input via the low-level signal terminal VGL pulls down the potential of the pull-up node PU, thereby completing the reset of the pull-up node PU and the signal output terminal OUTPUT.

[0089] It should be noted here that the output reset sub-circuit 4 may not be set in the shift register. After the pull-up node PU is reset in the reset phase, the pull-up node PU is at a low level. At this time, M3 is turned off, and the signal output terminal OUTPUT no longer outputs, thereby completing the reset of the signal output terminal OUTPUT.

[0090] In addition, for the gate drive circuit using the above shift register, if Figure 2 As shown, the cascade relationship of the 1st to 4th shift registers (GOA1-GOA4) is taken as an example; wherein the signal output terminal OUTPUT of the current stage shift register is connected to the pull-up reset signal terminal RST_PU of the previous stage shift register and the signal input terminal INPUT of the next stage shift register.

[0091] In another example, Figure 3As shown, to optimize the shift register, a device is provided that includes not only the aforementioned input subcircuit 1, output subcircuit 2, pull-up reset subcircuit 3, and output reset subcircuit 4, but also two pull-down control subcircuits, two pull-down subcircuits, two first noise reduction subcircuits, two second noise reduction circuits, two seventh auxiliary subcircuits, and a frame reset subcircuit 9. The two pull-down control subcircuits are pull-down control subcircuit 5 and pull-down control subcircuit 5'; the two pull-down subcircuits are pull-down subcircuit 6 and pull-down subcircuit 6'; the two first noise reduction subcircuits are first noise reduction subcircuit 7 and first noise reduction subcircuit 7'; the two second noise reduction subcircuits are second noise reduction subcircuit 8 and second noise reduction subcircuit 8'; and the two seventh auxiliary subcircuits are seventh auxiliary subcircuit 10 and seventh auxiliary subcircuit 10'. The connection node between pull-down control subcircuit 5 and pull-down subcircuit 6 is pull-down node PD1, and the connection node between pull-down control subcircuit 5' and pull-down subcircuit 6' is pull-down node PD2. The first noise reduction sub-circuit 7 and the second noise reduction sub-circuit 8 are both controlled by the pull-down node PD1, that is, connected to the pull-down control node PD1. The first noise reduction sub-circuit 7' and the second noise reduction sub-circuit 8' are both controlled by the pull-down node PD2, that is, connected to the pull-down control node PD2.

[0092] It should be noted that the pull-down control subcircuit 5 and the pull-down control subcircuit 5' have the same structure and function; the pull-down subcircuit 6 and the pull-down subcircuit 6' have the same structure and function; the first noise reduction subcircuit 7 and the first noise reduction subcircuit 7' have the same structure and function; the second noise reduction subcircuit 8 and the second noise reduction subcircuit 8' have the same structure and function; and the seventh auxiliary subcircuit 10 and the seventh auxiliary subcircuit 10' have the same structure and function. During the scan time of a single frame, the pull-down control subcircuit 5, the pull-down subcircuit 6, the first noise reduction subcircuit 7, the second noise reduction subcircuit 8, and the seventh auxiliary subcircuit 10 are all operational, or the pull-down control subcircuit 5', the pull-down subcircuit 6', the first noise reduction subcircuit 7', the second noise reduction subcircuit 8', and the seventh auxiliary subcircuit 10' are all operational. This approach can extend the service life of the shift register. The following description focuses on the operation of the pull-down control sub-circuit 5, pull-down sub-circuit 6, first noise reduction sub-circuit 7, second noise reduction sub-circuit 8, and seventh auxiliary sub-circuit 10 within the scanning time of a single frame. The input sub-circuit 1, output sub-circuit 2, pull-up reset sub-circuit 3, and output reset sub-circuit 4 have the same structures and functions as described above, and therefore are not repeated here.

[0093] Among them, the seventh auxiliary sub-circuit 10 responds to the input signal input by the signal input terminal INPUT, and pulls down the pull-down node PD1 through a low-level signal; the seventh auxiliary sub-circuit 10' responds to the input signal input by the signal input terminal INPUT, and pulls down the pull-down node PD2 through a low-level signal. The pull-down control sub-circuit 5 responds to the first power supply voltage input by the first power supply voltage signal terminal VDD1 to control the potential of the first pull-down node PD1; the pull-down control sub-circuit 5' responds to the first power supply voltage input by the first power supply voltage signal terminal VDD2 to control the potential of the pull-down node PD2; the pull-down sub-circuit 6 responds to the pull-up node PU, and pulls down the pull-down node PD1 and the pull-down control node PD_CN1 through a low-level signal input by the low-level signal terminal VGL; the pull-down sub-circuit 6' responds to the pull-up node PU, and pulls down the second pull-down node PD2 and the pull-down control node PD_CN2 through a low-level signal input by the low-level signal terminal VGL; A first noise reduction sub-circuit 7, in response to the potential of the pull-down node PD1, reduces noise on the output of the pull-up node PU via a level signal input from a low-level signal terminal. A first noise reduction sub-circuit 7', in response to the potential of the pull-down node PD2, reduces noise on the output of the pull-up node PU via a level signal input from a low-level signal terminal. A second noise reduction sub-circuit 8, in response to the potential of the pull-down node PD1, reduces noise on the output of the signal output terminal OUTPUT via a level signal input from a low-level signal terminal. A second noise reduction sub-circuit 8', in response to the potential of the pull-down node PD2, reduces noise on the output of the signal output terminal OUTPUT via a level signal input from a low-level signal terminal. A frame reset sub-circuit 9, in response to a frame reset signal STV, resets the pull-up node via a low-level signal input from a low-level signal terminal VGL.

[0094] In addition, for the gate drive circuit using the above shift register, if Figure 2 As shown, the signal output terminal OUTPUT of the current shift register is connected to the pull-up reset signal terminal RST_PU of the previous shift register and the signal input terminal INPUT of the next shift register. Figure 3As shown, the pull-down control subcircuit 5 and the pull-down control subcircuit 5' both include a fifth transistor and a ninth transistor; the fifth transistor in the pull-down control subcircuit 5 and the pull-down control subcircuit 5' are represented by M5 and M5', respectively, and the ninth transistor is represented by M9 and M9', respectively. The pull-down subcircuit 6 and the pull-down subcircuit 6' both include a sixth transistor and an eighth transistor; the sixth transistor in the pull-down subcircuit 6 and the pull-down subcircuit 6' are represented by M6 and M6', respectively, and the eighth transistor is represented by M8 and M8', respectively. The first noise reduction subcircuit 7 and the first noise reduction subcircuit 7' both include a tenth transistor; the tenth transistor in the first noise reduction subcircuit 7 and the first noise reduction subcircuit 7' are represented by M10 and M10', respectively. The second noise reduction subcircuit 8 and the second noise reduction subcircuit 8' both include an eleventh transistor; the eleventh transistor in the second noise reduction subcircuit 8 and the second noise reduction subcircuit 8' are represented by M11 and M11', respectively. The frame reset subcircuit 9 includes a seventh transistor, M7. The seventh auxiliary sub-circuit 10 and the seventh auxiliary sub-circuit 10 ′ each include a sixteenth transistor, and the sixteenth transistors in the seventh auxiliary sub-circuit 10 and the seventh auxiliary sub-circuit 10 ′ are denoted by M16 and M16 ′, respectively.

[0095] Continue to refer to Figure 3, the gate and source of M2 are connected to the signal input terminal INPUT, and the drain of M2 is connected to the pull-up node PU; the gate of M1 is connected to the pull-up reset signal terminal RST_PU, the source of M1 is connected to the pull-up node PU, and the drain of M2 is connected to the low-level signal terminal VGL; the gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal CLK, and the drain of M3 is connected to the signal output terminal OUTPUT; the first end of C is connected to the pull-up node PU, and the second end of C is connected to the signal output terminal OUTPUT; the gate and source of M9 are both connected to the first power supply voltage terminal VDD1, and the drain of M9 is connected to the pull-down control node PD_CN1; the gate of M5 is connected to the pull-down control node PD_CN1, and M The source of M5 is connected to the first power supply voltage terminal VDD1, and the drain of M5 is connected to the first pull-down node PD1; the gate and source of M9' are both connected to the first power supply voltage terminal VDD2, and the drain of M9' is connected to the pull-down control node PD_CN2; the gate of M5' is connected to the pull-down control node PD_CN2, the source of M5' is connected to the first power supply voltage terminal VDD2, and the drain of M5' is connected to the second pull-down node PD2; the gate of M6 is connected to the pull-up node PU, the source of M6 is connected to the pull-down node PD1, and the drain of M6 is connected to the low-level signal terminal VGL; the gate of M8 is connected to the pull-up node PU, the source of M8 is connected to the pull-down control node PD_CN1, and the drain of M8 is connected to the low-level signal terminal VGL ; The gate of M6' is connected to the pull-up node PU, the source of M6' is connected to the pull-down node PD2, and the drain of M6' is connected to the low-level signal terminal VGL; the gate of M8' is connected to the pull-up node PU, the source of M8' is connected to the second pull-down control node PD_CN2, and the drain of M8' is connected to the low-level signal terminal VGL; the gate of M10 is connected to the pull-down node PD1, the source of M10 is connected to the pull-up node PU, and the drain of M10 is connected to the low-level signal terminal VGL; the gate of M11 is connected to the pull-down node PD1, the source of M11 is connected to the signal output terminal OUTPUT, and the drain of M11 is connected to the low-level signal terminal VGL; the gate of M10' is connected to the pull-down node PD2, and the source of M10' is connected The pull-up node PU and the drain of M10' are connected to the low-level signal terminal VGL. The gate of M11' is connected to the pull-down node PD2, the source of M11' is connected to the signal output terminal OUTPUT, and the drain of M11' is connected to the low-level signal terminal VGL. The gate of M12' is connected to the second pull-down node PD2, the source of M12' is connected to the cascade signal output terminal OUT_C, and the drain of M12' is connected to the low-level signal terminal. The gate of M7 is connected to the frame reset signal terminal STV, the source of M7 is connected to the pull-up node PU, and the drain of M7 is connected to the low-level signal terminal. The gate of M16 is connected to the signal input terminal INPUT, the source of M16 is connected to the pull-down node PD1, and the drain of M16 is connected to the low-level signal terminal. The gate of M16' is connected to the signal input terminal INPUT, the source of M16' is connected to the pull-down node PD2, and the drain of M16' is connected to the low-level signal terminal VGL.

[0096] Frame reset stage: In the frame reset stage, before display, a high-level signal is input to the frame reset signal terminal STV, and a low-level signal is input through the low-level signal terminal VGL to discharge the pull-up node PU to prevent residual charge on the pull-up node PU from causing display abnormalities.

[0097] In the pre-charge stage, a high-level signal is input to the signal input terminal INPUT, M2 is turned on, the pull-up node PU is pulled high by the high-level signal, and C is charged. At the same time, M16 and M16' are both turned on, pulling down the pull-down nodes PD1 and PD2 to avoid affecting the potential of the pull-up node PU.

[0098] In the output stage, since the pull-up node PU is pulled high in the pre-charge stage, M3 is turned on, and the high-level signal input by the clock signal terminal CLK is output to the gate line connected to it through the signal output terminal OUTPUT. At the same time, the signal output by the signal output terminal OUTPUT is the same, that is, a high-level signal is output to the pull-up reset signal terminal RST_PU of the previous stage shift register and the signal input terminal INPUT of the next stage shift register.

[0099] During the reset phase, a high-level signal is input to the pull-up reset signal terminal RST_PU. M1 turns on, and a low-level signal is input via the low-level signal terminal VGL, pulling the potential of the pull-up node PU down to reset it. A high-level signal is input to the output reset signal terminal RST_OUTPUT. M4 turns on, and a low-level signal is input via the low-level signal terminal VGL, pulling the output of the signal output terminal OUTPUT down.

[0100] Noise reduction stage: the pull-down control node PD_CN1 and the pull-down node PD1 are both the first power supply voltage, that is, a high-level signal, M10 and M11 are turned on, and the output of the pull-up node and the signal output terminal OUTPUT are respectively subjected to noise reduction until the pull-up node PU potential is pulled high at the start of the next frame scan.

[0101] First, as Figure 4As shown, an embodiment of the present disclosure provides a shift register, which includes an input subcircuit 1, an output subcircuit 2, a pull-up reset subcircuit 3, an output reset subcircuit 4, a first auxiliary subcircuit 11, and a second auxiliary subcircuit 12. The connection node between the input subcircuit 1, the output subcircuit 2, and the pull-up reset subcircuit 33 is a pull-up node PU. The input subcircuit 1 is configured to respond to an input signal and precharge the pull-up node PU. The output subcircuit 2 is configured to output a clock signal through a signal output terminal OUTPUT under the control of the potential of the pull-up node PU. The output reset subcircuit 4 is configured to reset the output of the signal output terminal OUTPUT through a low-level signal under the control of an output reset signal. The pull-up reset subcircuit 3 may include a first transistor M1, the source of which is connected to the pull-up node PU, the drain of which is connected to the first auxiliary subcircuit 11 and the second auxiliary subcircuit 12, and the gate of which is connected to the pull-up reset signal terminal RST_PU. The first auxiliary sub-circuit 11 is configured to respond to a first control signal and, when the first transistor is turned off, pull down the potential of the drain of the first transistor M1 to a first potential. The second auxiliary sub-circuit 12 is configured to respond to a second control signal and, when the first transistor M1 is turned on, write a low-level signal into the drain of the first transistor M1 to reset the potential of the pull-up node PU.

[0102] It should be noted that the first potential is determined by the type of thin-film transistor. In the embodiments of the present disclosure, the thin-film transistors are A-Si thin-film transistors. The first potential includes, but is not limited to, ground potential, i.e., the first potential is 0 V. The potentials of the pull-up reset signal and the low-level signal include, but are not limited to, -8 V. In the embodiments of the present disclosure, the first potential is 0 V, and both the pull-up reset signal and the low-level signal are 8 V.

[0103] In the embodiment of the present disclosure, when the first transistor M1 is turned off, the first auxiliary sub-circuit 11 operates under the control of the first control signal and writes the first potential into the drain of the first transistor M1. At this time, the gate-source voltage of the first transistor M1 is -8V. Figure 5 As shown, according to the characteristic curve of the thin film transistor, it can be seen that when the gate-source voltage of the first transistor M1 is -8V, the leakage current is significantly reduced, thereby improving the performance of the display panel using the shift register according to the embodiment of the present disclosure.

[0104] In some examples, in order to reduce wiring, the potential of the pull-up node PU can be used as the first control signal, and the pull-up reset signal provided by the pull-up reset signal terminal RST_PU can be used as the second control signal. Figure 4As shown, the control terminal of the first auxiliary subcircuit 11 is connected to the pull-up node PU, the first terminal of the first auxiliary subcircuit 11 is connected to the drain of the first transistor M1, and the second terminal of the first auxiliary subcircuit 11 is connected to the first potential signal terminal VGND. The control terminal of the second auxiliary subcircuit 12 is connected to the pull-up reset signal terminal RST_PU, the first terminal of the second auxiliary subcircuit 12 is connected to the drain of the first transistor M1, and the second terminal of the second auxiliary subcircuit 12 is connected to the low-level signal terminal VGL. In this way, when the potential of the pull-up node PU is a high-level signal, the first auxiliary subcircuit 11 operates, pulling the drain potential of the first transistor down to the first potential, that is, 0V, so that the gate-source voltage of the first transistor M1 is -8V, thereby effectively reducing the leakage current of the first transistor. When the pull-up reset signal terminal RST_PU is a high-level signal, the first transistor M1 is turned on, and the second auxiliary sub-circuit 12 works, writing a low-level signal into the drain of the first transistor M1, and pulling the pull-up node PU down to a low-level signal through the first transistor M1, thereby realizing the reset of the pull-up node PU.

[0105] Furthermore, the first auxiliary sub-circuit 11 may include a fifteenth transistor M15, and the second auxiliary sub-circuit 12 may include a seventeenth transistor M17. In this case, the source, drain, and gate of the fifteenth transistor M15 serve as the first terminal, second terminal, and control terminal of the first auxiliary sub-circuit 11, respectively; the source, drain, and gate of the seventeenth transistor M17 serve as the first terminal, second terminal, and control terminal of the second auxiliary sub-circuit 12, respectively. The source of the fifteenth transistor M15 is connected to the drain of the first transistor M1 and the source of the seventeenth transistor M17, the drain of the fifteenth transistor M15 is connected to the first potential signal terminal VGND, and the gate of the fifteenth transistor M15 is connected to the pull-up node PU. The drain of the seventeenth transistor M17 is connected to the low-level signal terminal VGL, and the gate of the seventeenth transistor M17 is connected to the pull-up reset signal terminal RST_PU. For example, when the potential of the pull-up node PU is a high-level signal, the fifteenth transistor M15 turns on, and the first potential written to the first potential signal terminal VGND is written to the drain of the first transistor M1 through the fifteenth transistor M15. When a high-level signal is written to the pull-up reset signal terminal RST_PU, the first transistor M1 and the seventeenth transistor M17 are both turned on. At this time, the low-level signal written to the low-level signal terminal VGL pulls down the potential of the pull-up node PU through the seventeenth transistor and the first transistor M17, thereby resetting the pull-up node PU.

[0106] In some examples, the input sub-circuit 1, the output sub-circuit 2, and the output reset sub-circuit 4 can be connected to Figure 1The input subcircuit 1, output subcircuit 2 and output reset subcircuit 4 in the shift register shown in FIG have the same structure. That is, the input subcircuit 1 may include a second transistor M2, the output subcircuit 2 may include a third transistor M3 and a storage capacitor C, and the output reset subcircuit 4 may include a fourth transistor M4. The specific connection relationship is the same as Figure 1 The shift registers shown are the same and will not be described again here.

[0107] As an example, the structure and working process of the shift register of the embodiment of the present disclosure are more clearly shown. Figure 4 Taking the shift register shown in FIG. 1 as an example, the working process of the shift register is explained.

[0108] like Figure 4 As shown, the pull-up reset subcircuit 3 includes a first transistor, the input subcircuit 1 includes a second transistor, the output subcircuit 2 includes a third transistor and a storage capacitor, the output reset subcircuit 4 includes a fourth transistor, the first auxiliary subcircuit 11 includes a fifteenth transistor, and the second auxiliary subcircuit 12 includes a seventeenth transistor.

[0109] Pre-charge phase: A high-level signal is input to the signal input terminal INPUT, the second transistor is turned on, and the potential of the pull-up node PU is pulled high by the high-level signal written by the signal input terminal INPUT, thereby pre-charging the pull-up node PU. At the same time, since the potential of the pull-up node PU is pulled high, the fifteenth transistor M15 is turned on, and the first potential signal terminal VGND writes the first potential (0V) to the drain of the first transistor M1. At this time, the gate-source voltage Vgs of the first transistor M1 is -8V, and the first transistor M1 is turned off, which can effectively reduce the leakage current of the first transistor M1, thereby effectively avoiding the problem of power failure of the pull-up node PU.

[0110] Output phase: A high-level signal is written to the clock signal terminal CLK, further raising the potential of the pull-up node PU. The third transistor M3 turns on, and the signal output terminal OUTPUT outputs a high-level signal. During this phase, the gate-source voltage Vgs of the first transistor remains at -8V, and the first transistor M1 remains off.

[0111] Reset phase: A high-level signal is input to the output reset signal terminal RST_OUTPUT, turning on the fourth transistor. A low-level signal input via the low-level signal terminal VGL pulls the output of the signal output terminal OUTPUT low. A high-level signal is input to the pull-up reset signal terminal RST_PU, turning on the first transistor M1 and the seventeenth transistor M17. A low-level signal input via the low-level signal terminal VGL pulls the potential of the pull-up node PU low, thus completing the reset of the pull-up node PU and the signal output terminal OUTPUT.

[0112] like Figure 6As shown, the embodiment of the present disclosure also provides a shift register, which not only includes the above-mentioned input sub-circuit 1, output sub-circuit 2, pull-up reset sub-circuit 3, output reset sub-circuit 4, first auxiliary sub-circuit 11 and second auxiliary sub-circuit 12, but also includes at least one pull-down control sub-circuit, at least one pull-down sub-circuit, at least one first noise reduction sub-circuit and at least one second noise reduction sub-circuit. Figure 6 In the example, the number of the pull-down control sub-circuit, the pull-down sub-circuit 6, the first noise reduction sub-circuit and the second noise reduction sub-circuit is two. Figure 3 Similarly, the two pull-down control subcircuits are pull-down control subcircuit 5 and pull-down control subcircuit 5'; the two pull-down subcircuits are pull-down subcircuit 6 and pull-down subcircuit 6'; the two first noise reduction subcircuits are first noise reduction subcircuit 7 and first noise reduction subcircuit 7'; the two second noise reduction subcircuits are second noise reduction subcircuit 8 and second noise reduction subcircuit 8'; and the two seventh auxiliary subcircuits are seventh auxiliary subcircuit 10 and seventh auxiliary subcircuit 10'. The connection node between pull-down control subcircuit 5 and pull-down subcircuit 6 is pull-down node PD1, and the connection node between pull-down control subcircuit 5' and pull-down subcircuit 6' is pull-down node PD2. Both first noise reduction subcircuit 7 and second noise reduction subcircuit 8 are controlled by pull-down node PD1, that is, connected to pull-down control node PD1. Both first noise reduction subcircuit 7' and second noise reduction subcircuit 8' are controlled by pull-down node PD2, that is, connected to pull-down control node PD2.

[0113] It should be noted that the pull-down control subcircuit 5 and the pull-down control subcircuit 5' have the same structure and function; the pull-down subcircuit 6 and the pull-down subcircuit 6' have the same structure and function; the first noise reduction subcircuit 7 and the first noise reduction subcircuit 7' have the same structure and function; the second noise reduction subcircuit 8 and the second noise reduction subcircuit 8' have the same structure and function; and the seventh auxiliary subcircuit 10 and the seventh auxiliary subcircuit 10' have the same structure and function. During the scan time of a single frame, the pull-down control subcircuit 5, the pull-down subcircuit 6, the first noise reduction subcircuit 7, the second noise reduction subcircuit 8, and the seventh auxiliary subcircuit 10 are all operational, or the pull-down control subcircuit 5', the pull-down subcircuit 6', the first noise reduction subcircuit 7', the second noise reduction subcircuit 8', and the seventh auxiliary subcircuit 10' are all operational. This approach can extend the service life of the shift register. The following description focuses on the operation of the pull-down control sub-circuit 5, pull-down sub-circuit 6, first noise reduction sub-circuit 7, second noise reduction sub-circuit 8, and seventh auxiliary sub-circuit 10 within the scanning time of a single frame. The input sub-circuit 1, output sub-circuit 2, pull-up reset sub-circuit 3, and output reset sub-circuit 4 have the same structures and functions as described above, and therefore are not repeated here.

[0114] In some examples, the pull-down control subcircuit 5 and the pull-down control subcircuit 5' both include a fifth transistor and a ninth transistor; the fifth transistor in the pull-down control subcircuit 5 and the pull-down control subcircuit 5' is represented by M5 and M5', respectively, and the ninth transistor is represented by M9 and M9', respectively. The pull-down subcircuit 6 and the pull-down subcircuit 6' both include a sixth transistor and an eighth transistor; the sixth transistor in the pull-down subcircuit 6 and the pull-down subcircuit 6' is represented by M6 and M6', respectively, and the eighth transistor is represented by M8 and M8', respectively. The first noise reduction subcircuit 7 and the first noise reduction subcircuit 7' both include a tenth transistor; the tenth transistor in the first noise reduction subcircuit 7 and the first noise reduction subcircuit 7' is represented by M10 and M10', respectively. The second noise reduction subcircuit 8 and the second noise reduction subcircuit 8' both include an eleventh transistor; the eleventh transistor in the second noise reduction subcircuit 8 and the second noise reduction subcircuit 8' is represented by M11 and M11', respectively. The specific connection relationship is the same as Figure 3 The shift registers shown are the same and will not be described again here.

[0115] In some examples, the shift register in the embodiments of the present disclosure not only includes the above structure, but also may include a frame reset subcircuit 9, which is configured to reset the potential of the pull-up node PU through a low-level signal in response to a frame reset signal.

[0116] Among them, the frame reset sub-circuit 9 can be used with the above Figure 3 The frame reset subcircuit 9 in the shift register shown has the same structure, that is, it includes a seventh transistor M7, the source of which is connected to the pull-up node PU, the drain of which is connected to the low-level signal terminal VGL, and the gate of which is connected to the frame reset signal terminal. When a high-level signal is written to the frame reset signal terminal STV, the seventh transistor M7 turns on, and the low-level signal written to the low-level signal terminal VGL resets the potential of the pull-up node PU.

[0117] In some examples, the shift register in the embodiments of the present disclosure not only includes the above structure, but also may include at least one seventh auxiliary sub-circuit. Figure 6 In this example, two seventh auxiliary sub-circuits, namely the seventh auxiliary sub-circuit 10 and the seventh auxiliary sub-circuit 10', are used. The seventh auxiliary sub-circuit 10 is configured to pull down the potential of the pull-down node PD1 via a low-level signal under the control of an input signal. The seventh auxiliary sub-circuit 10' is configured to pull down the potential of the pull-down node PD1 via a low-level signal under the control of an input signal.

[0118] The seventh auxiliary sub-circuit 10 and the seventh auxiliary sub-circuit 10' each include a sixteenth transistor, which is represented by M16 and M16' in the seventh auxiliary sub-circuit 10 and the seventh auxiliary sub-circuit 10', respectively. The drain of M10 is connected to the low-level signal terminal VGL; the gate of M11 is connected to the pull-down node PD1, the source of M11 is connected to the signal output terminal OUTPUT, and the drain of M11 is connected to the low-level signal terminal VGL; the gate of M10' is connected to the pull-down node PD2, the source of M10' is connected to the pull-up node PU, and the drain of M10' is connected to the low-level signal terminal VGL. When a high-level signal is written to the signal input terminal INPUT, M16 and M16' are turned on, and the pull-down nodes PD1 and PD2 are pulled down by the low-level signal, thereby preventing leakage of the tenth and eleventh transistors from affecting the stable output of the pull-up node PU.

[0119] In order to make the structure of the shift register of the embodiment of the present disclosure clearer, Figure 6 The working process of the shift register shown in the figure is explained. The structure of the shift register is the same as Figure 3 The structures shown are substantially the same, differing only in that the shift register includes a first auxiliary sub-circuit 11 and two second auxiliary sub-circuits, namely a second auxiliary sub-circuit 12 and a second auxiliary sub-circuit 12'. The first auxiliary sub-circuit 11 includes a fifteenth transistor, designated M15, and the second auxiliary sub-circuit 12 and the second auxiliary sub-circuit 12' each include a seventeenth transistor, designated M17 and M17', respectively. The source of M15 is connected to the drain of M1, the drain of M15 is connected to the first potential signal terminal VGND, and the gate of M15 is connected to the pull-up node PU. The source of M17 and the source of M17' are both connected to the drain of M1, and the drain of M17 and the drain of M17' are both connected to the low-level signal terminal VGL. The gate of M17 is connected to the pull-down node PD1, and the gate of M17' is connected to the pull-down node PD2.

[0120] Frame reset stage: In this stage, before display, the frame reset signal terminal STV inputs a high-level signal, and the low-level signal written by the low-level signal terminal VGL discharges the pull-up node PU to prevent the residual charge of the pull-up node PU from causing display abnormalities.

[0121] Pre-charge phase: A high-level signal is input to the signal input terminal INPUT, M2 is turned on, and the pull-up node PU is pulled high by the high-level signal, and C is charged. At the same time, M16 and M16' are both turned on, pulling down the pull-down nodes PD1 and PD2 to avoid affecting the potential of the pull-up node PU. At the same time, since the potential of the pull-up node PU is pulled high, the fifteenth transistor is turned on, and the first potential signal terminal VGND writes the first potential (0V) to the drain of M1, M7, M10, and M10'. At this time, the gate-source voltage Vgs of M1 is -8V, and M1 is in the off state, which can effectively reduce the leakage current of M1, thereby effectively avoiding the problem of power failure of the pull-up node PU.

[0122] Output phase: Because the pull-up node PU is pulled high during the input phase, M3 turns on, outputting the high-level signal inputted by the clock signal terminal CLK through the signal output terminal OUTPUT to the gate line connected to it. Simultaneously, the signal output terminal OUTPUT outputs a high-level signal to the pull-up reset signal terminal RST_PURESET_PU of the previous-stage shift register and the signal input terminal INPUT of the next-stage shift register. During this phase, the gate-source voltage Vgs of the first transistor remains at -8V, and M1 remains off.

[0123] During the reset phase, a high-level signal is input to the output reset signal terminal RST_OUTPUT, turning on the fourth transistor. The low-level signal input to the low-level signal terminal VGL pulls the output of the signal output terminal OUTPUT low. A high-level signal is input to the pull-up reset signal terminal RST_PU, turning on M1 and M17. The low-level signal input to the low-level signal terminal VGL pulls the potential of the pull-up node PU low, thus completing the reset of the pull-up node PU and the signal output terminal OUTPUT.

[0124] In the noise reduction stage, the pull-down control node PD_CN1 and the pull-down node PD1 are both the first power supply voltage, that is, a high-level signal, M10 and M11 are turned on, and the output of the pull-up node PU and the signal output terminal OUTPUT are respectively subjected to noise reduction until the pull-up node PU potential is pulled high at the start of the next frame scan.

[0125] like Figure 7 As shown, the embodiment of the present disclosure also provides a shift register, the structure of which is similar to Figure 6 The structures are roughly the same, and the only difference is the location of the first auxiliary sub-circuit 11 and the two second auxiliary sub-circuits 12 in the shift register. Figure 7, the first auxiliary sub-circuit 11 of the shift register includes a fifteenth transistor, represented by M15, and the seventh auxiliary sub-circuit 10 and the seventh auxiliary sub-circuit 10' both include seventeenth transistors, represented by M17 and M17' respectively. Among them, the source of M15 is connected to the drain of M10', the drain of M15 is connected to the first potential signal terminal VGND, and the gate of M15 is connected to the pull-up node PU. The source of M17 and the source of M17' are both connected to the source of M15, and the drain of M17 and the drain of M17' are both connected to the low-level signal terminal VGL. The gate of M17 is connected to the pull-down node PD1 and the gate of M17' is connected to the pull-down node PD2. The rest of the structure of the shift register is the same as Figure 6 The shift register structures shown are the same and therefore will not be described again here.

[0126] In order to make the structure of the shift register of the embodiment of the present disclosure clearer, Figure 7 The working process of the shift register shown is explained.

[0127] Frame reset stage: In this stage, before display, a high-level signal is input to the frame reset signal end, and a low-level signal is written to the level signal end to discharge the pull-up node PU to prevent the residual charge of the pull-up node PU from causing display abnormalities.

[0128] Pre-charge phase: A high-level signal is input to the signal input terminal INPUT, M2 is turned on, the pull-up node PU is pulled high by the high-level signal, and C is charged. At the same time, M16 and M16' are both turned on, pulling down the pull-down nodes PD1 and PD2 to avoid affecting the potential of the pull-up node PU. At the same time, since the potential of the pull-up node PU is pulled high, M15 is turned on, and the first potential signal terminal VGND writes the first potential (0V) to the drain of the first transistor. At this time, the gate-source voltages of M1, M7, M10, and M10' are all -8V, and M1, M7, M10, and M10' are all in the off state, which can effectively reduce the leakage current of M1, M7, M10, and M10', thereby effectively avoiding the problem of power failure of the pull-up node PU.

[0129] Output phase: Since the pull-up node PU is pulled high during the input phase, M3 turns on, outputting the high-level signal inputted by the clock signal terminal CLK to the connected gate line through the signal output terminal OUTPUT. At the same time, the signal output terminal OUTPUT outputs a high-level signal to the pull-up reset signal terminal RST_PU of the previous-stage shift register and the signal input terminal INPUT of the next-stage shift register. The gate-source voltage of M1, M7, M10, and M10' all maintains -8V, and M1, M7, M10, and M10' remain in the off state.

[0130] During the reset phase, a high-level signal is input to the output reset signal terminal RST_OUTPUT, M4 turns on, and the low-level signal input to the low-level signal terminal VGL pulls the output of the signal output terminal OUTPUT low. A high-level signal is input to the pull-up reset signal terminal RST_PU, M1 and M17 turn on, and the low-level signal input to the low-level signal terminal VGL pulls the potential of the pull-up node PU low, thus completing the reset of the pull-up node PU and the signal output terminal OUTPUT.

[0131] In the noise reduction stage, the first pull-down control node PD_CN1 and the pull-down node PD1 are both the first power supply voltage, that is, a high-level signal, M17, M10, and M11 are turned on, and the output of the pull-up node PU and the signal output terminal OUTPUT are respectively subjected to noise reduction until the potential of the pull-up node PU is pulled high at the beginning of the next frame scan.

[0132] like Figure 8 As shown, the embodiment of the present disclosure also provides a shift register, which is Figure 7 The structure of the shift register shown is roughly similar, with the only difference being that a third auxiliary sub-circuit 13 and two fourth auxiliary sub-circuits 14 are added to the shift register, and the two fourth auxiliary sub-circuits are the fourth auxiliary sub-circuit 14 and the fourth auxiliary sub-circuit 14'. The third auxiliary sub-circuit 13 is configured to write a low-level signal into the source of M8 and M8' and the pull-down nodes PD1 and PD2 under the control of the potential of the pull-up node PU. The fourth auxiliary sub-circuit 14 is configured to pull down the potential of the drain of M6 and M8 to the first potential when M6 and M8 in a pull-down sub-circuit 6 are turned off; the fourth auxiliary sub-circuit 14' is configured to pull down the potential of the drain of M6' and M8' to the first potential when M6' and M8' in a pull-down sub-circuit 6' are turned off. Reference Figure 8 The third auxiliary sub-circuit 13 includes an eighteenth transistor M18; the fourth auxiliary sub-circuit 14 and the fourth auxiliary sub-circuit 14' each include a nineteenth transistor, represented by M19 and M19', respectively. The source of M18 is connected to the source of M19, the drain of M18 is connected to the low-level signal terminal VGL, and the gate of M18 is connected to the pull-up node PU. The source of M19 and the source of M19' are both connected to the source of M18, the drain of M19 and the drain of M19' are both connected to the first potential signal terminal VGND, the gate of M19 is connected to the pull-down node PD1, and the gate of M19' is connected to the pull-down node PD2.

[0133] In order to make the structure of the shift register of the embodiment of the present disclosure clearer, Figure 8 The working process of the shift register shown is explained.

[0134] Frame reset stage: In this stage, before display, a high-level signal is input to the frame reset signal end, and a low-level signal is written to the level signal end to discharge the pull-up node PU to prevent the residual charge of the pull-up node PU from causing display abnormalities.

[0135] Pre-charge phase: A high-level signal is input to the signal input terminal INPUT, M2 is turned on, and the pull-up node PU is pulled high by the high-level signal, and C is charged. At the same time, M16 and M16' are both turned on, pulling down the pull-down nodes PD1 and PD2 to avoid affecting the potential of the pull-up node PU. At the same time, since the potential of the pull-up node PU is pulled high, the fifteenth transistor is turned on, and the first potential signal terminal VGND writes the first potential (0V) to the drain of M1, M7, M10, and M10'. At this time, the gate-source voltage of M1, M7, M10, and M10' is -8V, and M1, M7, M10, and M10' are all in the off state, which can effectively reduce the leakage current of M1, M7, M10, and M10'. At the same time, since the pull-up node PU is at a high level, M18, M6, M6', M8, and M8 are turned on. At this time, PD1, PD2, PD_CN1, and PD_CN2 can be pulled down by a low-level signal, thereby effectively avoiding the problem of power failure of the pull-up node PU.

[0136] Output phase: Since the pull-up node PU is pulled high during the input phase, M3 turns on, outputting the high-level signal inputted by the clock signal terminal CLK to the connected gate line through the signal output terminal OUTPUT. At the same time, the signal output terminal OUTPUT outputs a high-level signal to the pull-up reset signal terminal RST_PU of the previous-stage shift register and the signal input terminal INPUT of the next-stage shift register. The gate-source voltage of M1, M7, M10, and M10' all maintains -8V, and M1, M7, M10, and M10' remain in the off state.

[0137] During the reset phase, a high-level signal is input to the output reset signal terminal RST_OUTPUT, turning on the fourth transistor. The low-level signal input to the low-level signal terminal VGL pulls the output of the signal output terminal OUTPUT low. A high-level signal is input to the pull-up reset signal terminal RST_PU, turning on M1 and M17. The low-level signal input to the low-level signal terminal VGL pulls the potential of the pull-up node PU low, thus completing the reset of the pull-up node PU and the signal output terminal OUTPUT.

[0138] During the noise reduction phase, the first pull-down control node PD_CN1 and the pull-down node PD1 are both at the first power supply voltage, i.e., a high-level signal. M17, M10, and M19 are turned on, respectively performing noise reduction on the outputs of the pull-up node PU and the signal output terminal OUTPUT, until the pull-up node PU is pulled high at the start of the next frame scan. Simultaneously, due to the turning on of M19, the drain potentials of M6 and M8 are pulled down to the first potential (0V), and the gate-source voltages of M6 and M8 are both -8V, effectively reducing the leakage current of M6 and M8, thereby preventing any impact on the potentials of PD1 and PD_CN1, and effectively improving the noise reduction effect of the pull-up node PU and the signal output terminal OUTPUT.

[0139] like Figure 9 As shown, the embodiment of the present disclosure also provides a shift register, which is Figure 8 The structure of the shift register shown is substantially the same, with the only difference being that a fifth auxiliary subcircuit 15 and two sixth auxiliary subcircuits 16 are added to the shift register, namely the sixth auxiliary subcircuit 16 and the sixth auxiliary subcircuit 16'. The fifth auxiliary subcircuit 15 is configured to write the first potential to the source of M11 under the control of the potential of the pull-up node PU and when M11 is turned off. The sixth auxiliary subcircuit 16 is configured to pull down the signal output terminal OUTPUT through a low-level signal when M11 is turned on. Figure 9 The fifth auxiliary sub-circuit 15 includes a twentieth transistor M20; the sixth auxiliary sub-circuit 16 includes a twenty-first transistor, with the twenty-first transistor in the sixth auxiliary sub-circuit 16 and the sixth auxiliary sub-circuit 16' being represented by M21 and M21', respectively. The source of M20 is connected to the source of M21, the drain of M20 is connected to the first potential signal terminal VGND, and the gate of M20 is connected to the pull-up node PU. The source of M21 is connected to the source of M21', the drain of M21 and the drain of M21' are both connected to the low-level signal terminal VGL, the gate of M21 is connected to the pull-down node PD1, and the gate of M21' is connected to the pull-down node PD2.

[0140] In order to make the structure of the shift register of the embodiment of the present disclosure clearer, Figure 9 The working process of the shift register shown is explained.

[0141] Frame reset stage: In this stage, before display, a high-level signal is input to the frame reset signal end, and a low-level signal is written to the level signal end to discharge the pull-up node PU to prevent the residual charge of the pull-up node PU from causing display abnormalities.

[0142] Pre-charge phase: A high-level signal is input to the signal input terminal INPUT, M2 is turned on, and the pull-up node PU is pulled high by the high-level signal, and C is charged. At the same time, M16 and M16' are both turned on, pulling down the pull-down nodes PD1 and PD2 to avoid affecting the potential of the pull-up node PU. At the same time, since the potential of the pull-up node PU is pulled high, M15 and M20 are turned on, and the first potential signal terminal VGND writes the first potential (0V) to the drain of M1, M7, M10, M10', M11, and M11'. At this time, the gate-source voltage of M1, M7, M10, M10', M11, and M11' is all -8V, and M1, M7, M10, M10', M11, and M11' are all in the off state, which can effectively reduce the leakage current of M1, M7, M10, M10', M11, and M11'. At the same time, since the pull-up node PU is at a high level, M18, M6, M6', M8, and M8 are turned on. At this time, PD1, PD2, PD_CN1, and PD_CN2 can be pulled down by a low-level signal, thereby effectively avoiding the problem of power failure of the pull-up node PU.

[0143] Output phase: Since the pull-up node PU is pulled high during the input phase, M3 turns on and outputs the high-level signal inputted by the clock signal terminal CLK to the gate line connected to it through the signal output terminal OUTPUT. At the same time, the signal output terminal OUTPUT outputs a high-level signal to the pull-up reset signal terminal RST_PU of the previous-stage shift register and the signal input terminal INPUT of the next-stage shift register. The gate-source voltage of M1, M7, M10, M10', M11, and M11' all maintains -8V, and M1, M7, M10, M10', M11, and M11' remain in the off state.

[0144] During the reset phase, a high-level signal is input to the output reset signal terminal RST_OUTPUT, turning on the fourth transistor. The low-level signal input to the low-level signal terminal VGL pulls the output of the signal output terminal OUTPUT low. A high-level signal is input to the pull-up reset signal terminal RST_PU, turning on M1, M17, and M20. The low-level signal input to the low-level signal terminal VGL pulls the potential of the pull-up node PU low, thus completing the reset of the pull-up node PU and the signal output terminal OUTPUT.

[0145] During the noise reduction phase, the first pull-down control node PD_CN1 and the pull-down node PD1 are both at the first power supply voltage, i.e., a high-level signal. M17, M10, and M19 are turned on, respectively performing noise reduction on the outputs of the pull-up node PU and the signal output terminal OUTPUT, until the pull-up node PU is pulled high at the start of the next frame scan. Simultaneously, due to the turning on of M19, the drain potentials of M6 and M8 are pulled down to the first potential (0V), and the gate-source voltages of M6 and M8 are both -8V, effectively reducing the leakage current of M6 and M8, thereby preventing any impact on the potentials of PD1 and PD_CN1, and effectively improving the noise reduction effect of the pull-up node PU and the signal output terminal OUTPUT.

[0146] In a second aspect, an embodiment of the present invention provides a gate driving circuit, which includes a plurality of cascaded shift registers of any one of the above types.

[0147] In a third aspect, an embodiment of the present invention provides a display panel including the above-mentioned gate drive circuit. Due to the inclusion of the above-mentioned gate drive circuit, the display panel has a better display effect and can achieve a narrow-edge design.

[0148] The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0149] Of course, the display device of this embodiment may also include other conventional structures, such as a power supply unit, a display driving unit, etc.

[0150] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A shift register comprising: an input subcircuit, an output subcircuit, a pull-up reset subcircuit, an output reset subcircuit, a first auxiliary subcircuit, and at least one second auxiliary subcircuit; wherein, The input sub-circuit is configured to respond to an input signal and precharge a pull-up node; the pull-up node is a connection node between the input sub-circuit, the output sub-circuit and the pull-up reset sub-circuit; The output sub-circuit is configured to output the clock signal through the signal output terminal under the control of the potential of the pull-up node; The output reset subcircuit is configured to reset the output of the signal output terminal through a non-working level signal under the control of the output reset signal; The pull-up reset subcircuit comprises a first transistor; a first electrode of the first transistor is connected to the pull-up node, a second electrode is connected to the first auxiliary subcircuit and the second auxiliary subcircuit, and a control electrode is connected to the pull-up reset signal terminal; The first auxiliary sub-circuit is configured to respond to a first control signal and, when the first transistor is turned off, pull down the potential of the second electrode of the first transistor to a first potential; the first potential is a ground potential; The second auxiliary sub-circuit is configured to respond to a second control signal and, when the first transistor is turned on, write the non-operating level signal into the second electrode of the first transistor to reset the potential of the pull-up node; The shift register further includes at least one pull-down control subcircuit and at least one pull-down subcircuit; one pull-down control subcircuit is electrically connected to one pull-down subcircuit, and a connection node between the two is a pull-down node; The pull-down control subcircuit is configured to respond to a first power supply voltage and control the potential of the pull-down node connected thereto via the first power supply voltage; each of the pull-down control subcircuits includes: a fifth transistor and a ninth transistor; a first electrode of the fifth transistor is connected to the first electrode of the ninth transistor and the first power supply voltage terminal, a second electrode is connected to one of the pull-down nodes, a control electrode is connected to the second electrode of the ninth transistor, and a first electrode of the ninth transistor is connected to the control electrode; The pull-down sub-circuit is configured to respond to the potential of the pull-up node and pull down the potential of the pull-down node connected thereto through the non-working level signal; any of the pull-down sub-circuits comprises: a sixth transistor and an eighth transistor; a first electrode of the sixth transistor is connected to one of the pull-down nodes, a second electrode is connected to the non-working level terminal, and a control electrode is connected to the pull-up node; a first electrode of the eighth transistor is connected to the second electrode of the ninth transistor in the pull-down control sub-circuit connected to the pull-down sub-circuit, a second electrode is connected to the non-working level terminal, and a control electrode is connected to the pull-up node; There are multiple second auxiliary sub-circuits; the potential of the pull-up node serves as the first control signal, and the potential of one pull-down node serves as the second control signal of one second auxiliary sub-circuit; a control end of the first auxiliary sub-circuit is connected to the pull-up node, a first end is connected to the second electrode of the first transistor, and a second end is connected to the first potential signal end; a control end of one second auxiliary sub-circuit is connected to one pull-down node, a first end is connected to the second electrode of the first transistor, and a second end is connected to the non-working level end; The first auxiliary sub-circuit includes a fifteenth transistor; any of the second auxiliary sub-circuits includes a seventeenth transistor; a first electrode of the fifteenth transistor is connected to the second electrode of the first transistor and the first electrode of the seventeenth transistor, a second electrode is connected to the first potential signal terminal, and a control electrode is connected to the pull-up node; a second electrode of any of the seventeenth transistors is connected to the non-working level terminal; a control electrode of one of the seventeenth transistors is connected to one of the pull-down nodes; the control electrodes of different seventeenth transistors are electrically connected to different pull-down nodes; and the first potential signal terminal is different from the non-working level terminal. The shift register further includes at least one seventh auxiliary sub-circuit; one of the seventh auxiliary sub-circuits is configured to pull down the potential of one of the pull-down nodes via a non-operating level signal under the control of an input signal; any of the seventh auxiliary sub-circuits includes a sixteenth transistor; one of the sixteenth transistors has a first electrode connected to one of the pull-down nodes, a second electrode connected to a non-operating level terminal, and a control electrode connected to a signal input terminal; The shift register further includes a third auxiliary subcircuit and at least one fourth auxiliary subcircuit; the third auxiliary subcircuit is configured to write a non-operating level signal into a first electrode of an eighth transistor and one of the pull-down nodes under control of the potential of the pull-up node; and one of the fourth auxiliary subcircuits is configured to pull down the potential of the second electrodes of the sixth transistor and the eighth transistor to the first potential when the sixth transistor and the eighth transistor in one of the pull-down subcircuits are turned off; The shift register further includes at least one second noise reduction sub-circuit, wherein one second noise reduction sub-circuit is configured to be controlled by the potential of a pull-down node and to reduce noise on the output of the signal output terminal via the non-working level signal, and different second noise reduction sub-circuits are controlled by different pull-down nodes; each second noise reduction sub-circuit includes an eleventh transistor; a first electrode of the eleventh transistor is connected to the signal output terminal, a second electrode is connected to the non-working level terminal, and a control electrode is connected to the pull-down node; The shift register also includes a fifth auxiliary sub-circuit and at least one sixth auxiliary sub-circuit; the fifth auxiliary sub-circuit is configured to write the first potential into the first electrode of the eleventh transistor under the control of the potential of the pull-up node and when the eleventh transistor is turned off; one sixth auxiliary sub-circuit is configured to pull down the potential of the signal output end through the non-working level signal when the eleventh transistor is turned on.

2. The shift register according to claim 1, wherein: Also included: at least one first noise reduction sub-circuit; One of the first noise reduction sub-circuits is configured to be controlled by the potential of one of the pull-down nodes and to reduce the potential of the pull-up node through the non-working level signal, and different first noise reduction sub-circuits are controlled by different pull-down nodes.

3. The shift register according to claim 2, wherein: Any of the first noise reduction sub-circuits includes a tenth transistor; The first electrode of the tenth transistor is connected to the pull-up node, the second electrode is connected to the non-working level end, and the control electrode is connected to the pull-down node.

4. The shift register according to claim 3, wherein: There are multiple second auxiliary sub-circuits; the potential of the pull-up node serves as the first control signal, and the potential of one pull-down node serves as the second control signal of one second auxiliary sub-circuit; The control end of the first auxiliary sub-circuit is connected to the pull-up node, the first end is connected to the second electrode of the tenth transistor, and the second end is connected to the first potential signal end; A control terminal of the second auxiliary sub-circuit is connected to one of the pull-down nodes, a first terminal is connected to the second electrode of the first transistor, and a second terminal is connected to the non-working level terminal.

5. The shift register according to claim 4, wherein: The first auxiliary sub-circuit includes a fifteenth transistor; any of the second auxiliary sub-circuits includes a seventeenth transistor; The first electrode of the fifteenth transistor is connected to the second electrode of the tenth transistor and the first electrode of the seventeenth transistor, the second electrode is connected to the first potential signal terminal, and the control electrode is connected to the pull-up node; The second electrode of any one of the seventeenth transistors is connected to the non-working level end; A control electrode of the seventeenth transistor is connected to the pull-down node. The shift register according to claim 1 , wherein: The third auxiliary sub-circuit includes an eighteenth transistor; any of the fourth auxiliary sub-circuits includes a nineteenth transistor; The first electrode of the eighteenth transistor is connected to the first electrode of the nineteenth transistor, the second electrode is connected to the non-working level end, and the control electrode is connected to the pull-up node; The first electrode of the nineteenth transistor is connected to the second electrode of the sixth transistor and the second electrode of the eighth transistor in the pull-down sub-circuit, the second electrode is connected to the first potential signal terminal, and the control electrode is connected to the pull-down node.

7. The shift register according to claim 1, wherein: The fifth auxiliary sub-circuit includes a 20th transistor; any of the sixth auxiliary sub-circuits includes a 21st transistor; The first electrode of the 20th transistor is connected to the second electrode of the 11th transistor, the second electrode is connected to the first potential signal terminal, and the control electrode is connected to the pull-up node; A first electrode of the twenty-first transistor is connected to the first electrode of the twentieth transistor, a second electrode is connected to the non-working level end, and a control electrode is connected to the pull-down node.

8. The shift register according to claim 1, wherein: The system further includes a frame reset subcircuit configured to reset the potential of the pull-up node through a non-working level signal in response to a frame reset signal.

9. The shift register according to claim 8, wherein: The frame reset sub-circuit includes a seventh transistor, The first electrode of the seventh transistor is connected to the pull-up node, the second electrode is connected to the non-working level end, and the control electrode is connected to the frame reset signal end.

10. The shift register according to claim 1, wherein: The input subcircuit includes a second transistor; The first electrode and the control electrode of the second transistor are connected to the signal input terminal, and the second electrode is connected to the pull-up node.

11. The shift register according to claim 1, wherein: The output sub-circuit includes a third transistor and a storage capacitor; The first electrode of the third transistor is connected to the clock signal terminal, the second electrode is connected to the signal output terminal, and the control electrode is connected to the pull-up node; A first end of the storage capacitor is connected to the pull-up node, and a second end is connected to the signal output end.

12. A gate drive circuit comprising a plurality of cascaded shift registers; the shift register comprising the shift register according to any one of claims 1 to 11. 13 . A display panel comprising the gate driving circuit according to claim 12 .

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