Semiconductor Modules

Abstract

The thickness of the solder is ensured and stress concentration between the chip and the lead frame is suppressed. The semiconductor module (1) includes: a semiconductor element (3) having a gate path (31) formed on the upper surface thereof in a manner extending in a predetermined direction; and a metal wiring plate (4) disposed on the upper surface of the semiconductor element. The metal wiring plate has a first bonding portion (40) bonded to the upper surface of the semiconductor element via a first bonding material. The first bonding portion has at least one first protrusion (45) protruding toward the semiconductor element. The first protrusion is provided at a position that does not overlap with the gate path when viewed from above. The gate path is separated from the first protrusion by more than 0.4 mm.

Description

Technical Field

[0001] The invention relates to a semiconductor module. Background Art

[0002] The semiconductor device has a substrate provided with semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor), a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a FWD (Free Wheeling Diode), and is used in an inverter device and the like.

[0003] For example, Patent Documents 1 to 3 shown below propose a structure in which a lead frame is bonded to an emitter electrode of a power semiconductor chip by soldering.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2001-110957

[0007] Patent Document 2: Japanese Patent Application Publication No. 2012-142521

[0008] Patent Document 3: Japanese Patent Application Publication No. 2018-163932 Summary of the invention

[0009] Problem that the invention aims to solve

[0010] In such semiconductor modules, the chip generates heat due to switching operations. As described above, in a structure where a lead frame is soldered to the surface of a power semiconductor chip, internal stress fluctuations due to temperature changes may cause strains to occur at the bonding portion.

[0011] The present invention has been made in view of this point, and one object of the present invention is to provide a semiconductor module that can ensure the thickness of the solder and suppress the stress concentration between the chip and the lead frame.

[0012] Solutions for solving problems

[0013] A technical solution of the present invention is a semiconductor module, which includes: a semiconductor element having a gate path formed on its upper surface in a manner extending in a prescribed direction; and a metal wiring plate arranged on the upper surface of the semiconductor element, the metal wiring plate having a first bonding portion, the first bonding portion being bonded to the upper surface of the semiconductor element via a first bonding material, the first bonding portion having at least one first protrusion protruding toward the semiconductor element, the first protrusion being provided at a position that does not overlap with the gate path when viewed from above, and the gate path being separated from the first protrusion by more than 0.4 mm.

[0014] Effects of the Invention

[0015] According to the present invention, it is possible to suppress stress concentration between a chip and a lead frame while ensuring the thickness of the solder. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a top view of the semiconductor device according to this embodiment.

[0017] Figure 2 Yes Figure 1 The semiconductor device shown is a cross-sectional view taken along line AA.

[0018] Figure 3 yes Figure 1 A partial enlarged view of .

[0019] Figure 4 yes Figure 2 A partial enlarged view of .

[0020] Figure 5 It is a top view of a semiconductor element according to a modified example.

[0021] Figure 6 It is a top view of a semiconductor element according to another modified example.

[0022] Figure 7 It is a top view of a metal wiring plate according to a modified example.

[0023] Figure 8 It is a top view of a metal wiring plate and its surroundings according to another modified example.

[0024] Fig. 9 It is a cross-sectional view of a metal wiring plate and its surroundings according to another modified example. DETAILED DESCRIPTION

[0025] Hereinafter, a semiconductor device to which the present invention can be applied will be described. Figure 1 It is a top view of the semiconductor device according to this embodiment. Figure 2 Yes Figure 1The semiconductor device shown is a cross-sectional view taken along line AA. The semiconductor device shown below is merely an example and is not limited thereto, and can be modified as appropriate.

[0026] In addition, in the following drawings, the long side direction of the semiconductor device (the direction in which the multiple circuit boards described later are arranged) is defined as the X direction, the short side direction is defined as the Y direction, and the height direction is defined as the Z direction. The X-axis, Y-axis, and Z-axis shown in the figure are orthogonal to each other and constitute a right-hand system. In addition, depending on the situation, the X direction is sometimes referred to as the left-right direction, the Y direction is referred to as the front-back direction, and the Z direction is referred to as the up-down direction. These directions (front-back, left-right, up-down, and left-right directions) are terms used for the convenience of explanation. Depending on the installation posture of the semiconductor module, the correspondence between the directions of the XYZ directions sometimes changes. For example, the heat dissipation surface side (cooler side) of the semiconductor device is referred to as the lower surface side, and the opposite side is referred to as the upper surface side. In addition, in this specification, looking down refers to the situation of observing the upper surface of the semiconductor module from the positive side of the Z direction.

[0027] The semiconductor device 100 is applied to a power conversion device such as a power module, for example. Figure 1 and Figure 2 As shown, the semiconductor device 100 is configured by placing the semiconductor module 1 on the upper surface of the cooler 10. The cooler 10 has an arbitrary structure relative to the semiconductor module 1.

[0028] The cooler 10 releases the heat of the semiconductor module 1 to the outside and has a rectangular parallelepiped shape as a whole. The cooler 10 is configured by providing a plurality of heat sinks on the lower surface side of the base plate and housing these heat sinks in a water cooling jacket, which is not particularly shown. In addition, the cooler 10 is not limited to this and can be appropriately changed.

[0029] Semiconductor module 1 is configured by arranging multilayer substrate 2 , semiconductor element 3 , metal wiring plate 4 and the like in casing 11 .

[0030] The laminated substrate 2 is formed by laminating a metal layer and an insulating layer, and is composed of, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazing) substrate, or a metal base substrate. Specifically, the laminated substrate 2 includes an insulating plate 20, a metal plate 21 disposed on the lower surface of the insulating plate 20, and a plurality of circuit boards (a first circuit board 22a and a second circuit board 22b described later) disposed on the upper surface of the insulating plate 20. The laminated substrate 2 is formed, for example, in a rectangular shape in top view that is longer in the X direction than in the Y direction.

[0031] The insulating plate 20 is formed in a flat plate shape having a predetermined thickness in the Z direction and having an upper surface and a lower surface. The insulating plate 20 is formed of, for example, a ceramic material such as alumina (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), a resin material such as epoxy, or an insulating material such as an epoxy resin material using a ceramic material as a filler. In addition, the insulating plate 20 may also be referred to as an insulating layer or an insulating film.

[0032] The metal plate 21 is formed to have a predetermined thickness in the Z direction and covers substantially the entire lower surface of the insulating plate 20. The metal plate 21 is formed of a metal plate having good thermal conductivity, such as copper, aluminum, or an alloy using copper or aluminum as a base material. The lower surface of the metal plate 21 serves as a heat dissipation surface. The metal plate 21 is joined to the upper surface of the cooler 10 via a joining material S1 such as solder. The metal plate 21 may also be arranged on the upper surface of the cooler 10 via a heat conductive material such as thermal grease or thermal paste.

[0033] On the main surface of the insulating plate 20, a plurality of circuit boards are formed in an island shape (electrically insulated from each other). In the present embodiment, two circuit boards (a first circuit board 22a and a second circuit board 22b) are formed on the upper surface of the insulating plate 20. These circuit boards are formed using a metal layer of a predetermined thickness formed of copper foil or the like. The first circuit board 22a and the second circuit board 22b have a rectangular shape when viewed from above and are arranged in an X direction on the insulating plate 20. Figure 1 In the figure, the first circuit board 22a is located on the left side (the negative side in the X direction), and the second circuit board 22b is located on the right side (the positive side in the X direction).

[0034] A semiconductor element 3 is arranged on the upper surface of the first circuit board 22a via a bonding material S2 such as solder. The semiconductor element 3 is formed into a square shape in a top view by a semiconductor substrate such as silicon (Si) or silicon carbide (SiC). In the present embodiment, the semiconductor element 3 is composed of an RC (Reverse Conducting: reverse conduction)-IGBT element that integrates the functions of an IGBT (Insulated Gate Bipolar Transistor) element and a FWD (Free Wheeling Diode) element.

[0035] In addition, the semiconductor element 3 is not limited to this, and can also be composed of a combination of switching elements such as IGBT, power MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and diodes such as FWD (Free Wheeling Diode). In addition, as the semiconductor element 3, RB (Reverse Blocking: Reverse Blocking)-IGBT with sufficient withstand voltage for reverse bias can also be used. The semiconductor element 3 can be a vertical switching element and a diode. In addition, the shape, configuration number, configuration location, etc. of the semiconductor element 3 can be appropriately changed.

[0036] In addition, the semiconductor element 3 has electrodes formed on the upper surface and the lower surface, respectively. For example, the electrode on the upper surface side (upper surface electrode) is composed of an emitter electrode (source electrode) or a gate electrode, and the electrode on the lower surface side (lower surface electrode) is composed of a collector electrode (drain electrode). In addition, a gate pad 30 and a gate path 31 constituting a gate wiring for the gate pad 30 are formed on the upper surface of the semiconductor element 3 in a manner that divides the center of the semiconductor element 3. The detailed structure of the surface of the semiconductor element 3 will be described later.

[0037] A metal wiring board 4 is disposed on the upper surface of the semiconductor element 3. The metal wiring board 4 is composed of a plate-like body having an upper surface and a lower surface, and is formed of, for example, a metal raw material such as a copper raw material, a copper alloy raw material, an aluminum alloy raw material, or an iron alloy raw material. The metal wiring board 4 is formed into a predetermined shape by, for example, stamping. In addition, the shape of the metal wiring board 4 shown below is only an example and can be appropriately changed. In addition, the metal wiring board can also be called a lead frame.

[0038] The metal wiring plate 4 of the present embodiment is a long strip extending in the X direction in a manner spanning the first circuit board 22a and the second circuit board 22b when viewed from above, and has a crank shape that is bent multiple times when viewed from the side. Specifically, the metal wiring plate 4 is configured to include a first bonding portion 40 bonded to the upper surface of the semiconductor element 3 via a bonding material S3 (first bonding material), a second bonding portion 41 bonded to the upper surface of the second circuit board 22b via a bonding material S4 (second bonding material), and a connecting portion 42 connecting the first bonding portion 40 and the second bonding portion 41. The width of the metal wiring plate 4 in the Y direction is the same size from the first bonding portion 40 to the second bonding portion 41. In addition, the first bonding portion 40, the second bonding portion 41, and the connecting portion 42 are arranged to be arranged in a row along the X direction when viewed from above. More specifically, the first bonding portion 40 , the second bonding portion 41 , and the connecting portion 42 are arranged in a row along a direction (X direction) perpendicular to the extending direction (Y direction) of the gate via 31 , that is, a direction in which a plurality of second protrusions 46 described later are arranged.

[0039] The first joint portion 40 has a rectangular shape that is smaller than the outer shape of the semiconductor element 3 when viewed from above. A first bent portion 43 that is bent at a substantially right angle and rises upward is formed at the end portion of the first joint portion 40 on the positive side in the X direction (on the second circuit board 22b side). One end (left end) of the connecting portion 42 is connected to the upper end of the first bent portion 43. A first protrusion 45 that protrudes toward the semiconductor element 3 is formed on the lower surface of the first joint portion 40, and its details will be described later.

[0040] The second joint portion 41 has a rectangular shape that is smaller than the outer shape of the second circuit board 22b when viewed from above. A second bent portion 44 that is bent at a substantially right angle and rises upward is formed at the end of the second joint portion 41 on the negative side in the X direction (on the first circuit board 22a side). The other end (right end) of the connecting portion 42 is connected to the upper end of the second bent portion 44. A second protrusion 46 that protrudes toward the second circuit board 22b is formed on the lower surface of the second joint portion 41, and its details will be described later.

[0041] The connecting portion 42 extends in the horizontal direction, and as described above, one end is connected to the first curved portion 43 , and the other end is connected to the second curved portion 44 .

[0042] The length of the first bent portion 43 in the Z direction is shorter than that of the second bent portion 44 by an amount corresponding to the thickness of the semiconductor element 3. That is, the first bonding portion 40 and the second bonding portion 41 are provided at different heights. More specifically, the first bonding portion 40 is provided at a position higher than the second bonding portion 41.

[0043] As described above, the first bonding portion 40 is electrically bonded to the upper surface of the main electrode of the semiconductor element 3 via a bonding material S3 such as solder. The second bonding portion 41 is electrically bonded to the upper surface of the second circuit board 22b via a bonding material S4 such as solder.

[0044] The stacked substrate 2, the semiconductor element 3, and the metal wiring plate 4 are surrounded by a housing 11. The housing 11 has a cylindrical shape or a frame shape that is a square ring when viewed from above, and is formed of, for example, a synthetic resin. The lower end of the housing 11 is bonded to the upper surface of the cooler 10 via an adhesive, and the upper end extends to a position that is sufficiently higher than the upper surface of the metal wiring plate 4. That is, the housing 11 defines a space for accommodating the stacked substrate 2, the semiconductor element 3, and the metal wiring plate 4.

[0045] As described above, the internal space defined by the housing 11 is filled with sealing resin 5. The sealing resin 5 may be filled until the upper surface reaches the upper end of the housing 11. Thus, the laminated substrate 2, the semiconductor element 3, and the metal wiring plate 4 are sealed. In addition, the sealing resin 5 can use epoxy resin or silicone gel.

[0046] In addition, as described above, in a structure where a semiconductor element made of a semiconductor substrate such as silicon or silicon carbide and a metal wiring plate (lead frame) made of a metal such as copper are welded, the chip will heat up as the semiconductor element switches. With such temperature changes, shear stress (internal stress) may be generated around the joint due to the difference in expansion and contraction. This shear stress tends to be the largest at the outer edge of the joint.

[0047] In addition, in a large-capacity semiconductor element, as described above, a gate via as a gate wiring is provided in a manner that divides the center of the semiconductor element. Therefore, the solder between the semiconductor element and the metal wiring plate is divided by the gate via. As a result, shear stress may also be concentrated on the boundary portion along the gate via.

[0048] Therefore, as a countermeasure for alleviating shear stress, increasing the thickness of the solder between the semiconductor element and the metal wiring plate or increasing the distance between the semiconductor element having a large elastic modulus and the metal wiring plate having a relatively small elastic modulus is effective.

[0049] However, in a structure where soldering is performed over multiple layers, such as the bonding between a semiconductor element and an insulating substrate, the bonding between an insulating substrate and a base plate for a cooler, etc., in addition to the bonding between a semiconductor element and a metal wiring plate, it is difficult to control the thickness of the solder to a level that can provide a stress relaxation effect. As a method for ensuring the thickness of the solder, a method of providing a boss on the metal wiring plate is also considered, but the boss itself may become a stress concentration point and cause fracture of the bonding portion.

[0050] Therefore, the inventors of the present application focused on the positional relationship between the boss for ensuring the thickness of the solder and the gate path that may cause stress concentration, and came up with the present invention. Specifically, in the present embodiment, a gate path 31 is formed on the upper surface of the semiconductor element 3 in a manner extending in a predetermined direction (in the present embodiment, the Y direction). The metal wiring plate 4 has a first bonding portion 40 bonded to the upper surface of the semiconductor element 3 via a bonding material S3. A first protrusion 45 protruding toward the semiconductor element 3 is formed on the back side of the first bonding portion 40. The first protrusion 45 is provided at a position that does not overlap with the gate path 31 when viewed from above. The first protrusion 45 can be provided to be separated from the gate path 31 when viewed from above. Moreover, the inventors have come to the following conclusion: by separating the gate path 31 from the first protrusion 45 by more than 0.4 mm, the thickness of the solder can be ensured, and stress concentration between the semiconductor element and the metal wiring plate can be suppressed.

[0051] According to this structure, since the first protrusion 45 is provided, a gap of at least the amount corresponding to the height of the first protrusion 45 can be ensured between the first bonding portion 40 and the semiconductor element 3. By filling the gap with the bonding material S3, the thickness of the bonding material S3 can be ensured. In addition, by arranging the first protrusion 45 in a manner that does not overlap with the gate path 31 when viewed from above, and ensuring that the distance between them is 0.4 mm or more, the thickness of the bonding material S3 around the gate path 31 can be fully ensured, and stress concentration can be suppressed. In this way, the thickness of the solder can be ensured, and stress concentration between the semiconductor element and the metal wiring plate can be suppressed.

[0052] In addition, a second protrusion 46 protruding toward the second circuit board 22b is formed on the back side of the second joining portion 41. Thus, a gap of at least the amount corresponding to the height of the second protrusion 46 can be ensured between the second joining portion 41 and the second circuit board 22b. By filling the gap with the joining material S4, the thickness of the joining material S4 can be ensured.

[0053] Next, refer to Figure 3 and Figure 4 , illustrating the detailed structure of the surface of a semiconductor element. Figure 3 yes Figure 1 A partial enlarged view of . Figure 4 yes Figure 2 The surface structure of the semiconductor element is not limited to the example shown below, and can be changed appropriately.

[0054] like Figure 3 As shown in FIG. 1 , on the upper surface of the semiconductor element 3, a gate pad 30 is arranged at the center of the end portion on the positive side in the Y direction. The gate pad 30 constitutes a gate electrode. In addition, a gate path 31 is formed on the upper surface of the semiconductor element 3. The gate path 31 has a predetermined width in the X direction and extends in the Y direction. In addition, one end of the gate path 31 is connected to the gate pad 30 and the other end extends to the end portion on the negative side in the Y direction of the semiconductor element 3. The gate path 31 divides the center of the upper surface of the semiconductor element 3 into two parts in the X direction.

[0055] In more detail, Figure 4 As shown, an upper surface electrode 32 of a predetermined thickness is provided on the upper surface of the semiconductor element 3. The upper surface electrode 32 is formed in a predetermined region on the upper surface of the substrate of the semiconductor element 3. The gate pad 30 described above is formed in a region separated (independent) from the upper surface electrode 32. The upper surface electrode 32 constitutes, for example, an emitter electrode. The upper surface electrode 32 is formed of, for example, aluminum or a metal containing aluminum.

[0056] A plating layer 33 having a predetermined thickness is provided on the upper surface of the upper surface electrode 32 . The plating layer 33 is formed of, for example, nickel or a metal containing nickel. The gate via 31 is formed on the upper surface of the upper surface electrode 32 so as to penetrate the plating layer 33 .

[0057] The gate via 31 has a conductive portion (not shown) formed of polysilicon doped with impurities or the like and an insulating portion formed of polyimide or the like covering the conductive portion. The insulating portion serves to insulate the conductive portion from the upper surface electrode 32, the plating layer 33, and the bonding material S3. The upper surface of the gate via 31 (insulating portion) is provided at a position higher than the upper surface of the plating layer 33. That is, the thickness of the gate via 31 is set to be greater than the thickness of the plating layer 33.

[0058] In addition, the two side surfaces of the gate via 31 in the X direction are inclined so that the relative distance (width) becomes narrower as they go upward. As a result, the cross section of the gate via 31 has a trapezoidal shape (see Figure 4 ). In contrast, the side surface of the plating layer 33 opposite to the side surface of the gate via 31 is inclined so as to be away from the side surface of the gate via 31 as it goes upward. That is, the relative distance between the side surface of the gate via 31 and the side surface of the plating layer 33 increases as it goes away from the upper surface electrode 32.

[0059] Thus, a boundary portion 34 is formed on the upper surface of the semiconductor element 3, and the gate via 31, the upper surface electrode 32, and the plating layer 33 are mutually concentrated at the boundary portion 34. At the boundary portion 34, the gate via 31, the upper surface electrode 32, and the plating layer 33 may be close to each other and partially contact or overlap. The boundary portion 34 is formed in a linear shape extending in the Y direction along the outer edge of the lower end of the gate via 31. Figure 4 In the cross-sectional view shown, the boundary 34 may also be referred to as a triple critical point. The semiconductor element 3 may also be provided with a guard ring 35 on its upper surface along the periphery of the plating layer 33. The end of the gate via 31 is connected to the guard ring 35.

[0060] Next, the detailed structure of metal wiring plate 4 will be described. Figure 3 and Figure 4 As shown, a plurality of first protrusions 45 are provided on the lower surface of the first joining portion 40. In this embodiment, two first protrusions 45 are provided in the X direction, three first protrusions 45 are provided in the Y direction, and a total of six first protrusions 45 are provided. The six first protrusions 45 are arranged along the outer periphery of the first joining portion 40.

[0061] For example, the first protrusion 45 is provided at a position separated from the guard ring 35 by a predetermined distance X1 and from the gate path 31 by a predetermined distance X2 in the X direction. In addition, in the Y direction, the first protrusion 45 located at the outermost peripheral side is provided at a position of the first joint 40 separated from the guard ring 35 by predetermined distances Y1 and Y2 in the Y direction. The distance (X2) between the gate path 31 and the first protrusion 45 is greater than 0.4 mm in a plan view. The first protrusions 45 arranged in pairs in the X direction are arranged so as to sandwich the gate path 31 in a plan view. The gate path 31 can be arranged between the two paired first protrusions 45. Moreover, the distance (X1, Y1, Y2) between the guard ring 35 and the first protrusion 45 can also be greater than 0.4 mm.

[0062] The first protrusion 45 has, for example, a cylindrical shape with an outer diameter of D1. In addition, the first protrusion 45 protrudes from the lower surface of the first bonding portion 40 toward the semiconductor element 3 at a protrusion height Z1. The side surface (cylindrical surface) of the first protrusion 45 is formed perpendicular to the lower surface of the first bonding portion 40. The outer diameter D1 of the first protrusion 45 is, for example, 0.4 mm to 1.5 mm, and preferably 0.6 mm to 1.2 mm. If the outer diameter D1 is large, the distance between the first protrusion 45 and the gate path 31 is reduced and the degree of freedom of design is reduced. If the outer diameter D1 is small, the stress acting on the upper surface electrode 32 is concentrated, which is not preferred. In addition, the protrusion height Z1 of the first protrusion 45 can be greater than 50 μm and less than 300 μm, and preferably 100 μm to 200 μm. If the protrusion height Z1 is large, voids are likely to be generated in the bonding material S3 , and if the protrusion height Z1 is small, the bonding material S3 becomes thinner, and the stress acting on the upper surface electrode 32 becomes large.

[0063] In addition, if Figure 1 and Figure 2 As shown, a plurality of second protrusions 46 are provided on the lower surface of the second joining portion 41. In the present embodiment, two second protrusions 46 are arranged in the Y direction. The two second protrusions 46 are arranged toward the outer peripheral side of the second joining portion 41. The shape of the second protrusion 46 may be the same as or different from the above-mentioned first protrusion 45.

[0064] The shapes, arrangements and number of the first protrusions 45 and the second protrusions 46 are not limited thereto and can be changed as appropriate. For example, the first protrusions 45 and the second protrusions 46 are not limited to cylindrical shapes and can be prismatic shapes, truncated cone shapes that taper downward, or hemispherical shapes.

[0065] In the semiconductor module 1 configured in this manner, the first protrusion 45 is provided at a position that does not overlap with the gate via 31 in a plan view (see Figure 3), the gate path 31 and the first protrusion 45 are provided at positions separated by a predetermined distance X2 (refer to Figure 4 ). More specifically, the boundary portion 34 is separated from the outer edge of the first protrusion 45 by a predetermined distance X2. In this case, the predetermined distance X2 is preferably greater than or equal to 0.4 mm.

[0066] According to this structure, since the first protrusion 45 does not overlap with the gate path 31, the thickness of the bonding material S3 corresponding to the protrusion height Z1 of the first protrusion 45 can be ensured between the semiconductor element 3 and the first bonding portion 40 around the gate path 31. As described above, since the boundary portion 34 is a portion where stress may be concentrated, by ensuring the thickness of the bonding material S3 around the boundary portion 34, the effect of suppressing stress concentration can be improved.

[0067] In addition, the thickness of the bonding material S3 is relatively thin between the lower surface of the first protrusion 45 and the upper surface of the semiconductor element 3. However, the first protrusion 45 is separated from the boundary portion 34 by a predetermined distance X2, and the lower surface of the first protrusion 45 is opposite to the plating layer 33. The plating layer 33 is more rigid than the boundary portion 34 and is not easily affected by stress concentration. Therefore, even if the thickness of the bonding material S3 is relatively thin, there is no problem.

[0068] In addition, in this embodiment, it is preferred that the total area of ​​the plurality of first protrusions 45 is greater than 0.5% and less than 25% of the area of ​​the first joint 40. That is, as a more preferred range, the area ratio of the plurality of first protrusions 45 to the first joint 40 is greater than 1.0% and less than 20%. Specifically, with respect to the first joint 40 having a width of 7 mm, in the case of a plurality of first protrusions 45 having four In the case of the first protrusion 45 with a diameter of 0.4 mm, the area ratio is 1%. In the case of the first protrusion 45 with a diameter of 1.5 mm, the area ratio is 20%. In the case of the first protrusion 45 of 1.6 mm, the area ratio is 25%. The reason for setting such a range is that if the first protrusion 45 is too small, stress is concentrated near the first protrusion 45, resulting in damage to the upper surface electrode 32. On the other hand, if the first protrusion 45 is too large, the area of ​​the thinner portion of the bonding material S3 becomes larger, and there is a concern that cracks and peeling will occur in the thinner portion of the bonding material S3.

[0069] In addition, in the present embodiment, a plurality of first protrusions 45 are arranged along the outer periphery of the first joint 40 within a prescribed range from the outer periphery. Therefore, the rectangular first joint 40 can be stably arranged on the semiconductor element 3, and the metal wiring plate 4 itself can be prevented from tipping over. Similarly, a plurality of second protrusions 46 are arranged toward the outer periphery of the second joint 41. Therefore, the rectangular second joint 41 can be stably arranged on the second circuit board 22b. In particular, since the first joint 40 and the second joint 41 have different heights in the Z direction, they are prone to tipping over. In the present embodiment, the posture of the metal wiring plate 4 can be easily maintained by utilizing a plurality of first protrusions 45 and second protrusions 46.

[0070] Next, a modified example is described. In the above embodiment, a gate path 31 extending in the Y direction is formed at the center of the upper surface of the semiconductor element 3, but the shape of the gate path is not limited to this and can be appropriately changed. Figure 5 and Figure 6 The structure shown. Figure 5 It is a top view of a semiconductor element according to a modified example. Figure 6 2 is a top view of a semiconductor element of another modified example. In the modified example described below, since only the structure of the gate path is different from the above-described embodiment, the different points will be mainly described, and the same reference numerals are given to the common structures and the description thereof will be omitted as appropriate.

[0071] like Figure 5 As shown in FIG. 1 , the gate path of the modified example is formed in a grid shape. Specifically, the gate path is composed of a first lead portion 31a extending in the Y direction and a second lead portion 31b extending in the X direction. One end of the first lead portion 31a is connected to the gate pad 30 and the other end extends to the end of the semiconductor element 3 on the negative side in the Y direction. The center of the upper surface of the semiconductor element 3 is divided into two parts in the X direction by the first lead portion 31a.

[0072] The second lead portion 31b extends from one end portion in the X direction to the other end portion of the semiconductor element 3 in a manner intersecting the first lead portion 31a. Two second lead portions 31b are arranged in parallel along the Y direction. The upper surface of the semiconductor element 3 is divided into three parts in the Y direction by the two second lead portions 31b. That is, the upper surface (plating layer 33) of the semiconductor element 3 is divided into six parts by the grid-like gate path.

[0073] In addition, a rectangular frame-shaped guard ring 35 is formed on the outer periphery of the six-divided plating layer 33. The guard ring 35 is connected to both ends of the first lead portion 31a and both ends of the second lead portion 31b.

[0074] The first protrusion 45 is disposed on each upper surface of the six-divided plating layer 33. That is, the first protrusion 45 is disposed at a position that does not overlap with the gate path. In addition, it is not limited to the case where one first protrusion 45 is disposed for one plating layer 33, and a plurality of first protrusions 45 may be disposed on one plating layer 33. The first protrusion 45 is disposed at a position separated from the guard ring 35 by a distance X1 and separated from the gate path 31a by a distance X2 in the X direction. In addition, in the Y direction, the first protrusion 45 is disposed at a position separated from the gate path 31b by a distance Y1 and separated from the guard ring 35 by a distance Y2. The distance (X2, Y1) between the gate paths 31a, 31b and the first protrusion 45 is 0.4 mm or more when viewed from above.

[0075] like Figure 6 As shown in FIG. 1 , the gate path of another modified example is formed in a T-shaped shape when viewed from above. Specifically, the gate path is composed of a first lead portion 31a extending in the Y direction and a second lead portion 31b extending in the X direction. One end of the first lead portion 31a is connected to the gate pad 30 and the other end is connected to the center of the second lead portion 31b. The second lead portion 31b extends from one end of the semiconductor element 3 in the X direction to the other end. The upper surface (plating layer) of the semiconductor element 3 is divided into three parts by the T-shaped gate path.

[0076] For convenience of explanation, the two regions on the negative side in the Y direction of the divided region are set as the plating layer 33a, and the one region on the positive side in the Y direction is set as the plating layer 33b. The two plating layers 33a are divided by the first lead portion 31a. In addition, the width of the plating layer 33b in the X direction corresponds to the width of the two plating layers 33a.

[0077] Furthermore, a rectangular frame-shaped guard ring 35 is formed on the outer periphery of the three-divided plating layers 33a and 33b. The guard ring 35 is connected to one end of the first lead portion 31a and both ends of the second lead portion 31b.

[0078] A first protrusion 45 is disposed on each upper surface of the three-divided plating layers 33a and 33b. Specifically, one first protrusion 45 is disposed for one plating layer 33a, and two first protrusions are disposed in the plating layer 33b along the X direction. That is, the first protrusion 45 is disposed at a position that does not overlap with the gate path. The first protrusion 45 is disposed at a position that is separated from the guard ring 35 by a distance X1 and from the gate path 31a by a distance X2 in the X direction. In addition, in the Y direction, the first protrusion 45 is disposed at a position that is separated from the gate path 31b by a distance Y1 and from the guard ring 35 by a distance Y2. The distance (X2, Y1) between the gate paths 31a, 31b and the first protrusion 45 is greater than 0.4 mm when viewed from above. In this way, Figure 5 and Figure 6In the structure shown in FIG. 1 , the same effects as those in the above-mentioned embodiment can also be obtained. Figure 3 , Figure 5 , Figure 6 In the example shown, the gate paths 31, 31a, 31b are separated from the first protrusion 45 by more than 0.4 mm. Furthermore, the distance between the guard ring 35 and the first protrusion 45 may also be more than 0.4 mm. If the first protrusion 45 is separated from the guard ring 35 by more than 0.4 mm, the influence of the first protrusion 45 on the upper surface electrode 32 can be reduced. Furthermore, the first protrusion 45 is arranged on the inner side of the first joint 40 in a manner that the distance L from the outer edge of the first joint 40 is in the range of more than 0.4 mm and less than 2.0 mm, and more preferably, the first protrusion 45 is arranged on the inner side of the first joint 40 in a manner that the distance L is in the range of more than 0.8 mm and less than 1.3 mm. By configuring the first protrusion 45 in this way, the unintentional tilting of the metal wiring plate 4 can be reduced. In addition, if the distance from the outer edge of the first bonding portion 40 to the first protrusion 45 is not separated to a certain extent, stress is concentrated on the outer edge of the bonding material S3, especially on the rounded corner of the bonding material S3, and cracks are likely to occur. In addition, if the distance from the outer edge of the first bonding portion 40 to the first protrusion 45 is too large, there is a risk that the metal wiring plate 4 will be accidentally tilted.

[0079] In the above embodiment, the metal wiring plate 4 is formed to have the same width from the first joint portion 40 to the second joint portion 41, and the first joint portion 40, the second joint portion 41 and the connecting portion 42 are arranged in a row along the X direction in a plan view, but the present invention is not limited to this structure. Figure 7 The structure shown. Figure 7 FIG. 1 is a top view of a metal wiring board of a modified example. Figure 7 In the description, the differences are mainly described, the same figure marks are given to the common structures, and the description is appropriately omitted.

[0080] like Figure 7 As shown, in the metal wiring plate 4 of the modified example, the first joint portion 40 and the second joint portion 41 are arranged in a manner that they are inclined opposite to each other with the connecting portion 42 therebetween when viewed from above. Specifically, the connecting portion 42 has a rectangular shape that is long in the Y direction when viewed from above. In addition, two through holes 42a are formed in the connecting portion 42 that penetrate in the thickness direction. The two through holes 42a are arranged in an array along the Y direction. There may be one through hole 42a, or there may be no through hole 42a.

[0081] The first joining portion 40 is arranged to be biased toward the negative side in the Y direction relative to the connecting portion 42. A first bent portion 43 that is bent and raised upward at a substantially right angle is formed at the end portion on the positive side in the X direction of the first joining portion 40. The width in the Y direction of the first bent portion 43 is smaller than the width in the Y direction of the first joining portion 40. In addition, a notch portion 40a is formed in the first joining portion 40 by cutting off a part of the outer edge connected to the first bent portion 43 and extending toward the negative side in the X direction.

[0082] The notch 40a functions as an escape portion for obtaining the curved shape of the first curved portion 43. The notch 40a is located on the negative side (outer side) in the Y direction relative to the end of the connecting portion 42 on the negative side in the Y direction. The first curved portion 43 is connected to the negative side in the X direction of the connecting portion 42 and is the end on the negative side in the Y direction. That is, the width of the first curved portion 43 in the Y direction is smaller than the width of the connecting portion 42 in the Y direction.

[0083] Four first protrusions 45 are formed on the lower surface of the first joining portion 40. The four first protrusions 45 are arranged to be biased toward the outer peripheral side of the first joining portion 40. That is, the first protrusions 45 are arranged at the four corners of the first joining portion 40. Two of the four first protrusions 45 on the negative side in the Y direction are arranged at a position closer to the negative side (outer side) in the Y direction than the notch 40a.

[0084] The second joining portion 41 is arranged to be biased toward the positive side in the Y direction relative to the connecting portion 42. A second curved portion 44 is formed at the end of the second joining portion 41 on the negative side in the X direction, and the second curved portion 44 is bent and raised upward at a substantially right angle. The width of the second curved portion 44 in the Y direction is smaller than the width of the second joining portion 41 in the Y direction. In addition, a notch portion 41a is formed in the second joining portion 41 by cutting off a part of the outer edge connected to the second curved portion 44 and extending toward the positive side in the X direction.

[0085] The notch 41a functions as an escape portion for obtaining the curved shape of the second curved portion 44. The notch 41a is located closer to the positive side (outer side) in the Y direction than the end portion on the positive side in the Y direction of the connecting portion 42. The second curved portion 44 is connected to the positive side in the X direction of the connecting portion 42 and is the end portion on the positive side in the Y direction. That is, the width of the second curved portion 44 in the Y direction is smaller than the width of the connecting portion 42 in the Y direction.

[0086] Two second protrusions 46 are formed on the lower surface of the second joint 41. The two second protrusions 46 are arranged side by side along the Y direction. The second protrusion 46 located on the positive side in the Y direction of the two second protrusions 46 is arranged on the positive side (outside) of the notch 41a in the Y direction. Figure 7 In the structure shown in FIG. 1 , the same effects as those in the above-mentioned embodiment can also be obtained. Figure 7In the embodiment, the first protrusion 45 located outside the notch 40a does not need to be entirely located outside the notch 40a, and only a portion of the first protrusion 45 can be located outside the notch 40a. The second protrusion 46 located outside the notch 41a is the same. The two first protrusions 45 on the negative side in the Y direction can be arranged to be farther from the connecting portion 42 than the notch 40a when viewed from above, and the second protrusion 46 on the positive side in the Y direction can be arranged to be farther from the connecting portion 42 than the notch 41a when viewed from above. In addition, the first joining portion 40, the connecting portion 42, and the second joining portion 41 can be configured as a whole so that their outer edges are serrated or W-shaped.

[0087] In addition, in the above-mentioned embodiment, the case where the first protrusion 45 has a cylindrical shape is described. In this case, the surface of the first protrusion 45 facing the gate path 31 has a curved surface when viewed from above. For example, in the case where the facing surface is a flat surface, stress cannot be relieved in the portion sandwiched between the first protrusion 45 and the gate path 31, and stress is concentrated in this portion, which may cause damage. As described above, since the surface facing the gate path 31 is a curved surface, the stress between the first protrusion 45 and the gate path 31 can be relieved, and the generation of local stress can also be prevented.

[0088] In addition, the first protrusion 45 is not limited to a cylindrical shape, and may also be Figure 8 In this case, it is preferable that a rounded corner portion 45a is formed at the corner of the first protrusion 45. The rounded corner portion 45a has a curved surface on the surface facing the gate via 31 in a plan view. In this case, the same effect as described above can be obtained.

[0089] In addition, it is preferred that it is not limited to the top view. Fig. 9 As shown, the first protrusion 45 also has a curved surface at the top in cross-sectional view. Specifically, a rounded corner 45b is formed at the corner of the lower end of the first protrusion 45. Since the first protrusion 45 has a curved surface in cross-sectional view, the stress relaxation effect can be further obtained.

[0090] In addition, in the above-mentioned embodiment, the number and arrangement positions of the semiconductor elements 3 are not limited to the above-mentioned configurations, and can be changed as appropriate.

[0091] In addition, in the above-mentioned embodiment, the number and layout of the circuit boards are not limited to the above-mentioned configuration, and can be changed as appropriate.

[0092] In the above embodiment, the laminated substrate 2 and the semiconductor element 3 are formed in a rectangular or square shape in plan view, but the present invention is not limited to this structure. The laminated substrate 2 and the semiconductor element 3 may be formed in a polygonal shape other than the above.

[0093] In the above embodiment, the bonding materials S1 to S4 are described as being made of solder, but the present invention is not limited to this structure. The bonding material may be made of, for example, a sintered material.

[0094] In addition, in the above embodiment, the case where the distance between the boundary portion 34 and the first protrusion 45 is represented by the predetermined distance X2 parallel to the X direction is described, but the present invention is not limited to this structure. Alternatively, the starting point representing the predetermined distance X2 may be changed according to the shape of the first protrusion 45, for example, the shortest distance between the boundary portion 34 and the outer edge of the first protrusion 45 may be set as the predetermined distance X2. In this case, the predetermined distance X2 does not need to be defined by a direction parallel to the X direction.

[0095] In addition, although this embodiment and the modification example have been described, the above-mentioned embodiment and the modification example may be combined in whole or in part as another embodiment.

[0096] In addition, the present embodiment is not limited to the above-mentioned embodiment and variation, and various changes, substitutions, and variations can be made within the scope of the main purpose of the technical idea. In addition, if the technical idea can be realized in other ways by utilizing technological progress or other derived technologies, the method can also be used for implementation. Therefore, the claims cover all embodiments that can be included in the scope of the technical idea.

[0097] The characteristic points of the above-mentioned embodiments are summarized below.

[0098] The semiconductor module described in the above embodiment includes: a semiconductor element having a gate path formed on its upper surface in a manner extending in a specified direction; and a metal wiring plate arranged on the upper surface of the semiconductor element, the metal wiring plate having a first bonding portion, the first bonding portion being bonded to the upper surface of the semiconductor element via a first bonding material, the first bonding portion having a plurality of first protrusions protruding toward the semiconductor element, the first protrusions being arranged at a position separated from the gate path by a specified distance when viewed from above.

[0099] Furthermore, in the above-mentioned semiconductor module, an area of ​​the plurality of first protrusions is not less than 0.5% and not more than 25% of an area of ​​the first bonding portion.

[0100] Furthermore, in the above-mentioned semiconductor module, the first protrusion is provided at a position which is separated from an outer edge portion of the first bonding portion by a predetermined distance or more.

[0101] Furthermore, in the above-mentioned semiconductor module, a surface of the first protrusion facing the gate via in a plan view has a curved surface.

[0102] Furthermore, in the above-mentioned semiconductor module, the first protrusion has a curved surface at a tip thereof in a cross-sectional view.

[0103] Furthermore, in the above-mentioned semiconductor module, the first protrusion is in the shape of a cylinder, a truncated cone, or a hemispherical shape.

[0104] Furthermore, in the above-mentioned semiconductor module, the plurality of first protrusions are arranged along the outer peripheral edge of the first bonding portion and sandwiching the gate via in a plan view.

[0105] Furthermore, in the above-mentioned semiconductor module, the plurality of first protrusions are arranged side by side along the extending direction of the gate via in a plan view.

[0106] Furthermore, in the above-mentioned semiconductor module, the first protrusion is separated from the gate via by 0.4 mm or more in a plan view.

[0107] Furthermore, in the above-mentioned semiconductor module, the first protrusion is provided in a range of 0.4 mm to 2.0 mm inside the outer edge of the first bonding portion.

[0108] Furthermore, in the above-mentioned semiconductor module, a protrusion height of the first protrusion is not less than 50 μm and not more than 300 μm.

[0109] Furthermore, in the above-mentioned semiconductor module, the first protrusion has a cylindrical shape or a truncated cone shape, and an outer diameter is not less than 0.4 mm and not more than 1.5 mm.

[0110] In addition, in the above-mentioned semiconductor module, the semiconductor element has: an upper surface electrode, which is arranged on the upper surface of the semiconductor element; and a plating layer, which is arranged on the upper surface of the upper surface electrode, the gate path is formed on the upper surface of the upper surface electrode in a manner of penetrating the plating layer, and the first protrusion is separated from the gate path, the upper surface electrode and the boundary portion where the plating layer is concentrated by a specified distance.

[0111] Furthermore, in the above-mentioned semiconductor module, the gate via extends so as to divide the upper surface of the semiconductor element into a plurality of parts, and the plurality of first protrusions are arranged on each of the upper surfaces of the semiconductor element divided by the gate via.

[0112] In addition, in the above-mentioned semiconductor module, the upper surface of the semiconductor element is formed in a grid shape, and one of the first protrusions is arranged on each upper surface of the semiconductor element divided by the grid-shaped gate path, and on each divided upper surface of the semiconductor element, the area of ​​the first protrusion is greater than 0.5% and less than 25% of the area of ​​the first bonding portion.

[0113] In addition, in the above-mentioned semiconductor module, the semiconductor element is rectangular in shape and has a gate pad in the center of one side. On the upper surface of the semiconductor element, the gate path extends from the gate pad in a direction perpendicular to the one side and stops at a position between the one side and the other side and extends from there in a direction parallel to the one side. The overall shape is the letter T, and one of the first protrusions is arranged in each area divided by the letter T-shaped gate path on the upper surface of the semiconductor element, and a plurality of the first protrusions are arranged in an area on the other side.

[0114] In addition, in the above-mentioned semiconductor module, the semiconductor module also has a stacked substrate, which has a first circuit board and a second circuit board arranged on the upper surface of an insulating plate, the semiconductor element is arranged on the first circuit board, and the metal wiring plate has: a second joining portion, which is joined to the second circuit board via a second joining material; and a connecting portion, which connects the first joining portion and the second joining portion, and the second joining portion has at least one second protrusion protruding toward the second circuit board.

[0115] Furthermore, in the above-mentioned semiconductor module, the first joining portion, the second joining portion, and the connecting portion are arranged in a row in a plan view.

[0116] Furthermore, in the above-mentioned semiconductor module, the first bonding portion and the second bonding portion are arranged so as to be obliquely opposed to each other with the connection portion interposed therebetween in a plan view.

[0117] In addition, in the above-mentioned semiconductor module, the semiconductor module also has a first bent portion, which is bent from the end of the first joint portion toward the connecting portion to connect the first joint portion and the connecting portion, the width of the first bent portion is smaller than the width of the first joint portion, and at least a portion of the first protrusion is arranged on the inner side of the end connected to the first bent portion, and at least a portion is arranged on the outer side of the end connected to the first bent portion.

[0118] In addition, in the above-mentioned semiconductor module, the semiconductor module also has a second bent portion, which is bent from the end of the second joint portion toward the connecting portion to connect the second joint portion and the connecting portion, the width of the second bent portion is smaller than the width of the second joint portion, and at least a portion of the second protrusion is arranged on the inner side of the end connected to the second bent portion, and at least a portion is arranged on the outer side of the end connected to the second bent portion.

[0119] Furthermore, in the above-mentioned semiconductor module, the first joining portion has a notch portion formed by cutting away a part of an outer edge thereof connected to the first bent portion.

[0120] Furthermore, in the above-mentioned semiconductor module, the semiconductor element further includes a guard ring provided around the plating layer, and the first protrusion is separated from the guard ring by a predetermined distance.

[0121] Industrial Applicability

[0122] As described above, the present invention has the effect of ensuring the thickness of the solder and suppressing the stress concentration between the chip and the lead frame, and is particularly useful for semiconductor modules.

[0123] This application is based on Japanese Patent Application No. 2019-188628 filed on October 15, 2019. The entire contents are incorporated herein by reference.

Claims

1. A semiconductor module, wherein: The semiconductor module includes: A semiconductor element having a gate via formed on an upper surface so as to extend in a predetermined direction; and a metal wiring plate disposed on the upper surface of the semiconductor element, The metal wiring plate has a first bonding portion bonded to the upper surface of the semiconductor element via a first bonding material. The first bonding portion has a plurality of first protrusions protruding toward the semiconductor element. The first protrusion is provided at a position separated from the gate path by a predetermined distance in a plan view. The semiconductor element has: an upper surface electrode disposed on an upper surface of the semiconductor element; and a coating layer disposed on the upper surface of the upper surface electrode, The first protrusion is separated from the gate via and a boundary portion where the plating layer is concentrated by a predetermined distance.

2. The semiconductor module according to claim 1, wherein: The area of ​​the plurality of first protrusions is not less than 0.5% and not more than 25% of the area of ​​the first bonding portion.

3. The semiconductor module according to claim 1 or 2, wherein: The first protrusion is provided at a position spaced apart from an outer edge of the first joining portion by a predetermined distance or more.

4. The semiconductor module according to claim 1 or 2, wherein: The first protrusion has a curved surface on a surface facing the gate via in a plan view.

5. The semiconductor module according to claim 1 or 2, wherein: The first protrusion has a curved surface at the tip when viewed in cross section.

6. The semiconductor module according to claim 1 or 2, wherein: The first protrusion is in the shape of a cylinder, a truncated cone, or a hemisphere.

7. The semiconductor module according to claim 1 or 2, wherein: The plurality of first protrusions are arranged along the outer peripheral edge of the first bonding portion and sandwiching the gate via in a plan view.

8. The semiconductor module according to claim 1 or 2, wherein: The plurality of first protrusions are arranged side by side along the extending direction of the gate via in a plan view.

9. The semiconductor module according to claim 1 or 2, wherein: The first protrusion is spaced apart from the gate via by 0.4 mm or more in a plan view.

10. The semiconductor module according to claim 1 or 2, wherein: The first protrusion is provided in a range of 0.4 mm to 2.0 mm inside the outer edge of the first joining portion.

11. The semiconductor module according to claim 1 or 2, wherein: The protrusion height of the first protrusion is not less than 50 μm and not more than 300 μm.

12. The semiconductor module according to claim 1 or 2, wherein: The first protrusion has a cylindrical shape or a truncated cone shape, and an outer diameter is greater than or equal to 0.4 mm and less than or equal to 1.5 mm.

13. The semiconductor module according to claim 1 or 2, wherein: The gate via is formed on the upper surface of the upper surface electrode in a manner penetrating the plating layer. The first protrusion is separated from the gate via, the upper surface electrode, and a boundary portion where the plating layer is concentrated by the predetermined distance.

14. The semiconductor module according to claim 13, wherein: The semiconductor element is rectangular in shape and has a gate pad at the center of one side. The gate path extends from the gate pad on the upper surface of the semiconductor element in a direction perpendicular to the one side to a position between the one side and another side opposite to the one side. The first protrusions are arranged line-symmetrically with respect to the gate via as a center.

15. The semiconductor module according to claim 13, wherein: The gate via extends so as to divide the upper surface of the semiconductor element into a plurality of parts, and the plurality of first protrusions are arranged on each of the upper surfaces of the semiconductor element divided by the gate via.

16. The semiconductor module according to claim 15, wherein: The gate path is formed in a grid shape on the upper surface of the semiconductor element. One of the first protrusions is disposed on each upper surface of the semiconductor element divided by the grid-shaped gate path, and an area of ​​the first protrusion on each divided upper surface of the semiconductor element is greater than 0.5% and less than 25% of an area of ​​the first bonding portion.

17. The semiconductor module according to claim 15, wherein: The semiconductor element is rectangular in shape and has a gate pad at the center of one side. On the upper surface of the semiconductor element, the gate path is formed in a T-shape as a whole in a manner that the gate path extends from the gate pad in a direction perpendicular to the one side and stops at a position between the one side and another side opposite to the one side and extends from there in a direction parallel to the one side. One first protrusion is disposed in each of two regions on one side of the upper surface of the semiconductor element divided by the T-shaped gate via, and a plurality of first protrusions are disposed in one region on the other side.

18. The semiconductor module according to claim 1 or 2, wherein: The semiconductor module further includes a laminate substrate having a first circuit board and a second circuit board arranged on an upper surface of an insulating plate. The semiconductor element is arranged on the first circuit board. The metal wiring plate has: a second bonding portion bonded to the second circuit board via a second bonding material; and a connecting portion connecting the first bonding portion and the second bonding portion. The second engaging portion has at least one second protrusion protruding toward the second circuit board.

19. The semiconductor module according to claim 18, wherein: The first joining portion, the second joining portion, and the connecting portion are arranged in a row in a plan view.

20. The semiconductor module according to claim 18, wherein The first joining portion and the second joining portion are arranged so as to be obliquely opposed to each other with the connecting portion interposed therebetween in a plan view.

21. The semiconductor module according to claim 18, wherein The semiconductor module further includes a first bent portion that is bent from an end of the first bonding portion toward the connecting portion to connect the first bonding portion and the connecting portion. The width of the first curved portion is smaller than the width of the first joint portion, At least a portion of the first protrusion is disposed inside the end portion connected to the first bent portion, and at least a portion of the first protrusion is disposed outside the end portion connected to the first bent portion.

22. The semiconductor module according to claim 21, wherein The semiconductor module further includes a second bent portion that is bent from an end of the second bonding portion toward the connecting portion to connect the second bonding portion and the connecting portion. The width of the second curved portion is smaller than the width of the second joint portion, At least a portion of the second protrusion is disposed inside the end portion connected to the second bent portion, and at least a portion of the second protrusion is disposed outside the end portion connected to the second bent portion.

23. The semiconductor module according to claim 21, wherein: The first joining portion has a notch portion formed by cutting away a portion of an outer edge thereof connected to the first bent portion.

24. The semiconductor module according to claim 1 or 2, wherein: The semiconductor element has: an upper surface electrode disposed on an upper surface of the semiconductor element; and a coating layer disposed on the upper surface of the upper surface electrode, The semiconductor element further comprises a guard ring disposed around the plating layer. The first protrusion is separated from the protective ring by a predetermined distance in a plan view.

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