Source driving device

Abstract

The present disclosure discloses a source driving apparatus having a test pad for probe testing. The source driving apparatus includes an output circuit including channels having a plurality of channel pairs and configured to output a source signal for each channel, and a test multiplexer configured to selectively provide a test path connecting a channel pair selected from the plurality of channel pairs and a preset test pad.

Description

TECHNICAL FIELD

[0001] Various embodiments relate generally to a source driving apparatus, and more particularly, to a source driving apparatus having test pads for probe testing. BACKGROUND

[0002] A display apparatus can include a source driving apparatus for driving a display panel such as an LCD panel or an LED panel. The source driving apparatus can be manufactured as an integrated circuit, and can be mounted to the display panel.

[0003] The source driving apparatus is configured to receive display data for a display screen, to generate a source signal corresponding to the display data, and to provide the source signal to the display panel.

[0004] To perform the above operations, the source driving apparatus has input pads for receiving the display data or an input voltage, and output pads for outputting the source signal.

[0005] The source driving apparatus manufactured as an integrated circuit undergoes a probe test for determining pass or fail before shipment.

[0006] The probe test is performed by a test apparatus, and the test apparatus is manufactured to have a substrate and a large number of pins connected to the substrate for the probe test. In the probe test, the large number of pins of the test apparatus are in contact with all pads of the source driving apparatus for measurement. For the probe test, a test signal is supplied through some pins, and an output signal corresponding to a test result is output through some other pins.

[0007] To achieve high resolution and multi-function, the source driving apparatus is gradually designed to have a large number of output pads, and thus the test apparatus is gradually required to have a large number of pins for probe testing of the source driving apparatus. However, there is a limit in increasing the number of pins of the test apparatus.

[0008] Therefore, in a case where the output pads of the source driving apparatus exceed the accommodation limit of the test apparatus, it is difficult to normally perform the probe test on the source driving apparatus due to the limited number of pins of the test apparatus.

[0009] Therefore, there is a need to design the source driving apparatus to be able to perform the probe test using a small number of pins. SUMMARY

[0010] Various embodiments relate to a source driving apparatus capable of performing a probe test using a small number of pins.

[0011] In addition, various embodiments relate to a source driving apparatus capable of performing a probe test on a large number of channels, having a small number of test pads.

[0012] In an embodiment, the source driving apparatus can include an output circuit including channels having a plurality of channel pairs, and configured to output source signals for each channel, and a test multiplexer configured to selectively provide a test path connecting a channel pair selected from among the plurality of channel pairs and a preset test pad.

[0013] In an embodiment, the source driving apparatus can include first and second logic units each configured to process a preset number of bits among display data in parallel, a first output circuit including channels having a plurality of channel pairs, and configured to output source signals corresponding to outputs of the first logic unit, a second output circuit including channels having a plurality of channel pairs, and configured to output source signals corresponding to outputs of the second logic unit, a test pad configured between the first and second output circuits, and a test multiplexer configured to selectively provide a test path connecting a channel pair selected from among channel pairs of the first and second output circuits and the test pad.

[0014] In an embodiment, the source driving apparatus can include an output circuit including a plurality of channels for outputting source signals, and a test multiplexer configured to selectively provide a test path connecting a channel selected from among the plurality of channels and a preset test pad.

[0015] The present disclosure is configured to sequentially perform a probe test on a plurality of channels through one test pad.

[0016] Accordingly, according to the present disclosure, a probe test on a source driving apparatus can be performed on a large number of channels using a small number of test pads.

[0017] That is, according to the present disclosure, a test apparatus can perform a probe test on a source driving apparatus having a large number of output pads using a small number of pins. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 FIG. 1 is a circuit diagram illustrating a source driving apparatus according to an embodiment of the present disclosure.

[0019] Figure 2 FIG. 2 is a circuit diagram illustrating another embodiment of the present disclosure.

[0020] Figure 3 FIG. 3 is a circuit diagram illustrating still another embodiment of the present disclosure.

[0021] Figure 4 FIG. 4 is a diagram illustrating an example of a layout for forming a test multiplexer according to an embodiment of the present disclosure.

[0022] Figure 5 FIG. 5 is a diagram illustrating another example of a layout for forming a test multiplexer according to an embodiment of the present disclosure.

[0023] Figure 6 FIG. 4 is a diagram illustrating yet another example of a layout for forming a test multiplexer according to an embodiment of the disclosure.

[0024] Figure 7 FIG. 5 is a diagram illustrating still another example of a layout for forming a test multiplexer according to an embodiment of the disclosure.

[0025] Figures 8 to 11 FIG. 6 is a circuit diagram illustrating other embodiments of the disclosure. DETAILED DESCRIPTION

[0026] The source driving apparatus for a display device is configured to receive display data and provide a source signal to a display panel to display a screen.

[0027] For example, the source driving apparatus includes a reception and reset unit (not shown), a latch unit (not shown), a shift register (e.g., SR1 and SR2 of FIG. 1), a digital-to-analog converter (not shown), an output buffer (e.g., B1 to B8 of FIG. 1), and an output multiplexer (e.g., M1 to M8 of FIG. 1). Figure 3 Figure 1 Figure 2 Figure 1 Figure 2

[0028] The reception and reset unit is configured to receive and reset the display data, the latch unit includes a latch (not shown) for aligning the serial display data in parallel with the reset, the shift register is configured to transfer the latched data to the digital-to-analog converter, the digital-to-analog converter is configured to receive the display data transferred through the shift register and select and output a gamma voltage corresponding to the display data, the output buffer is configured to generate and output a source signal corresponding to the gamma voltage output from the digital-to-analog converter, and the output multiplexer is configured to select a channel for outputting the source signal of the output buffer.

[0029] Among the above components, the latch unit, the shift register, and the digital-to-analog converter correspond to a logic unit, each of which is configurable to process the display data in parallel with, for example, a 6-channel or 8-channel unit. Embodiments of the disclosure show that the display data is processed in parallel with an 8-channel unit by the logic unit. The logic unit can be understood as a digital component that processes a digital signal.

[0030] Among the above components, the output buffer and the output multiplexer form an output circuit and are configured to output a source signal for a corresponding channel. The output circuit including the output buffer and the output multiplexer can be understood as an analog component that outputs a source signal through an output pad.

[0031] ​​​​​The present disclosure includes a test pad to measure an output characteristic of a corresponding channel for outputting a source signal, and is implemented to measure the output characteristic of the corresponding channel using the test pad. The test pad can be designated as one of the output pads, or can be configured separately from the output pads. The test pad can be contacted with a needle of a test device for probe testing, and thus can provide the source signal of the selected channel to the test device.

[0032] Embodiments of the present disclosure include a test multiplexer so that the source signal can be normally output through the test pad for testing without being affected by the surrounding environment.

[0033] Through the above configuration, embodiments of the present disclosure can output the source signal of the channel selected by the test multiplexer through the test pad and contacting the needle with the test pad to perform probe testing.

[0034] Embodiments for this can be configured as shown in Figure 1 and Figure 2 Figure 1 is an embodiment configured to use one of the output pads as a test pad, and Figure 2 is an embodiment in which the test pad is configured separately from the output pads.

[0035] First, the configuration and operation of embodiments of the present disclosure will be described below with reference to Figure 1

[0036] In Figure 1 , eight channels CH1 to CH8 form the output circuit described above.

[0037] In other words, it can be understood that the output circuit includes eight channels CH1 to CH8 and is configured to output a source signal in each channel. To this end, the output circuit includes output buffers B1 to B8, output multiplexers M1 to M8, and output pads P1 to P8 for forming the eight channels CH1 to CH8.

[0038] Each channel includes one output buffer, one output multiplexer, and one output pad, and outputs a source signal through the output pad. For example, the channel CH1 includes the output buffer B1, the output multiplexer M1, and the output pad P1, and outputs a source signal through the output pad P1. The channel CH2 includes the output buffer B2, the output multiplexer M2, and the output pad P2, and outputs a source signal through the output pad P2.

[0039] ​​As described above, the output buffers B1 to B8 are configured to correspond to outputs of digital-to-analog converters for the respective channels, and generate and output source signals corresponding to gamma voltages. Since the outputs of the output buffers B1 to B8 are used as inputs of the output multiplexers M1 to M8, the outputs of the output buffers B1 to B8 will be referred to as input signals hereinafter.

[0040] For example, in order to improve the image quality of the display panel, the source driving apparatus performs polarity inversion on the source signals so that vertically or horizontally adjacent pixels of the display panel have opposite polarities.

[0041] To this end, the output buffers B1 to B8 are configured so that adjacent output buffers output input signals having opposite polarities. For example, the output buffer B1, the output buffer B3, the output buffer B5, and the output buffer B7 are buffers outputting input signals having positive polarity, while the output buffer B2, the output buffer B4, the output buffer B6, and the output buffer B8 are buffers for outputting input signals having negative polarity. In order to distinguish the output polarities, the output buffers B1 to B8 are distinguished by "VH" and "VL". "VH" refers to positive polarity, and "VL" refers to negative polarity. The positive polarity and the negative polarity can be defined by, for example, a driving voltage, a ground voltage, and an intermediate voltage, and the intermediate voltage can be understood as having an intermediate level between the driving voltage and the ground voltage. That is, the positive polarity means a level between the driving voltage and the intermediate voltage, and the negative polarity means a level between the intermediate voltage and the ground voltage.

[0042] Through the above description, among the channels CH1 to CH8, the channel CH1 and the channel CH2, the channel CH3 and the channel CH4, the channel CH5 and the channel CH6, and the channel CH7 and the channel CH8 form channel pairs, respectively. The two channels included in each channel pair are configured to share two input signals of polarity inversion, and each output a source signal corresponding to one of the two input signals.

[0043] In order for the two channels included in each channel pair to share the two input signals, the output multiplexers of each channel are configured to receive two input signals of the two channels of the channel pair.

[0044] For example, the channel CH1 and the channel CH2 form one channel pair, and the respective output multiplexers M1 and M2 of the channel CH1 and the channel CH2 are configured to share two input signals of one channel pair by receiving two input signals of the output buffer B1 and the output buffer B2 through their input terminals. Each of the output multiplexers M1 and M2 of the channel CH1 and the channel CH2 is configured to select one of the two input signals, and output the selected input signal as a source signal through the output pad P1 or the output pad P2 connected to its output terminal.

[0045] Thus, the input signal having the positive polarity output from the output buffer B1 of the channel CH1 can be transmitted to the output pad P1 through the output multiplexer M1 or can be transmitted to the output pad P2 through the output multiplexer M2. Also, the input signal having the negative polarity output from the output buffer B2 of the channel CH2 can be transmitted to the output pad P2 through the output multiplexer M2 or can be transmitted to the output pad P1 through the output multiplexer M1.

[0046] When the output multiplexer M1 selects the input signal of the output buffer B1, the output multiplexer M2 selects the input signal of the output buffer B2. Conversely, when the output multiplexer M1 selects the input signal of the output buffer B2, the output multiplexer M2 selects the input signal of the output buffer B1.

[0047] As in the case of the channel CH1 and the channel CH2, each of the channel pairs formed by the channel CH1 and the channel CH2, the channel CH3 and the channel CH4, the channel CH5 and the channel CH6, and the channel CH7 and the channel CH8 is configured to share two input signals, select one of the two input signals different from each other, and output the selected input signal as a source signal through the corresponding output pad.

[0048] The test multiplexer MUX is configured to selectively provide a test path connected between a selected channel pair among the plurality of channel pairs and a preset test pad. In Figure 1 the test pad is configured to use the output pad P8.

[0049] In order to provide the test path, the test multiplexer MUX includes a switch S2, a switch S4, a switch S6, and a switch S8. One ends of the switches S2, S4, S6, and S8 are commonly connected to the output pad P8 and form an output end of the test multiplexer MUX. The other ends of the switches S2, S4, S6, and S8 form an input end of the test multiplexer MUX. Among the switches S2, S4, S6, and S8, the switch S2 is connected between the output end of the output multiplexer M2 and the output pad P2 of the channel CH2 between the channel CH1 and the channel CH2 as a channel pair, the switch S4 is connected between the output end of the output multiplexer M4 and the output pad P4 of the channel CH4 between the channel CH3 and the channel CH4 as a channel pair, the switch S6 is connected between the output end of the output multiplexer M6 and the output pad P6 of the channel CH6 between the channel CH5 and the channel CH6 as a channel pair, and the switch S8 is connected between the output end of the output multiplexer M8 and the output pad P8 of the channel CH8 between the channel CH7 and the channel CH8 as a channel pair.

[0050] The test multiplexer MUX sequentially turns on the switches S2, S4, S6 and S8, thereby selecting one channel pair among the plurality of channel pairs and forming a test path connecting the selected channel pair and the output pad P8 as a test pad. The test multiplexer MUX can selectively form the test path described above. To this end, the test multiplexer MUX can sequentially form the test path by sequentially turning on the switches S2, S4, S6 and S8, for example, according to a predetermined order.

[0051] In the case of a normal operation in which the source signals are output to each of the output pads P1 to P8, the source driving apparatus according to the embodiment of the disclosure turns off all of the corresponding switches S2, S4, S6 and S8 of the test multiplexer MUX. Figure 1

[0052] In the case of a normal operation, Figure 1 The source driving apparatus of the disclosure can directly output or cross output the input signals of the channel pairs according to the on / off states of the output multiplexers M1 to M8. The direct output means outputting the input signals of the corresponding output buffers of each channel pair through the output pads of the corresponding channels, and the cross output means outputting the input signals of the paired output buffers of each channel pair through the output pads of the corresponding channels.

[0053] In the case of a probe test, the source driving apparatus according to the embodiment of the disclosure can sequentially form the test path by sequentially turning on the corresponding switches S2, S4, S6 and S8 of the test multiplexer MUX. Figure 1

[0054] When the switch S2 is turned on, a test path between the output terminal of the output multiplexer M2 and the output pad P8 as a test pad is formed, and the remaining switches S4, S6 and S8 remain in an off state.

[0055] When the switch S2 is turned on, the output multiplexer M2 sequentially transitions to a first switch state for cross output and a second switch state for direct output.

[0056] The input signal of the output buffer B1 can be output to the output pad P8 as a source signal of the channel CH1 through the output multiplexer M2 in the first switch state and the test multiplexer MUX in which the switch S2 is turned on. The source signal of the channel CH1 can be provided to a test apparatus for a probe test through a needle in contact with the output pad P8 as a test pad.

[0057] ​​Then, the input signal of the output buffer B2 can be output to the output pad P8 as a source signal of the channel CH2 through the output multiplexer M2 in the second switch state and the test multiplexer MUX in which the switch S2 is on. The source signal of the channel CH2 can be provided to the test device for probe testing through a needle in contact with the output pad P8 as a test pad.

[0058] Thereafter, the switches S4, S6, and S8 of the test multiplexer MUX can be sequentially turned on one by one. The source signals of the channels CH1 and CH2, CH3 and CH4, CH5 and CH6, and CH7 and CH8 forming the channel pairs can be output to the output pad P8 through the test paths formed by the test multiplexer MUX, and can be provided to the test device through the needles in contact with the output pad P8.

[0059] As described above, Figure 1 Embodiments of the present disclosure can perform probe testing on a plurality of channels using one test pad.

[0060] Accordingly, one source driving apparatus can perform probe testing using a small number of needles. Specifically, when a source driving apparatus has N output pads and a test pad configured in units of eight channels, the number of needles required for a test device to perform probe testing on one source driving apparatus can be reduced to N / 8.

[0061] When a test device has N needles, the test device can simultaneously perform probe testing on eight source driving apparatuses implemented according to the present disclosure. Accordingly, according to the present disclosure, in a case in which probe testing is performed on a plurality of source driving apparatuses implemented on one wafer, the time required to perform probe testing on the source driving apparatuses of the entire wafer can be shortened, and thus the manufacturing cost of each source driving apparatus can be reduced.

[0062] As Figure 2 indicated, as an embodiment of the present disclosure, a source driving apparatus can include a test pad PT configured separately from the output pads.

[0063] In Figure 2 , the test pad PT can be configured separately from the output pads P1 to P8. For example, the test pad PT can be configured adjacent to the output pad P8.

[0064] The test pad PT is commonly connected to one ends of the switches S2, S4, S6, and S8 forming the output end of the test multiplexer MUX.

[0065] Except that the test pad PT is separately configured and the output end of the test multiplexer MUX is configured by the test pad PT, Figure 2 the embodiment of the present disclosure performs probe testing on a plurality of channels using one test pad.Figure 1 Therefore, in Figure 2 In the embodiment of Figure 1 Configuration and operations in the same configuration and operations are repeated descriptions.

[0066] exist Figure 2 In the embodiment, the test multiplexer MUX turns on the switch S2, the switch S4, the switch S6 and the switch S8 one by one, and thereby selects one channel pair from among the plurality of channel pairs and forms a test path connecting the selected channel pair and the test pad PT.

[0067] Therefore, in Figure 2 In an embodiment, a test path can be formed by sequentially turning on switches S2, S4, S6, and S8 of the test multiplexer MUX. Source signals of channels CH1 and CH2, CH3 and CH4, CH5 and CH6, and CH7 and CH8 forming channel pairs can be sequentially output to the test pad PT via the test path formed by the output multiplexers M1 to M8 and the test multiplexer MUX, and can be provided to the test equipment via a pin in contact with the test pad PT.

[0068] exist Figure 1 and Figure 2 In the embodiment, due to routing selection, parasitic circuits EC may exist. This parasitic circuit EC affects the source signals between output multiplexers M1 to M8 and output pads P1 to P8 of corresponding channels CH1 to CH8 through parasitic components. Parasitic circuits EC may include resistor components or diode components and may be formed differently in the corresponding channels. For illustration purposes, parasitic circuits EC are shown identically.

[0069] exist Figure 1 In the embodiment of , since one selected output pad is used as a test pad, it can be understood that a uniform parasitic circuit EC acts on the corresponding source signal. Figure 1 In the embodiment, the probe test on the source signal of the corresponding channel can be performed by ignoring the non-uniform influence of the parasitic circuit EC of the corresponding channel.

[0070] In addition, Figure 2 In the embodiment, a separate test pad is used. Therefore, even if Figure 2 In the embodiment, the probe test on the source signal of the corresponding channel can also be performed by ignoring the non-uniform influence of the parasitic circuit EC of the corresponding channel.

[0071] at the same time, Figure 3Embodiments of the test pad PT are configured with a first logic unit and a second logic unit, each of which processes a preset number of bits in parallel from the display data.

[0072] In Figure 3 Embodiments of the test pad PT are configured with a first logic unit and a second logic unit, each of which processes a preset number of bits in parallel from the display data. Figure 3 Embodiments of the test pad PT are configured with a first logic unit and a second logic unit, each of which processes a preset number of bits in parallel from the display data.

[0073] In Figure 3 Embodiments of the test pad PT are configured with a first logic unit and a second logic unit, each of which processes a preset number of bits in parallel from the display data.

[0074] Further, in Figure 3 Embodiments of the test pad PT are configured with a first logic unit and a second logic unit, each of which processes a preset number of bits in parallel from the display data.

[0075] In Figure 3 Embodiments of the test pad PT are configured with a first logic unit and a second logic unit, each of which processes a preset number of bits in parallel from the display data.

[0076] Since the above-described embodiments are described by referring toFigure 1 and Figure 2 It can be understood that the configurations of the first output circuit, the second output circuit, and the test multiplexer MUX and the method of providing a test path through them, and thus detailed descriptions thereof will be omitted herein.

[0077] Figure 3 Embodiments of the present disclosure can perform probe testing on more number of channels using one test pad than Figure 1 and Figure 2 than the prior art.

[0078] Thus, in the case of Figure 3 , the number of pins required by the test equipment to perform probe testing on one source driver device can be reduced to N / 16.

[0079] When the test equipment has N pins, the test equipment can perform probe testing on 16 source driver devices simultaneously through Figure 3 Embodiments of the present disclosure. Thus, the time required to perform probe testing on source driver devices of the entire wafer can be shortened, and the manufacturing cost of each source driver device can be reduced.

[0080] The test multiplexer MUX configured as shown in Figures 1 to 3 may be formed through a layout as shown in Figure 4 .

[0081] Figure 4 The layout of Figure 4 is divided into P-well HPW(M2), N-well HNW(M2), P-well HPW(MUX(S2)), N-well HNW(MUX(S2)), P-well HPW(I / O space), N-well HNW(Resd, diode), and P-well HPW(diode). The P-well HPW(M2) and the N-well HNW(M2) are used to form the output multiplexer M2, the P-well HPW(MUX(S2)) and the N-well HNW(MUX(S2)) are used to form the switch S2 of the test multiplexer MUX, the P-well HPW(I / O space) is used to connect the input / output (I / O) to the core space, and the N-well HNW(Resd, diode) and the P-well HPW(diode) form the equivalent diode of the parasitic circuit EC, in which the N-well HNW(Resd, diode) serves as a resistive component.

[0082] The layout of Figure 5 may be modified as shown in Figure 4 to reduce the layout size.

[0083] Figure 5The layout shows that the switch S2 of the test multiplexer MUX is formed using parts of the P-well HPW (M2) and the N-well HNW (M2), and the area where the switch S2 of the test multiplexer MUX is formed in the P-well HPW (M2) and the N-well HNW (M2) is designated as P-well HPW (MUX (S2)) and N-well HNW (MUX (S2)).

[0084] exist Figure 5 In the layout of , the P-well HPW(M2) and the N-well HNW(M2) can be shared in the formation of the output multiplexer M2 and the switch S2 of the test multiplexer MUX, and due to this fact, Figure 5 The layout can have less than Figure 4 The dimensions of the layout.

[0085] Can be based on Figure 6 Modifications shown Figure 5 layout to reduce the layout size.

[0086] Figure 6 The layout is shown for forming Figure 5 The N-well HNW (MUX ( S2 )) of the switch S2 of the test multiplexer MUX is formed as an N-well HNW (MUX ( S2 ), Resd) to serve as a resistance component (Resd).

[0087] Figure 6 The layout can be somewhat better than Figure 5 The size is smaller because Figure 5 The N-well HNW (Resd, diode) is not used as a resistance component (Resd).

[0088] According to Figure 7 Modifications shown Figure 6 layout to reduce the layout size.

[0089] Figure 7 The layout is shown in Figure 6 The P-well HPW (I / O space) is removed from the layout and the channel length of the P-well HPW (MUX (S2)) is reduced.

[0090] Figure 7 The layout can be somewhat better than Figure 6 The size of the MCU is smaller because the P-well HPW (I / O space) is removed.

[0091] Meanwhile, the source driving device according to the present disclosure may be implemented such that the test multiplexer MUX selectively provides a test path connecting a channel selected from among a plurality of channels and a preset test pad.

[0092] The implementation for this can be based on Figures 8 to 11 Implementation shown.

[0093] In Figures 8 to 11 Embodiments of the test multiplexer MUX can include switches S1 to S8 respectively corresponding to the channels CH1 to CH8, and can selectively connect a selected channel and a test pad.

[0094] More specifically, one end of the switches S1 to S8 is commonly connected to the test pad, and forms an output end of the test multiplexer MUX. The other end of the switches S1 to S8 forms an input end of the test multiplexer MUX.

[0095] As shown in Figure 8 and Figure 10 Embodiments, the input end of the test multiplexer MUX can be connected to the input ends of the output multiplexers M1 to M8 of the channels CH1 to CH8, or as shown in Figure 9 and Figure 11 Embodiments, can be connected between the output multiplexers M1 to M8 of the channels CH1 to CH8 and the output pads P1 to P8.

[0096] As shown in Figure 8 and Figure 9 Embodiments, the test pad can be provided to use one of the output pads P1 to P8 of the channels CH1 to CH8 (for example, the output pad P8). In this case, the output end of the test multiplexer MUX is connected to the output pad P8. Also, as shown in Figure 10 and Figure 11 Embodiments, the test pad PT can be separately configured from the output pads P1 to P8 of the channels CH1 to CH8.

[0097] Hereinafter, embodiments of Figures 8 to 11 will be described in detail.

[0098] In Figure 8 Embodiments, the test multiplexer MUX includes switches S1 to S8 respectively corresponding to the channels CH1 to CH8. The output end of the test multiplexer MUX (i.e., one end of the switches S1 to S8) is connected to the output pad P8 provided as a test pad, and the input end of the test multiplexer MUX (i.e., the other end of the switches S1 to S8) is connected to the input ends of the output multiplexers M1 to M8, respectively.

[0099] In Figure 8 Embodiments, since the configurations of the respective channels CH1 to CH8 can be understood by referring to Figure 1 and Figure 2 , a repeated description thereof will be omitted.

[0100] In Figure 8In an embodiment, by turning on switches S1 to S8 of the test multiplexer MUX one by one for probe testing, a test path is formed connecting the input terminals of the output multiplexers M1 to M8 of the selected channels CH1 to CH8 and the output pad P8 serving as the test pad. The test multiplexer MUX can sequentially form the test paths by turning on switches S1 to S8 one by one in a predetermined order.

[0101] When one switch of the test multiplexer MUX is turned on, the other switches remain off.

[0102] exist Figure 8 In an embodiment, the input signals of the input ends of the multiplexers M1 to M8 can be output sequentially to the output pad P8 as source signals by sequentially turning on the switches S1 to S8 of the test multiplexer MUX, and the source signal of the output pad P8 can be provided to the test equipment for probe testing through the needle in contact with the output pad P8.

[0103] exist Figure 8 In the embodiment, test paths for corresponding channels may be sequentially formed as described above, and a probe test on the channels may be performed using one output pad P8 set as a test pad.

[0104] Figure 9 The implementation method and Figure 8 The embodiment of the present invention is different in that the input terminal of the test multiplexer MUX (i.e., the other end of the switches S1 to S8) is connected between the output multiplexers M1 to M8 and the output pads P1 to P8 of the channels CH1 to CH8, and its other configurations are the same as those of the present invention. Figure 8 Therefore, the configuration of the embodiment of Figure 9 Repeated description of the configuration and operation of the embodiment.

[0105] exist Figure 9 In an embodiment, the source signals of the output ends of the multiplexers M1 to M8 can be output to the output pad P8 in sequence by sequentially turning on the switches S1 to S8 of the test multiplexer MUX, and the source signal of the output pad P8 can be provided to the test equipment for probe testing through the needle in contact with the output pad P8.

[0106] Therefore, even in Figure 9 In the embodiment, test paths for corresponding channels may also be formed in sequence, and a probe test on the channel may be performed using one output pad P8 set as a test pad.

[0107] At the same time, Figure 10In an embodiment of the test apparatus, the test multiplexer MUX includes switches S1 to S8 corresponding to the channels CH1 to CH8, respectively. An output terminal of the test multiplexer MUX (i.e., one end of the switches S1 to S8) is connected to the test pad PT, and input terminals of the test multiplexer MUX (i.e., the other end of the switches S1 to S8) are connected to the input terminals of the output multiplexers M1 to M8, respectively.

[0108] In an embodiment of the test apparatus, Figure 10 In an embodiment of the test apparatus, since the configurations of the respective channels CH1 to CH8 are understood by referring to the above description of the test apparatus, a repeated description thereof will be omitted. Figure 1 Figure 2 It can be understood that the configurations of the respective channels CH1 to CH8, and thus a repeated description thereof will be omitted.

[0109] In an embodiment of the test apparatus, Figure 10 In an embodiment of the test apparatus, the test paths connecting the input terminals of the output multiplexers M1 to M8 of the selected channels CH1 to CH8 and the test pad PT are formed by sequentially turning on the switches S1 to S8 of the test multiplexer MUX one by one for the probe test. The test multiplexer MUX can sequentially form the test paths by sequentially turning on the switches S1 to S8 one by one according to a predetermined order.

[0110] When one of the switches of the test multiplexer MUX is turned on, the other switches remain turned off.

[0111] In an embodiment of the test apparatus, Figure 10 In an embodiment of the test apparatus, the input signals of the input terminals of the multiplexers M1 to M8 can be sequentially output to the test pad PT as source signals by sequentially turning on the switches S1 to S8 of the test multiplexer MUX, and the source signals of the test pad PT can be provided to the test device through the needle in contact with the test pad PT for the probe test.

[0112] In an embodiment of the test apparatus, Figure 10 In an embodiment of the test apparatus, the test paths for the respective channels can be sequentially formed as described above, and the probe test on the channels can be performed using one test pad PT.

[0113] Figure 11 An embodiment of the test apparatus differs from the embodiment of the test apparatus in that the input terminals of the test multiplexer MUX (i.e., the other end of the switches S1 to S8) are connected between the output multiplexers M1 to M8 of the channels CH1 to CH8 and the output pads P1 to P8, and its other configuration is the same as that of the embodiment of the test apparatus. Figure 10 Figure 10 Thus, a repeated description of the configuration and operation of the embodiment of the test apparatus will be omitted. Figure 11

[0114] In an embodiment of the test apparatus, Figure 11 ​​​In an embodiment of the present application, source signals of the output terminals of the multiplexers M1 to M8 can be sequentially output to the test pad PT by sequentially turning on the switches S1 to S8 of the test multiplexer MUX, and the source signal of the test pad PT can be provided to a test device through a needle in contact with the test pad PT for probe testing.

[0115] Therefore, even in Figure 11 In an embodiment of the present application, test paths for respective channels can be sequentially formed, and probe testing of the channels can be performed using one test pad PT.

[0116] As is apparent from the above-described embodiments, in the present disclosure, probe testing of a plurality of channels can be performed using one test pad.

[0117] Therefore, according to the present disclosure, one source driving apparatus can perform probe testing using a small number of needles.

[0118] Further, according to the present disclosure, a test device can simultaneously perform probe testing on a plurality of source driving apparatuses. Therefore, in a case in which probe testing is performed on a plurality of source driving apparatuses implemented on one wafer, the time required to perform probe testing on the source driving apparatuses of the entire wafer can be shortened, and thus the manufacturing cost of each source driving apparatus can be reduced.

Claims

1. A source driving apparatus, comprising: an output circuit including channels having a plurality of channel pairs, and configured to output a source signal for each of the channels; and a test multiplexer configured to provide a test path connecting a selected channel pair from among the plurality of channel pairs and a preset test pad, wherein each of the channel pairs includes a first channel and a second channel adjacent to each other, the first channel and the second channel are configured to share a first input signal and a second input signal, and output a source signal corresponding to one of the first input signal and the second input signal, and the test multiplexer sequentially provides the test path connecting the second channel of the selected channel pair and the test pad, wherein the test multiplexer includes a plurality of switches, and the test multiplexer is configured to sequentially turn on the switches one by one to make the source signals of the first channel and the second channel forming the channel pair to be output to the test pad through the test path formed by the test multiplexer, wherein each channel includes an output multiplexer and an output pad, and each of the output multiplexers is sequentially switched to a first switch state for cross output and a second switch state for direct output when each of the switches is turned on, wherein the cross output indicates that the input signals of the output buffers of each channel pair are respectively output through the output pads of the paired channels, wherein the direct output indicates that the input signals of the output buffers of each channel pair are respectively output through the output pads of the channels corresponding to the output buffers, wherein the input signals of the output buffers are output to the output pad and the test pad as the source signals of the first channel through the output multiplexer in the first switch state and the test multiplexer in which the switch is turned on, wherein the input signals of the output buffers are output to the output pad and the test pad as the source signals of the second channel through the output multiplexer in the second switch state and the test multiplexer in which the switch is turned on. 2.The source driving apparatus of claim 1, wherein the output multiplexer receives the first input signal and the second input signal corresponding to the channel pair, and outputs a source signal selected between the first input signal and the second input signal to the output pad. the test pad is provided to use one of the output pads of the channels.

3. The source driving apparatus according to claim 2, wherein the test pad is separately configured from the output pads of the channels.

4. The source driving apparatus according to claim 2, wherein 5.The source driving apparatus of claim 2, wherein an input terminal of the test multiplexer is connected between the output multiplexer and the output pad of the second channel of the corresponding channel pair. 6.The source driving apparatus of claim 2, wherein the first channel includes a first buffer outputting the first input signal, and the second channel includes a second buffer outputting the second input signal. the output multiplexer and the test multiplexer are formed to share a P-well and an N-well.

7. The source driving apparatus according to claim 2, wherein ​ 8. The source driving apparatus according to claim 7, wherein The N-wells forming the test multiplexer are formed to function as a resistance component.

9. A source driving apparatus comprising: first and second logic units each configured to process a predetermined number of bits among display data in parallel; a first output circuit including channels having a plurality of channel pairs and configured to output source signals corresponding to outputs of the first logic unit; a second output circuit including channels having a plurality of channel pairs and configured to output source signals corresponding to outputs of the second logic unit; a test pad configured between the first and second output circuits; and a test multiplexer configured to provide a test path connecting a channel pair selected from among the channel pairs of the first and second output circuits and the test pad, wherein each of the channel pairs includes first and second channels adjacent to each other, the first and second channels are configured to share first and second input signals and output a source signal corresponding to one of the first and second input signals, and the test multiplexer sequentially provides the test path connecting the second channel of the selected channel pair and the test pad, wherein the test multiplexer includes a plurality of switches, and the test multiplexer is configured to sequentially turn on the switches one by one to cause source signals of the first and second channels forming the channel pair to be output to the test pad through the test path formed by the test multiplexer, wherein each channel includes an output multiplexer and an output pad, and each output multiplexer is sequentially switched to a first switch state for cross output and a second switch state for direct output when each of the switches is turned on, wherein the cross output indicates that input signals of output buffers of each channel pair are respectively output through output pads of paired channels, wherein the direct output indicates that input signals of output buffers of each channel pair are respectively output through output pads of channels corresponding to the output buffers, wherein the input signals of the output buffers are output to the output pad and the test pad as source signals of the first channel through the output multiplexer in the first switch state and the test multiplexer in which the switch is turned on, wherein the input signals of the output buffers are output to the output pad and the test pad as source signals of the second channel through the output multiplexer in the second switch state and the test multiplexer in which the switch is turned on.

10. The source driving apparatus of claim 9, wherein the output multiplexer receives the first and second input signals corresponding to the channel pair and outputs a source signal selected between the first and second input signals to the output pad, and input terminals of the test multiplexer are connected between output multiplexers and output pads of the second channels of the corresponding channel pairs. ​

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