Method for Measuring Chip Bonding Stress and Chip Bonding Auxiliary Structure

Abstract

The present invention discloses a method for measuring chip bonding stress and a chip bonding auxiliary structure. The method for measuring chip bonding stress includes the following steps: First, form an auxiliary pattern on a first surface of a first chip. Then, bond a second surface of a second chip to the first surface to form at least one gap space surrounding the auxiliary pattern. Next, measure a plurality of spatial dimensions of the at least one gap space and the auxiliary pattern respectively; and estimate the bonding stress between the first chip and the second chip based on the plurality of spatial dimensions.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor element and an auxiliary structure thereof, and particularly to a method for measuring bonding stress of a semiconductor chip and a chip bonding auxiliary structure. Background Art

[0002] Chip bonding technology refers to bonding two semiconductor chips (e.g., wafers) together after cleaning, and then performing high-temperature annealing treatment to form a chemical bond connection at the interface between the two. Currently, it has been widely used in the semiconductor circuit manufacturing process and has become an important means for fabricating composite materials of integrated circuits and realizing microelectromechanical structures (including technologies such as substrate engineering, integrated circuit wiring, microelectromechanical systems (MEMS), and packaging).

[0003] In the chip bonding technology of the semiconductor manufacturing process, bonding stress (adhesive strength) is a very important manufacturing process parameter and an important part related to the quality of the manufacturing process. Insufficient bonding stress strength is likely to cause the risk of chip peeling and cracking during the processing, resulting in component failure. Therefore, after performing the chip bonding step, it is necessary to measure and inspect the bonding stress of the bonded chip structure to ensure the yield and quality of the manufacturing process.

[0004] Currently, the plug blade terminal strength method (also known as the blade method) is commonly used to measure bonding stress. It is to insert a blade along the bonding interface between two chips and estimate the bonding strength between the chips by observing the fracture depth. Although this method uses relatively simple instruments and equipment, it is a destructive testing method. Moreover, due to the brittleness of the chips, the step of inserting the blade relies on manual operation and experience. The measured values may vary due to different operators, resulting in a relatively large measurement error.

[0005] Therefore, there is a need to provide an advanced method for measuring chip bonding stress and a chip bonding auxiliary structure to solve the problems faced by the prior art. Summary of the Invention

[0006] An embodiment of this specification discloses a method for measuring bonding strength of a chip, including the following steps: First, form an auxiliary pattern on a first surface of a first chip. Then bond a second surface of a second chip to the first surface to form at least one gap space surrounding the auxiliary pattern. Next, measure multiple spatial dimensions of this at least one gap space and the auxiliary pattern respectively; and estimate the bonding stress between the first chip and the second chip based on these multiple spatial dimensions.

[0007] Another embodiment of this specification discloses a chip bonding auxiliary structure, including: a first chip, at least one auxiliary pattern, and a second chip. The first chip has a first surface. The auxiliary pattern is formed on the first surface. The second chip has a second surface bonded to the first surface to form a gap space around the auxiliary pattern.

[0008] According to the above embodiment, this specification provides a method for measuring chip bonding stress and a chip bonding auxiliary structure. First, a convex or concave auxiliary pattern is formed on the bonding surface of one of the chips to be bonded, so that a gap space around the auxiliary pattern is generated after the two chips are bonded. By a non-destructive measurement method (for example, ultrasonic, optical or other suitable technologies), the dimensions of the auxiliary pattern and the gap space are measured, and according to the measured dimension data, combined with the elastic modulus of the chip, the bonding stress of the two chips is estimated. Since the bonding structure of the chip is not damaged during the measurement process, the manufacturing process cost can be reduced. At the same time, the variation factors of manual operation can be excluded, and the measurement accuracy can be improved. Brief Description of the Drawings

[0009] To have a better understanding of the above and other aspects of this specification, the following specific embodiments are given and described in detail in conjunction with the accompanying drawings:

[0010] Figures 1A to 1E A series of manufacturing process structure cross-sectional schematic diagrams for manufacturing semiconductor components shown in an embodiment of this specification;

[0011] Figures 2A to 2B Another embodiment of this specification shows a manufacturing process structure cross-sectional schematic diagram of forming an auxiliary pattern on the surface of a carrier substrate by using another method; and

[0012] Figure 3 For Figure 1D The top view of the chip bonding auxiliary structure shown.

[0013] Symbol Description

[0014] 100: Semiconductor component 101: Component substrate

[0015] 101a: Surface of the component substrate 101c: First part of the component substrate surface

[0016] 101d: Second part of the component substrate surface 101e: p-type well region

[0017] 102: Semiconductor component 103a, 104a: Gate dielectric layer

[0018] 103b, 104b: Gate electrode 103, 104: Gate structure

[0019] 105: n-type contact region 106: p-type contact region

[0020] 107: interlayer dielectric layer 108: interconnect structure

[0021] 110: shallow trench isolation 111: carrier substrate

[0022] 111a: surface of the carrier substrate 112, 212: auxiliary pattern

[0023] 112a: stud 112b, 212b: deposition interface

[0024] 113: focused ion beam deposition process 113a: charged particle beam

[0025] 113b: reaction gas 114: clearance space

[0026] 120: chip bonding assist structure 115: thermal annealing step

[0027] 116: thinning process 201: deposition process

[0028] 202: deposition layer 203: photoresist etching process

[0029] 204: patterned photoresist layer 212a: protrusion

[0030] h: height of the stud t1: thickness of the carrier substrate

[0031] t2: thickness of the device substrate R: average radius of the clearance space Detailed Description of the Invention

[0032] This specification provides a method for measuring chip bonding stress and a chip bonding assist structure, which can achieve the purpose of reducing the manufacturing process cost, reducing the variation factors of manual operation, and improving the measurement accuracy. To make the above embodiments and other purposes, features, and advantages of this specification more obvious and understandable, multiple embodiments are specifically given below and detailed descriptions are made in conjunction with the accompanying drawings.

[0033] However, it must be noted that these specific embodiments and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The presentation of the preferred embodiments is only used to illustrate the technical features of the present invention and is not intended to limit the claims of the present invention. Those with ordinary knowledge in the technical field can make equivalent modifications and changes within the spirit of the present invention based on the following description of the specification. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0034] Please refer to Figures 1A to 1E ,Figures 1A to 1E A series of process structure cross-sectional schematic diagrams for fabricating the semiconductor device 100 are shown according to an embodiment of the present specification. The method for fabricating the semiconductor device 100 includes the following steps: First, provide a device substrate 101. In some embodiments of the present specification, the device substrate 101 may be a substrate, chip, wafer, or other plate, sheet, or film made of a semiconductor material, such as silicon (Si), germanium (Ge), or a compound semiconductor material, such as gallium arsenide (GaAs). However, in other embodiments, the device substrate 101 may also be a silicon-on-insulator (SOI) substrate. In the present embodiment, the device substrate 101 is preferably a silicon substrate, such as a silicon wafer.

[0035] Next, perform a front-end-of-line (FEOL) fabrication process on the front surface 101a of the device substrate 101 to form at least one semiconductor device 102, such as a transistor, capacitor, resistor, other active / passive components, microelectronics / microelectromechanical structures (not shown), or any combination thereof, on the front surface 101a of the device substrate 101. In some embodiments of the present specification, the semiconductor device 102 may include a complementary metal-oxide-semiconductor (CMOS) transistor.

[0036] Among them, the front-end manufacturing process may include (but is not limited thereto) cleaning and planarizing the front-side surface 101a of the component substrate 101 by using Chemical-Mechanical Polishing (CMP); forming a Shallow Trench Isolation (STI) structure 110 in the component substrate 101 to divide the front-side surface 101a of the component substrate 101 into a first part 101c and a second part 101d. And covering a part of the first part 101c on the front-side surface 101a of the component substrate 101 with a patterned photoresist (not shown), and performing a primary ion doping manufacturing process to form a P-type well region 101e in the second part 101d of the front-side surface 101a of the component substrate 101. Then, on the first part 101c and the second part 101d of the front-side surface 101a of the component substrate 101, a gate structure 103 including a gate dielectric layer 103a and a gate electrode 103b and a gate structure 104 including a gate dielectric layer 104a and a gate electrode 104b are respectively formed. After that, using the gate structures 103 and 104 as masks respectively, an ion doping manufacturing process is performed to form two n-type contact regions 105 (denoted as N+) in the p-type well region 101e, adjacent to the gate structure 104; and two p-type contact regions 106 (denoted as P+) are formed in the n-type component substrate 101 (denoted as N), adjacent to the gate structure 103, completing the preparation of the complementary metal-oxide-semiconductor transistor (semiconductor component 102) (as Figure 1A shown).

[0037] After that, a Back-End-Of-Line (BEOL) manufacturing process is performed to form an Interlayer Dielectric (ILD) 107 on the semiconductor component 102, and an interconnect structure 108 including at least one metal layer is formed in the interlayer dielectric 107, which is electrically contacted with the gate structures 103 and 104, the n-type contact regions 105, and the p-type contact regions 106 respectively (as Figure 1B shown).

[0038] Meanwhile, a carrier substrate 111 is provided, and an auxiliary pattern 112 is formed on the surface 111a of the carrier substrate 111. In some embodiments of the present specification, the carrier substrate 111 may be a substrate, chip, wafer, or other plate, sheet, or film made of a semiconductor material, such as silicon, germanium, or a compound semiconductor material, such as gallium arsenide. However, in some other embodiments, the carrier substrate 111 may also be a silicon-on-insulator substrate. In this embodiment, the carrier substrate 111 is preferably also a silicon wafer.

[0039] In some embodiments of the present specification, the auxiliary pattern 112 may be a deposited pattern layer. The manufacturing method of this deposited pattern layer includes: performing a focused ion beam (FIB) deposition process 113 on the surface 111a of the carrier substrate 111, applying a charged particle (or other) beam 113a to the surface 111a of the carrier substrate 111, and mixing with a reaction gas 113b using tetraethoxysilane (TEOS) as a precursor; causing the reaction gas 113b to crack by the ion beam 113a, and then generating a plurality of protrusions 112a made of silicon dioxide (SiO2) at a predetermined position on the surface 111a of the carrier substrate 111. Among them, there is a deposition interface 112b between each protrusion 112a and the surface 111a of the carrier substrate 111; and the auxiliary pattern 112 is composed of these protrusions 112a (as Figure 1C shown).

[0040] In some embodiments of the present specification, the plurality of protrusions 112a may be evenly dispersed on the surface 111a of the carrier substrate 111; or may be concentrated in the central region of the surface 111a of the carrier substrate 111, or dispersed at positions adjacent to the edge 111b of the carrier substrate 111. And the size and shape of each protrusion 112a may be the same or different. For example, in some implementations of the present specification, any one of these protrusions 112a may be a cylinder, a cone, a polygonal column, or a polygonal column with a side surface having other regular or irregular shapes.

[0041] In this embodiment, the plurality of protrusions 112a may be evenly dispersed on the surface 111a of the carrier substrate 111. Each protrusion 112a is a cylinder with the same size. Among them, each protrusion 112a has a bottom area substantially between 0.002 square millimeters (mm 2 ) and 0.03 square millimeters. The height h of each protrusion 112a may be the same or may vary with the change of the configuration position.

[0042] However, the method of manufacturing the auxiliary pattern is not limited to this. Please refer to Figures 2A to 2B , Figures 2A to 2BAccording to another embodiment of the present specification, a schematic cross-sectional view of a manufacturing process structure for forming an auxiliary pattern 212 on the surface 111a of a carrier substrate 111 using another method is shown. In this embodiment, the formation of the auxiliary pattern 212 includes the following steps: First, a deposition manufacturing process 201 is performed to form a deposition layer 202 on the surface 111a of the carrier substrate 111, so that the deposition layer 202 contacts the surface 111a of the carrier substrate 111 to form a deposition interface 202a.

[0043] Next, a photoresist etching manufacturing process 203 is performed to use the patterned photoresist layer 204 as an etching mask to remove a part of the deposition layer 202 for forming a plurality of protrusions 212a on the surface 111a of the carrier substrate 111. Among them, each protrusion 212a is located at a predetermined position, and the auxiliary pattern 212 is formed by these protrusions 212a.

[0044] In this embodiment, except for the difference in the manufacturing method, the structural appearance, size, and distribution position of the plurality of protrusions 212a constituting the auxiliary pattern 212 and the plurality of studs 112a constituting the auxiliary pattern 112 can be exactly the same. In some other embodiments of the present specification, even the above different methods can be used to separately form the above-mentioned auxiliary patterns 112 and 212 at different positions on the surface 111a of the carrier substrate 111.

[0045] After forming the auxiliary pattern 112, the component substrate 101 and the carrier substrate 111 are bonded to form a chip bonding auxiliary structure 120 (as Figure 1D shown). In this embodiment, the bonding method of the component substrate 101 and the carrier substrate 111 is to make the front surface 101a of the component substrate 101 face the surface 111a of the carrier substrate 111; at the same time, a force perpendicular to the front surface 101a of the component substrate 101 and the surface 111a of the carrier substrate 111 is applied to the component substrate 101 and the carrier substrate 111, so that the interlayer dielectric layer 107 on the front surface 101a of the component substrate 101 contacts and fits together with the surface 111a of the carrier substrate 111.

[0046] Among them, the tops of the plurality of studs 112a of the auxiliary pattern 112 contact a part of the interlayer dielectric layer 107 of the component substrate 101, and the parts of the interlayer dielectric layer 107 and the surface 111a of the carrier substrate 111 close to the studs 112a are separated from each other, for defining a plurality of gap spaces 114 between the front surface 101a of the component substrate 101 and the surface 111a of the carrier substrate 111, and making each gap space 114 correspondingly surround a part of the studs 112a in the auxiliary pattern 112. For the sake of clear description, the semiconductor element 102 and the interconnection structure 108 will be omitted in the following drawings.

[0047] For example, in some embodiments of the present specification, each gap space 114 correspondingly surrounds a single stud 112a. In other embodiments of the present specification, each gap space 114 correspondingly surrounds a plurality of studs 112a. Each gap space 114 has a projected area (represented by an average radius R) on the front surface 101a of the component substrate 101 or the surface 111a of the carrier substrate 111, which is substantially between 500 square millimeters and 1000 square millimeters.

[0048] Please refer to Figure 3 , Figure 3 is the top view of the chip bonding assist structure 120 shown according to Figure 1D . In this embodiment, the plurality of studs 112a of the assist pattern 112 are evenly scattered on the surface 111a of the carrier substrate 111. Each gap space 114 is a circular chamber that respectively surrounds or houses a stud 112a, and each stud 112a is located at the center of the corresponding gap space 114.

[0049] In some embodiments of the present specification, after bonding the component substrate 101 and the carrier substrate 111 to form the chip bonding assist structure 120, an annealing step 115 can be optionally performed on the bonded component substrate 101 and carrier substrate 111. By heating at a high temperature, a physical and chemical reaction occurs at the bonding interface between the interlayer dielectric layer 107 of the component substrate 101 and the surface 111a of the carrier substrate 111, forming a chemical bond connection, thereby making the chip bonding assist structure 120 more stable.

[0050] Then, the spatial dimensions of the gap spaces 114 and the assist pattern 112 are measured respectively, and based on the measured spatial dimensions, the bonding stress between the component substrate 101 and the carrier substrate 111 is estimated. In some embodiments of the present specification, the methods for measuring the spatial dimensions of the gap spaces 114 and the assist pattern 112 include using ultrasonic measurement methods or optical measurement methods to measure the average radius R of the plurality of gap spaces 114, the average height h of the plurality of studs 112a, the thickness t1 of the carrier substrate 111, and the thickness t2 of the component substrate 101.

[0051] Among them, the ultrasonic measurement includes using confocal scanning acoustic microscopy (CSAM), which can utilize the differences in the acoustic properties of an object (e.g., acoustic impedance rate and acoustic attenuation) to display the microscopic structure inside the object, so as to obtain the acoustic image or elastic image of the object. It does not require light transmission and can directly observe the inner layer without damaging the object to be measured. The optical measurement includes performing a laser triangulation, which uses one or more laser lines to scan the surface curvature of the object to be measured, and uses basic geometric operations to obtain the distance of the third point based on the known positions of two points. Since both belong to non-contact measurement methods and have the advantages of non-destructiveness, non-contact, fast and convenient instrument setup, etc., it can greatly reduce the inspection cost and avoid the problem of poor measurement quality caused by the interference of human operation factors in the prior art (e.g., the blade terminal strength method).

[0052] In some embodiments of the present specification, for the estimation of the bonding stress γ, in addition to referring to the average radius R of the gap space 114, the average height h of the stud 112a, the thickness t1 of the carrier substrate 111, and the thickness t2 of the component substrate 101 obtained by measurement, it can also be estimated in combination with the modulus of elasticity E1 of the carrier substrate 111 and the modulus of elasticity E2 of the component substrate 101.

[0053] For example, in this embodiment, Young's modulus can be used to estimate the bonding stress γ between the carrier substrate 111 and the component substrate 101, where Young's modulus is as shown in formula (I):

[0054]

[0055] Formula (I)

[0056] The estimated result shows that the bonding stress between the carrier substrate 111 and the component substrate 101 is substantially between 1 joule per square meter (J / m 2 ) and 4 joules per square meter.

[0057] However, it is worth noting that although in this embodiment, the bonding stress γ of the chip bonding structure corresponding to each gap space 114 around a single convex post 112a is estimated using formula (I). However, those with ordinary knowledge in this technical field can still adjust the elastic modulus used to calculate the bonding stress γ according to the differences in the auxiliary pattern 112 (for example, the number or distribution of multiple convex posts 112a) and the relative configuration or parameter range change between the auxiliary pattern 112 and the gap space 114, and use different formulas to estimate the bonding stress γ between the carrier substrate 111 and the component substrate 101.

[0058] After the bonding stress γ of both the component substrate 101 and the carrier substrate 111 meets the manufacturing process standards, the back surface 101b of the component substrate 101 is thinned by process 116 to remove a part of the component substrate 101, exposing a part of the shallow trench isolation structure 110 to the outside (as Figure 1E shown).

[0059] Subsequently, the carrier substrate 111 is removed, and a post - process manufacturing process, such as a metal damascene process, is performed on the back surface 101b of the component substrate 101 to form a metal interconnection structure (not shown) on the back surface 101b of the semiconductor substrate 101, thereby forming the transistor element 100 as Figure 1E shown. The removed carrier substrate 111 can be reused after a cleaning and recycling manufacturing process.

[0060] According to the above - mentioned embodiment, this specification provides a method for measuring chip bonding stress and a chip bonding auxiliary structure. First, a convex or concave auxiliary pattern is formed on the bonding surface of one of the chips to be bonded, so that a gap space around the auxiliary pattern is generated after the two chips are bonded. By a non - destructive measurement method (such as ultrasonic, optical, or other suitable technologies), the dimensions of the auxiliary pattern and the gap space are measured, and based on the measured dimension data, combined with the elastic modulus of the chip, the bonding stress between the two chips is estimated. Since the bonding structure of the chip is not damaged during the measurement process, the manufacturing process cost can be reduced. At the same time, the variation factors of manual operation can be excluded, and the measurement accuracy can be improved.

[0061] Although the present invention is disclosed in combination with the above - mentioned preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in this technical field can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be defined by the appended claims.

Claims

1. A method for measuring chip bonding stress, comprising: Form an auxiliary pattern on the first surface of the first chip; Bond the second surface of the second chip to the first surface to form at least one gap space around the auxiliary pattern; Measure a plurality of spatial dimensions of the at least one gap space and the auxiliary pattern respectively; And Estimate the bonding stress between the first chip and the second chip according to the plurality of spatial dimensions, the elastic modulus of the first chip, and the elastic modulus of the second chip.

2. The method for measuring chip bonding stress according to claim 1, wherein the formation of the auxiliary pattern includes: Performing a deposition process to form a deposition layer on the first surface, such that the deposition layer contacts the first surface to form an interface; and Removing a part of the deposition layer by an etching process to form a patterned layer.

3. The method for measuring chip bonding stress according to claim 1, wherein the formation of the auxiliary pattern includes performing a focused ion beam deposition process on the first surface to form a deposited pattern layer.

4. The method for measuring chip bonding stress according to claim 1, wherein the auxiliary pattern includes a plurality of studs, the at least one gap space includes a plurality of gap spaces, and each of the plurality of gap spaces only surrounds one of the plurality of studs.

5. The method for measuring chip bonding stress according to claim 4, wherein the step of estimating the bonding stress includes: Obtaining a first elastic modulus E1 and a first thickness t1 of the first chip, a second elastic modulus E2 and a second thickness t2 of the second chip, an average height h of the plurality of studs, and an average radius R of the plurality of gap spaces; and Using the formula: To calculate the bonding stress γ.

6. The method for measuring chip bonding stress according to claim 1, wherein the auxiliary pattern includes a plurality of studs, the at least one gap space includes a plurality of gap spaces, and each of the plurality of gap spaces surrounds a plurality of the plurality of studs.

7. The method for measuring chip bonding stress according to claim 1, wherein the step of measuring the plurality of spatial dimensions includes ultrasonic measurement or optical measurement.

8. The method for measuring chip bonding stress according to claim 7, wherein the ultrasonic measurement includes using a confocal scanning acoustic microscope.

9. The method for measuring chip bonding stress according to claim 7, wherein the optical measurement includes performing laser triangulation detection.

10. The method for measuring the chip bonding stress as described in claim 5, wherein each of the plurality of studs has a bottom area between 0.002 square millimeters and 0.03 square millimeters; the average height h is between 50 micrometers and 100 micrometers; and each of the plurality of gap spaces has a projected area between 500 square millimeters and 1000 square millimeters.

11. The method for measuring the chip bonding stress as described in claim 1, further comprising a thermal annealing step for the bonded first chip and second chip before measuring the plurality of spatial dimensions.

Images