Semiconductor package and method of forming the same

Abstract

The semiconductor package includes a first package component, the first package component including: a first semiconductor die; a first encapsulant located around the first semiconductor die; and a first redistribution structure electrically connected to the first semiconductor die. The semiconductor package also includes a second package component bonded to the first package component, wherein the second package component includes: a second semiconductor die; a heat sink located between the first semiconductor die and the second package component; and a second encapsulant located between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat sink. Embodiments of the present application also relate to methods of forming semiconductor packages.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor packages and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement of the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, iterative reduction of the minimum component size can improve the integration density, so that more components can be integrated into a given area. With the growth of the demand for shrinking electronic devices, there has been a demand for smaller and more creative semiconductor die packaging technology. An example of such a packaging system is a stacked package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor package, comprising: a first packaging component, comprising: a first semiconductor die; a first encapsulant, located around the first semiconductor die; and a first redistribution structure, electrically connected to the first semiconductor die; a second packaging component, bonded to the first packaging component, wherein the second packaging component includes a second semiconductor die; a heat sink, located between the first semiconductor die and the second packaging component; and a second encapsulant, located between the first packaging component and the second packaging component, wherein the second encapsulant has a lower thermal conductivity than the heat sink.

[0004] Other embodiments of the present application provide a semiconductor package, comprising: a first packaging component, comprising: a first semiconductor die, including a first semiconductor substrate; a first encapsulant, located around the first semiconductor die; and a first redistribution structure, electrically connected to the semiconductor die; a second packaging component, bonded to the first packaging component, wherein the second packaging component comprises a second semiconductor die on a second semiconductor substrate, and wherein the first semiconductor substrate is directly attached to the second semiconductor substrate via a film; and a second encapsulant, located between the first packaging component and the second packaging component.

[0005] Some other embodiments of the present application provide a method for forming the semiconductor package, comprising: forming a redistribution structure, wherein the redistribution structure includes a first contact pad and a second contact pad in an insulating layer; forming a through hole on the second contact pad; bonding a first die to the redistribution structure, wherein the dielectric layer of the first die contacts the insulating layer, and wherein the third contact pad of the first die contacts the first contact pad; attaching a heat sink to a surface of the first die opposite to the redistribution structure; and bonding a packaging assembly including a second die to the through hole, wherein the heat sink is located between the first die and the packaging assembly. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present invention can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 A cross-sectional view of an integrated circuit die is shown in accordance with some embodiments.

[0008] Figures 2 to 13 Cross-sectional views of intermediate steps during a process for forming a semiconductor package are shown in accordance with some embodiments.

[0009] Fig.14A , Fig. 14B and Fig. 14C A cross-sectional view of a semiconductor package in accordance with some embodiments is shown.

[0010] Figures 15 to 19 Cross-sectional views of intermediate steps during a process for forming a semiconductor package are shown in accordance with some embodiments.

[0011] Fig. 20 A cross-sectional view of a semiconductor package in accordance with some embodiments is shown.

[0012] Figure 21 to Figure 29 Intermediate steps during a process for forming a package assembly and cross-sectional views of an implemented device stack are shown in accordance with some embodiments.

[0013] Fig.30 A cross-sectional view of a semiconductor package in accordance with some embodiments is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] According to some embodiments, the package includes a memory package assembly bonded to an integrated circuit (IC) package assembly including one or more IC dies. In some embodiments, a heat sink with relatively high thermal conductivity is disposed between the memory package assembly and the IC package assembly for improving heat dissipation. For example, a heat sink can be attached to the back side of the IC die, and the heat sink can extend from the IC die to the memory package. In other embodiments, the IC die can be directly attached to the memory package for improving heat dissipation. Therefore, in an embodiment semiconductor package, heat can be effectively dissipated from the IC die to the heat sink by a heat sink or by directly attaching the IC die to the memory package.

[0017] Figure 1A cross-sectional view of an integrated circuit die 50 according to some embodiments is shown. The integrated circuit die 50 will be packaged in a subsequent process to form an integrated circuit package. The integrated circuit die 50 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0018] An integrated circuit die 50 may be formed in a wafer that may include different device regions that are segmented in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 50 may be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 50 includes a semiconductor substrate 52 (such as doped or undoped silicon) or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer or gradient substrates. The semiconductor substrate 52 has an active surface sometimes referred to as a front side (e.g., at the Figure 1 The surface facing upward in the middle) and the passive surface sometimes called the back side (e.g., in Figure 1 downward facing surface).

[0019] Devices (represented by transistors) 54 may be formed at the front side of semiconductor substrate 52. Devices 54 may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interlayer dielectric (ILD) 56 is located over the front side of semiconductor substrate 52. ILD 56 surrounds and may cover device 54. ILD 56 may include one or more dielectric layers formed of materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc.

[0020] Conductive plug 58 extends through ILD 56 to electrically and physically couple device 54. For example, when device 54 is a transistor, conductive plug 58 can couple the gate and source / drain regions of the transistor. Conductive plug 58 can be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, etc. or a combination thereof. Interconnect structure 60 is located above ILD 56 and conductive plug 58. Interconnect structure 60 interconnects device 54 to form an integrated circuit. Interconnect structure 60 can be formed by, for example, a metallization pattern in a dielectric layer on ILD 56. The metallization pattern includes metal lines and vias formed in one or more low-k dielectric layers. The metallization pattern of interconnect structure 60 is electrically coupled to device 54 through conductive plug 58.

[0021] The integrated circuit die 50 also includes a pad 62, such as an aluminum pad, that is made to connect to the outside. The pad 62 is located on the active side of the integrated circuit die 50, such as in and / or on the interconnect structure 60. One or more passivation films 64 are located on the integrated circuit die 50, such as on portions of the interconnect structure 60 and the pad 62. An opening extends through the passivation film 64 to the pad 62. A die connector 66, such as a conductive column (e.g., formed of a metal such as copper), extends through the opening in the passivation film 64 and is physically and electrically coupled to the corresponding pad 62. The die connector 66 can be formed by, for example, plating. The die connector 66 electrically couples the corresponding integrated circuit of the integrated circuit die 50.

[0022] Optionally, a solder region (e.g., a solder ball or solder bump) may be provided on the pad 62. The solder ball may be used to perform a chip probe (CP) test on the integrated circuit die 50. The CP test may be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Thus, only the integrated circuit die 50 that is a KGD after subsequent processing is packaged, and the die that fails the CP test is not packaged. After testing, the solder region may be removed in a subsequent processing step.

[0023] The dielectric layer 68 may or may not be located on the active side of the integrated circuit die 50, such as on the passivation film 64 and the die connector 66. The dielectric layer 68 laterally seals the die connector 66, and the dielectric layer 68 is laterally coterminal with the integrated circuit die 50. Initially, the dielectric layer 68 may bury the die connector 66, so that the topmost surface of the dielectric layer 68 is located above the topmost surface of the die connector 66. In some embodiments where the solder region is disposed on the die connector 66, the dielectric layer 68 may also bury the solder region. Optionally, the solder region may be removed before the dielectric layer 68 is formed.

[0024] The dielectric layer 68 may be a polymer, such as PBO, polyimide, BCB, etc.; a nitride, such as silicon nitride, etc.; an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; etc. or a combination thereof. The dielectric layer 68 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. In some embodiments, during the formation of the integrated circuit die 50, the die connector 66 is exposed through the dielectric layer 68. In some embodiments, the die connector 66 remains buried and exposed during subsequent processes for packaging the integrated circuit die 50. Exposing the die connector 66 may remove any solder areas that may be present on the die connector 66.

[0025] In some embodiments, the integrated circuit die 50 is a stacked device including a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including a plurality of memory dies, such as a hybrid memory multidimensional cube (HMC) module, a high bandwidth memory (HBM) module, etc. In such an embodiment, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by through substrate vias (TSVs). Each of the semiconductor substrates 52 may (or may not) have an interconnect structure 60.

[0026] Figures 2 to 13 A cross-sectional view of manufacturing an integrated circuit package with improved heat dissipation according to some embodiments is shown. Figure 2 In the embodiment of the present invention, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, etc. The carrier substrate 102 may be a wafer, so that a plurality of packages may be formed simultaneously on the carrier substrate 102. For example, a first packaging region 100A and a second packaging region 100B are shown, and one or more integrated circuit dies 50 are packaged to form an integrated circuit package in each of the packaging regions 100A and 100B. The completed integrated circuit package may also be referred to as an integrated fan-out (InFO) package.

[0027] The release layer 104 may be formed of a polymer-based material that can be removed from the upper structure to be formed in a subsequent step together with the carrier substrate 102. In some embodiments, the release layer 104 is an epoxy-based thermal release material that loses its adhesiveness when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultraviolet (UV) glue that loses its adhesiveness when exposed to UV light. The release layer 104 may be dispensed as a liquid and cured, may be a laminated film laminated on the carrier substrate 102, or may be the like. The top surface of the release layer 104 may be horizontal and may have a high degree of planarity.

[0028] exist Figure 3, a front side redistribution structure 122 is formed on the release layer 104. The front side redistribution structure 122 includes dielectric layers 124, 128, 132 and 136; and metallization patterns 126, 130, 134 and 110 (including conductive pads 110A and 110B). The metallization patterns 126, 130 and 134 may also be referred to as redistribution layers or redistribution lines. The front side redistribution structure 122 is shown as an example having four metallization pattern layers. More or fewer dielectric layers and metallization patterns may be formed in the front side redistribution structure 122. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below may be repeated.

[0029] As an example of forming the redistribution structure 122, a dielectric layer 124 is deposited on the release layer 104. In some embodiments, the dielectric layer 124 is formed of a photosensitive material such as PBO, polyimide, BCB, etc. that can be patterned using a photolithography mask. The dielectric layer 124 can be formed by spin coating, lamination, CVD, etc., or a combination thereof.

[0030] Then a metallization pattern 126 is formed on the dielectric layer 124. As an example of forming the metallization pattern 126, a seed layer is formed above the dielectric layer 124. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD, etc. Then, a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 126. Patterning forms an opening through the photoresist to expose the seed layer. Then a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (such as electroplating, chemical plating, etc.). The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The combination of the conductive material and the lower portion of the seed layer forms the metallization pattern 126. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed by an acceptable ashing or stripping process, such as using an oxygen plasma, etc. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

[0031] A dielectric layer 128 may then be deposited over the metallization pattern 126 and the dielectric layer 124. The dielectric layer 128 may be formed in a manner similar to the dielectric layer 124 and may be formed of similar materials as the dielectric layer 124. An opening may then be patterned through the dielectric layer 124 to expose the underlying metallization pattern 126. The patterning may be formed by an acceptable process, such as by exposing the dielectric layer 124 to light when the dielectric layer 124 is a photosensitive material or by etching using, for example, anisotropic etching. If the dielectric layer 124 is a photosensitive material, the dielectric layer 124 may be developed after exposure.

[0032] The metallization pattern 130 is then formed. The metallization pattern 130 includes a portion located on and extending along the main surface of the dielectric layer 128 and a portion extending through the dielectric layer 128 to physically and electrically couple the metallization pattern 126. The metallization pattern 130 can be formed in a similar manner as the metallization pattern 126 and from a similar material as the metallization pattern 126. In some embodiments, the metallization pattern 130 has a different size than the metallization pattern 126. For example, the wires and / or vias of the metallization pattern 130 can be wider or thicker than the wires of the metallization pattern 126. In addition, the metallization pattern 130 can be formed with a larger pitch than the metallization pattern 126.

[0033] A dielectric layer 132 is deposited over the metallization pattern 130 and the dielectric layer 128 and may be patterned to expose the metallization pattern 130. The dielectric layer 132 may be formed and patterned in a similar manner as the dielectric layer 124 and may be formed of similar materials as the dielectric layer 124.

[0034] The metallization pattern 134 is then formed. The metallization pattern 134 includes a portion located on and extending along the main surface of the dielectric layer 132 and a portion extending through the dielectric layer 132 to physically and electrically couple the metallization pattern 130. The metallization pattern 134 can be formed in a similar manner to the metallization pattern 126 and from a similar material to the metallization pattern 126. In some embodiments, the metallization pattern 134 has a different size than the metallization patterns 126 and 130. For example, the wires and / or vias of the metallization pattern 134 can be wider or thicker than the wires and / or vias of the metallization patterns 126 and 130. In addition, the metallization pattern 134 can be formed with a larger pitch than the metallization pattern 130.

[0035] A dielectric layer 136 is deposited on the metallization pattern 134 and the dielectric layer 132, and may be patterned to expose the metallization pattern 134. The dielectric layer 136 may be formed in a similar manner to the dielectric layer 124 and may be formed of the same material as the dielectric layer 124.

[0036] A metallization pattern 110 is then formed in the opening of the dielectric layer 136. The metallization pattern 110 includes conductive pads 110A and 110B that extend through the dielectric layer 136 to physically and electrically couple to the underlying metallization patterns 134, 130, and 126.

[0037] like Figure 3 As further shown, a through hole 116 is formed on the conductive pad 110A of the metallization pattern 110. The through hole 116 can extend away from the topmost dielectric layer (e.g., dielectric layer 136) of the redistribution structure 122. As an example of forming the through hole 116, a seed layer (not shown) is formed above the front side redistribution structure 122 (e.g., on the dielectric layer 136 and the metallization pattern 110). In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In a specific embodiment, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD, etc. Optionally, in an embodiment where the through hole 116 is not wider than the conductive pad 110A below, the different seed layers can be omitted, and the conductive pad 110A can be used as the seed layer.

[0038] A photoresist is formed and patterned on the seed layer (if present) and the front side redistribution structure 122. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the through hole 116. Patterning forms an opening through the photoresist to expose the seed layer or the conductive pad 110A. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating (such as electroplating, chemical plating, etc.). The conductive material can include metals such as copper, titanium, tungsten, aluminum, etc. The portion of the photoresist and the seed layer on which the conductive material is not formed is removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer (if present) is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material forms a through hole 116.

[0039] exist Figure 4In the embodiment shown, an integrated circuit die 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B) are bonded in each of the package areas 100A and 100B. In the illustrated embodiment, a plurality of integrated circuit dies 50 are bonded adjacent to each other, including a first integrated circuit die 50A and a second integrated circuit die 50B in each of the first package area 100A and the second package area 100B. The first integrated circuit die 50A may be a logic device, such as a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), a microcontroller, etc. The second integrated circuit die 50B may be a memory device, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory multidimensional data set (HMC) module, a high bandwidth memory (HBM) module, etc. In some embodiments, the integrated circuit dies 50A and 50B may be dies of the same type, such as SoC dies. The first integrated circuit die 50A and the second integrated circuit die 50B may be formed in a process of the same technology node, or may be formed in processes of different technology nodes. For example, the first integrated circuit die 50A may be a higher process node than the second integrated circuit die 50B. The integrated circuit dies 50A and 50B may have different sizes (e.g., different heights and / or surface areas), or may have the same size (e.g., the same height and / or surface area). Although two integrated circuit dies 50 are shown as being placed in each of the package regions, fewer (e.g., one) or more numbers of integrated circuit dies may be disposed in each of the package regions on the substrate 102.

[0040] The die 50 is arranged to face downward so that the front side of the die 50 faces the conductive pad 110B and the back side of the die 50 faces away from the conductive pad 110B. In some embodiments, the integrated circuit die 50 is bonded to the conductive pad 110B of the metallization pattern 110 in a hybrid bonding configuration. For example, the passivation layer 68 of the die 50 can be directly bonded to the dielectric layer 136, and the contact pad 66 of the die 50 can be directly bonded to the conductive pad 110B. In an embodiment, the bonding between the passivation layer 68 and the dielectric layer 136 can be an oxide-to-oxide bonding, etc. The hybrid bonding process also directly bonds the contact pad 66 of the die 50 to the conductive pad 110B by direct metal-to-metal bonding. Therefore, the electrical connection between the die 50 and the front side redistribution structure 122 is provided by the physical connection of the contact pad 66 to the contact pad 110B.

[0041] As an example, the hybrid bonding process can begin by applying a surface treatment to the dielectric layer 136 of the front side redistribution structure 122 and / or the passivation layer 68 of the die 50. The surface treatment may include a plasma treatment. The plasma treatment may be implemented in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinsing with deionized water, etc.) that may be applied to the dielectric layer 136 and / or the passivation layer 68 of the die 50. Then, the hybrid bonding process may continue to align the contact pad 66 with the contact pad 110B. Next, the hybrid bonding includes a pre-bonding step during which the contact pad 66 is brought into physical contact with the contact pad 110B. The pre-bonding may be implemented at room temperature (e.g., between about 21° C. and about 25° C.). The hybrid bonding process continues with an anneal, for example, at a temperature between about 150° C. and about 400° C. for a duration between about 0.5 hours and about 3 hours, so that the metal (e.g., copper) in contact pad 66 and the metal (e.g., copper) of contact pad 110B interdiffuse with each other, thereby forming a direct metal-to-metal bond. The anneal may further form a covalent bond between passivation layer 68 and dielectric layer 136. In other embodiments, other bonding parameters and / or methods (e.g., solder bonding) are also possible.

[0042] like Figure 4 As further shown, an encapsulant 120 is formed on and around the various components. After formation, the encapsulant 120 seals the through-holes 116 and the integrated circuit die 50. The encapsulant 120 may be a molding compound, an epoxy resin, etc. The encapsulant 120 may be applied by compression molding, transfer molding, etc. and may be formed over the carrier substrate 102 so that the through-holes 116 and / or the integrated circuit die 50 are buried or covered. The encapsulant 120 is further formed in the gap areas between the integrated circuit dies 50. The encapsulant 120 may be applied in a liquid or semi-liquid form and then subsequently cured.

[0043] exist Figure 5 In the embodiment of the present invention, a planarization process is performed on the encapsulant 120 to expose the via 116 and the die 50. The planarization process may also remove the material of the via 116. After the planarization process, the top surfaces of the via 116, the die 50, and the encapsulant 120 are substantially coplanar within process variations. The planarization process may be, for example, a chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, for example, if the via 116 and the die 50 are already exposed, the planarization may be omitted.

[0044] exist Figure 6, a heat sink 170 is attached to the die 50 by a film 168. The heat sink 170 may be formed of a conductive material having a relatively high thermal conductivity, such as at least about 149 W / m*K or at least about 380 W / m*K. For example, in some embodiments, the heat sink 170 is made of copper, diamond, boron arsenide, silver, silicon, etc. It has been observed that when the heat sink 170 is formed of a material having a thermal conductivity of less than about 380 W / m*K, insufficient heat dissipation is achieved in the resulting package. The heat sink 170 may be attached to the back side of the substrate 52 of the die 50 using a film 168. The back side of the substrate 52 may refer to the side opposite to the surface on which the active devices are formed. The film 168 may be a high-k polymer (e.g., a high-k DAF), a metal (e.g., In, Sn, etc.) attached by a reflow process, a thermal interface material (TIM), a solder paste, etc. In the illustrated embodiment, each of the heat spreaders 170 has the same width as a corresponding one of the die 50 and is coterminal with a corresponding one of the die 50. In other embodiments, the heat spreaders 170 may be wider or narrower than the die 50, and / or the sidewalls of the heat spreaders 170 may be offset from the die 150 (see, e.g., FIG. 14A to FIG. 14C ). In addition, multiple physically separate heat sinks 170 may be attached to each of the dies 50 (see, e.g. FIG. 14A to FIG. 14C ).

[0045] like Figure 6 As further shown, a metallization pattern 190 may be formed on the via 116. The metallization pattern 190 may be formed using similar processes and similar materials as described above with respect to the contact pad 110B. In various embodiments, the metallization pattern 190 may be formed before or after the heat sink 170 is attached to the die 50.

[0046] Thus, a first package assembly 100 is formed in each of the package regions 100A and 100B. The first package assembly 100 includes an integrated circuit die 50, an encapsulant 120, vias 116, a front side redistribution structure 122, and a metallization pattern 190. A heat spreader 170 is formed on the integrated circuit die 50 of the first package assembly 100.

[0047] exist Figure 7, the second package component 200 is coupled to the first package component 100 through the conductive connector 152. One of the second package components 200 is coupled in each of the package regions 100A and 100B to form an integrated circuit device stack on each of the package regions. In some embodiments, the second package component 200 can physically contact the heat sink 170. For example, the heat sink 170 can span the distance between the tube core 50 and the second package component 200. In this way, the heat sink 170 can provide a heat dissipation path from the tube core 50 to the second package component 200. In other embodiments, an intermediate layer can be provided between the heat sink 170 and the second package component 200. For example, a thermally conductive film (not explicitly shown) can be used as a buffer layer between each of the heat sinks 170 and the corresponding second package component 200. In some embodiments, the thermally conductive film can include a high-k polymer (e.g., high-kDAF), a metal (e.g., In, Sn, etc.) attached by a reflow process, a TIM, a solder paste, etc.

[0048] The second package assembly 200 includes, for example, a substrate 202 and one or more stacked dies 210 (e.g., 210A and 210B) coupled to the substrate 202. Although a set of stacked dies 210 (210A and 210B) is shown, in other embodiments, a plurality of stacked dies 210 (each having one or more stacked dies) may be arranged to be coupled side by side to the same surface of the substrate 202. The substrate 202 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these, and the like may also be used. In addition, the substrate 202 may be a silicon on insulator (SOI) substrate. Typically, an SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. In an optional embodiment, the substrate 202 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin such as FR4. Optional materials for the core material include bismaleimide triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. Build-up films such as Ajinomoto Build-up Film (ABF) or other laminates can be used for substrate 202.

[0049] Substrate 202 may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, etc. may be used to generate the structural and functional requirements for the design of second package assembly 200. The devices may be formed using any suitable method.

[0050] The substrate 202 may also include metallization layers (not shown) and conductive vias 208. Metallization layers may be formed over active and passive devices to connect the various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric materials (e.g., low-k dielectric materials) and conductive materials (e.g., copper), with vias interconnecting the conductive material layers, and may be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). In some embodiments, the substrate 202 is substantially free of active and passive devices.

[0051] The substrate 202 may have a bonding pad 204 on a first side of the substrate 202 to couple to the stacked die 210, and may have a bonding pad 206 on a second side of the substrate 202, the second side being opposite to the first side of the substrate 202 to couple to the conductive connector 152. In some embodiments, the bonding pads 204 and 206 are formed by forming grooves (not shown) in a dielectric layer (not shown) on the first side and the second side of the substrate 202. The grooves may be formed to allow the bonding pads 204 and 206 to be embedded in the dielectric layer. In other embodiments, the grooves are omitted because the bonding pads 204 and 206 may be formed on the dielectric layer. In some embodiments, the bonding pads 204 and 206 include a thin seed layer (not shown) made of copper, titanium, nickel, gold, palladium, etc., or a combination thereof. The conductive material of the bonding pads 204 and 206 may be deposited above the thin seed layer. The conductive material may be formed by electrochemical plating process, chemical plating process, CVD, atomic layer deposition (ALD), PVD, etc. or a combination thereof. In an embodiment, the conductive material of the bonding pads 204 and 206 is copper, tungsten, aluminum, silver, gold, etc. or a combination thereof.

[0052] In some embodiments, the bonding pads 204 and the bonding pads 206 are UBMs including three conductive material layers, such as a titanium layer, a copper layer, and a nickel layer. Other arrangements of materials and layers, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / gold, may be used to form the pads 204 and 206. Any suitable material or material layer that may be used for the bonding pads 204 and 206 is fully intended to be included within the scope of the present application. In some embodiments, the conductive vias 208 extend through the substrate 202 and couple at least one of the bonding pads 204 to at least one of the bonding pads 206.

[0053] In the illustrated embodiment, the stacked die 210 is coupled to the substrate 202 via wire bonds 212, but other connections, such as conductive bumps, may be used. In an embodiment, the stacked die 210 is a stacked memory die. For example, the stacked die 210 may be a memory die, such as a low power (LP) double data rate (DDR) memory module, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or a similar memory module.

[0054] The stacked die 210 and the wire bonds 212 may be sealed by a molding material 214. For example, the molding material 214 may be molded on the stacked die 210 and the wire bonds 212, for example, using compression molding. In some embodiments, the molding material 214 is a molding compound, a polymer, an epoxy resin, a silicon oxide filling material, etc., or a combination thereof. A curing process may be performed to cure the molding material 214; the curing process may be thermal curing, UV curing, etc., or a combination thereof.

[0055] In some embodiments, the stacked die 210 and wire bonds 212 are buried in molding material 214 , and after curing the molding material 214 , a planarization step such as grinding is performed to remove excess portions of the molding material 214 and provide a substantially planar surface for the second package assembly 200 .

[0056] After forming the second package assembly 200, the second package assembly 200 is mechanically and electrically bonded to the first package assembly 100 through the conductive connectors 152, the bonding pads 206, and the metallization pattern 190. In some embodiments, the stacked die 210 can be coupled to the integrated circuit dies 50A and 50B through wire bonds 212, the bonding pads 204 and 206, the conductive vias 208, the conductive connectors 152, the metallization pattern 190, the vias 116, and the front side redistribution structure 122.

[0057] In some embodiments, a solder resist (not shown) is formed on the side of the substrate 202 opposite the stacked die 210. The conductive connectors 152 may be disposed in openings in the solder resist to electrically and mechanically couple to conductive features (e.g., bonding pads 206) in the substrate 202. The solder resist may be used to protect areas of the substrate 202 from external damage.

[0058] In some embodiments, the conductive connectors 152 are formed with epoxy flux (not shown) thereon and then at least some epoxy portions of the epoxy flux remaining after the second package assembly 200 is attached to the first package assembly 100 are reflowed.

[0059] exist Figure 8In the embodiment of the present invention, an encapsulant 250 is formed between the first package component 100 and the second package component 200 around the conductive connector 152 and the heat sink 170. The encapsulant 250 may be further formed around the second package component 200, and the encapsulant 250 may be formed around the first package component 100 (not explicitly shown). The encapsulant 250 may be a molding compound, an epoxy resin, a molded underfill, etc. In some embodiments, the encapsulant 250 may have a lower thermal conductivity than the heat sink 170. For example, the encapsulant 250 may have a thermal conductivity of less than about 10 W / m*K. Therefore, the heat sink 170 allows for improved heat dissipation from the integrated circuit die 50 to the second package component 200 through the encapsulant 250. For example, by including the heat sink 170 passing through the encapsulant 250, a reduction in operating temperature of about 22% or more has been observed.

[0060] The sealant 250 may be applied by compression molding, transfer molding, etc. and may be formed over the second package component 200 until the second package component 200 is buried or covered. The sealant 250 is further formed in the gap region between the second package component 200 and the first package component 100 below. The sealant 250 may be applied in a liquid or semi-liquid form and then subsequently cured. After the sealant 250 is formed, a planarization process (e.g., CMP, grinding, etc.) may be applied to the sealant 250 until the second package component 200 is exposed. After the planarization process, the top surfaces of the second package component 200 and the sealant 250 may be flush.

[0061] exist Fig. 9 , the frame 252 is attached to the second package component 200. For example, the frame 252 is attached to a surface of the second package component 200 opposite to the first package component 100.

[0062] exist Fig.10 In the embodiment, carrier substrate peeling is performed to separate (or "peel") carrier substrate 102 from front-side redistribution structure 122 (e.g., dielectric layer 124). According to some embodiments, peeling includes projecting light, such as laser or UV light, onto release layer 104, so that release layer 104 decomposes under the heat of the light and carrier substrate 102 can be removed. The structure is then turned over.

[0063] exist Fig.11In the embodiment of the present invention, a UBM 138 and a conductive connector 150 for external connection to the front side redistribution structure 122 are formed. The UBM 138 has a bump portion located on and extending along the main surface of the dielectric layer 124, and has a via portion extending through the dielectric layer 124 to physically and electrically couple the metallization pattern 126. Therefore, the UBM 138 is electrically coupled to the via 116 and the integrated circuit die 50. The UBM 138 can be formed of the same material and in the same process as the metallization pattern 126. In some embodiments, the UBM 138 has a different size than the metallization patterns 110, 126, 130, and 134.

[0064] exist Fig.11 In the embodiment of the present invention, a conductive connector 150 is formed on the UBM 138. The conductive connector 150 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium immersion gold technology (ENEPIG), etc. The conductive connector 150 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 150 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, the conductive connector 150 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal cap layer is formed on the top of the metal column. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by a plating process.

[0065] exist Fig.12 In the embodiment, the singulation process is performed by sawing along a scribe line region between, for example, the first package region 100A and the second package region 100B. The sawing separates the first package region 100A from the second package region 100B. The resulting, singulated device stack comes from one of the first package region 100A or the second package region 100B. In some embodiments, the singulation process is performed after the second package component 200 is coupled to the first package component 100. In other embodiments (not shown), the singulation process is performed before the second package component 200 is coupled to the first package component 100.

[0066] exist Fig.13, each segmented first package assembly 100 can then be mounted to a package substrate 300 using a conductive connector 150. The package substrate 300 includes a substrate core 302 and a bonding pad 304 above the substrate core 302. The substrate core 302 can be made of a semiconductor material such as silicon, germanium, diamond, etc. Optionally, composite materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations of these, etc. can also be used. In addition, the substrate core 302 can be an SOI substrate. Typically, the SOI substrate includes a semiconductor material layer such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an optional embodiment, the substrate core 302 is based on an insulating core, such as a glass fiber reinforced resin core. An exemplary core material is a glass fiber resin, such as FR4. Optional materials for the core material include bismaleimide triazine (BT) resin, or alternatively, other PCB materials or films. A build-up film such as ABF or other laminate may be used for the substrate core 302 .

[0067] The substrate core 302 may include active and passive devices (not shown). A wide variety of devices such as transistors, capacitors, resistors, combinations of these, etc. may be used to generate the structural and functional requirements for the design of the device stack. The devices may be formed using any suitable method.

[0068] The substrate core 302 may also include metallization layers and vias (not shown), to which the bonding pads 304 are physically and / or electrically coupled. Metallization layers may be formed over the active and passive devices to connect the various devices to form functional circuits. The metallization layers may be formed of alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), with vias interconnecting the conductive material layers, and may be formed by any suitable process (such as deposition, damascene, dual damascene, etc.). In some embodiments, the substrate core 302 is substantially free of active and passive devices.

[0069] In some embodiments, the conductive connectors 150 are reflowed to attach the first package component 100 to the bonding pads 304. The conductive connectors 150 electrically and / or physically couple the package substrate 300 including the metallization layer in the substrate core 302 to the first package component 100. In some embodiments, a solder resist 306 is formed on the substrate core 302. The conductive connectors 150 can be disposed in openings in the solder resist 306 to electrically and mechanically couple to the bonding pads 304. The solder resist 306 can be used to protect areas of the substrate 202 from external damage.

[0070] The conductive connector 150 is formed with an epoxy flux (not shown) thereon, and then at least some epoxy portions of the epoxy flux remaining after the first package component 100 is attached to the package substrate 300 are reflowed. This remaining epoxy portion can be used as an underfill to reduce stress and protect the joints created by the reflowed conductive connector 150. In some embodiments, an underfill 308 surrounding the conductive connector 150 can be formed between the first package component 100 and the package substrate 300. The underfill 308 can be formed by a capillary flow process after the first package component 100 is attached, or can be formed by a suitable deposition method before the first package component 100 is attached.

[0071] In some embodiments, passive devices (e.g., surface mount devices (SMDs), not shown) may also be attached to the first package component 100 (e.g., UBM 138) or to the package substrate 300 (e.g., to bonding pads 304). For example, the passive device may be bonded to the same surface of the first package component 100 or the package substrate 300 as the conductive connector 150. The passive device may be attached to the package component 100 before mounting the first package component 100 on the package substrate 300, or may be attached to the package substrate 300 before or after mounting the first package component 100 on the package substrate 300.

[0072] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used together with a test method for intermediate verification incorporating known good dies to increase yield and reduce costs.

[0073] Thus, a semiconductor package 400 including the first package assembly 100 bonded to the second package assembly 200 and the third package assembly 300 is formed. One or more heat sinks 170 are disposed between the first package assembly 100 and the second package assembly 200 to improve heat dissipation from the die 50 of the first package assembly 100 to the second package assembly 200. The heat sink 170 may have a relatively high thermal conductivity, for example, higher than the thermal conductivity of the sealant 250 between the first package assembly 100 and the second package assembly 200. Thus, improved heat dissipation and device performance may be achieved in the semiconductor package 400. For example, by including the heat sink 170, the operating temperature in the semiconductor package 400 may be reduced by 22% or more.

[0074] Fig.14A , Fig. 14B and Fig. 14C Cross-sectional views of semiconductor packages 420, 430, and 440 are shown, respectively. Each of semiconductor packages 420, 430, and 440 may be similar to semiconductor package 400 and similar to each other, where the same reference numerals indicate the same elements formed using the same process. However, the second package assembly 200 in each of semiconductor packages 420, 430, and 440 may further include a heat dissipation cover 254 attached to the substrate 202 of the second package assembly 200. The heat dissipation cover 254 may be made of a conductive material having a relatively high thermal conductivity, such as copper, etc., and the heat dissipation cover 254 may be attached to the top surface of the substrate 202 by an adhesive, a thermal interface material (TIM), etc. The substrate 202 thermally connects the heat sink 170 to the heat dissipation cover 254. Therefore, heat can be dissipated from the die 50 to the heat dissipation cover 254 through the heat sink 170 and the substrate 202. Furthermore, in packages 420 , 430 , and 440 , the sealant 250 may be formed only between the first package component 100 and the second package component 200 , and the sealant 250 may not extend along the sidewall of the second package component 200 .

[0075] Fig.14A The package 420 of FIG. 4 shows an embodiment in which the heat spreader 170 has the same width as the die 50 and is coterminal with the die 50 . In addition, the heat spreader 170 in the package 320 may contact the substrate 202 , and the heat spreader 170 may span the entire distance between the die 50 and the substrate 202 .

[0076] Fig. 14B Package 430 of FIG. 4 shows an embodiment in which heat spreader 170 is narrower than and offset from die 50, and multiple heat spreaders 170 are attached to each of die 50. For example, in package 430, heat spreader 170 may overlap the sidewalls of die 50. Additionally, heat spreader 170 in package 330 may contact substrate 202, and heat spreader 170 may span the entire distance between die 50 and substrate 202.

[0077] Fig. 14C The package 340 of FIG. 3 shows an embodiment in which the heat sink 170 has the same width as the die 50 and ends at the same end as the die 50. In addition, the heat sink 170 in the package 320 may be physically separated from the substrate 202 by the encapsulant 250. For example, the heat sink 170 may not be attached to the package 200, and the encapsulant 250 may be formed between the top surface of the heat sink 170 and the bottom surface of the substrate 202. Although the heat sink 170 does not contact the substrate 202, including the heat sink 170 in the encapsulant 250 still improves the heat dissipation between the first package assembly 100 and the second package assembly 200.

[0078] Figures 15 to 19FIG. 4 shows a cross-sectional view of a semiconductor package 450 formed according to some other embodiments. The package 450 may be similar to Fig.12 4 , wherein like reference numerals denote like elements formed by like processes. Fig.15 Shown above Figure 4 A cross-sectional view of a similar process stage but before forming the sealant 120. For example, Fig.15 In the embodiment, a front side redistribution structure 122 is formed on a carrier substrate 102, a through hole 116 is formed on a contact pad 110A of the front side redistribution structure 122, and a die 50 is bonded to a contact pad 110B of the front side redistribution structure 122. Fig.15 In the structure of FIG. 1 , the die 50 may be taller than the via 116 and extend higher.

[0079] exist Fig.16 In the embodiment of the present invention, an encapsulant 120 is formed on and around the various components. After formation, the encapsulant 120 extends along the sidewalls of the through-hole 116 and the integrated circuit die 50. The encapsulant 120 can be a molding compound, an epoxy resin, etc. The encapsulant 120 can be applied by compression molding, transfer molding, etc. and can be formed over the carrier substrate 102 so that the through-hole 116 and / or the integrated circuit die 50 are disposed in the encapsulant 120. The encapsulant 120 can be applied in a liquid or semi-liquid form and then subsequently cured.

[0080] The encapsulant 120 is formed in the gap region between the integrated circuit dies 50. However, the encapsulant 120 may be deposited so as not to cover the top surface of the via 116. For example, after depositing the encapsulant 120, the top surface of the via 116 may remain exposed without applying any patterning or planarization process to the encapsulant 120. Alternatively, the encapsulant 120 may be deposited so as to bury the via 116, and an etch-back process may be applied to expose the top surface of the via 116. In such an embodiment, the etch-back process may be isotropic.

[0081] In some embodiments, encapsulant 120 may further include fillets along at least an upper portion of the sidewalls of die 50. Fig.16 The top surface of the encapsulant 120 is shown to be at the same level as the top surface of the through-hole 116 , but in other embodiments, the encapsulant 120 may also have a top surface lower than the top surface of the through-hole 116 .

[0082] exist Fig.17In the embodiment, the second package component 200 is coupled to the first package component 100. One of the second package components 200 is coupled in each of the package regions 100A and 100B to form an integrated circuit device stack in each region of the first package component 100. For example, the second package component 200 can be directly bonded to the through hole 116 by reflowing the conductive connector 152. The second package component 200 can be similar to the above in Figure 7 , and additional details of the second packaging assembly 200 are omitted for brevity.

[0083] In package 450, die 50 may be directly attached to second package component 200 via film 154. Film 154 may be a high-k polymer (e.g., high-k DAF), a metal (e.g., In, Sn, etc.), a TIM, a solder paste, etc. For example, substrate 52 of die 50 may be attached to substrate 202 of second package component 200 via film 154. Because substrate 52 includes a semiconductor material (e.g., having a relatively high thermal conductivity), heat dissipation may be facilitated by placing it near second package component 200. Heat dissipation may be further improved by using a material having a relatively high thermal conductivity (e.g., film 154) as an interface material between die 50 and substrate 202. For example, it has been observed that by directly attaching die 50 to second package component 200 using a material having a relatively high thermal conductivity, the operating temperature in the completed package may be reduced by at least 18%.

[0084] exist Fig.18 In the embodiment, a sealant 250 is formed around the conductive connection 152 between the first package component 100 and the second package component 200. The sealant 250 may be formed in the same manner as in the embodiment shown in FIG. Figure 8 In a similar manner as described in Figure 8 The encapsulant 250 may be formed of a similar material as described in . The encapsulant 250 may have a lower thermal conductivity than the substrate 52 of the die 50. Because the die 50 is directly attached to the second package component 200 through the film 154, the encapsulant 250 may not extend directly perpendicularly to the top surface of the die 50 between the top surface of the die 50 and the bottom surface of the substrate 202. Therefore, heat dissipation may be improved.

[0085] exist Fig.19 In the above, you can implement something similar to Figures 9 to 13The additional processing of the processing described above is performed to separate and bond the first package component 100 and the second package component 200 to the third package component 300. Thus, a semiconductor package 450 including the first package component 100 bonded to the second package component 200 and the third package component 300 is formed. The substrate 52 of the die 50 of the first package component 100 is directly attached to the substrate 202 of the second package component 200 to improve heat dissipation from the die 50 of the first package component 100 to the second package component 200. The substrate 52 of the die 50 can have a relatively high thermal conductivity, for example, higher than the thermal conductivity of the encapsulant 250 between the first package component 100 and the second package component 200. Thus, improved heat dissipation and device performance can be achieved in the semiconductor package 450. For example, the operating temperature in the semiconductor package 450 can be reduced by 18%.

[0086] Fig. 20 A cross-sectional view of a semiconductor package 460 is shown. The semiconductor package 460 may be similar to the semiconductor package 450, where the same reference numerals indicate the same elements formed using the same process. However, the second package component 200 in the semiconductor package 460 may further include a heat dissipation cover 254 attached to the substrate 202 of the second package component 200. The heat dissipation cover 254 may be made of a conductive material with high thermal conductivity, such as copper, etc., and the heat dissipation cover 254 may be attached to the top surface of the substrate 202 by an adhesive, a thermal interface material (TIM), etc. The substrate 202 thermally connects the die 50 to the heat dissipation cover 254. In addition, in the semiconductor package 460, the sealant 250 may be formed only between the first package component 100 and the second package component 200, and the sealant 250 may not extend along the sidewalls of the second package component 200.

[0087] Figure 21 to Figure 29 FIG. 4 shows a cross-sectional view of forming a semiconductor package 470 according to some other embodiments. The package 470 may be similar to Fig.12 4 , wherein like reference numerals denote like elements formed by like processes.

[0088] exist Fig.21In the embodiment, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. A backside redistribution structure 106 may be formed on the release layer 104. In the embodiment shown, the backside redistribution structure 106 includes a dielectric layer 108, a metallization pattern 111 (sometimes referred to as a redistribution layer or a redistribution line), a metallization pattern 110, and a dielectric layer 112. The metallization patterns 110 and 111 may be formed by a similar process and similar materials as the metallization pattern 136 described above. The backside redistribution structure 106 is optional. In some embodiments, a dielectric layer without a metallization pattern is formed on the release layer 104 instead of the backside redistribution structure 106.

[0089] exist Fig. 22 In the embodiment of the present invention, the opening 113 is patterned through the backside redistribution structure 106. For example, a combination of photolithography and etching may be used to pattern the opening 113. The opening may expose the release layer 104.

[0090] exist Fig.23 In the embodiment of the present invention, a heat sink 170 is formed in the opening 113. The heat sink 170 can be formed, for example, in a similar manner to the metallization patterns 110 and 111. The heat sink 170 may include a conductive material having a relatively high thermal conductivity, such as copper, etc. In some embodiments, the heat sink 170 may have a thermal conductivity of at least about 380 W / m*K. In some embodiments, the heat sink 170 may be formed to cover the top surface of the dielectric layer 112, and a planarization process may be used to remove excess portions of the heat sink 170 and expose the metallization pattern 110.

[0091] exist Fig.24 In the embodiment, a via 116 is formed on the metallization pattern 110. The via 116 may extend away from the topmost dielectric layer (eg, dielectric layer 112) of the backside redistribution structure 106. The via 116 may be formed using the same dielectric layer as above. Figure 3 The same process and similar materials as described in are used to form.

[0092] exist Fig.24, the integrated circuit die 50 (e.g., the first integrated circuit die 50A and the second integrated circuit die 50B) are bonded to the heat sink 170 by the adhesive 118. The desired type and number of integrated circuit dies 50 are bonded in each of the package areas 100A and 100B. In the illustrated embodiment, a plurality of integrated circuit dies 50 are bonded adjacent to each other, including the first integrated circuit die 50A and the second integrated circuit die 50B in each of the first package area 100A and the second package area 100B. The first integrated circuit die 50A may be a logic device, such as a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SoC), a microcontroller, etc. The second integrated circuit die 50B may be a memory device, such as a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory multidimensional cube (HMC) module, a high bandwidth memory (HBM) module, etc. In some embodiments, the integrated circuit dies 50A and 50B may be the same type of die, such as a SoC die. The first integrated circuit die 50A and the second integrated circuit die 50B can be formed in a process of the same technology node, or can be formed in processes of different technology nodes. For example, the first integrated circuit die 50A can be a process node that is more advanced than the second integrated circuit die 50B. The integrated circuit dies 50A and 50B can have different sizes (e.g., different heights and / or surface areas), or can have the same size (e.g., the same height and / or surface area). The spacing available for the through-holes 116 in the first package area 100A and the second package area 100B may be limited, particularly when the integrated circuit die 50 includes a device with a large footprint (such as a SoC). When the first package area 100A and the second package area 100B have limited spacing available for the through-holes 116, the use of the backside redistribution structure 106 allows for an improved interconnection arrangement.

[0093] Adhesive 118 is located on the back side of the integrated circuit die 50 and bonds the integrated circuit die 50 to the heat sink 170. The adhesive 118 may be a high-k polymer (e.g., high-k DAF), a metal attached by a reflow process (e.g., In, Sn, etc.), a thermal interface material (TIM), a solder paste, etc. The adhesive 118 may be applied to the back side of the integrated circuit die 50, or may be applied to the upper surface of the backside redistribution structure 106. For example, the adhesive 118 may be applied to the back side of the integrated circuit die 50 before singulation to separate the integrated circuit die 50. The adhesive 118 may have a relatively high thermal conductivity to facilitate heat dissipation from the die 50 to the heat sink 170.

[0094] exist Fig.25In the embodiment of the present invention, an encapsulant 120 is formed on and around the various components. After being formed, the encapsulant 120 seals the through-holes 116 and the integrated circuit die 50. The encapsulant 120 may be a molding compound, an epoxy resin, etc. The encapsulant 120 may be applied by compression molding, transfer molding, etc. and may be formed over the carrier substrate 102 so that the through-holes 116 and / or the integrated circuit die 50 are buried or covered. The encapsulant 120 is further formed in the gap areas between the integrated circuit dies 50. The encapsulant 120 may be applied in a liquid or semi-liquid form and then subsequently cured.

[0095] A planarization process is performed on the encapsulant 120 to expose the vias 116 and the die connections 66. The planarization process may also remove material of the vias 116, the dielectric layer 68, and / or the die connections 66 until the die connections 66 and the vias 116 are exposed. After the planarization process, the top surfaces of the vias 116, the die connections 66, the dielectric layer 68, and the encapsulant 120 are substantially coplanar within process variations. The planarization process may be, for example, a chemical mechanical polishing (CMP), a grinding process, etc. In some embodiments, for example, if the vias 116 and / or the die connections 66 are already exposed, the planarization may be omitted.

[0096] exist Fig.26 In the embodiment, a front side redistribution structure 122 is formed over the encapsulant 120, the vias 116, and the integrated circuit die 50. The front side redistribution structure 122 includes dielectric layers 124, 128, 132, and 136; and metallization patterns 126, 130, and 134. The metallization patterns may also be referred to as redistribution layers or redistribution lines. The front side redistribution structure 122 is shown as an example having three metallization pattern layers. More or fewer dielectric layers and metallization patterns may be formed in the front side redistribution structure 122. The front side redistribution structure 122 may be used. Figure 3 The invention is formed by the processes and / or materials described in.

[0097] exist Fig. 27 1, UBM 138 and conductive connector 150 are formed for external connection to front side redistribution structure 122. UBM 138 has a bump portion located on and extending along the main surface of dielectric layer 136, and has a via portion extending through dielectric layer 136 to physically and electrically couple metallization pattern 134. Thus, UBM 138 is electrically coupled to via 116 and integrated circuit die 50. UBM 138 can be formed of the same material as metallization pattern 126. In some embodiments, UBM 138 has a different size than metallization patterns 126, 130, and 134.

[0098] Conductive connector 150 is formed on UBM 138. Conductive connector 150 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium immersion gold technology (ENEPIG), etc. Conductive connector 150 can include conductive materials, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, conductive connector 150 is formed by first forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, conductive connector 150 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal cap layer is formed on the top of the metal column. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process. Thus, a first package assembly 100 including a backside redistribution structure 106, a heat sink 170, a through hole 116, a die 50, an encapsulant 120, a frontside redistribution structure 122, a UBM 138, and a conductive connector 150 is formed.

[0099] exist Fig.28 In the embodiment of the present invention, carrier substrate peeling is performed to separate (or "peel off") carrier substrate 102 from backside redistribution structure 106 (e.g., dielectric layer 108). According to some embodiments, peeling includes projecting light such as laser or UV light onto release layer 104, so that release layer 104 decomposes under the heat of the light, and carrier substrate 102 can be removed.

[0100] Further in Fig.28 In the embodiment of the present invention, an opening 115 is formed through the dielectric layer 108 to expose a portion of the metallization pattern 111. The opening 115 may be formed, for example, using laser drilling, etching, or the like.

[0101] Subsequently, the second package assembly 200 is formed in the same manner as described above. Figure 7 The first package assembly 100 is attached to the second package assembly 200 in a similar manner as described above. For example, the conductive connector extends through the opening in the dielectric layer 108 to electrically connect the metallization pattern 111 of the first package assembly 100 to the second package assembly 200. The heat sink 170 can be disposed between the die 50 of the first package 100 and the substrate 202 of the second package assembly 200 to improve heat dissipation from the die 50 to the second package assembly 200.

[0102] Additional processing may be performed (e.g., similar to Figure 8 , Fig.12 and Fig.13described) to arrive at Fig.29 The package 470 may include a heat sink 170 formed within the backside redistribution structure 106 of the first package assembly 100. By placing the heat sink 170 between the die 50 and the second package assembly 200, heat dissipation and device performance may be improved.

[0103] Fig.30 A cross-sectional view of a semiconductor package 480 according to some optional embodiments is shown. Semiconductor package 480 is similar to semiconductor package 400, where the same reference numerals indicate the same elements formed by the same process. However, the dies 50 in semiconductor package 480 are directly bonded to each other in a stacked configuration. In some embodiments, die 50A can be directly bonded to die 50B by the hybrid bonding process described above. For example, the passivation layer 68A of die 50A can be directly bonded to the passivation layer 68B of die 50B using dielectric to dielectric bonding, and the die connector 66A of die 50A can be directly bonded to the die connector 66B of die 50B using metal to metal bonding. In addition, die 50B may include a substrate through-hole (TSV) 70 extending through the substrate 52 of die 50B. For example, TSV 70 can be directly bonded to the contact pad 110B of the front-side redistribution layer 122 using a hybrid bonding configuration.

[0104] The die 50A and 50B are thermally connected to the heat sink 170 in the package 480. For example, the heat sink 170 can be directly attached to the substrate 52A of the die 50A through the film 168. In addition, a thermal via 172 can be formed on the conductive connector 66B of the die 50B, and the thermal via 172 can thermally connect the die 50B to the heat sink 170. In some embodiments, the thermal via 172 is made of a similar material to the through hole 116 and is formed with a similar process. In some embodiments, the thermal via 172 can be a pseudo through hole that is not electrically connected to any active device in the die 50A and 50B. Therefore, heat dissipation can be achieved in the package 480 by the heat sink 170 that is thermally connected to the die 50A and 50B. Heat can also be dissipated from the die 50B through the front side redistribution structure 122.

[0105] According to some embodiments, the package includes a memory package assembly bonded to an integrated circuit (IC) package assembly including one or more IC dies. In some embodiments, a heat sink with relatively high thermal conductivity is disposed between the memory package assembly and the IC package assembly for improving heat dissipation. For example, a heat sink can be attached to the back side of the IC die, and the heat sink can extend from the IC die to the memory package. In other embodiments, the IC die can be directly attached to the memory package for improving heat dissipation. Therefore, in an embodiment semiconductor package, heat can be effectively dissipated from the IC die to the heat sink by a heat sink or by directly attaching the IC die to the memory package.

[0106] In some embodiments, a semiconductor package includes a first package component, the first package component including: a first semiconductor die; a first encapsulant located around the first semiconductor die; and a first redistribution structure electrically connected to the first semiconductor die. The semiconductor package also includes a second package component bonded to the first package component, wherein the second package component includes: a second semiconductor die; a heat sink located between the first semiconductor die and the second package component; and a second encapsulant located between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat sink. Optionally, in some embodiments, the heat sink has a thermal conductivity of at least 149 W / m*K. Optionally, in some embodiments, the heat sink contacts the substrate of the second package component. Optionally, in some embodiments, the second encapsulant extends between the top surface of the heat sink and the bottom surface of the substrate of the second package component. Optionally, in some embodiments, the heat sink is attached to the semiconductor substrate of the first semiconductor die by a film. Optionally, in some embodiments, the film includes a high-k polymer, indium, tin, a thermal interface material (TIM), or a solder paste. Optionally, in some embodiments, the second heat sink is disposed between the first semiconductor die and the second package component, and wherein the second sealant is located between the heat sink and the second heat sink. Optionally, in some embodiments, the semiconductor package further comprises: a heat sink cap attached to a top surface of a substrate of the second package component, wherein the first package component is attached to a bottom surface of the substrate of the second package component. Optionally, in some embodiments, the second sealant is disposed along a sidewall of the second package component.

[0107] In some embodiments, a semiconductor package includes a first package component, the first package component including: a first semiconductor die including a first semiconductor substrate; a first encapsulant located around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die. The semiconductor package also includes: a second package component bonded to the first package component, wherein the second package component includes a second semiconductor die on a second semiconductor substrate, and wherein the first semiconductor substrate is directly attached to the second semiconductor substrate through a film; and a second encapsulant located between the first package component and the second package component. Optionally, in some embodiments, the second encapsulant has a lower thermal conductivity than the first semiconductor substrate. Optionally, in some embodiments, the film includes a high-k polymer, indium, tin, a thermal interface material (TIM), or a solder paste. Optionally, in some embodiments, the semiconductor package also includes: a conductive via located in the first encapsulant, wherein the first semiconductor die extends higher than the via. Optionally, in some embodiments, the second encapsulant extends below the top surface of the first semiconductor die.

[0108] In some embodiments, a method includes: forming a redistribution structure, wherein the redistribution structure includes a first contact pad and a second contact pad in an insulating layer; forming a through hole on the second contact pad; bonding a first die to the redistribution structure, wherein a dielectric layer of the first die contacts the insulating layer, and wherein a third contact pad of the first die contacts the first contact pad; attaching a heat sink to a surface of the first die opposite to the redistribution structure; and bonding a package assembly including the second die to the through hole, wherein the heat sink is located between the first die and the package assembly. Optionally, in some embodiments, the method further includes: sealing the through hole and the first die in a first sealant. Optionally, in some embodiments, the method further includes: dispensing a second sealant around the heat sink and between the first die and the package assembly, wherein the heat sink has a higher thermal conductivity than the second sealant. Optionally, in some embodiments, the method further includes: dispensing the second sealant between a top surface of the heat sink and a bottom surface of the package assembly. Optionally, in some embodiments, bonding the package assembly includes contacting the heat sink with the package assembly. Optionally, in some embodiments, attaching the heat sink to the surface of the first die opposite the redistribution structure includes: attaching the heat sink to the surface of the first die using a film, and wherein the film includes high-k polymer, indium, tin, thermal interface material (TIM) or solder paste.

[0109] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor package, comprising: The first packaging component comprises: a first semiconductor die; a first encapsulant disposed around the first semiconductor die; a first redistribution structure electrically connected to the first semiconductor die; and a contact pad located on a surface of the first encapsulant opposite to the first redistribution structure; a second package component bonded to the first package component, wherein the second package component includes a second semiconductor die, wherein the second package component is directly bonded to the contact pad; a heat sink located between the first semiconductor die and the second package component, wherein the heat sink is attached to the semiconductor substrate of the first semiconductor die through a film; and A second encapsulant is located between the first package component and the second package component, wherein the second encapsulant has a lower thermal conductivity than the heat sink, and wherein an interface between the semiconductor substrate of the first semiconductor die and the film is flush with an interface between the contact pad and the first encapsulant.

2. The semiconductor package according to claim 1, wherein: The heat sink has a thermal conductivity of at least 149 W / m*K.

3. The semiconductor package according to claim 1, wherein: The heat sink contacts the substrate of the second package assembly.

4. The semiconductor package according to claim 1, wherein: The second encapsulant extends between a top surface of the heat spreader and a bottom surface of a substrate of the second package assembly.

5. The semiconductor package according to claim 1, wherein: An interface between the heat spreader and the film is closer to the second package component than an interface between the second encapsulant and the first encapsulant.

6. The semiconductor package according to claim 5, wherein: The films include high-k polymers, indium, tin, thermal interface materials, or solder pastes.

7. The semiconductor package according to claim 5, wherein: A second heat spreader is disposed between the first semiconductor die and the second package assembly, and wherein the second encapsulant is located between the heat spreader and the second heat spreader.

8. The semiconductor package according to claim 1, further comprising: A heat dissipation cover is attached to a top surface of a substrate of the second package assembly, wherein the first package assembly is attached to a bottom surface of the substrate of the second package assembly.

9. The semiconductor package according to claim 1, wherein: The second encapsulant is disposed along sidewalls of the second package assembly.

10. A semiconductor package, comprising: The first packaging component comprises: A first semiconductor die including a first semiconductor substrate; a first encapsulant disposed around the first semiconductor die; and a first redistribution structure electrically connected to the semiconductor die; a second package assembly bonded to the first package assembly, wherein the second package assembly includes a second semiconductor die on a second semiconductor substrate, and wherein the first semiconductor substrate is directly attached to the second semiconductor substrate by a film; and a second sealant disposed between the first packaging component and the second packaging component; and A conductive via extends completely through the first encapsulant, wherein a surface of the first encapsulant facing the second package component includes a curved portion, the curved portion extending continuously from a first level of the top surface of the semiconductor substrate to a second level of the top surface of the conductive via, the first level being higher than the second level.

11. The semiconductor package according to claim 10, wherein: The second sealant has a lower thermal conductivity than the first semiconductor substrate.

12. The semiconductor package according to claim 10, wherein: The films include high-k polymers, indium, tin, thermal interface materials, or solder pastes.

13. The semiconductor package according to claim 10, further comprising: A conductive via is located in the first encapsulant, wherein the first semiconductor die extends higher than the via.

14. The semiconductor package according to claim 10, wherein: The second encapsulant extends below a top surface of the first semiconductor die.

15. A method of forming a semiconductor package, comprising: forming a redistribution structure, wherein the redistribution structure comprises a first contact pad and a second contact pad in the insulating layer; forming a through hole on the second contact pad; bonding a first die to the redistribution structure, wherein the dielectric layer of the first die contacts the insulating layer, and wherein the third contact pad of the first die contacts the first contact pad; sealing the through-hole and the first die in a first encapsulant; forming a contact pad over the through hole; attaching a heat spreader to a surface of the first die opposite to the redistribution structure through a film; and A package assembly including a second die is bonded to the contact pad over the through hole, wherein the heat sink is located between the first die and the package assembly, and wherein an interface between a top surface of the first die and a bottom surface of the film is flush with an interface between a bottom surface of the contact pad and a top surface of the first encapsulant.

16. The method according to claim 15, further comprising: After forming the via and bonding the first die, the via and the first die are encapsulated in a first encapsulant.

17. The method according to claim 15, further comprising: A second encapsulant is dispensed around the heat spreader and between the first die and the package assembly, wherein the heat spreader has a higher thermal conductivity than the second encapsulant.

18. The method according to claim 17, further comprising: The second encapsulant is dispensed between the top surface of the heat spreader and the bottom surface of the package assembly.

19. The method according to claim 15, wherein: Engaging the package assembly includes contacting the heat sink with the package assembly.

20. The method according to claim 15, wherein: Attaching the heat spreader to a surface of the first die opposite the redistribution structure includes attaching the heat spreader to the surface of the first die using a film, and wherein the film includes a high-k polymer, indium, tin, a thermal interface material, or a solder paste.

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