Multi-screen display method for vehicle display device, vehicle display device and vehicle

Abstract

The embodiment of the present invention provides a multi-screen display method of a vehicle display device, a vehicle display device and a vehicle, which relates to the field of vehicle technology and can realize multi-screen display on a vehicle display device. The scheme of the embodiment of the present invention includes: FPGA receives video data through a DPI interface, and divides any frame of RGB image in the video data into a first image and a second image. Then, the first RGB data corresponding to the first image is converted into first LVDS data, and the first LVDS data is sent to the first display through the first LVDS interface, so that the first display displays the first image according to the first LVDS data. And the second RGB data corresponding to the second image is converted into second LVDS data, and the second LVDS data is sent to the second display through the second LVDS interface, so that the second display displays the second image according to the second LVDS data.

Description

Technical Field

[0001] The present invention relates to the technical field of vehicle computers, and in particular to a multi-screen display method of a vehicle computer display device, a vehicle computer display device and a vehicle. Background Art

[0002] With the development of smart cockpit technology, more and more applications are integrated into the vehicle's on-board system, enabling the on-board system to provide users with functions such as multimedia data playback, assisted driving, vehicle positioning, and making phone calls.

[0003] At present, the vehicle display device generally has only one display screen for displaying various application interfaces. At present, the vehicle display device cannot be configured with multiple display screens, and multiple display screens cannot be set to display different images respectively, that is, it is impossible to perform multi-screen display on the vehicle display device. Summary of the invention

[0004] The purpose of the embodiment of the present invention is to provide a multi-screen display method of a vehicle display device, a vehicle display device and a vehicle, so as to realize multi-screen display on the vehicle display device. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present invention provides a multi-screen display method for a vehicle display device, which is applied to a field programmable gate device FPGA of the vehicle display device, wherein the FPGA has a DPI interface, a first LVDS interface, and a second LVDS interface; the method comprises:

[0006] Receive video data through the DPI interface, and divide any frame of RGB image in the video data into a first image and a second image;

[0007] Converting first RGB data corresponding to the first image into first LVDS data, and sending the first LVDS data to a first display through a first LVDS interface, so that the first display displays the first image according to the first LVDS data;

[0008] The second RGB data corresponding to the second image is converted into second LVDS data, and the second LVDS data is sent to the second display through a second LVDS interface, so that the second display displays the second image according to the second LVDS data.

[0009] In a second aspect, an embodiment of the present invention provides a multi-screen display method for a vehicle display device, which is applied to a system-on-chip (SOC) of the vehicle display device, wherein the SOC has a DPI interface; the method comprises:

[0010] Get the first video and the second video;

[0011] Splicing each frame of the first image of the first video with each frame of the second image of the second video at a corresponding moment to obtain each frame of RGB image of the video data;

[0012] The video data is sent to the FPGA through the DPI interface, so that the FPGA receives the video data through the DPI interface, divides any frame of RGB image in the video data into a first image and a second image, converts first RGB data corresponding to the first image into first LVDS data, and sends the first LVDS data to the first display through the first LVDS interface, so that the first display displays the first image according to the first LVDS data; and converts second RGB data corresponding to the second image into second LVDS data, and sends the second LVDS data to the second display through the second LVDS interface, so that the second display displays the second image according to the second LVDS data.

[0013] In a third aspect, an embodiment of the present invention provides a vehicle display device, comprising: a system-on-chip (SOC), a field programmable gate device (FPGA), a first display and a second display;

[0014] The SOC is connected to the FPGA via a DPI interface, and is used to send video data to the FPGA via the DPI interface;

[0015] The FPGA is used to receive video data through the DPI interface, divide any frame of RGB image in the video data into a first image and a second image, convert first RGB data corresponding to the first image into first LVDS data, and send the first LVDS data to the first display through the first LVDS interface; and convert second RGB data corresponding to the second image into second LVDS data, and send the second LVDS data to the second display through the second LVDS interface;

[0016] The first display is connected to the FPGA via a first LVDS interface, and is configured to receive the first LVDS data via the first LVDS interface, and display the first image according to the first LVDS data;

[0017] The second display is connected to the FPGA via a second LVDS interface, and is configured to receive the second LVDS data via the second LVDS interface and display the second image according to the second LVDS data.

[0018] In a fourth aspect, an embodiment of the present invention provides a vehicle, comprising a vehicle display device as described in any one of the third aspects.

[0019] In the multi-screen display method of the vehicle display device, the vehicle display device and the vehicle provided by the embodiment of the present invention, the FPGA can receive video data through the DPI interface and divide any frame of RGB image in the video data into a first image and a second image. Moreover, the FPGA can also convert the RGB data corresponding to the two images into LVDS data respectively, and send the LVDS data to the two displays respectively, so that the two displays display the first image and the second image respectively. In this way, the data received from an input interface of the FPGA is distributed to different displays for display, that is, multi-screen display is realized on the vehicle display device.

[0020] Of course, it is not necessary to achieve all of the advantages described above at the same time to implement any product or method of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0022] Figure 1 A schematic diagram of the structure of a vehicle display device provided by an embodiment of the present invention;

[0023] Figure 2 A flow chart of a multi-screen display method for a vehicle display device provided by an embodiment of the present invention;

[0024] Figure 3 An exemplary schematic diagram of an RGB image provided by an embodiment of the present invention;

[0025] Figure 4 An exemplary schematic diagram of a JEIDA format provided by an embodiment of the present invention;

[0026] Figure 5 An exemplary schematic diagram of a VESA format provided by an embodiment of the present invention;

[0027] Figure 6 An exemplary schematic diagram of a timing diagram of a VESA signal provided by an embodiment of the present invention;

[0028] Figure 7 An exemplary schematic diagram of a video timing diagram provided by an embodiment of the present invention;

[0029] Figure 8 A flowchart of a multi-screen display method of another vehicle display device provided by an embodiment of the present invention;

[0030] Fig. 9A schematic diagram of the structure of another vehicle display device provided by an embodiment of the present invention;

[0031] Fig.10 A schematic structural diagram of another vehicle display device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the present invention.

[0033] To display multiple screens on the vehicle display device, see Figure 1 The embodiment of the present invention provides a vehicle display device, including: a system on chip (System on Chip, SOC) 101, a field programmable gate array (Field Programmable Gate Array, FPGA) 102, a first display 103 and a second display 104. The SOC 101 is connected to the FPGA 102 through a display pixel interface (Display Pixel Interface, DPI), the FPGA 102 is connected to the first display 103 through a first low-voltage differential signaling (Low-Voltage Differential Signaling, LVDS) interface, and the FPGA 102 is connected to the second display 104 through a second LVDS interface.

[0034] The DPI interface is also called the RGB interface, or pixel interface, which transmits the data of one pixel in one clock cycle. RGB represents the three color channels of red (Red, R), green (Green, G) and blue (Blue, B).

[0035] The multi-screen display method of the vehicle display device provided by the embodiment of the present invention is applied in Figure 1 The FPGA of the vehicle display device shown in the figure has a DPI interface, a first LVDS interface and a second LVDS interface. Figure 2 As shown, the method comprises the following steps:

[0036] S201, receiving video data through a DPI interface, and dividing any frame of RGB image in the video data into a first image and a second image.

[0037] The first image and the second image in the embodiment of the present invention may be image frames in different video data processed in the SOC, and the SOC splices the two image frames in the different video data to form a frame of RGB image transmitted in the current step.

[0038] S202 , converting first RGB data corresponding to the first image into first LVDS data, and sending the first LVDS data to the first display through a first LVDS interface, so that the first display displays the first image according to the first LVDS data.

[0039] S203, converting second RGB data corresponding to the second image into second LVDS data, and sending the second LVDS data to the second display through a second LVDS interface, so that the second display displays the second image according to the second LVDS data.

[0040] In the embodiment of the present invention, S202 and S203 may be executed sequentially or in parallel. The embodiment of the present invention does not specifically limit the order in which the FPGA executes S202 and S203.

[0041] In the multi-screen display method of the vehicle display device provided by the embodiment of the present invention, the FPGA can receive video data through the DPI interface and divide any frame of RGB image in the video data into a first image and a second image. In addition, the FPGA can also convert the RGB data corresponding to the two images into LVDS data respectively, and send the LVDS data to the two displays respectively, so that the two displays display the first image and the second image respectively. In this way, the data received from an input interface of the FPGA is distributed to different displays for display, that is, multi-screen display is realized on the vehicle display device.

[0042] It should be noted that the "first" and "second" in the embodiments of the present invention are only used for distinction and are not used to limit modules or data. For example, the "first" and "second" in the first LVDS interface and the second LVDS interface are only used to distinguish the two LVDS interfaces. The first LVDS interface and the second LVDS interface can be the same type of LVDS interface or different types of LVDS interfaces, and the embodiments of the present invention do not specifically limit this. For example, the LVDS interface includes two types, and the data signal formats thereof are respectively compliant with the VESA standard of the Video Electronics Standards Association (VESA) and the JEIDA standard of the Japanese Electronics Industry Development Association (JEIDA).

[0043] In an embodiment of the present invention, the DPI interface includes: a DPI data channel, a clock (Clock, CLK) channel, a column synchronization channel, a row synchronization channel and a data enable (Data Enable, DE) channel. Among them, the clock channel is used to transmit the DPI clock signal, and the DPI clock signal is used to determine when to transmit data, to ensure the transmission order of the group of RGB data corresponding to each pixel point, thereby improving the accuracy of data transmission; the column synchronization channel is used to transmit the column synchronization signal, and the column synchronization signal is used to count and obtain the column number of the currently transmitted pixel point in the image, that is, the pixel column of the currently transmitted RGB image; the row synchronization channel is used to transmit the row synchronization signal, and the row synchronization signal is used to count and obtain the row number of the currently transmitted pixel point in the image, that is, the pixel row of the currently transmitted RGB image, and determine the position of the currently transmitted pixel point according to the obtained row number (pixel row) and column number (pixel column); the data enable channel is used to transmit the data enable signal, which is used to control signal transmission and close transmission.

[0044] In an embodiment of the present invention, the video data received by the FPGA may come from the SOC, and the DPI data channel includes D0 to D11 channels. When the SOC sends video data to the FPGA through the DPI interface, a clock dual-edge sampling mode is adopted. The RGB data transmitted by the D0 to D11 channels corresponding to the rising edge and falling edge of the DPI clock signal are shown in Table 1.

[0045] Table 1

[0046]

[0047]

[0048] In the embodiment of the present invention, a pixel is represented by a set of RGB data. For example, the RGB data of a pixel in RGB555 format is arranged from high to low as follows:

[0049] X R0 R1 R2 R3 R4 G0 G1 G2 G3 G4 B0 B1 B2 B3 B4

[0050] Each channel of the SOC's DPI interface corresponds to each channel of the FPGA's DPI interface, and is used to send each bit of a set of RGB data. For example, in Table 1, when the clock signal sent by the SOC is at the rising edge, the D0 channel sends G4 data, and correspondingly, when the clock signal received by the FPGA is at the rising edge, the D0 channel receives G4 data.

[0051] In an embodiment of the present invention, a register is provided in the FPGA for storing the first RGB data and the second RGB data. The register is divided into a plurality of cache units according to the source of the stored data. Based on this, the above-mentioned S101 of dividing any frame of RGB image in the video data into the first image and the second image can be implemented as follows: the first RGB data of the first image and the second RGB data of the second image are determined from the RGB image respectively according to the preset first specified range and the second specified range, wherein a pixel point is represented by a set of RGB data, the first RGB data of the first image is used to represent the set of RGB data of all the pixel points constituting the first image, and the second RGB data of the second image is used to represent the set of RGB data of all the pixel points constituting the second image. Then the first RGB data corresponding to the first image is stored in the first cache unit, and the second RGB data corresponding to the second image is stored in the second cache unit.

[0052] The first designated range is the range occupied by the first image in the RGB image, and the second designated range is the range occupied by the second image in the RGB image. The first designated range and the second designated range can be pre-configured in the FPGA.

[0053] In the embodiment of the present invention, the first RGB data includes multiple groups of RGB data, each group of RGB data in the first RGB data is used to represent a pixel in the first image; the second RGB data includes multiple groups of RGB data, each group of RGB data in the second RGB data is used to represent a pixel in the second image. For example, taking the RGB data format as RGB888 format, each group of RGB data includes 24 bits, and these 24 bits represent the color values ​​of three channels of a pixel.

[0054] In the embodiment of the present invention, the FPGA splits the RGB image into the first image and the second image according to the ranges occupied by the first image and the second image in the RGB image, and sends the images to different displays, so that the data sent by the SOC through one DPI interface can be transmitted to different displays for display, thereby reducing the number of DPI interfaces configured in the SOC and having low hardware requirements for the SOC.

[0055] In the embodiment of the present invention, the DPI interface includes a column synchronization channel and a row synchronization channel; based on this, the above-mentioned FPGA determines the first RGB data of the first image and the second RGB data of the second image from the RGB image according to the preset first specified range and the second specified range, respectively, which can be implemented as follows:

[0056] The pixel columns of the currently transmitted RGB image are determined according to the signals of the column synchronization channel, and the pixel rows of the RGB image are determined according to the signals of the row synchronization channel; the currently transmitted pixel points are determined according to the pixel rows and pixel columns, and whether the currently transmitted pixel points belong to the first specified range or the second specified range, thereby determining the image to which the pixel points belong. If they belong to the first specified range, it is determined that the group of RGB data corresponding to the pixel points belongs to the first RGB data of the first image; if they belong to the second specified range, it is determined that the group of RGB data corresponding to the pixel points belongs to the second RGB data of the second image.

[0057] Since the pixel row of a pixel point indicates the number of rows of the pixel point in the RGB image, the pixel column indicates the number of columns of the pixel point in the RGB image, and the first specified range is the range occupied by the first image in the RGB image, and the second specified range is the range occupied by the second image in the RGB image, for each pixel point in the RGB image, if the number of rows and columns of the pixel point belongs to the first specified range, it is determined that the pixel point belongs to the first image, and the group of RGB data corresponding to the pixel point belongs to the first RGB data. If the number of rows and columns of the pixel point belongs to the second specified range, it is determined that the pixel point belongs to the second image, and the group of RGB data corresponding to the pixel point belongs to the second RGB data.

[0058] In the embodiment of the present invention, the FPGA can determine the image to which each pixel belongs according to the position of the pixel in the RGB image, thereby splitting the RGB image into a first image and a second image. Figure 3 As shown, the first specified range is 1920*720, that is, the RGB data corresponding to the pixel points whose pixel rows do not exceed 1920 and whose pixel columns do not exceed 720 are used as the first RGB data. The second specified range is [1921,2720]*480, that is, the RGB data corresponding to the pixel points whose pixel rows belong to [1921,2720] and whose pixel columns do not exceed 480 are used as the second RGB data, so as to subsequently display the first image and the second image on different displays.

[0059] In an embodiment of the present invention, the DPI interface further includes a DPI clock channel and a DPI data channel. Based on this, the above FPGA stores the first RGB data corresponding to the first image into the first cache unit and stores the second RGB data corresponding to the second image into the second cache unit in a manner that can be implemented as follows:

[0060] Within one clock cycle of the clock information received by the DPI clock channel, the DPI data transmission channel obtains the group of RGB data corresponding to the pixel point currently being transmitted, and stores the group of RGB data in the cache unit corresponding to the image to which the pixel point belongs, so as to determine whether the group of RGB data belongs to the first RGB data or the second RGB data. Among them, the pixel points belonging to the first image are stored in the first cache unit, and the pixel points belonging to the second image are placed in the second cache unit. In the embodiment of the present invention, the FPGA can store the RGB data of different images in different cache units, improve the orderliness of data storage, so that when converting the RGB data into LVDS data, the RGB data of different images can be read from different cache units, thereby improving the efficiency of data conversion.

[0061] In an embodiment of the present invention, the way in which the FPGA in the above S202 converts the first RGB data corresponding to the first image into the first LVDS data can be implemented as follows: reading the first RGB data from the first cache unit, and sending the first RGB data to the first LVDS interface in the first LVDS format.

[0062] Similarly, the way in which the FPGA converts the second RGB data corresponding to the second image into the second LVDS data in the above S203 can be implemented as follows: reading the second RGB data from the second cache unit, and sending the second RGB data to the second LVDS interface in the second LVDS format.

[0063] The first LVDS data can be converted based on the first display rule, and the second LVDS data can be converted based on the second display rule. Both the first display rule and the second display rule are timing requirements for driving the first display and the second display to display, and can display data in LVDS format.

[0064] In the embodiment of the present invention, the FPGA sends the first LVDS data to the first LVDS interface, and sends the first LVDS data to the first display through the first LVDS interface. Correspondingly, the FPGA sends the second LVDS data to the second LVDS interface, and sends the second LVDS data to the second display through the second LVDS interface.

[0065] The first LVDS interface may be a VESA interface or a JEIDA interface, and the second LVDS interface may be a VESA interface or a JEIDA interface. Similarly, the first LVDS format and the second LVDS format may both be VESA format or JEIDA format, and the first LVDS format and the second LVDS format may be the same or different.

[0066] In the embodiment of the present invention, the FPGA can read the RGB data of different images from different cache units, and convert them into LVDS format data respectively, and transmit them to different displays. Since the FPGA can convert the RGB data of different images into different LVDS formats, the embodiment of the present invention can realize the display of data of different formats on different displays.

[0067] In the embodiment of the present invention, a pixel point can be represented by a set of RGB data. Based on this, the method in which the FPGA in S202 converts the first RGB data corresponding to the first image into first LVDS data and sends the first LVDS data to the first display through the first LVDS interface can be implemented as follows:

[0068] The first LVDS interface includes a first LVDS clock channel and a first LVDS data channel, and the FPGA configures a first clock signal of the first LVDS clock channel according to a first display rule;

[0069] According to the first clock signal, the position of the first LVDS pixel point currently being transmitted is determined, and the first LVDS data channel reads the group of RGB data corresponding to the first LVDS pixel point position from the first cache unit according to the first LVDS format to obtain the first LVDS data, and transmits it to the first display. The first LVDS pixel point position is used to indicate the position of the pixel point displayed on the first display.

[0070] Accordingly, in the above S203, the FPGA converts the second RGB data corresponding to the second image into second LVDS data, and sends the second LVDS data to the second display through the second LVDS interface, which can be implemented as follows:

[0071] The second LVDS interface includes a second LVDS clock channel and a second LVDS data channel, and the FPGA configures a second clock signal of the second LVDS clock channel according to a second display rule;

[0072] According to the second clock signal, the position of the second LVDS pixel point currently being transmitted is determined, and the second LVDS data channel reads the group of RGB data corresponding to the second LVDS pixel point position from the second cache unit according to the second LVDS format to obtain the second LVDS data, and transmits it to the second display, wherein the second VDS pixel point position is used to indicate the position of the pixel point displayed on the second display.

[0073] The LVDS interface includes an LVDS clock channel (CLK) and four LVDS data channels (TxOUT0 to TxOUT3). The LVDS clock channel is used to transmit the clock signal. Each LVDS data channel transmits a serial signal through a pair (i.e., two) of differential data lines. Each LVDS data channel transmits 7 bits of data in one clock cycle.

[0074] like Figure 4 As shown, Figure 4 The data in JEIDA format corresponding to a pixel transmitted through the JEIDA interface. Figure 4 The broken line below CLK represents the clock signal transmitted by the LVDS clock channel in one signal cycle, and the data corresponding to TxOUT0 to TxOUT3 respectively represent the data transmitted by the LVDS data channel in one clock cycle.

[0075] like Figure 5 As shown, Figure 5 The data in VESA format corresponding to a pixel transmitted through the VESA interface. Figure 5 The broken line below CLK represents the clock signal transmitted by the LVDS clock channel in one signal cycle, and the data corresponding to TxOUT0 to TxOUT3 respectively represent the data transmitted by the LVDS data channel in one clock cycle.

[0076] in, Figure 4 and Figure 5 DE in stands for data enable. VS stands for vertical synchronization (Vsync), i.e., column synchronization signal, HS stands for horizontal synchronization (Hsync), i.e., row synchronization signal, and XX stands for space.

[0077] For example, Figure 6 is a timing diagram of the signal transmitted through the VESA interface. R_0[i](n) represents the Ri data in the RGB data of the n-th pixel in RGB888 format, and so on, i=0,1,2,…,7. G_0[i](n) represents the Gi data in the RGB data of the n-th pixel in RGB888 format, and so on, i=0,1,2,…,7. B_0[i](n) represents the Bi data in the RGB data of the n-th pixel in RGB888 format, and so on, i=0,1,2,…,7.

[0078] The embodiment of the present invention can display different image data on different displays, and the resolutions of the image data displayed on different displays can be different, thereby realizing multi-screen display of pictures with different resolutions. Optionally, the resolutions of the first image and the second image can be the same or different, which is not specifically limited in the embodiment of the present invention.

[0079] In the embodiment of the present invention, when the transmitted image is a video frame image, the display plays the video based on the received video frame image, such as Figure 7 As shown, Figure 7 A synchronization timing diagram of a video provided by an embodiment of the present invention.

[0080] Figure 7 In the figure, the first line of broken lines represents the VSYNC (Vertical synchronization signal, vertical synchronization signal field synchronization) signal. The second line of broken lines represents the HSYNC (Horizontal synchronization signal, horizontal synchronization signal) signal. The VSYNC signal and the HSYNC signal are used to indicate the position of the pixel represented by the transmitted LVDS data in the image. The third line of broken lines represents ENABLE, which is used to control the input and output of the signal. The fourth line of broken lines represents the DCK (Data Clock, data clock) signal.

[0081] Among them, 1frame means transmitting one image frame. When transmitting one image frame, it includes VBP (Vertical BackPorch), VACT (Vertical Active) and VFP (Vertical Front Porch). Among them, VBP indicates the number of invalid lines at the beginning of the image frame after the vertical synchronization period. VBP includes VLW (Vertical Low Pulse width) and VBP. VLW indicates the time to display one row of pixels. VACT indicates the image frame height. VFP indicates the number of invalid lines from the end of the output of the image frame transmitted this time to the beginning of the vertical synchronization period of the next frame.

[0082] Figure 7 “Zoom in” means that the broken lines of the HSYNC signal, ENABLE signal and DCK signal are zoomed in at the same time period, and the enlarged broken lines are shown below “Zoom in”.

[0083] 1H (1Line time) represents the line time of the HSYNC signal, and 1H includes HBP (Horizontal Back Porch), HACT (Horizontal Active) and HFP (Horizontal Front Porch). Among them, HBP represents the number of pixel clock cycles to be inserted when the pixel data of each row or column starts to be output, HACT represents the image frame width, and HFP represents the number of pixel clock cycles between the end of the pixel data of each row or column and the row clock output pulse. HBP includes HLW (Horizontal Low Pulse width) and HBP, and HLW represents the pixel clock cycle. The HBP period corresponds to DTST (Data Transfer Startup Time) in the ENABLE signal. DB represents the transmitted pixel data, and vaid data represents valid data. Optionally, the above pixel data is the LVDS data of the pixel point.

[0084] The functional characteristics of the embodiments of the present invention are described below:

[0085] In the embodiment of the present invention, for the video data inputted by the DPI interface of the FPGA, the clock frequency may be 120 Mega Hertz (Mhz), and the resolution of the image corresponding to the video data may be 2720*720@60Hz, where 60 is the refresh rate of the display.

[0086] For the LVDS data output by the LVDS interface of the FPGA, the clock frequency may be 100 MHz, and the resolution of the image corresponding to the LVDS data may include 1920*720@60 Hz and 800*480@60 Hz, that is, it supports the simultaneous output of two different video formats.

[0087] In the embodiment of the present invention, the signal name transmitted by each channel (ie, pin) of the above-mentioned DPI, the transmitted data, the corresponding FPGA pin position and the input and output (IO) standard are shown in Table 2.

[0088] Table 2

[0089]

[0090]

[0091] Among them, rst_n represents the reset signal, which is valid at a low level. The SOC can also send a reset signal to the FPGA through the rst_n channel to control the FPGA reset.

[0092] Optionally, the FPGA may also be connected to the SOC via a status pin, and the FPGA may also send the status of the FPGA to the SOC via the status pin.

[0093] Referring to Table 3, the first LVDS interface pin and the second LVDS interface pin are described below by taking the case where the resolution of the first image is 1920*720 and the resolution of the second image is 800*480 as an example.

[0094] Table 3

[0095]

[0096] The embodiment of the present invention provides a multi-screen display method for a vehicle display device, which is applied to Figure 1 The SOC of the vehicle display device shown in the figure is as follows: Figure 8 As shown, the method comprises the following steps:

[0097] S801, obtaining a first video and a second video.

[0098] S802, splicing each frame of the first image of the first video with each frame of the second image of the second video at a corresponding moment, to obtain each frame of RGB image of the video data.

[0099] In one implementation, each first image may be spliced ​​with each second image in a one-to-one correspondence according to the playback order of the video frames.

[0100] For example, Figure 3 As shown in the figure, the resolution of the first image is 1920*720, which means that the length of the first image is 1920 pixels and the width is 720 pixels. The resolution of the second image is 800*480, which means that the length of the second image is 800 pixels and the width is 480 pixels. The resolution of the RGB image spliced ​​by the first image and the second image is (1920+800)*720=2720*720.

[0101] S803, sending video data to the FPGA through the DPI interface, so that the FPGA receives the video data through the DPI interface, dividing any frame of RGB image in the video data into a first image and a second image, converting first RGB data corresponding to the first image into first LVDS data, and sending the first LVDS data to the first display through the first LVDS interface, so that the first display displays the first image according to the first LVDS data; and converting second RGB data corresponding to the second image into second LVDS data, and sending the second LVDS data to the second display through the second LVDS interface, so that the second display displays the second image according to the second LVDS data.

[0102] In the multi-screen display method of the vehicle display device provided by the embodiment of the present invention, the FPGA can receive the video data sent by the SOC through the DPI interface, and divide any frame of the RGB image in the video data into a first image and a second image. In addition, the FPGA can also convert the RGB data corresponding to the two images into LVDS data respectively, and send the LVDS data to the two displays respectively, so that the two displays display the first image and the second image respectively. In this way, the data received from an input interface of the FPGA is distributed to different displays for display, that is, multi-screen display is realized on the vehicle display device.

[0103] Optionally, before sending the video data to the FPGA through the DPI interface, the SOC may also set the format of the RGB image, including: converting the RGB data of each frame of the RGB image of the video data from an initial RGB format to a specified RGB format.

[0104] The bit position occupied by each pixel in the RGB data in the specified RGB format is greater than the bit position occupied by each pixel in the RGB data in the initial RGB format.

[0105] For example, the initial RGB format of RGB data can be RGB555 format. In RGB555 format RGB data, each pixel is represented by 16 bits = 2 bytes = 1 word, that is, each pixel occupies 16 bits. In the RGB data of a pixel, the three color channels are represented by 5 bits respectively, and the highest bit is empty. The RGB data of a pixel in RGB555 format is arranged from high bit to low bit as follows:

[0106] X R0 R1 R2 R3 R4 G0 G1 G2 G3 G4 B0 B1 B2 B3 B4

[0107] Among them, X represents empty, R0~R4 represent the color value of the red channel of the pixel, G0~G4 represent the color value of the green channel of the pixel, and B0~B4 represent the color value of the blue channel of the pixel.

[0108] For another example, the initial RGB format of RGB data can be RGB24 format. In RGB24 format RGB data, each pixel is represented by 24 bits = 3 bytes, that is, each pixel occupies 24 bits. In the RGB data of a pixel, the three color channels are represented by 8 bits respectively. The RGB data of a pixel in RGB24 format is arranged from high to low as follows:

[0109] R0 R1 R2 R3 R4 R5 R6 R7 G0 G1 G2 G3 G4 G5 G6 G7 B0 B1 B2 B3 B4 B5 B6B7

[0110] Among them, R0~R7 represent the color value of the red channel of the pixel point, G0~G7 represent the color value of the green channel of the pixel point, and B0~B7 represent the color value of the blue channel of the pixel point.

[0111] Exemplarily, the specified RGB format may be RGB888 format. In RGB data in RGB888 format, each pixel is represented by 24 bits, that is, each pixel occupies 24 bits, and the color value of each color channel is represented by 8 bits.

[0112] In the embodiment of the present invention, the SOC may use a quantization compensation method when converting the RGB data of the RGB image from an initial RGB format to a specified RGB format.

[0113] Optionally, the SOC may fill the RGB data of the initial RGB format to the high bits of the specified RGB format. After filling, if the bits of the specified RGB format are not filled completely, the low bits of the RGB data of the initial RGB format are used to fill. If the bits of the specified RGB format are still not filled completely after filling with the low bits of the RGB data of the initial RGB format, the RGB data is used for cyclic compensation.

[0114] For example, the RGB data in RGB555 format is "X R0 R1 R2 R3 R4 G0 G1 G2 G3 G4 B0 B1 B2B3 B4". The RGB data is converted from RGB555 format to RGB888 format to obtain "{R0 R1 R2 R3 R4 R2 R3 R4}{G0 G1 G2 G3 G4 G2 G3 G4}{B0 B1 B2 B3 B4 B2 B3 B4}".

[0115] For example, the RGB data in RGB332 format is “R2 R1 R0 G2 G1 G0 B1 B0”. Converting the RGB data from RGB332 format to RGB888 format yields “{R2 R1 R0 R2 R1 R0 R2 R1}{G2 G1 G0 G2 G1 G0G2 G1}{B1 B0 B1 B0 B1 B0 B1 B0}”.

[0116] In the embodiment of the present invention, RGB data is converted into a unified specified format for transmission, which can improve data transmission efficiency.

[0117] In the embodiment of the multi-screen display method applied to SOC and the embodiment of the multi-screen display method applied to FPGA, the descriptions of corresponding steps can be referenced to each other and will not be repeated here.

[0118] Based on the same inventive concept, corresponding to the above method embodiment, an embodiment of the present invention provides a vehicle display device, such as Figure 1 As shown, it includes: SOC 101, FPGA 102, a first display 103 and a second display 104;

[0119] The SOC 101 is connected to the FPGA 102 via a DPI interface, and is used to send video data to the FPGA 102 via the DPI interface;

[0120] FPGA 102 is used to receive video data through the DPI interface, divide any frame of RGB image in the video data into a first image and a second image, convert first RGB data corresponding to the first image into first LVDS data, and send the first LVDS data to the first display through the first LVDS interface; and convert second RGB data corresponding to the second image into second LVDS data, and send the second LVDS data to the second display through the second LVDS interface;

[0121] The first display 103 is connected to the FPGA 102 via a first LVDS interface, and is used to receive first LVDS data via the first LVDS interface, and display a first image according to the first LVDS data;

[0122] The second display 104 is connected to the FPGA 102 via a second LVDS interface, and is configured to receive second LVDS data via the second LVDS interface and display a second image according to the second LVDS data.

[0123] Optional, such as Fig. 9 As shown, FPGA 102 includes: a receiving unit 1021, a register 1022, a first conversion unit 1023 and a second conversion unit 1024; SOC 101 is connected to the receiving unit 1021 through a DPI interface, the first conversion unit 1023 is connected to the first display 103 through a first LVDS interface, the second conversion unit 1024 is connected to the second display 104 through a second LVDS interface, and the register 1022 is respectively connected to the receiving unit 1021, the first conversion unit 1023 and the second conversion unit 1024.

[0124] Optionally, the receiving unit 1021 is used to determine the first RGB data of the first image and the second RGB data of the second image from the RGB image according to a preset first specified range and a second specified range, respectively; wherein a pixel point is represented by a group of RGB data; the first RGB data corresponding to the first image is stored in the first cache unit, and the second RGB data corresponding to the second image is stored in the second cache unit.

[0125] The first cache unit and the second cache unit belong to the register 1022 .

[0126] Optionally, the first conversion unit 1023 is used to read the first RGB data from the first cache unit, and send the first RGB data to the first LVDS interface according to the first LVDS format.

[0127] The second conversion unit 1024 is used for reading the second RGB data from the second buffer unit, and sending the second RGB data to the second LVDS interface according to the second LVDS format.

[0128] Optionally, the receiving unit 1021 is specifically configured to:

[0129] The DPI interface includes a column synchronization channel and a row synchronization channel;

[0130] Determine the pixel column of the currently transmitted RGB image according to the signal of the column synchronization channel, and determine the pixel row of the currently transmitted RGB image according to the signal of the row synchronization channel;

[0131] Determine the pixel point currently being transmitted according to the pixel row and the pixel column, and whether the pixel point currently being transmitted belongs to the first specified range or the second specified range, thereby determining the image to which the pixel point belongs;

[0132] If it belongs to the first specified range, it is determined that the group of RGB data corresponding to the pixel point belongs to the first RGB data of the first image; if it belongs to the second specified range, it is determined that the group of RGB data corresponding to the pixel point belongs to the second RGB data of the second image.

[0133] Optionally, the receiving unit 1021 is specifically configured to:

[0134] The DPI interface also includes a DPI clock channel and a DPI data channel;

[0135] Within a clock cycle of the clock information received by the DPI clock channel, the DPI data transmission channel obtains the group of RGB data corresponding to the pixel point currently being transmitted, and stores the group of RGB data in a cache unit corresponding to the image to which the pixel point belongs;

[0136] The pixels belonging to the first image are stored in the first cache unit, and the pixels belonging to the second image are placed in the second cache unit.

[0137] Optionally, the first conversion unit 1023 is specifically configured to:

[0138] The first LVDS interface includes a first LVDS clock channel and a first LVDS data channel, and a first clock signal of the first LVDS clock channel is configured according to a first display rule;

[0139] According to the first clock signal, the position of the first LVDS pixel point currently being transmitted is determined, and the first LVDS data channel reads the group of RGB data corresponding to the first LVDS pixel point position from the first cache unit according to the first LVDS format to obtain the first LVDS data, and transmits it to the first display; wherein the first LVDS pixel point position is used to indicate the position of the pixel point displayed on the first display;

[0140] The second conversion unit 1024 is specifically configured to:

[0141] The second LVDS interface includes a second LVDS clock channel and a second LVDS data channel, and a second clock signal of the second LVDS clock channel is configured according to a second display rule;

[0142] According to the second clock signal, the position of the second LVDS pixel point currently being transmitted is determined, and the second LVDS data channel reads the group of RGB data corresponding to the second LVDS pixel point position from the second cache unit according to the second LVDS format to obtain the second LVDS data, and transmits it to the second display, wherein the second VDS pixel point position is used to indicate the position of the pixel point displayed on the second display.

[0143] In the embodiment of the present invention, the FPGA 102 and the first display 103 as well as the FPGA 102 and the second display 104 may be connected via a serial chip and a deserialization chip.

[0144] Specifically, Fig.10 As shown, the vehicle display device provided by the embodiment of the present invention also includes: a first serial chip (Serializer) 105, a first deserializer chip (Deserializer) 106, a second serial chip 107 and a second deserializer chip 108. Among them, the first conversion unit 1023 is connected to the first serial chip 105 through the first LVDS interface, the first serial chip 105 is connected to the first deserializer chip 106, the first deserializer chip 106 is connected to the first display 103 through the first LVDS interface, the second conversion unit 1024 is connected to the second serial chip 107 through the second LVDS interface, the second serial chip 107 is connected to the second deserializer chip 108, and the second deserializer chip 108 is connected to the second display 104 through the second LVDS interface.

[0145] The first serial chip 105 is connected to the first conversion unit 1023 , and is used for receiving the first LVDS data sent by the first conversion unit 1023 , converting the first LVDS data into first serial data, and sending the first serial data to the first deserialization chip 106 .

[0146] The first deserialization chip 106 is connected to the first serialization chip 105 , and is used for receiving the first serial data sent by the first serialization chip 105 , and restoring the first serial data into first LVDS data.

[0147] The first deserialization chip 106 is connected to the first display 103 , and is also used to send the restored first LVDS data to the first display 103 .

[0148] The second serial chip 107 is connected to the second conversion unit 1024 , and is used for receiving the second LVDS data sent by the second conversion unit 1024 , converting the first LVDS data into second serial data, and sending the second serial data to the second deserialization chip 108 .

[0149] The second deserialization chip 108 is connected to the second serialization chip 107, and is used for receiving the second serial data sent by the second serialization chip 107, and restoring the second serial data into second LVDS data;

[0150] The second deserialization chip 108 is connected to the second display 104 , and is also used to send the restored second LVDS data to the second display 104 .

[0151] In an embodiment of the present invention, the first serial chip 105 and the first deserialization chip 106 can be connected via an in-vehicle cable, and the second serial chip 107 and the second deserialization chip 108 can be connected via an in-vehicle cable. The in-vehicle cable can be a differential twisted pair. By adding a serial chip and a deserialization chip between the FPGA 102 and the display, the transmission distance of the LVDS data can be increased, and the limitation of the display position on the multi-screen display can be reduced.

[0152] Optionally, SOC 101 is also used to: obtain the first video and the second video before sending the video data to the FPGA through the DPI interface; splice each frame of the first image of the first video with each frame of the second image of the second video at the corresponding moment to obtain each frame of RGB image of the video data.

[0153] Optionally, SOC 101 is further used to: before sending the video data to the FPGA through the DPI interface, convert the RGB data of each frame of the RGB image of the video data from the initial RGB format to the specified RGB format; wherein the number of bits occupied by each pixel in the RGB data in the specified RGB format is greater than the number of bits occupied by each pixel in the RGB data in the initial RGB format.

[0154] The specific description in the embodiment of the vehicle display device can refer to the description in the embodiment of the multi-screen display method of the vehicle display device, which will not be repeated here.

[0155] An embodiment of the present invention provides a vehicle, comprising any of the above-mentioned vehicle display devices.

[0156] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0157] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the vehicle display device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0158] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A multi-screen display method for a vehicle display device, characterized in that: A field programmable gate device FPGA applied to a vehicle display device, wherein the FPGA has a DPI interface, a first LVDS interface, and a second LVDS interface; the method comprises: Receive video data through a DPI interface, and divide any frame of RGB image in the video data into a first image and a second image, wherein the video data is: a video obtained by splicing each frame of the first image of the first video with each frame of the second image at a corresponding moment of the second video; Converting first RGB data corresponding to the first image into first LVDS data, and sending the first LVDS data to a first display through a first LVDS interface, so that the first display displays the first image according to the first LVDS data; Converting second RGB data corresponding to the second image into second LVDS data, and sending the second LVDS data to a second display through a second LVDS interface, so that the second display displays the second image according to the second LVDS data; The step of dividing any frame of RGB image in the video data into a first image and a second image comprises: Determine first RGB data of the first image and second RGB data of the second image from the RGB image according to a preset first specified range and a second specified range, respectively; wherein one pixel is represented by a set of RGB data; The first RGB data corresponding to the first image is stored in the first cache unit, and the second RGB data corresponding to the second image is stored in the second cache unit; Determining first RGB data of the first image and second RGB data of the second image from the RGB image respectively according to a preset first specified range and a second specified range, comprising: The DPI interface includes a column synchronization channel and a row synchronization channel; Determine the pixel column of the currently transmitted RGB image according to the signal of the column synchronization channel, and determine the pixel row of the currently transmitted RGB image according to the signal of the row synchronization channel; Determine a currently transmitted pixel point according to the pixel row and the pixel column, and whether the currently transmitted pixel point belongs to the first specified range or the second specified range, thereby determining the image to which the pixel point belongs; If it belongs to the first specified range, it is determined that the group of RGB data corresponding to the pixel point belongs to the first RGB data of the first image; if it belongs to the second specified range, it is determined that the group of RGB data corresponding to the pixel point belongs to the second RGB data of the second image.

2. The method according to claim 1, characterized in that Converting the first RGB data corresponding to the first image into the first LVDS data includes: reading the first RGB data from the first buffer unit, and sending the first RGB data to the first LVDS interface according to the first LVDS format; Converting the second RGB data corresponding to the second image into second LVDS data includes: reading the second RGB data from the second buffer unit, and sending the second RGB data to the second LVDS interface according to the second LVDS format.

3. The method according to claim 1, characterized in that Storing first RGB data corresponding to the first image into a first cache unit, and storing second RGB data corresponding to the second image into a second cache unit comprises: The DPI interface also includes a DPI clock channel and a DPI data channel; Within a clock cycle of the clock information received by the DPI clock channel, the DPI data transmission channel obtains the group of RGB data corresponding to the pixel point currently being transmitted, and stores the group of RGB data in a cache unit corresponding to the image to which the pixel point belongs; The pixels belonging to the first image are stored in the first cache unit, and the pixels belonging to the second image are placed in the second cache unit.

4. The method according to claim 1, characterized in that The converting the first RGB data corresponding to the first image into first LVDS data, and sending the first LVDS data to the first display through the first LVDS interface includes: The first LVDS interface includes a first LVDS clock channel and a first LVDS data channel, and a first clock signal of the first LVDS clock channel is configured according to a first display rule; According to the first clock signal, the position of the first LVDS pixel point currently being transmitted is determined, and the first LVDS data channel reads the group of RGB data corresponding to the first LVDS pixel point position from the first cache unit according to the first LVDS format to obtain the first LVDS data, and transmits it to the first display; wherein the first LVDS pixel point position is used to indicate the position of the pixel point displayed on the first display; The converting the second RGB data corresponding to the second image into second LVDS data, and sending the second LVDS data to the second display through the second LVDS interface includes: The second LVDS interface includes a second LVDS clock channel and a second LVDS data channel, and a second clock signal of the second LVDS clock channel is configured according to a second display rule; According to the second clock signal, the second LVDS pixel position currently being transmitted is determined, and the second LVDS data channel reads the group of RGB data corresponding to the second LVDS pixel position from the second cache unit according to the second LVDS format to obtain the second LVDS data, and transmits it to the second display, wherein the second VDS pixel position is used to indicate the position of the pixel displayed on the second display.

5. A multi-screen display method for a vehicle display device, characterized in that: A system-on-chip (SOC) applied to a vehicle display device, wherein the SOC has a DPI interface; the method comprises: Get the first video and the second video; Splicing each frame of the first image of the first video with each frame of the second image of the second video at a corresponding moment to obtain each frame of RGB image of the video data; The video data is sent to a field programmable gate device FPGA through a DPI interface, so that the FPGA receives the video data through the DPI interface, and the first RGB data of the first image and the second RGB data of the second image are determined from the RGB image according to a preset first specified range and a second specified range, respectively; wherein one pixel point is represented by a group of RGB data, the first RGB data corresponding to the first image is stored in a first cache unit, and the second RGB data corresponding to the second image is stored in a second cache unit, the first RGB data corresponding to the first image is converted into first LVDS data, and the first LVDS data is sent to a first display through a first LVDS interface, so that the first display displays the first image according to the first LVDS data; and the second RGB data corresponding to the second image is converted into second LVDS data, and the second LVDS data is sent to a second display through a second LVDS interface, so that the second display displays the second image according to the second LVDS data; Determining first RGB data of the first image and second RGB data of the second image from the RGB image respectively according to a preset first specified range and a second specified range, comprising: The DPI interface includes a column synchronization channel and a row synchronization channel; Determine the pixel column of the currently transmitted RGB image according to the signal of the column synchronization channel, and determine the pixel row of the currently transmitted RGB image according to the signal of the row synchronization channel; Determine a currently transmitted pixel point according to the pixel row and the pixel column, and whether the currently transmitted pixel point belongs to the first specified range or the second specified range, thereby determining the image to which the pixel point belongs; If it belongs to the first specified range, it is determined that the group of RGB data corresponding to the pixel point belongs to the first RGB data of the first image; if it belongs to the second specified range, it is determined that the group of RGB data corresponding to the pixel point belongs to the second RGB data of the second image.

6. The method according to claim 5, characterized in that Before sending the video data to the FPGA through the DPI interface, the method further includes: The RGB data of each frame of the RGB image of the video data is converted from an initial RGB format to a specified RGB format.

7. A vehicle display device, characterized in that: include: System-on-chip SOC, field programmable gate device FPGA, a first display and a second display; The SOC is connected to the FPGA via a DPI interface, and is used to send video data to the FPGA via the DPI interface, wherein the video data is a video obtained by splicing each frame of a first image of a first video with each frame of a second image of a second video at a corresponding moment; The FPGA is used to receive video data through the DPI interface, divide any frame of RGB image in the video data into a first image and a second image, convert first RGB data corresponding to the first image into first LVDS data, and send the first LVDS data to the first display through the first LVDS interface; and convert second RGB data corresponding to the second image into second LVDS data, and send the second LVDS data to the second display through the second LVDS interface; The first display is connected to the FPGA via a first LVDS interface, and is configured to receive the first LVDS data via the first LVDS interface, and display the first image according to the first LVDS data; The second display is connected to the FPGA via a second LVDS interface, and is used to receive the second LVDS data via the second LVDS interface, and display the second image according to the second LVDS data; The FPGA is specifically used to determine first RGB data of the first image and second RGB data of the second image from the RGB image according to a preset first specified range and a second specified range, respectively; wherein one pixel point is represented by a group of RGB data; the first RGB data corresponding to the first image is stored in a first cache unit, and the second RGB data corresponding to the second image is stored in a second cache unit; The FPGA, specifically used for the DPI interface, includes a column synchronization channel and a row synchronization channel; determines the pixel column of the currently transmitted RGB image according to the signal of the column synchronization channel, and determines the pixel row of the currently transmitted RGB image according to the signal of the row synchronization channel; determines the currently transmitted pixel point according to the pixel row and the pixel column, and whether the currently transmitted pixel point belongs to the first specified range or the second specified range, thereby determining the image to which the pixel point belongs; if it belongs to the first specified range, determines that the group of RGB data corresponding to the pixel point belongs to the first RGB data of the first image, and if it belongs to the second specified range, determines that the group of RGB data corresponding to the pixel point belongs to the second RGB data of the second image.

8. A vehicle, characterized in that: It includes the vehicle display device as claimed in claim 7.

Images