Three-dimensional capacitive structure and method of manufacturing the same

Abstract

A three-dimensional capacitive structure (150) can be generated by conformally forming capacitive stacks (153 to 155) above holes (151) in a porous anodic oxide region (152a). The porous anodic oxide region is disposed on a stack of conductive layers (158, 159) including an anti-anodized layer and an interconnect layer (159). In the holes, there are locations (P) with a limited diameter (D) very close to the bottom of the holes. In a first percentage of the holes in the anodic oxide region (152a), functional portions (F) of the capacitive stacks (153 to 155) are formed to extend into the holes, not exceeding the location (P) with the limited diameter. Cracks that may exist in the anti-anodized layer (159) have a degrading effect on the characteristics of the capacitive structure. An increase in the thickness of the anti-anodized layer (159) can be tolerated, allowing the equivalent series resistance of the entire capacitive structure to be reduced.

Description

[0001] This invention relates to the field of electrical / electronic devices and methods of manufacturing them. More specifically, this invention relates to devices incorporating three-dimensional capacitive structures and methods of manufacturing such devices.

[0002] In recent years, as part of the trend towards increasing the integration of electronic components, there has been a demand for integrated capacitors with increased capacitance density. One solution adopted to achieve higher capacitance density is to increase the surface area of ​​the electrodes used to provide capacitance. For example, the silicon capacitors proposed by Murata Integrated Passive Solutions are fabricated in a process that uses semiconductor technology to form three-dimensional structures (embossing, texture), such as holes, trenches, or pillars, in silicon, and then conformally forms a metal / dielectric layer on top of the 3D structure to provide large-area electrodes.

[0003] Another proposed method for providing high-density capacitors involves creating porous regions of an anodic metal oxide (e.g., anodic aluminum oxide, AAO), and then conformally depositing single or repeating metal-insulator-metal (MIM) stacks over the porous regions, such that the MIM layers follow the contours of the holes and have the resulting large surface area. According to this method, a metal layer (e.g., an aluminum layer) is typically formed on a silicon substrate, and then an anodization process is performed on selected areas of the metal layer to create high-density, uniformly self-assembled trenches, or “holes,” therein. The porous regions of the anodic oxide act as templates on which conductive and dielectric layers are then deposited. Strictly speaking, the holes are defined within the anodic metal oxide layer formed during the anodization process. Figure 1A illustrates a template of this type formed by anodization.

[0004] US 2019 / 0088419 describes a high-density capacitor created by forming a conductive layer and an insulating layer in a porous anodic oxide matrix.

[0005] Using porous anodic oxides is an effective technique for increasing the surface area of ​​electrodes, but it can present challenges in achieving sufficiently low equivalent series resistance (ESR) for the fabricated capacitive structures. To overcome this difficulty, (WO2015 / 063420) has proposed removing the anodic oxide layer at the bottom of the holes, allowing the interior of each hole to communicate with a stack of conductive layers disposed on the substrate side. In this way, the lower layer of the MIM stack in each hole is connected on the substrate side to the lower layer of the MIM stack in the adjacent hole, reducing the overall ESR of the structure.

[0006] Figure 1B is a simplified diagram illustrating a capacitive structure 50 of a general type described in WO2015 / 063420. A porous AAO region 52a is formed in an aluminum layer 52 disposed on a silicon substrate 51. More specifically, the aluminum layer 52 is formed on a stack comprising a lower conductive layer 58 and an upper layer 59 resistant to anodizing / anodizing. The holes in the anodized region 52a are open on the substrate side. Therefore, a first metal layer 53, conformally formed above the porous region 52a, contacts the stack of the underlying layers 58 and 59. The anodizing-resistant layer 59 has sufficient conductivity to allow a good electrical connection to be formed at the bottom of the holes between the conductive layer 58 and the first metal layer 53. A dielectric layer 54 and a second conductive layer 55, together with the first conductive layer 53, form a MIM stack serving as a capacitor element.

[0007] Typically, the first terminal of the capacitor element is formed on the side 56 away from the substrate by being connected to the second conductive layer 55. The second terminal of the capacitor element can be formed on either side of the structure (i.e., on side 56 or the substrate side) by being connected to the conductive layer 58.

[0008] It has been found that the yield of the manufacturing process for producing the capacitive structure of the type shown in Figure 1B depends on the thickness of layers 58 and 59, as shown in Table 1 below.

[0009] Table 1

[0010]

[0011] As can be seen from Table 1, the best yield was achieved when both layers 58 and 59 were thin (note that the composition for "thin" of layer 59 is different from that for layer 58). However, for a good ESR reduction, layers 58 and 59 are preferably relatively thick.

[0012] Experiments have been conducted to investigate which phenomena may affect the manufacturing process yield, and it is believed that the surface condition of the anti-anodized layer may have a significant impact on the performance of capacitive stacks.

[0013] Based on the examination of the microstructure of the architecture, using scanning electron microscopy, a potential crack has been found in the anti-anodizing layer 59. Figure 1B schematically illustrates the crack marked C, and... Figure 1C Images obtained using scanning electron microscopy show cracks in an anti-anodizing layer made of tungsten (W). These cracks adversely affect portions of the MIM stack formed at the bottom of the pores, leading to unwanted leakage current flow. Studies have shown that, typically, cracks can affect more than 0.6% of the surface area of ​​the usable porous region.

[0014] The present invention was developed in view of the above-mentioned problems.

[0015] This invention provides a capacitive structure, comprising:

[0016] A substrate providing conductive interconnect layers;

[0017] An anti-anodic oxidation layer is formed above and in electrical contact with the interconnect layer;

[0018] A region of porous anodic oxide formed on the anti-anodic oxide layer, with multiple elongated pores extending through the region of porous anodic oxide and extending between the anti-anodic oxide layer and the substrate-remote surface of the anodic oxide; and

[0019] A capacitive stack of layers, the layers comprising: a lower conductive layer, a first insulating layer and an upper conductive layer, the stack being conformally formed over pores in the region of the porous anodic oxide, and the lower conductive layer being in electrical contact with the anti-anodic oxide layer;

[0020] The hole has a limited diameter at a location along its length;

[0021] The feature is that, in a first non-zero percentage of the pores in the region of the porous anolyte, the stacked upper conductive layer extends into the pores, not exceeding the location where the pore diameter is limited.

[0022] In the capacitive structure according to an embodiment of the invention, in a first percentage of the holes in the anodized region, the functional portion of the capacitive stack contributing to the capacitance of the finished structure extends into the holes, not exceeding the location where the hole diameter is limited, so that this functional portion does not directly contact the portion of the anti-anodized layer where cracks may occur. A second portion of the capacitive stack, whose contribution to the capacitance of the capacitive structure is negligible, is located between the anti-anodized layer and the location in the holes where the hole diameter is limited, thereby providing electrical contact with the anti-anodized layer, and thus providing electrical contact with the interconnect layer. Therefore, the negative impact of cracks in the anti-anodized layer is reduced. More specifically, undesirable leakage current is reduced and the electrical characteristics of the finished structure are improved, thereby increasing the yield of the process used to manufacture the structure. Considering the increased yield, it becomes feasible to use relatively thick layers for the anti-anodized layer and the conductive interconnect layer, which is beneficial for achieving low ESR values ​​while achieving high capacitance density. Therefore, for example, it becomes feasible to use an anti-anodized layer that is 600 nm thick and an interconnect layer that is 3 μm thick. These are just examples of the dimensions of relatively thick layers that can be used; other thicknesses can be employed.

[0023] Furthermore, as will be explained below, by positioning the functional portions of the capacitive stack above a location with a reduced aperture diameter, the irregularity in the shape of the functional portions of the MIM stack that contribute to the capacitance of the finished structure near the bottom of the aperture is reduced. Therefore, the target characteristics of the capacitive structure can be obtained more reliably, resulting in capacitive components with improved reliability and increased lifespan.

[0024] Furthermore, vias typically have a high aspect ratio, and at the bottom of the via, it is difficult to deposit the capacitive stack layers to the desired thickness. This can adversely affect the ESR and breakdown voltage of the entire capacitive structure. However, by positioning the functional portions of the capacitive stack above a location with a reduced via diameter, the non-uniformity in the thickness of the capacitive stack layers near the bottom of the via has a degrading effect on the overall performance of the capacitive structure (which may be negligible).

[0025] In some embodiments of the invention, in at least 1% of the pores in the porous anodic oxide region, a first portion of the capacitive stack of layers contributing to the capacitance of the capacitive structure is located in the portion between the diameter-limited location of the pores and the surface of the anodic oxide away from the substrate.

[0026] In some embodiments of the invention, a stacked lower conductive layer is conformally formed over a hole in a porous region, a first insulating layer is formed on the lower conductive layer, and an upper conductive layer is formed on the first insulating layer. Since the upper conductive layer does not extend beyond the location where the hole diameter is limited, the functional portion of the capacitive structure (including both the first and second conductive layers and the inserted insulating layer) is located between the location where the hole diameter decreases and the surface of the anodic oxide region away from the substrate.

[0027] In some embodiments of the present invention, the following relationship is established:

[0028]

[0029] Where D is the diameter of the hole at the location where the diameter is restricted, and T c1 Let T be the thickness of the lower conductive layer, and T i1 The thickness of the first insulating layer.

[0030] By ensuring adherence to the above relationships, it is possible to prevent the upper conductive layer from extending into the hole beyond the point where the hole diameter decreases.

[0031] In some embodiments of the invention, the hole diameter is limited at a distance of 10 nm to 300 nm from the bottom of the hole.

[0032] In some embodiments of the invention, the anti-anodizing layer is made of tungsten. However, the anti-anodizing layer can be made of other materials, including but not limited to Ti, Ta, Hf, and Nd. In some embodiments of the invention, the average thickness of the anti-anodizing layer is in the range of 10 nm to 1 μm. In some embodiments of the invention, the anodic oxide is anodic aluminum oxide. However, the porous material can be made of other substances, including but not limited to porous anodized titanium (Ti), silicon (Si), tantalum (Ta), or zirconium (Zr).

[0033] The present invention further provides a method for fabricating a capacitive structure, comprising:

[0034] A substrate is formed to provide conductive interconnect layers;

[0035] An anti-anodic oxidation layer is formed above the interconnect layer and is in electrical contact with the interconnect layer;

[0036] A metal layer is formed on the anti-anodization layer;

[0037] A region of the metal layer is anodized to form a region of porous anodic oxide through which multiple elongated holes extend between the anti-anodic oxide layer and the surface of the anodic oxide away from the substrate.

[0038] Remove oxides formed at the bottom of the pores during the anodizing step from the anti-anodizing layer; and

[0039] A capacitive stack of layers is conformally formed above the pores in the region of the porous anodic oxide, the layers comprising a lower conductive layer, a first insulating layer and an upper conductive layer, wherein the lower conductive layer is in electrical contact with the anti-anodic oxide layer;

[0040] The hole has a limited diameter at a location along its length;

[0041] The feature is that at least one of the anodizing step, the oxide removal step, and the capacitive stacking step is controlled such that in a first percentage of the pores in the porous anodized region, the upper conductive layer of the stack extends into the pores without exceeding the pore diameter limit.

[0042] The method described above offers advantages comparable to those mentioned above in terms of capacitive structures. Furthermore, this method improves yield compared to existing fabrication methods.

[0043] Referring to the accompanying drawings, further features and advantages of the invention will become apparent from the following description of certain embodiments according to the invention, which are given by way of illustration rather than limitation, in which:

[0044] Figure 1 shows a known structure containing porous anodic oxides. In Figure 1:

[0045] Figure 1A schematically shows a porous anodized aluminum template formed on a substrate.

[0046] Figure 1B illustrates a capacitive structure formed in a region of porous anodic oxide and having a reduced equivalent series resistance, and

[0047] Figure 1C A scanning electron micrograph showing cracks in the anti-anodization layer of a structure such as Figure 1B is shown.

[0048] Figure 2 illustrates how holes in a structure such as Figure 1B can have locations with decreasing diameters. In Figure 2:

[0049] Figure 2A It is a schematic cross-sectional view showing the location where the diameter decreases in the hole, and

[0050] Figure 2B This is a scanning electron microscope image showing the bottom of the hole at a high magnification.

[0051] Figure 3 A capacitive structure according to an embodiment of the present invention is schematically shown;

[0052] Figure 4 This illustrates an embodiment of the invention for manufacturing such as Figure 3 A flowchart of the main stages in the method for constructing a capacitive structure; and

[0053] Figure 5 This shows how the current changes during the anodizing process.

[0054] The inventors have investigated the potential origins of cracks that may occur in the anti-anodizing layer. Their research indicates that such cracks may occur due to weak points in the anti-anodizing layer 59 near the bottom of the hole. The current understanding of the origin of such weak points is described below.

[0055] During the fabrication of a capacitive structure such as structure 50 shown in Figure 1B, an anodizing process is performed to create pores in the porous anodized region 52a, and the anodizing process continues until the bottom of the pores is opened sufficiently to reach the upper layer 59. During that portion of the anodizing process that opens the bottom of the pores, atoms of the material (e.g., tungsten W) forming the anti-anodized layer 59 in the region below the pores migrate to a certain extent, forming small regions of undesirable oxides (e.g., tungsten oxide). Each of these small regions of undesirable oxides is roughly shaped like a biconvex lens. These undesirable oxides are typically removed by an etching process before depositing the MIM stack in the pores. It is believed that this atomic migration in the material forming the anti-anodized layer 59 leads to weak points and a tendency to crack in the anodized layer 59.

[0056] Based on this technical analysis, techniques have been designed to mitigate the negative effects of such cracks in the anti-anodized layer. Embodiments of the present invention utilize the fact that pores in the anodized oxide can have a reduced diameter location facing the bottom of the pore.

[0057] It has been recognized that, such as Figure 2A As schematically shown, the holes formed by the manufacturing method described above with reference to FIG1B do not have a uniform cross-sectional area along their entire length. Instead, they have, for example, a uniform cross-sectional area. Figure 2B The unusual and distinctive shapes that can be seen in it Figure 2B This is an enlarged view of the bottom of a set of holes produced by scanning electron microscopy.

[0058] More specifically, a neck N with a reduced diameter has been found near the bottom of each pore, close to the anti-anodizing layer 59. This reduction in pore diameter does not occur directly above the surface of the anti-anodizing layer 59; it typically occurs between 10 nm and 300 nm from that surface (e.g., in the case of using a tungsten layer as the anti-anodizing layer). Furthermore, in the region below the location with the minimum pore diameter, the periphery of the pore has a fan-like shape. Alternatively, a roughly annular protrusion S extends into the pore not far from the anti-anodizing layer. It should be understood that this distinctive shape is due to the formation and removal of undesirable oxides during the anodizing process at the bottom of the pore.

[0059] In an embodiment of the invention, capacitive stacks are formed in the holes of the anodized region such that, in at least 1% of the holes, the functional portion F of the capacitive stack that determines the capacitance of the entire structure is located above the position where the diameter decreases in the hole ("above" means farther from the substrate than the position where the hole diameter decreases). Therefore, the performance of the capacitive stack is less affected by the surface condition of the anti-anodized layer, such as cracks formed therein.

[0060] Various methods can be used to form the functional portion of a capacitive stack above a location where the diameter decreases in the aperture. Below is a description of some techniques that control the relationship between the thickness of certain layers in the capacitive stack and the diameter of the aperture at the location where the diameter decreases, ensuring that the functional portion of the capacitive stack lies above this location. More specifically, according to these techniques, the first conductive layer and the first insulating layer of the capacitive stack have a thickness relative to the diameter of the location where the diameter decreases in the aperture, meaning that these layers block the bottom of the aperture and the second conductive layer does not pass through the "throat" of the location where the diameter decreases. In other words:

[0061] D ≤ 2 (T c1 + T i1 (1)

[0062] Where D is the diameter of the hole at the location where the diameter is restricted, and T c1 Let T be the thickness of the first conductive layer, and T i1 The thickness of the first insulating layer.

[0063] Now refer to Figure 3 To describe the capacitive stack according to an embodiment of the present invention, and referring to Figure 4 Here are some example implementations of the methods used to manufacture this structure.

[0064] from Figure 3 As shown in the enlarged view, the capacitive structure 150 according to this embodiment includes a region 152a of porous anodic oxide formed on a stack of layers, the layers including: a lower conductive layer 158; and an upper layer 159 resistant to anodizing / anodic etching. The stack of layers 158, 159 can be disposed on a substrate (not shown), for example, when the capacitive structure is integrated with other electronic components and / or when the substrate can increase the strength of the overall structure. When a substrate is used and the substrate is conductive, the substrate itself can be used as an interconnect layer to electrically connect the lowest conductive layer at the bottom of a hole to those conductive layers in adjacent holes. Therefore, in such cases, a separate layer 158 may not be necessary. The hole 151 in the anodized region 152a opens on the substrate side and has a position P where the diameter of the hole decreases. The position where the diameter of the hole decreases has a diameter designated as D.

[0065] A first conductive layer 153 is conformally formed above the porous region 152a, and this first conductive layer 153 is in contact with the stacked layers 158 and 159 below. The anti-anodizing layer 159 has sufficient conductivity to form a good electrical connection between the conductive layer 158 and the first conductive layer 153 at the bottom of the hole. Figure 3In the illustrated embodiment, the first conductive layer 153 covers the wall of the hole 151 and follows a generally cylindrical shape for most of the length of the hole, as well as the shape of the hole wall at the bottom of the hole. Therefore, the first conductive layer 153 passes through the throat of the hole, where the diameter decreases, at location P and contacts the anti-anodizing layer 159. Figure 3 A single hole 151 in the porous anodic oxide region is shown, but it should be understood that the first conductive layer 153 will conformally cover the walls of a group of adjacent holes in the porous anodic oxide region.

[0066] like Figure 3 As shown, a first insulating layer 154 is disposed on a first conductive layer 153, and the first insulating layer 154 generally follows the shape of the underlying first conductive layer 153. However, the thickness of the first conductive layer 153 and the first insulating layer 154 closes the throat of the hole with a reduced diameter. More specifically, the first insulating layer 154 covering the opposing surface of the hole contacts itself at a position directly above the position P of the reduced diameter in the hole. Therefore, the inner surface of the first insulating layer 154 defines a generally cylindrical hole with a substantially constant diameter along its length. A second conductive layer 155 is disposed on the inner surface of the first insulating layer 154. The second conductive layer 155 does not penetrate the throat of the hole with a reduced diameter; instead, the second conductive layer 155 conformally follows the shape of the inner surface of the first insulating layer 154, and therefore, the second conductive layer 155 has a regular shape. In this example, the first conductive layer 153 may be, for example, an exemplary implementation of the "lower conductive layer" described above, and the second conductive layer 155 may be, for example, an exemplary implementation of the "upper conductive layer" described above.

[0067] The second conductive layer 155 forms a capacitive stack with the first conductive layer 153 and the intervening first insulating layer 154. Capacitive stacks with these types of layers are generally referred to as MIM stacks (from "metal-insulator-metal"), even though the conductive layers can be formed from non-pure metallic materials.

[0068] The second conductive layer 155 is not present below the location P where the aperture has a reduced diameter. Only the portion F of the stacked layers, where the first conductive layer, the first insulating layer, and the second conductive layer are all present, operates as a capacitor. However, at the location P where the aperture diameter is reduced, and below the location P where the aperture diameter is reduced, the lower portion of the first conductive layer covering the aperture wall forms an electrical contact between the functional portion F of the capacitive stack and the underlying interconnect layers 158 and 159.

[0069] Capacitive stacks can be formed by additional layers besides layers 153, 154, and 155. Thus, for example, a capacitive stack can be a MIMIM stack, a MIMIMIM stack, and so on. Typically, when a capacitive stack includes additional layers, the "throat" at the location where the diameter decreases in the aperture becomes closed between the first MIM structure and the second MIM structure. Where the lowest conductive layer does not close the "throat" at the location where the diameter decreases, it is preferable that the throat be closed by the lowest dielectric layer so that the second conductive layer (and the third conductive layer, if present) in the stack does not reach the region below the throat, where cracks in the anti-anodized layer may have an adverse effect. However, if the conductive layer is very thin (e.g., about 5 nm or less), it may simply be the uppermost conductive layer that fails to penetrate the location where the diameter decreases. In the latter example, the lowest conductive layer of a MIMIM or MIMIMIM stack could be, for example, an exemplary implementation of the "lower conductive layer" described above, while the uppermost conductive layer that fails to penetrate the location where the diameter decreases in the aperture could be, for example, an exemplary implementation of the "upper conductive layer" described above.

[0070] The first conductive layer can be made of TiN. Typically, the thickness of the first conductive layer 153 is in the range of 1 nm to 30 nm, and can be, for example, about 10 nm. The material of the first conductive layer 153 is not limited to TiN, and can be made of, for example, TiAlN, TaN, TaAlN, Ru, RuO2, W, Ni, Co, Al, Ag, Au, Cu and Si.

[0071] The first insulating layer can be made of SiO2. Typically, the thickness of the first insulating layer 154 is in the range of 1 nm to 30 nm, and can be, for example, about 5 nm. The material of the first insulating layer 154 is not limited to SiO2, and can be made of, for example, Al2O3, HfO2, ZrO2, TiO2, La2O3, Y2O3, SrTiO3 and their silicates and aluminates, as well as laminated structures.

[0072] The second conductive layer can be made of TiN. Typically, the thickness of the second conductive layer 155 is in the range of 1 nm to 30 nm, and can be, for example, about 10 nm. The material of the second conductive layer 155 is not limited to TiN, and can be made of, for example, TiAlN, TaN, TaAlN, Ru, RuO2, W, Ni, Co, Al, Ag, Au, Cu and Si.

[0073] The anti-anodizing layer 159 can be made of W. Typically, the thickness of the anti-anodizing layer 159 is in the range of 10 nm to 1 µm. The material of the anti-anodizing layer 159 is not limited to W, and can be made of, for example, Ti, Ta, Hf and Nd.

[0074] If provided, the interconnect layer 158 can be made of AlCu. Typically, the thickness of the interconnect layer 158 is in the range of 100 nm to 5 µm, with a thickness of 140 nm or more preferred for ESR considerations. The material of the interconnect layer 158 is not limited to AlCu, and can be made of, for example, Al, AlSi, and AlSiCu.

[0075] The substrate (not shown) can be made of p ++ Made of doped silicon. The substrate material is not limited to p-doped silicon. ++ Doped silicon, and can be made, for example, from n-doped or undoped Si, polycrystalline silicon, and glass substrates.

[0076] The capacitive structures according to the invention can be stacked on top of each other in a manner similar to the capacitive structures described in WO2015 / 063420. Therefore, lateral insulating bands can be provided in this structure, as described in WO2015 / 063420.

[0077] Figure 4 The invention illustrates the fabrication of capacitive structures, for example, according to certain embodiments of the invention. Figure 3 The method shown includes forming a conductive interconnect layer, such as layer 158, on a substrate and forming an anti-anodizing layer, such as layer 159, on the interconnect layer (S1). In this process S1, any suitable deposition technique can be used, such as chemical vapor deposition, physical vapor deposition, etc. If desired, additional layers (not shown) can be provided between the substrate and the interconnect layer 158, and between the interconnect layer 158 and the anti-anodizing layer 159. Therefore, for example, additional layers for improving adhesion can be inserted between the substrate and the interconnect layer 158, and between the interconnect layer 158 and the anti-anodizing layer 159. For example, a laminated structure formed by stacking thin Ti layers and TiN layers can be provided as an adhesion-enhancing layer.

[0078] Then, a (S2) metal layer is formed on the anti-anodization layer using any suitable method, such as chemical vapor deposition, physical vapor deposition, etc. The thickness of this metal layer is typically in the range of 1 µm to 20 µm.

[0079] An anodizing process (S3) is performed to anodize the metal layer region to form a porous anodized oxide region, such as 152a, through which a plurality of elongated holes extending between the anti-anodizing layer and the anodic oxide surface 156 away from the substrate pass. A mask may be used to define the metal region to be anodized.

[0080] Typically, during the anodizing process S3, some undesirable oxide forms at the bottom of the hole. The undesirable oxide is removed to open the bottom of the hole (S4). The oxide can be removed by any suitable technique suitable for the material used as the anti-anodizing layer; for example, by wet etching with pH controlled during the process, etc.

[0081] Next, capacitively stacked layers, such as layers 153, 154, and 155, are conformally deposited on the pores in the porous anolyte region using any suitable method, such as atomic layer deposition, chemical vapor deposition, etc. As described above, the layer thickness can be set to ensure compliance with the above relationship (1).

[0082] As is well known, the operating conditions of the anodizing process can be set and controlled to obtain an array of elongated holes, which on average have the target hole diameter and target hole spacing. Not all holes in the final structure will have the target hole diameter and target hole spacing, but the operating conditions can be set and controlled so that statistically, a greater or lesser percentage of holes will meet the target values. In embodiments of the present invention, the following steps are performed... Figure 4 The method is to generate a capacitive structure, wherein in at least 1% of the pores in the porous anodic oxide region, a first portion of the capacitance of the capacitive stack of layers contributing to the capacitance of the capacitive structure is formed in a portion of the pores at a diameter-limited location within the pores and between the anodic oxide and the surface of the substrate away from the substrate.

[0083] Different techniques can be used to ensure compliance with the above relationship (1). Thus, for example, the anodizing process (S3) can be controlled so that, near the end, when the material in the anti-anodized layer begins to migrate and form an undesirable oxide plug, the lateral dimensions of the oxide plug are controlled, thereby affecting the diameter of the portion of the hole with a restricted diameter.

[0084] Anodizing processes suitable for producing regularly arranged nanoscale pores in anodic oxides are known and therefore will not be described in detail here. However, when such processes are applied during the manufacture of capacitive structures according to embodiments of the invention, it may be advantageous to employ known processes.

[0085] Therefore, for example, the beginning of the stage in which material in the anti-anodized layer begins to migrate and form undesirable oxide plugs can be detected, for example, by measuring the current drawn during the anodizing process. Figure 5 The diagram illustrates a typical pattern of current variation during the anodizing process of an aluminum layer to form anodized aluminum oxide (AAO). The appropriate time to stop anodizing to obtain an oxide plug of a specific width can be determined by measuring the time elapsed after a specific current value has been reached.

[0086] In some embodiments of the invention, the anodizing conditions are intentionally altered midway through the anodizing step to slow the anodizing rate during the period when undesirable oxide plugs form on the anti-anodized layer 158. By slowing the anodizing process at this stage, it is easier to prevent undesirable oxide plugs from forming in the lateral direction (i.e., Figure 3 The dimensions (from left to right) are precisely controlled. An example of a technique that can be used to slow down the anodizing process at this stage is to lower the operating temperature.

[0087] Another technique that can be used to help ensure compliance with the above relationship (1) is to determine the diameter of the hole at the location where the diameter decreases, and then set the thickness of the first conductive layer and the first insulating layer of the capacitive stack based on the diameter at the location where the diameter decreases. In principle, the diameter of the hole at the diameter-restricted location in each individual capacitive structure can be measured after the manufacture of each individual capacitive structure, but time can be saved by conducting experiments in advance to determine the diameter value D produced by a specific set of manufacturing conditions (e.g., for a specific profile of the anodizing process).

[0088] Typically, it is preferable to set the thickness of the conductive and insulating layers of the capacitive stack according to the desired capacitance value of the final structure. Therefore, it is preferable to first design the specifications of the capacitive stack and then control the anodizing process to produce holes with a diameter D at the locations where the diameter is reduced, ensuring compliance with the above relationship (1).

[0089] Although the invention has been described above with reference to certain specific embodiments, it should be understood that the invention is not limited to the specific embodiments described herein. Many changes, modifications, and improvements can be made to the specific embodiments within the scope of the appended claims.

Claims

1. A capacitive structure (150), comprising: A substrate providing a conductive interconnect layer (158); An anti-anodic oxidation layer (159) is formed above the interconnect layer (158) and in electrical contact with the interconnect layer. A region (152a) of porous anodic oxide is formed on the anti-anodic oxide layer (159), and a plurality of elongated holes (151) pass through the region of porous anodic oxide, the plurality of elongated holes (151) extending between the anti-anodic oxide layer (159) and the surface (156) of the anodic oxide away from the substrate. as well as The capacitive stack of layers includes a lower conductive layer (153), a first insulating layer (154), and an upper conductive layer (155), the stack being conformally formed over the holes (151) in the region (152a) of the porous anodic oxide, and the lower conductive layer (153) being in electrical contact with the anti-anodic oxide layer (159); Wherein, the hole (151) has a position along its length where the hole diameter is limited; The feature is that, in a first non-zero percentage of the pores (151) in the region of the porous anodic oxide, the stacked upper conductive layer (155) extends into the pores, not exceeding the position where the pore diameter is limited.

2. The capacitive structure (150) according to claim 1, wherein The stacked lower conductive layer (153) is conformally formed over the hole (151) in the porous region (152a), the first insulating layer (154) is formed on the lower conductive layer (153), and the upper conductive layer (155) is formed on the first insulating layer (154).

3. The capacitive structure (150) according to claim 2, wherein: ， where D is a diameter of the hole (151) at a position where the hole diameter is limited, T c1 is a thickness of the lower conductive layer (153), and T i1 is a thickness of the first insulator layer (154).

4. The capacitive structure (150) according to any one of claims 1 to 3, wherein, The hole diameter is limited at a distance of 10 nm to 300 nm from the bottom of the hole (151).

5. The capacitive structure (150) according to any one of claims 1 to 3, wherein, In at least 1% of the pores (151) of the porous anodic oxide region (152a), the stacked upper conductive layer (155) extends into the pores, not exceeding the location where the pore diameter is limited.

6. The capacitive structure (150) according to any one of claims 1 to 3, wherein, The anti-anodizing layer (159) is made of tungsten.

7. The capacitive structure (150) according to any one of claims 1 to 3, wherein, The average thickness of the anti-anodized layer (159) is in the range of 10 nm to 1 μm.

8. The capacitive structure (150) according to any one of claims 1 to 3, wherein, The anodic oxide is anodic aluminum oxide.

9. A method for fabricating a capacitive structure (150), comprising: A substrate is formed to provide a conductive interconnect layer (158); An anti-anodic oxidation layer (159) is formed above the interconnect layer (158) and is in electrical contact with the interconnect layer (158). A metal layer is formed on the anti-anodizing layer (159); A region of the metal layer is anodized to form a region (152a) of porous anodic oxide through which a plurality of elongated holes (151) extend, the plurality of elongated holes (151) extending between the anti-anodic oxide layer and the surface (156) of the anodic oxide away from the substrate. Remove the oxides formed at the bottom of the pores during the anodizing step from the anti-anodizing layer; as well as A capacitive stack of layers is conformally formed over the pores (151) in the region (152a) of the porous anodic oxide, the layers comprising a lower conductive layer (153), a first insulating layer (154) and an upper conductive layer (155), wherein the lower conductive layer (153) is in electrical contact with the anti-anodic oxide layer (159); Wherein, the hole (151) has a position along its length where the hole diameter is limited; The feature is that at least one of the anodizing step, the oxide removal step, and the capacitive stacking step is controlled such that in at least 1% of the pores in the region of the porous anodized oxide, the stacked upper conductive layer (155) extends into the pores without exceeding the pore diameter limit.

10. The method for fabricating a capacitive structure according to claim 9, wherein, The stacked lower conductive layer (153) is conformally formed over the hole (151) in the region (152a) of the porous anodic oxide, the first insulating layer (154) is formed on the lower conductive layer (153), and the upper conductive layer (155) is formed on the first insulating layer (154).

11. The method for fabricating a capacitive structure according to claim 10, wherein: ， wherein D is a diameter of the hole (151) at a diameter-restricted position, T c1 is a thickness of the lower conductive layer (153), and T i1 is a thickness of the first insulator layer (154).

12. The method for fabricating a capacitive structure according to any one of claims 9 to 11, wherein, The diameter of the hole is limited at a distance of 10 nm to 300 nm from the bottom of the hole (151).

13. The method for fabricating a capacitive structure according to any one of claims 9 to 11, wherein, The anti-anodizing layer (159) is made of tungsten.

14. The method for fabricating a capacitive structure according to any one of claims 9 to 11, wherein, The average thickness of the anti-anodized layer (159) is in the range of 10 nm to 1 μm.

15. The method for fabricating a capacitive structure according to any one of claims 9 to 11, wherein, The anodic oxide is anodic aluminum oxide.

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