Static memory and display driving method thereof

Abstract

The application discloses a static memory and a display driving method thereof. The static memory comprises a static memory array, a latch, a multiplexer and an output circuit. The latch is connected with a bit line of a memory cell, and latches data of a first frame of a static image and maintains a level state when the data of the first frame is read. The multiplexer is connected with the latch, and selects the memory cell storing the data of the first frame. The output circuit is connected with the multiplexer, and outputs the data of the first frame as data of remaining frames according to a time sequence. When data other than the data of the first frame is read, the bit line does not need to be pre-charged again, and power consumption can be reduced.

Description

Technical Field

[0001] This application relates to the field of static storage, specifically to a static memory and its display driving method. Background Technology

[0002] SRAM (Static Random-Access Memory) is an indispensable and important component of electronic systems. Used for temporary storage of data or instructions, SRAM offers advantages such as high speed, low power consumption, and ease of embedded integration, making it the preferred cache device in Central Processing Units (CPUs).

[0003] In modern high-performance processors, SRAM occupies an increasingly larger portion of the chip area. In the coming years, with the explosive growth of mobile internet, the Internet of Things, and wearable electronic devices, chip power consumption will face stringent requirements and severe challenges, with SRAM bearing the brunt. Therefore, how to reduce SRAM power consumption is an urgent problem to be solved in the field of static memory.

[0004] In a display, the Static RAM Cell Array 11 is integrated into the driver IC (also known as the driver chip) and is primarily used to store image data. Each row of the SRAM has a word line (WL), and each column has two bit lines, namely a bit line (BL) and a bit line inverse (BLB), hereinafter collectively referred to as a bit line. When reading data from each row of memory cells, please refer to [link to relevant documentation]. Figure 1 and Figure 2 The word line WL receives the enable signal EN-WL to enable each row of memory cells. The multiplexer (MUX switch) 12 selects the memory cell to be read each time. The sense amplifier (SA) receives the enable signal EN-SA, precharges the bit line BL of the selected memory cell to a high level V-BL, and then outputs the data of the selected memory cell. For memory cells connected to the same word line WL (i.e., located in the same row), before each read of the selected memory cell's data, the word line WL must receive the enable signal EN-WL. Correspondingly, the sense amplifier SA must also receive the enable signal EN-SA and precharge the bit line BL of the selected memory cell to a high level V-BL each time. The driver IC reads data many times, and the multiple precharging consumes a lot of power, which is not conducive to reducing SRAM power consumption. Summary of the Invention

[0005] In view of this, this application provides a static memory and its display driving method to solve the problem of high power consumption of SRAM.

[0006] This application provides a static memory, comprising:

[0007] A static storage array consists of several storage units;

[0008] A latch is connected to the bit lines of multiple memory units connected to the same word line, latches the data of the first frame of a still image, and maintains its output at the level state when reading the data of the first frame, wherein the data of all frames of the still image are stored in multiple memory units connected to the same word line.

[0009] A multiplexer is connected to the latch and selects the storage unit for storing the data of the first frame in the still image;

[0010] The output circuit is connected to the multiplexer and outputs the data of the remaining frames in the static image according to the timing sequence, wherein the data of the first frame in the latched static image is output.

[0011] Optionally, the static memory also includes a sense amplifier connected to two bit lines of each memory cell. The sense amplifier is used to amplify the differential input voltage of the two bit lines into an output voltage, and the latch maintains the two bit lines at the level state when the output voltage is output.

[0012] Alternatively, the sensing amplifier and latch can be integrated into a latching sensing amplifier.

[0013] Optionally, the bit lines of multiple memory cells connected to the same word line are connected to a latch.

[0014] Optionally, the number of latches can be set according to the duration of the latched data.

[0015] Optionally, the data of any two frames in a static image are the same, or the amount of data change is less than a preset threshold.

[0016] This application provides a display driver method, including:

[0017] A storage unit is selected to store the data of the first frame of the static image, and the data of all frames of the static image are stored in multiple storage units connected to the same word line;

[0018] An enable signal is applied to the word line of the static memory array, and the bit line of the selected memory cell is charged to read the data of the first frame in the static image.

[0019] The latch latches the data of the first frame in the static image and maintains the output of the latch at the level when reading the data of the first frame.

[0020] The remaining frames in the static image are output in sequence, wherein the data of the first frame in the static image is latched.

[0021] Optionally, the data of the first frame in the still image is latched, including:

[0022] Amplify the differential input voltage of the two bit lines into the output voltage;

[0023] The latch latches the data of the first frame in the static image and maintains the output of the latch at the level when the output voltage is output.

[0024] Optionally, the bit lines of multiple memory cells connected to the same word line are connected to a latch, and the data of the first frame of the static image is latched by the latch.

[0025] As described above, the static memory and display driving method of this application, after reading the data of the first frame of the static image, the latch not only latches the data of the first frame, but also maintains the level state when reading the data (of the first frame). When reading the data of the remaining frames, the bit lines do not need to be pre-charged again, thus reducing power consumption. Attached Figure Description

[0026] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the specification, serve to explain the principles of this application. To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments are briefly introduced below. Obviously, those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of an existing SRAM in a display.

[0028] Figure 2 This is a timing diagram of signals for reading image data from SRAM in an existing display.

[0029] Figure 3 This is a schematic diagram of the structure of a static memory according to an embodiment of this application;

[0030] Figure 4 yes Figure 3 The diagram shows the equivalent circuit of the static memory.

[0031] Figure 5 This is a timing diagram of the signals for reading image data from SRAM in this application;

[0032] Figure 6This is a schematic flowchart of a display driving method according to an embodiment of this application. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are described clearly and completely below with reference to specific embodiments and corresponding drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the following description, the various embodiments and their technical features can be combined with each other unless otherwise specified.

[0034] Considering that in the current process of reading image data from SRAM, the two bit lines connected to the storage unit need to be pre-charged (to a high level) for each frame of data read by the driver IC, the more times the driver IC reads data, the more pre-charging is required, resulting in greater power consumption and hindering the reduction of SRAM power consumption. To address this, this embodiment of the application, after reading the data of the first frame of a static image, latches the data of the first frame using a latch and maintains the output of the latch at the level at which the data of the first frame was read. When reading the data of the remaining frames, the bit lines do not need to be pre-charged again, thereby reducing power consumption.

[0035] Figure 3 This is a schematic diagram of the structure of a static memory according to an embodiment of this application. Figure 4 yes Figure 3 The diagram shows the equivalent circuit of the static memory. Please refer to it as well. Figure 3 and Figure 4 The static memory 20 includes a static memory array (SRAM CellArray) 21, a latch 22, a multiplexer (MUX Switch) 23, and an output circuit (Data output) 24.

[0036] The static storage array 21 can be an SRAM used to store data for each frame of an image, or related instructions for the display during image display. The static storage array 21 includes several storage cells 21a, which can be arranged in an array. Each row of storage cells 21a is connected to the same word line WL, and each storage cell 21a in each column is connected to two bit lines, namely a bit line BL and a bit line BLB. For ease of description, this application will hereinafter refer to it as two bit lines BL.

[0037] For memory cells 21a connected to the same word line WL, latch 22 is connected to the two bit lines BL of each memory cell 21a. For example... Figure 4 As shown, the two bit lines BL of each row of storage cell 21a are connected to the same latch 22.

[0038] The latch 22 has the following two main functions:

[0039] 1. Latching the data of the first frame in a still image. Latch 22 has a buffering function. After the word line WL is opened, the storage unit 21a outputs the data of the first frame through the two bit lines BL, and latch 22 buffers it.

[0040] 2. The output of latch 22 is maintained at the same level as when the data of the first frame was read. The output of latch 22 does not change with the level of the input. Therefore, when reading the data of the first frame, the output of latch 22 maintains a certain level, and this level is maintained when outputting the data of the remaining frames. Thus, all bit lines BL connected to the output of latch 22 do not need to be charged to maintain this level.

[0041] In one implementation, the static memory 20 may further include a sense amplifier 25 connected to the two bit lines BL of each memory cell 21a. The sense amplifier 25 is used to amplify the differential input voltage of the two bit lines BL into an output voltage. For example, when reading the data of the first frame, the output voltage of the two bit lines BL of a certain memory cell 21a is V1, and the output of the latch 22 is maintained at this level.

[0042] Alternatively, the sensing amplifier 25 and the latch 22 can be integrated into a latching sensing amplifier.

[0043] Multiplexer 23 is connected to latch 22 and is used to select the storage unit that stores the data of the first frame in the still image. That is, multiplexer 23 is used to select storage unit 21a that stores the data of the first frame and connect the read channel of storage unit 21a. Multiplexer 23 is equivalent to a switch, connecting storage unit 21a, which is to be read, to output circuit 24, so as to transmit the data to be read to output circuit 24.

[0044] The output circuit 24 is connected to the multiplexer 23 and outputs the data of the remaining frames in the static image according to the timing sequence, wherein the data of the first frame in the latched static image is output.

[0045] In a static image, the data of any two frames are the same, or the data change is less than a preset threshold. For example, in scenarios where the image is relatively simple or in news reading, the image changes little. Therefore, the changes between the remaining frames and the first frame are minimal. Thus, according to the timing sequence, the data of the first frame is used as the data of the remaining frames and displayed. This can reduce the frame rate of the static image. For example, during normal display, the driver IC refreshes the image at a frame rate of 50Hz to 60Hz. However, in this embodiment, the frame rate is reduced from 50Hz to 60Hz to 10Hz, or even less than 10Hz, thereby reducing the frequency at which the driver IC refreshes the image and reducing current consumption.

[0046] Please see Figure 5 The word line driver 27 applies an enable signal EN-WL to the word line WL. During the stage of reading the data of the first frame in the still image, the word line WL receives the enable signal EN-WL to control the memory cell 21a of a certain row to be turned on. The sense amplifier 25 (or latch-type sense amplifier) ​​receives the enable signal EN-SA to amplify the differential input voltage of the two bit lines BL into the output voltage. The two bit lines BL of the memory cell 21a of that row are precharged until they reach the high level V-BL, and the data of the first frame is output. Then, the latch 22 (or latch-type sense amplifier) ​​receives the enable signal EN-LA, latches the data of the first frame, and maintains the level state when reading the data of the first frame.

[0047] During the stage of reading the data of the second frame in the still image, latch 22 (or latch-type sensor amplifier) ​​receives the enable signal EN-LA. Latch 22 uses the data of the latched first frame as the data of the second frame and outputs it to output circuit 24. Output circuit 24 then outputs it to control block 26 of static memory 20, where it is displayed under the control of control block 26. Similarly, during the stage of reading the data of the remaining frames in the still image, latch 22 (or latch-type sensor amplifier) ​​receives the enable signal EN-LA and outputs the data of the first frame as the data of the corresponding frame.

[0048] Therefore, after reading the data of the first frame in the static image, the latch 22 not only latches the data of the first frame, but also maintains the level state when reading the data (of the first frame). When reading the data of the remaining frames in the static image, the bit line BL does not need to be pre-charged again, thus reducing power consumption.

[0049] The latch duration (the duration of latching data) of latch 22 is limited. Therefore, the number of latches 22 can be set according to the latch duration of a single latch 22. For example, in the scenario where the same row of storage unit 21a is connected to a latch 22, the latch duration of the latch 22 is longer than the duration of reading data from all frames in the still image.

[0050] This application also provides a display driving method, please refer to the embodiments therein. Figure 6 The display driving method may include the following steps S11 to S14.

[0051] S11: Select the storage unit to store the data of the first frame of the still image. The data of all frames of the still image are stored in multiple storage units connected to the same word line.

[0052] S12: Apply an enable signal to the word line of the static memory array and charge the bit line of the selected memory cell to read the data of the first frame of the static image.

[0053] S13: The latch latches the data of the first frame of the static image and maintains the output of the latch at the level when reading the data of the first frame.

[0054] S14: Output the data of the remaining frames in the static image according to the time sequence, where the data of the first frame in the latched static image is output.

[0055] After reading the data of the first frame in a still image, the latch not only latches the data of the first frame, but also maintains the level state at which the data (of the first frame) was read. When reading the data of the remaining frames, the bit lines do not need to be precharged again, thus reducing power consumption.

[0056] In the display driving method, the execution entity of each step can be the corresponding component in the aforementioned static memory 20. For example, the storage unit storing the data of the first frame in the static image can be selected by the multiplexer 23, the word line driving unit 27 can apply the enable signal EN-WL to the word line WL, the latch 22 uses the data of the latched first frame as the data of the remaining frames and outputs it to the output circuit 24, and then the output circuit 24 outputs it to the control module 26 of the static memory 20 for final display.

[0057] The above description is only a part of the embodiments of this application and does not limit the patent scope of this application. All equivalent structural transformations made using the content of this specification and drawings are similarly included in the patent protection scope of this application.

[0058] Without further restrictions, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same name in different embodiments may have the same meaning or may have different meanings, the specific meaning of which needs to be determined by its interpretation in that specific embodiment or by further consideration of the context of that specific embodiment.

[0059] Furthermore, although this document uses terms such as "first," "second," and "third" to describe various types of information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. The singular forms "a," "an," and "the" used herein are intended to also include the plural forms. The terms "or" and "and / or" are interpreted as inclusive, or meaning either one or any combination thereof. Exceptions to this definition only occur when combinations of elements, functions, steps, or operations are inherently mutually exclusive in some way.

Claims

1. A static memory, characterized by, The static storage array comprises: a static storage array comprising a plurality of memory cells; a latch connected to two bit lines of a plurality of memory cells connected to the same word line, and latching data of a first frame of a static image, and maintaining an output end of the latch at a level state when reading the data of the first frame; a multiplexer connected to the latch, and selecting the memory cell storing the data of the first frame of the static image; an output circuit connected to the multiplexer, and outputting data of remaining frames of the static image in a time sequence, wherein the data of the first frame of the static image is latched and outputted, and the two bit lines do not need to be pre-charged when reading the data of the remaining frames of the static image, and the latch maintains the two bit lines at a level state when outputting corresponding voltages.

2. The static memory of claim 1, wherein, The static storage array further comprises a sense amplifier connected to the two bit lines of each memory cell, and the sense amplifier is configured to amplify a differential input voltage of the two bit lines into an output voltage, and the latch maintains the two bit lines at a level state when outputting the output voltage.

3. The static memory of claim 2, wherein, The sense amplifier and the latch are integrated into a latch-type sense amplifier.

4. The static memory of claim 1, wherein, The bit lines of the plurality of memory cells connected to the same word line are connected to one of the latches.

5. The static memory of claim 1, wherein, The number of the latches is set according to a time length of latching data of the latch.

6. The static memory of claim 1, wherein, Data of any two frames of the static image is the same, or a data variation is less than a preset threshold.

7. A display driving method, comprising: The static storage array comprises: a plurality of memory cells connected to the same word line, and storing data of all frames of a static image; applying an enable signal to a word line of the static storage array, and charging two bit lines of a selected memory cell to read data of a first frame of the static image; latching the data of the first frame of the static image by a latch, and maintaining an output end of the latch at a level state when reading the data of the first frame; outputting data of remaining frames of the static image in a time sequence, wherein the data of the first frame of the static image is latched and outputted, and the two bit lines do not need to be pre-charged when reading the data of the remaining frames of the static image, and the latch maintains the two bit lines at a level state when outputting corresponding voltages.

8. The method of claim 7, wherein, The latching the data of the first frame of the static image comprises: amplifying a differential input voltage of the two bit lines into an output voltage; latching the data of the first frame of the static image, and maintaining the output end of the latch at a level state when outputting the output voltage.

9. The method of claim 7, wherein, The bit lines of the plurality of memory cells connected to the same word line are connected to one of the latches, and the data of the first frame of the static image is latched by the one latch.

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