Passive compensation for electrical distance

Abstract

This application relates to passive compensation for electrical distance. An architecture of a memory device can utilize a transmission path resistance compensation scheme for memory cells to reduce the effect of parasitic loading when accessing memory cells. The memory cells of this memory device can experience a total resistance that includes a transmission path resistance associated with a respective access line of the memory cells and an additional compensation resistance. The aforementioned memory device can utilize a spike mitigation scheme to mitigate the deleterious effects of voltage and / or inrush current on nearby memory cells of the memory device. Additionally, a spike mitigation circuit can include a resistor coupled on an access line near a respective decoder. Furthermore, a spike mitigation circuit can include a resistor coupled between the decoders.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to memory devices, and particularly to passive compensation for electrical distance. BACKGROUND

[0002] This section is intended to introduce the reader to various aspects of art that can be related to various aspects of the various technologies described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.

[0003] Generally, a computing system includes processing circuitry, such as one or more processors or other suitable components, and memory devices, such as chips or integrated circuits. One or more memory devices can be used on a memory module, such as a dual in-line memory module (DIMM), to store data that can be accessed by the processing circuitry. For example, based on user input to the computing system, the processing circuitry can request that the memory module retrieve data corresponding to the user input from its memory devices. In some cases, the retrieved data can include firmware, or instructions that can be executed by the processing circuitry to perform an operation, and / or can include data that is to be used as input to the operation. Additionally, in some cases, data output from the operation can be stored in memory, so as to enable subsequent retrieval of the data from the memory.

[0004] Some memory devices include memory cells that are accessed by turning on a transistor that couples the memory cell (e.g., a capacitor) with a word line or a bit line. In contrast, threshold-type memory devices include memory devices that are accessed by providing a voltage across the memory cell, where a data value is stored based on a threshold voltage of the memory cell. For example, the data value can be based on whether the threshold voltage of the memory cell is exceeded, and the memory cell conducts current in response to the voltage provided across the memory cell. The stored data value can be changed, for example, by applying a voltage sufficient to change the threshold voltage of the memory cell.

[0005] For threshold-type memory, word lines and bit lines are used to transmit selection signals to respective memory cells. The selection signals can include signals characterized by voltage levels used to save data into or retrieve data from the memory cells. The word lines and bit lines can be coupled to a source of the selection signals by a decoding circuit, such as a decoder. In a standard “buried” architecture, the decoder can be coupled to one side of the word lines or one side of the bit lines.

[0006] Standard architectures of memory cells in memory devices can cause different memory cells to have different physical distances on word lines and bit lines from decoders. The word lines and bit lines can each introduce parasitic resistances on the memory cells depending on the location of the memory cells on the word line drivers or bit line drivers. Memory cells disposed relatively farther away from the decoders on the respective word lines or bit lines can suffer from higher parasitic resistances introduced by the word lines or bit lines. However, memory cells disposed closer to the decoders of the respective word lines or bit lines can experience lower parasitic resistances. Moreover, due to the parasitic resistances introduced by the word lines and bit lines, the memory cells can experience net resistances. That is, due to the different distances of the memory cells from the decoders on their respective word lines and bit lines, different memory cells can experience different net parasitic resistances. Subsequently, during programming due to high resistance paths to the decoders, memory cells disposed relatively farther away from the decoders on the word lines or bit lines can suffer from low current delivery amplitudes on the word lines or bit lines. Methods for uniform current delivery from the decoders to the memory cells can be needed. SUMMARY

[0007] One aspect of the disclosure provides an apparatus, wherein the apparatus comprises: a memory array; a plurality of memory cells disposed at designated locations in the memory array; a first plurality of access lines, wherein a first access line of the first plurality of access lines associated with accessing a target memory cell comprises a first current path configured to provide access to the target memory cell, and wherein the first current path comprises a first parasitic resistance associated with accessing the target memory cell; and a second plurality of access lines, wherein a second access line of the second plurality of access lines associated with accessing the target memory cell comprises a second current path configured to provide access to the target memory cell on a second side, and wherein the second current path comprises a second parasitic resistance associated with accessing the target memory cell and a first compensating resistance associated with accessing the target memory cell.

[0008] Another aspect of the disclosure provides a method for applying uniform resistance when accessing memory cells of a memory array, wherein the method comprises: compensating for a parasitic resistance associated with accessing a memory cell on a second access line on a first access line associated with accessing the memory cell, wherein the compensation on the first access line comprises applying an additional resistance on the first access line; and compensating for a parasitic resistance associated with accessing the memory cell on the first access line on the second access line, wherein the compensation on the second access line comprises applying an additional resistance on the second access line.

[0009] Another aspect of the disclosure provides a semiconductor device, wherein the semiconductor device comprises: a memory array comprising a plurality of memory cells, wherein a resistance associated with accessing a first memory cell of the plurality of memory cells is configured to be independent of a location of the first memory cell in the memory array; a first plurality of access lines, wherein the first plurality of access lines is configured to access a first portion of the plurality of memory cells on a first side of the memory array, wherein a first access line of the first plurality of access lines is configured to provide a first access signal to access a second memory cell of the first portion of the first plurality of memory cells, and wherein a voltage associated with the first access signal is independent of a location of the second memory cell in the memory array. BRIEF DESCRIPTION OF DRAWINGS

[0010] Various aspects of the disclosure can be better understood after a reading of the following detailed description together with the drawings wherein:

[0011] Figure 1 is a block diagram of a portion of a memory according to an embodiment;

[0012] Figure 2 is a diagram of a portion of a memory according to an embodiment Figure 1

[0013] Figure 3 is a portion of a decode circuit that can be used in Figure 1 Figure 2 is a particular embodiment of a memory array of

[0014] Figure 4 is a diagram of a portion of a memory according to an embodiment Figure 1

[0015] Figure 5 is a portion of a memory array according to an embodiment Figure 2

[0016] Figure 6 is a block diagram of a portion of a memory according to an embodiment Figure 1

[0017] Figure 7 is a schematic diagram depicting a first embodiment associated with the block diagram of Figure 6

[0018] Figure 8 is a schematic diagram depicting a second embodiment associated with the block diagram of Figure 6 DETAILED DESCRIPTION ​​​​​​​

[0019] In introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there can be additional elements other than the listed elements. One or more particular embodiments of the present application described herein will be described below. In an effort to provide a concise description of these embodiments, all features of an actual implementation can not be described in the specification. It should be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which can vary from one implementation to another. Moreover, it should be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill in the art having the benefit of this disclosure.

[0020] The memory generally includes an array of memory cells, where each memory cell is coupled to at least two access lines. For example, a memory cell can be coupled to a bit line and a word line. As such, each access line can be coupled to a large number of memory cells. To select a memory cell, a decoder circuit associated with a first access line for the memory cell and a decoder circuit associated with a second access line for the memory cell can provide both a voltage and / or a current on the respective access lines. By applying the voltage and / or current to the respective access lines, the memory cell can be accessed in order to write data to the memory cell and / or read data from the memory cell.

[0021] Because each access line can be coupled to a large number of memory cells, each memory cell can be at a different physical distance from the respective decoder circuit of the access line. Further, because the distance between a memory cell and a source of a select signal can vary, the parasitic load associated with each memory cell can vary based on the distance. The parasitic load can include the resistance of the metal traces used to form the access line, as well as the parasitic capacitance associated with both the metal traces and the associated decoder circuit. As such, due to the different physical distances from the respective decoder circuit of the access line, each memory cell can have a different associated transmission path resistance or parasitic resistance that is non-negligible. When the respective decoder circuit provides a voltage and / or current to the respective access line of each memory cell, the transmission path resistance associated with each memory cell can affect the voltage and / or current (e.g., select signal) received by each memory cell. That is, while the voltage provided by the decoder circuit to the access line can be the same for each memory cell associated with the access line, the voltage received by a particular memory cell and the voltage delay associated with the received voltage can vary along the same access line from other memory cells. This is due to the location of the memory cell along the access line relative to the decoder circuit (e.g., the physical distance between the decoder circuit and the memory cell), the received voltage at the memory cell can vary at least in part.

[0022] In view of the foregoing, when providing a select signal to a memory cell, a larger voltage and / or current can be used to compensate for any transmission path resistance affecting a memory cell disposed at an end of an access line. However, this can result in current spikes and / or voltage spikes (e.g., a voltage or current greater than a threshold amount of voltage or current) being delivered to memory cells disposed closer to the decoder. Accordingly, it can be desirable to improve the design of a memory cell array to improve the delivery of select signals (e.g., reduce the likelihood and / or occurrence of current spikes and / or voltage spikes).

[0023] According to embodiments described herein, an architecture of a memory device can utilize a transmission path resistance compensation scheme for memory cells to reduce the impact of parasitic loads in accessing memory cells. The memory cells of the memory device can experience a total resistance that includes the transmission path resistance associated with the respective access line of the memory cell and an additional compensation resistance. The memory device can compensate for the transmission path resistance of the respective bit line and respective word line of the memory cell using a transmission path resistance compensation scheme as described in detail below.

[0024] At access of each memory cell, a compensation resistance can be applied to any of the access lines of the memory cell, which can be proportional to the transmission path resistance of the opposite access line of the memory cell. In some embodiments, a memory device can include a predetermined total resistance associated with accessing a memory cell, and can include the transmission path resistance of the respective access line of a target memory cell and the applied compensation resistance. In these embodiments, the compensation resistance applied to the access line can be inversely proportional to the transmission path resistance of the opposite access line to apply the predetermined total resistance. In view of the foregoing, the compensation resistance can be applied externally and / or passively to the access line.

[0025] The compensation resistance value can depend on the physical distance of the memory cell being accessed from the respective decoding circuit. In some instances, the compensation resistance can cause the total resistance of each memory cell of the memory device to be approximately equal to the transmission path resistance of the full length of the bit line and word line of the respective memory device. That is, the compensation resistance can proportionally increase the total resistance of the memory cell to cause the total resistance of each memory cell to be approximately equal to the transmission path resistance between the decoder and the farthest memory cell of the memory device.

[0026] The transmission path resistance compensation scheme can allow the decoders of a memory device to provide the same voltage and / or current to access different memory cells. Moreover, due to the equal total resistance of each memory cell, each memory cell can receive an equal voltage and / or current regardless of its physical distance to the respective decoder. The transmission path resistance compensation scheme can require the decoders to provide a voltage and / or current proportional to the voltage and / or current required to access the farthest memory cell to access different memory cells of such memory device.

[0027] In some embodiments, the voltage provided by the decoders for accessing the memory cells on the respective bit lines and / or word lines can initially include a higher voltage and / or current (e.g., a voltage spike, a surge current, or both). In these embodiments, the memory cells near the decoders can experience a voltage spike, a current surge, or both, which can be undesirable or even detrimental to the near memory cells.

[0028] The foregoing embodiments of the memory device can utilize a spike mitigation scheme to mitigate the deleterious effects of the voltage and / or surge current on the near memory cells of the memory device. In one embodiment, a spike mitigation circuit can include a resistor coupled on the access line near the respective decoder. In other embodiments, the spike mitigation circuit can include a resistor coupled between the decoders. Moreover, different embodiments can include selective coupling of one or more resistors on the access lines near the decoders and / or between the decoders. Particular embodiments of this architecture are described below.

[0029] In view of the foregoing, Figure 1is a block diagram of a portion of a memory 100. The memory 100 can be any suitable form of memory, such as non-volatile memory (e.g., cross-point memory) and / or volatile memory. The memory 100 can include one or more memory cells 102, one or more bit lines 104 (e.g., 104-0, 104-1, 104-2, 104-3), one or more word lines 106 (e.g., 106-0, 106-1, 106-2, 106-3), one or more word line decoders 108 (e.g., word line decode circuitry), and one or more bit line decoders 110 (e.g., bit line decode circuitry). The memory cells 102, bit lines 104, word lines 106, word line decoders 108, and bit line decoders 110 can form a memory array 112.

[0030] Each of the memory cells 102 can include a selector and / or a storage element. When a voltage across the selector of a respective memory cell reaches a threshold value, the storage element can be accessed to read a data value from the storage element and / or write a data value to the storage element. In some embodiments, each of the memory cells 102 can not include a separate selector and storage element, and have a configuration such that the memory cell still functions as having a selector and storage element (e.g., can include using a material that behaves similar to both a selector material and a storage element material). When the memory cells 102 have a single material that functions as both a selector and a storage element, these architectures can utilize a single material (e.g., chalcogenide) process architecture, and can have respective values set within each memory cell by setting a logic high value in the memory cell using a positive signal (e.g., positive voltage, positive current) and clearing the logic high value or setting a logic low value in the memory cell by using a negative signal or lower voltage signal (e.g., negative voltage, negative current). During operation of the memory 100, the single material process architecture can use a bipolar decoder (e.g., drive circuitry) to access the memory cells. In some cases, such as when a neutral midpoint between a positive signal level and a negative signal level is shifted to equal half a voltage difference between the bit lines 104 and the word lines 106, a unipolar decoder can be used.

[0031] For ease of discussion, the bit lines 104, word lines 106, word line decoders 108, and bit line decoders 110 can be discussed with respect to a single bit line 104, a single word line 106, a single word line decoder 108, and a single bit line decoder 110, but these designations are non-limiting. The scope of the disclosure should be understood to cover memory cells 102 coupled to multiple access lines and accessed by respective decoders, where the access lines can be used to store data into the memory cells and read data from the memory cells. Figure 1

[0032] ​The bit line decoders 110 can be organized into groups of decoders. For example, the memory 100 can include a first group of bit line decoders 114 (e.g., a plurality of bit line decoders 110) and / or a second group of bit line decoders 116 (e.g., a different plurality of bit line decoders 110). Similarly, the word line decoders 108 can also be arranged into groups of word line decoders 108, e.g., a first group of word line decoders 118 and / or a second group of word line decoders 120. In different embodiments, a group of bit line decoders 114 and 116 and / or a group of word line decoders 118 and 120 can be referred to as a decoder segment. The decoders can be used in combination with one another to drive the memory cells 102 (e.g., in pairs and / or pairs on either side of the word lines 106 and / or the bit lines 104). For example, the bit line decoder 110-3 can operate in conjunction with the bit line decoder 110'-3 and / or in conjunction with the word line decoders 108-0, 108'-0 to select the target memory cell 102-A. As can be appreciated herein, the decoder circuitry on either end of the word lines 106 and / or the bit lines 104 can be different.

[0033] In some embodiments, to reduce or eliminate the occurrence of voltage spikes and / or current surges when selecting and / or accessing a target memory cell, and thereby improve the operation of the memory 100, a spike mitigation scheme can be used between the bit lines 104, the word lines 106, and the respective word line decoders 108 and bit line decoders 110 when operating the memory 100. For example, when targeting the memory cell 102-A, the memory 100 can activate one or more resistors located proximate to the word line decoders 108-0 and 108'-0 and the bit line decoders 110-3 and 110'-3 to mitigate the effects of possible voltage spikes for the respective decoders. Reference can be made to Figures 6-8 The selection and location of the resistors are discussed in further detail. This can allow for the expected voltage or current to be delivered to the memory cell while mitigating the deleterious effects of possible voltage / current spikes on the memory cell proximate to the decoders.

[0034] Each of the bit lines 104 and / or word lines 106 can be a metal trace disposed in the memory array 112 and formed of a metal such as copper, aluminum, silver, tungsten, etc. Thus, the bit lines 104 and word lines 106 can have a uniform resistance per length and a uniform parasitic capacitance per length, such that the resulting parasitic load can increase uniformly per length. As such, the transmission path resistance of each of the memory cells 102 can differ relative to each of the word line decoders 108 and / or bit line decoders 110 due, at least in part, to differences in physical distance between each of the memory cells 102 and associated decoding circuitry. It should be noted that the depicted components of the memory 100 can include additional circuitry not specifically depicted and / or can be disposed in any suitable arrangement. For example, a subset of the word line decoders 108 and / or bit line decoders 110 can be disposed intermediate or at both ends of the bit lines 104 and / or word lines 106 of the memory array 112 and / or on different physical sides of any plane of circuitry.

[0035] These parasitic effects can affect the driving of the decoding circuitry when accessing the memory cells 102, as accessing (e.g., thresholding) a target memory cell 102 can include supplying a voltage and / or current to the target memory cell, such as the target memory cell 102-A. The inconsistent parasitic resistance between the memory cells 102 can make driving selection of the memory cells 102 difficult, as a signal received by a relatively close memory cell can be greater than a signal received by a relatively far memory cell. Thus, conventional approaches can use a relatively large signal when accessing a far memory cell relative to the decoders. As such, the word line decoders 108 and / or bit line decoders 110 can access a far memory cell by providing a higher voltage and / or current to adjust the voltage across the target memory cell (e.g., the target memory cell 102-A) to achieve a threshold voltage.

[0036] For example, a ground reference voltage can be provided on the bit line 104-3, while a positive voltage is provided on the word line 106-0, such that the voltage difference between the ground voltage and the positive voltage is greater than a threshold voltage. However, when the distance between the memory cells 102 causes the resistance of the transmission path taken by the signal (e.g., a particular length of the bit line and / or word line) to be inconsistent between the memory cells 102, some of the resulting transmission voltage and / or current provided to each of the memory cells 102 can vary based on the resistance of the transmission path used to transmit the signal. Thus, the memory 100 can include a transmission path resistance compensation scheme to allow for uniform provision and reception of voltages between the decoding circuitry (e.g., a subset of the word line decoders 108 and / or bit line decoders 110) and the different memory cells 102 of the memory 100, as described below with reference to Figure 3 and 4 .

[0037] Memory 100 can also include control circuitry 122. Control circuitry 122 can be communicatively coupled to respective word line decoders 108 and / or bit line decoders 110 to perform memory operations, such as by causing the decoding circuitry to generate or provide selection signals (e.g., selection voltages and / or selection currents) for selecting a target of memory cells. In some embodiments, a positive voltage and a negative voltage can be provided to a target memory cell of memory cells 102 on one or more of bit lines 104 and / or word lines 106. In some embodiments, the decoder circuitry can provide an electrical pulse (e.g., a voltage and / or a current) to an access line that accesses the target memory cell. The electrical pulse can be a rectangular pulse, or in other embodiments, other shapes of pulses can be used. In some embodiments, the voltage provided to the access line can be a constant voltage.

[0038] Activating the decoder circuitry can enable control circuitry 122 to access a data storage region of the target memory cell in order to read from or write to the data storage region, delivering an electrical pulse to target memory cell 102-A. Control circuitry 122 receives control signals (e.g., selection inputs) that can determine which of a respective pair of bit line decoders 110 and / or word line decoders 108 to activate first. The control signals can be based on which of bit line decoders 110 and word line decoders 108 is physically farther and / or closer to target memory cell 102-A. The relative physical distance from the decoder circuitry to the target memory cell can be based on a memory address of the target memory cell. The order in which the decoder circuitry is activated can be determined by various other logic of memory 100 (not shown in the figure), such as control logic that receives address information.

[0039] After accessing the target memory cell 102-A, data stored in the storage medium of the target memory cell can be read or written. Writing to the target memory cell can include changing a data value stored by the target memory cell. As previously discussed, a data value stored by a memory cell can be based on a threshold voltage of the memory cell. In some embodiments, a memory cell can be "set" to have a first threshold voltage, or can be "reset" to have a second threshold voltage. A set memory cell can have a lower threshold voltage than a reset memory cell. By setting or resetting a memory cell, different data values can be stored by the memory cell. Reading the target memory cell 102-A can include determining whether the target memory cell is characterized by the first threshold voltage and / or by the second threshold voltage. In this way, a threshold voltage window can be analyzed to determine a value stored by the target memory cell 102-A. The threshold voltage window can be created by applying a programming pulse having an opposite polarity to the memory cell 102 (e.g., specifically to a select / storage material (SD) of the memory cell) and reading the memory cell 102 (e.g., specifically reading a threshold voltage of the memory cell) using a signal having a given (e.g., known) fixed polarity.

[0040] In some cases, to access the target memory cell 102-A, the respective ones of the bit line decoders 110 and the word line decoders 108 that are farther from the target memory cell 102-A can be activated by the control circuit 122. For example, the bit line decoder and the word line decoder that are farthest from the target memory cell 102-A (e.g., the bit line decoder 110'-0 and the word line decoder 108-3) can provide a voltage via a transmission path that is characterized as a large parasitic load (e.g., has a higher resistance) due to the large physical distance between the target memory cell 102-A and the bit line decoder 110'-3 or the word line decoder 108-3. The transmission path that is characterized as a large parasitic load and / or resistance can reduce the impact of a current spike created when accessing the target memory cell 102-A. Additionally or alternatively, after selecting the target memory cell 102-A, the control circuit 122 can operate to activate the bit line decoder and the word line decoder that are closest to the target memory cell 102-A to cause current to be delivered to the target memory cell 102-A. The current can be a maximum current that can be provided by the decoders and / or associated with a given (e.g., known) fixed polarity used to read or write to the SD material of the target memory cell 102-A. The delivery of current from the second decoders can occur after a kickback of the memory cell 102-A.

[0041] Figure 2is a diagram illustrating a portion of a memory array 200 in accordance with embodiments of the present disclosure. The memory array 200 can be a cross-point array including word lines 106 (e.g., 106-0, 106-1,..., 106-N) and bit lines 104 (e.g., 104-0, 104-1,..., 104-M). Memory cells 102 can be located at each of the intersections of the word lines 106 and the bit lines 104. The memory cells 102 can function in a two-terminal architecture (e.g., where a particular one of the word lines 106 and the bit lines 104 acts as an electrode for a particular one of the memory cells 102). It should be noted, Figure 2 The memory array 200 of FIG. 1 is by way of example and relates to a particular embodiment of the memory 100. Different memory array arrangements can be used in different embodiments of the present disclosure.

[0042] Each of the memory cells 102 can be a resistive variable memory cell, such as a resistive random access memory (RRAM) cell, a conductive-bridge random access memory (CBRAM) cell, a phase change memory (PCM) cell, and / or a spin-transfer torque magnetic random access memory (STT-RAM) cell, among other types of memory cells. Each of the memory cells 102 can include a memory element (e.g., a memory material) and a selector element (e.g., a select / storage material (SD)), and / or a layer of material that functionally replaces separate memory element and selector element layers. The selector element (e.g., the SD material) can be disposed between a word line contact and a bit line contact associated with a word line or a bit line forming the memory cell 102. When a read or write operation is performed on the memory cell 102, an electrical signal can be transmitted between the word line contact and the bit line contact.

[0043] The selector element can be a diode, a non-ohmic device (NOD), or a chalcogenide switching device, among others, or formed similarly to the underlying cell structure. In some examples, the selector element can include a selector material, a first electrode material, and a second electrode material. The memory element of the memory cell 102 can include a memory portion (e.g., a portion that is programmable to different states). For example, in a resistive variable memory cell, the memory element can include a portion of the memory cell having a resistance that is programmable to a particular level corresponding to a particular state in response to an applied programming voltage and / or current pulse. In some embodiments, the memory cell 102 can be characterized as a threshold type memory cell that is selected (e.g., activated) based on a voltage and / or current across a threshold associated with the selector element and / or the memory element. Embodiments are not limited to one or more particular resistive variable materials associated with the memory element of the memory cell 102. For example, the resistive variable material can be a chalcogenide formed from a variety of doped or undoped chalcogenide-based materials. Other examples of resistive variable materials that can be used to form the memory element include bi-stable metal oxide materials, giant magnetoresistive materials, and / or various polymer-based resistive variable materials, among others.

[0044] In operation, the memory cells 102 can be programmed by applying a voltage (e.g., a write voltage) across the memory cells 102 via the selected word lines 106 and bit lines 104. Sensing (e.g., read) operations can be performed to determine the state of one or more memory cells 102 by sensing a current. For example, in response to a particular voltage applied to a selected one of the word lines 106 forming a respective memory cell 102, a current can be sensed on one or more bit lines 104 corresponding to the respective memory cell 102.

[0045] As illustrated, memory array 200 can be arranged in a cross-point memory array architecture (e.g., a three-dimensional (3D) cross-point memory array architecture) that extends in any direction (e.g., x-axis, y-axis, z-axis). Multi-level cross-point memory array 200 can include a plurality of contiguous memory cells (e.g., 102B, 102C) disposed between alternating (e.g., interleaved) levels of bit lines 104 and word lines 106. The number of levels can increase in number or can decrease in number, and should not be limited to the depicted volume or arrangement. Each of memory cells 102 can be formed between a word line 106 and a bit line 104 (e.g., between two access lines) such that a respective one of memory cells 102 can be directly electrically coupled (e.g., serially electrically coupled) with its respective pair of bit line 104 and word line 106, and / or formed by electrodes (e.g., contacts) made of respective portions of metal in the respective pair of bit line 104 and word line 106. For example, memory array 200 can include a three-dimensional matrix of individually addressable (e.g., randomly accessible) memory cells 102 that can be accessed at a granularity of as small as a single storage element and / or multiple storage elements for data operations (e.g., sensing and writing). In some cases, memory array 200 can include more or fewer bit lines 104, word lines 106, and / or memory cells 102 than shown in the example. Figure 2

[0046] It should be noted that memory array 200 is with reference to certain embodiments of the present disclosure. The embodiments described below can be incorporated into memory 100 using memory array 200 or any other feasible memory array.

[0047] Figure 3 A portion of decoding circuit 300 is depicted that can be used in a particular embodiment of memory 100 that includes memory array 112. Figure 1 Figure 2 Figure 1 Figure 1

[0048] ​​​​​Decoding circuit 300 may include a positive global bit line 306-A and a negative global bit line 306-B, which can drive a first local bit line 308 and a second local bit line 310. Decoding circuit 300 may also include a positive global word line 312-A and a negative global word line 312-B, which can drive a first local word line 314 and a second local word line 316 in the illustrated portion of memory array 200. Second-level decoder circuit 318 or an external decoder may control global bit lines, such as global bit lines 306-A and 306-B or global word lines 312-A and 312-B. Furthermore, first-level decoder circuit 320 or an internal decoder may control local bit lines (e.g., the first local bit line 308 or the second local bit line 310) or local word lines (e.g., the first local word line 314 or the second local word line 316). In different embodiments, switching circuits (e.g., transistors) may be used to implement second-level decoder circuit 318 and first-level decoder circuit 320.

[0049] In some embodiments, global bit lines 306-A and 306-B may drive the first local bit line 308 and the second local bit line 310 differently, while in other embodiments, other voltage configurations may be provided to the respective local bit lines. Furthermore, other embodiments may use different circuit arrangements to drive the respective memory cells 102 of the memory 100.

[0050] exist Figure 3 In the described embodiment, the first local bit line 308 can drive bit line 104-0, and the second local bit line 310 can drive Figure 2 Bit line 104-1. Furthermore, the first local word line 314 can drive word line 106-0, and the second local word line 316 can drive... Figure 2 Word line 106-1. That is, the first local bit line 308 and the first local word line 314 can implement access to memory cell 102-B, the first local bit line 308 and the second local word line 316 can implement access to memory cell 102-C, the second local bit line 310 and the first local word line 314 can implement access to memory cell 102-D, and when indicated by the control circuit 122, the second local bit line 310 and the second local word line 316 can implement access to memory cell 102-E.

[0051] It should be noted that portions of global bit lines 306 and global word lines 312 are shown in the depicted portion of decode circuit 300. For example, in some embodiments, each global bit line of global bit lines 306 can drive 32 local bit lines, including first local bit line 308 and second local bit line 310. Global word line 312 can drive 32 local word lines, including first local word line 314 and second local word line 316. It should also be noted that the depicted portion of decode circuit 300 is one embodiment of word line decoder 108 and / or bit line decoder 110, and other embodiments can be used in different embodiments of memory 100 as described.

[0052] Figure 4 is a side view of a diagram of a portion of memory 100 including memory array 200 and resistance compensation scheme 400, with reference to some embodiments of the present disclosure. Figure 1 Figure 2 When accessing a memory cell of memory cells 102, resistance compensation scheme 400 can include additional circuitry to add resistance and compensate for the transmission path resistance of the respective bit line and / or word line of target memory cell 102-A. Resistance compensation scheme 400 can result in the same total resistance associated with accessing target memory cell 102-A.

[0053] When accessing target memory cell 102-A (not shown in Figure 4 ), resistance compensation scheme 400 can facilitate compensating for the transmission path resistance of bit line 104-3 through a compensating resistance on respective word line 106-1. At the same time, resistance compensation scheme 400 can facilitate compensating for the transmission path resistance of word line 106-1 through a compensating resistance on bit line 104-3 associated with target memory cell 102-A. In this way, resistance compensation scheme 400 can result in a total resistance on memory cells 102 of memory device 100 equal to the transmission path resistance associated with the full length of a bit line of bit lines 104 (e.g., bit line 104-3), and equal to the transmission path resistance of the full length of a word line of word lines 106 (e.g., word line 106-1 of memory device 100). As such, the total resistance associated with memory cells 102 of resistance compensation scheme 400 can be predetermined and can be independent of the location of the memory cells in memory 100.

[0054] Figure 4 The depicted portion of memory 100 in Figure 4 ​Additional sockets for other word lines 106 and / or bit lines 104 not shown. Furthermore, sockets associated with bit lines 104 may be positioned perpendicular to the word line sockets. Additional circuitry for socket 402 may be used when transmitting signals to access memory cells 102.

[0055] Figure 4 The described portion of the resistor compensation scheme 400 may include compensation resistors 404 disposed on bit lines 104-3 between different decoder segments 406. In different embodiments, decoder segment 406 may include one or more decoding circuits, for example... Figure 3 The decoding circuit 300. In other embodiments, different arrangements or architectures of the decoding circuit and / or word lines may be used to drive the memory cell 102. Furthermore, the compensation resistor 404 may be implemented in any feasible form, such as a polymer-based resistive material or any resistive metal layer. Additionally, the resistance compensation scheme 400 may be implemented passively. This prevents the application of unwanted parasitic loads to the memory 100.

[0056] In the depicted embodiments, Figure 4 Each decoder segment 406 may include four secondary decoder circuits 318 to drive four global word lines. Furthermore, each global word line may drive 32 primary decoder circuits 320, each decoder circuit coupled to a local word line. That is, each decoder segment 406 may include 128 local word lines to access memory cells 102 located on the respective 128 local word lines. In some embodiments, differential secondary decoder circuits and differential global word lines may be used to drive primary decoder circuits and local word lines.

[0057] In some embodiments, when accessing a target memory cell, a compensation resistor 404 on a corresponding bit line of bit line 104 associated with the target memory cell can compensate for the transmission path resistance associated with a corresponding word line of word line 106, which is associated with the target memory cell. Therefore, the compensation resistor 404 on the word line can compensate for the transmission path resistance of the corresponding bit line.

[0058] Considering the foregoing, the resistance compensation scheme 400 may include compensation resistors 404 coupled to the bit line 104 and word line 106 of the memory 100. For example, in Figure 4In particular embodiments, the resistance compensation scheme 400 can include a compensation resistor 404 coupled to the bit line 104-3 to compensate for the transmission path resistance of the word line 106-1 when accessing a target memory cell using the bit line 104-3 and the word line 106-1. In this embodiment, the resistance of the bit line 104-3 can be calculated using the following equation when accessing a memory cell. Rbl can be the transmission path resistance of the bit line segment between the bit line decoder and the memory cell. Rext can be the resistance added by the compensation resistor 404 on the bit line 104-3 to compensate for the transmission path resistance of the word line 106-1. Rblmax can be equal to the resistance of a full length bit line.

[0059] Rext + Rbl = Rblmax

[0060] The Rext resistance value can depend on the placement of the decoder segment 406 and the location of the word line 106 in the memory array in different embodiments. Rext can be equal to the compensation resistor 404 of the respective bit line 104 or word line 106 that is coupled in series to the word line 106 / bit line 104. For example, the word line 106-1 can be coupled to the socket 402 of the decoder segment 406-1, which can be coupled to the BL NEAR node of the bit line 104-3. In one instance, the word line 106-1 and the bit line 104-3 can be used to access a respective memory cell. In this instance, Rext on the bit line 104-3 can be equal to the series connected equivalent of the compensation resistor 404-1 and the compensation resistors 404-2, 404-3, 404-4, 404-5, and 404-6.

[0061] In another instance, if the word line 106 is coupled to the word line socket of the decoder segment 406-2, Rext on the bit line 104-3 can be determined from the BL FAR node. That is, Rext can be equal to the series connected compensation resistors 404-5 and 404-6. It should be noted that the compensation resistors shown above are with reference to particular embodiments of the disclosure, and any suitable placement of the compensation resistors 404 can be used on the bit lines and word lines of the memory 100 in different embodiments. Figure 4

[0062] The compensation scheme 400 can also include a compensation resistor 404 coupled to the bit line 104-3 to compensate for the transmission path resistance of the word line 106-1 that is not shown in the description section. Figure 4 In addition, Rext on the word line 106-1 can be determined in the same manner.

[0063] ​The resistance compensation scheme 400 can use the compensation resistors 404 to impose a compensation resistance on the word lines 106 and the bit lines 104. In some embodiments, the bit line transmission path resistance value can be inversely proportional to the respective compensation resistance value imposed on the respective word line of the memory cell. Further, the word line transmission path resistance value can be inversely proportional to the respective compensation resistance value imposed on the respective bit line when accessing the memory cell. That is, the total resistance of each memory cell can include the transmission path resistance of the respective bit line, the respective word line compensation resistance imposed by the compensation resistors 404, the transmission path resistance of the respective word line, and the bit line compensation resistance imposed by the compensation resistors 404.

[0064] In particular embodiments, the resistance compensation scheme 400 can cause each of the memory cells 102 to include the same total resistance value. Thus, due to the equal total resistance values of the memory cells 102, the memory 100 can use the same voltage and / or current to access different memory cells 102. As such, each of the memory cells 102 can receive an equal voltage and / or current regardless of its physical distance to the respective decoder. In such embodiments, the decoding circuitry can provide a voltage and / or current proportional to that required to access the farthest memory cell from the decoding circuitry to access the rest of the memory cells 102.

[0065] Figure 5 is Figure 4 a side view of an alternative embodiment 500 of the compensation resistors 404 on the bit line 104-3. Figure 5 Embodiments of the resistance compensation scheme 400 can use transistors 502 in place of the compensation resistors 404. The transistors 502 can be positioned on the bit line compensation bias lines 504. The bit line compensation bias lines 504 can provide a gate bias voltage to each of the transistors 502. The transistors 502 can impose a DC resistance on the bit line 104-3 based at least in part on the provided gate bias voltage.

[0066] The transistors 502 can be positioned in series in the memory 100 along the rest of the bit line 104 and on their respective bit line compensation bias lines (e.g., the compensation bit lines 504). This can allow for the use of the transistors 502 to compensate for the transmission path resistance of the word lines 106 on the respective bit lines 104 when accessing the memory cells. Additionally, the transistors 502 can be positioned in series in the memory 100 along the word lines 106 and on their respective word line compensation bias lines (not shown in FIG. 5). As such, the alternative embodiment 500 of the resistance compensation scheme 400 can use transistors 502 disposed on compensation bias lines to compensate for the transmission path resistance of the respective bit lines 104 and the respective word lines 106 in the same manner as the resistance compensation scheme 400 of FIG. 4. Figure 5 Figure 4

[0067] ​​Figure 6 depiction Figure 1 of a portion of the memory 100, including the spike mitigation circuit 600 and a portion of the decode circuit 300. The illustrated portion of the memory 100 includes a level one decoder circuit 320, a hook metal 602, and a via 604. The hook metal 602 can hook from the level one decoder circuit 320 to the via 604 to provide access to memory cells 102 located on an opposite access line from the level one decoder circuit 320. The via 604 can be coupled to a different bit line 104 or word line 106 to facilitate access to memory cells 102 having different electrical distances from the decoder circuit.

[0068] The spike mitigation circuit 600 can reduce the effects of inrush current and / or voltage spikes on the memory cells of the memory 100. The hook metal 602 can include a higher resistance proximate to the level one decoder circuit 320 of the decode circuit 300. In different embodiments, the hook metal 602 can include a high resistance material, a coupled external resistor, or both. In certain embodiments, the external resistor can be programmable to allow resistance adjustment for different electrical distances. Additional resistance can be passively applied to the hook metal 602. Specific embodiments related to the hook metal 602 resistance can be described below with respect to Figure 7 and 8 .

[0069] The via 604 can also include a high resistance material. As such, the via 604 can reduce the effects of spike voltages proximate to the decoder circuit of the near memory cells. Thus, the via 604 can reduce the damaging effects of possible voltage spikes to the near memory cells 102 (not shown in Figure 6 ).

[0070] In particular embodiments, the spike mitigation circuit 600 and the resistance compensation scheme 400 can be incorporated onto the memory 100. As described above, the resistance compensation scheme 400 can cause voltage and / or current to be provided in proportion to that required to access the farthest memory cells 102. In these embodiments, it is more likely that voltage spikes will occur. The spike mitigation circuit 600 can mitigate the damaging effects of voltages above a threshold on the near memory cells 102 by the resistance compensation scheme 400. It should be noted that in different embodiments, the specific values of the hook metal 602 and the via 604 can be adjusted according to different factors, such as the size of the memory 100.

[0071] Furthermore, the illustrated level one decoder circuit 320, hook metal 602, and via 604 can be uniformly replicated across other level one decoder circuits 320 of the memory 100. This can allow for uniform spike mitigation across all decoders of the decode circuit 300 and / or the memory 100.

[0072] Figure 7 depicted in FIG. 7 can be used in connection with the spike mitigation circuit 600 of Figure 6 A schematic diagram 700 depicting a first embodiment that can be used in connection with the spike mitigation circuit 600 of

[0073] In the first embodiment of the spike mitigation circuit 600, a resistor 702 can be disposed between the word line 106-1 and the primary decoder circuit 320. When a memory cell is accessed via the word line 106-1 and the bit line 104-1, the resistor 702 can impose a resistance to a voltage spike to mitigate damaging effects of the voltage spike to nearby memory cells. In different embodiments, the hook metal 602 or the via 604 can include the resistor 702 between the word line 106-1 and the primary decoder circuit 320.

[0074] Figure 8 A schematic diagram 800 depicting certain embodiments that can be used in connection with the spike mitigation circuit 600 of Figure 6 The schematic diagram 800 can include the bit line 104, the word line 106, and the decoder circuit 300 including the secondary decoder circuit 318 and the primary decoder circuit 320 coupled to the word line 106. The decoder circuit 300 can include a resistor 802 disposed between the primary decoder circuit 320 and the secondary decoder circuit 318. In addition, the decoder circuit 300 can include a switch 804 that can enable or disable the effect of the resistor 802. The switch 804 can be programmable to bypass the resistor 802 when accessing a memory cell on the word line 106-1 or to include the resistor 802 in the decoder circuit 300 when the voltage associated with the decoder circuit 300 is above a threshold value.

[0075] For example, the switch 804 can be shorted to bypass the resistor 802 when the voltage associated with the decoder circuit 300 is below a threshold value. Alternatively, the switch 804 can be opened to effectively dispose the resistor 802 in the decoder circuit 300 between the secondary decoder circuit 318 and the primary decoder circuit 320 when the voltage associated with the decoder circuit 300 is above a threshold value. It should be noted that the use of one resistor 802 in the depicted embodiment of the spike mitigation circuit 600 is by way of example, and different numbers of resistors and switches can be used in different embodiments to effectively reduce the effect of a spike voltage. It should be noted that the schematic diagram 800 shows a single decoder circuit 300 connected to the word line 106-1, however, the schematic diagram can be used to drive the word lines 104 of the memory 100 by way of one or more decoder circuits 300. Figure 8 In the first embodiment of the spike mitigation circuit 600, a resistor 702 can be disposed between the word line 106-1 and the primary decoder circuit 320. When a memory cell is accessed via the word line 106-1 and the bit line 104-1, the resistor 702 can impose a resistance to a voltage spike to mitigate damaging effects of the voltage spike to nearby memory cells. In different embodiments, the hook metal 602 or the via 604 can include the resistor 702 between the word line 106-1 and the primary decoder circuit 320.

[0074] Figure 8 A schematic diagram 800 depicting certain embodiments that can be used in connection with the spike mitigation circuit 600 of Figure 6 The schematic diagram 800 can include the bit line 104, the word line 106, and the decoder circuit 300 including the secondary decoder circuit 318 and the primary decoder circuit 320 coupled to the word line 106. The decoder circuit 300 can include a resistor 802 disposed between the primary decoder circuit 320 and the secondary decoder circuit 318. In addition, the decoder circuit 300 can include a switch 804 that can enable or disable the effect of the resistor 802. The switch 804 can be programmable to bypass the resistor 802 when accessing a memory cell on the word line 106-1 or to include the resistor 802 in the decoder circuit 300 when the voltage associated with the decoder circuit 300 is above a threshold value.

[0075] For example, the switch 804 can be shorted to bypass the resistor 802 when the voltage associated with the decoder circuit 300 is below a threshold value. Alternatively, the switch 804 can be opened to effectively dispose the resistor 802 in the decoder circuit 300 between the secondary decoder circuit 318 and the primary decoder circuit 320 when the voltage associated with the decoder circuit 300 is above a threshold value. It should be noted that the use of one resistor 802 in the depicted embodiment of the spike mitigation circuit 600 is by way of example, and different numbers of resistors and switches can be used in different embodiments to effectively reduce the effect of a spike voltage. It should be noted that the schematic diagram 800 shows a single decoder circuit 300 connected to the word line 106-1, however, the schematic diagram can be used to drive the word lines 104 of the memory 100 by way of one or more decoder circuits 300. Figure 8 In the first embodiment of the spike mitigation circuit 600, a resistor 702 can be disposed between the word line 106-1 and the primary decoder circuit 320. When a memory cell is accessed via the word line 106-1 and the bit line 104-1, the resistor 702 can impose a resistance to a voltage spike to mitigate damaging effects of the voltage spike to nearby memory cells. In different embodiments, the hook metal 602 or the via 604 can include the resistor 702 between the word line 106-1 and the primary decoder circuit 320.

[0074] Figure 8 A schematic diagram 800 depicting certain embodiments that can be used in connection with the spike mitigation circuit 600 of Figure 6 The schematic diagram 800 can include the bit line 104, the word line 106, and the decoder circuit 300 including the secondary decoder circuit 318 and the primary decoder circuit 320 coupled to the word line 106. The decoder circuit 300 can include a resistor 802 disposed between the primary decoder circuit 320 and the secondary decoder circuit 318. In addition, the decoder circuit 300 can include a switch 804 that can enable or disable the effect of the resistor 802. The switch 804 can be programmable to bypass the resistor 802 when accessing a memory cell on the word line 106-1 or to include the resistor 802 in the decoder circuit 300 when the voltage associated with the decoder circuit 300 is above a threshold value.

[0075] For example, the switch 804 can be shorted to bypass the resistor 802 when the voltage associated with the decoder circuit 300 is below a threshold value. Alternatively, the switch 804 can be opened to effectively dispose the resistor 802 in the decoder circuit 300 between the secondary decoder circuit 318 and the primary decoder circuit 320 when the voltage associated with the decoder circuit 300 is above a threshold value. It should be noted that the use of one resistor 802 in the depicted embodiment of the spike mitigation circuit 600 is by way of example, and different numbers of resistors and switches can be used in different embodiments to effectively reduce the effect of a spike voltage. It should be noted that the schematic diagram 800 shows a single decoder circuit 300 connected to the word line 106-1, however, the schematic diagram can be used to drive the word lines 104 of the memory 100 by way of one or more decoder circuits 300. Figure 8 In the first embodiment of the spike mitigation circuit 600, a resistor 702 can be disposed between the word line 106-1 and the primary decoder circuit 320. When a memory cell is accessed via the word line 106-1 and the bit line 104-1, the resistor 702 can impose a resistance to a voltage spike to mitigate damaging effects of the voltage spike to nearby memory cells. In different embodiments, the hook metal 602 or the via 604 can include the resistor 702 between the word line 106-1 and the primary decoder circuit 320.

[0076] With these technical effects in mind, multiple memory devices can be included on a memory module, thereby enabling the memory devices to be communicatively coupled to processing circuitry as a unit. For example, a dual in-line memory module (DIMM) can include a printed circuit board (PCB) and multiple memory devices. The memory module is communicatively coupled to a client device or a host device via a communication network in response to commands from a memory controller. Or in some cases, the memory controller can be used on the host side of a memory host interface; for example, a processor, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC), or the like can each include a memory controller. This communication network can enable data communication therebetween, and thus, the client device utilizes hardware resources that are accessible through the memory controller. Based at least in part on user input to the client device, the processing circuitry of the memory controller can perform one or more operations to facilitate retrieval or transfer of data between the client device and the memory devices. Data transferred between the client device and the memory devices can be used for a variety of purposes, including but not limited to presenting a visualization to a user through a graphical user interface (GUI) at the client device, processing operations, computations, or the like. Thus, for this consideration, the above-described improvements to memory controller operations and memory write operations can manifest as improvements in visualization quality (e.g., rendering speed, rendering quality), improvements in processing operations, improvements in computations, or the like.

[0077] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments can be susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the particular forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure.

[0078] The technology presented and claimed herein is to be understood to apply to any novel, useful, and novel industrial application of the technology set forth in the description, including elements and combinations of elements thereof, and equivalents thereof, in any form or for any purpose or in any combination of any or all of the same. The technology presented and claimed herein is to be understood to apply to any novel, useful, and novel industrial application of the technology described, including elements and combinations of elements thereof, and equivalents thereof, in any form or for any purpose or in any combination of any or all of the same. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. Furthermore, if any claims appended to the end of this specification contain provisions that are not specifically recited in the specification and drawings, such provisions are to be construed as modifications only within the pertinence of 35 U.S.C. § 112(f) and equivalent provisions in patent laws of foreign nations. However, for any claims containing elements that are not specifically recited in the specification and drawings, such elements are not to be construed as modifications within the pertinence of 35 U.S.C. § 112(f) and equivalent provisions in patent laws of foreign nations.

Claims

1. An apparatus comprising: A memory array comprising a plurality of memory cells disposed between at least two access lines of a plurality of access lines of the memory array. Wherein: a first access line of the plurality of access lines includes a first current path configured to provide access to the target memory cell on a first side of the plurality of memory cells, wherein the first current path includes a first parasitic resistance associated with accessing the target memory cell; and The second access line of the plurality of access lines includes a second current path configured to provide access to the target memory cell on a second side of the target memory cell, wherein the second access line includes one or more compensation elements coupled to the second access line between at least two memory cells of the plurality of memory cells, and is configured to provide a first compensation resistance when providing access to the target memory cell, and wherein the second current path includes a second parasitic resistance associated with accessing the target memory cell.

2. The device according to claim 1, wherein, The resistance value of the first compensation resistor of the second access line is proportional to the resistance value of the first parasitic resistor of the first access line.

3. The device of claim 1, wherein each of the at least two memory cells is coupled to the second access line on a first side and to a corresponding access line of the plurality of access lines on a second side.

4. The device of claim 3, wherein each of the respective access lines coupled to the second side of the at least two memory cells is associated with a different decoder segment of the memory array, wherein each decoder segment includes a plurality of decoder elements configured to drive a plurality of access lines among the plurality of access lines.

5. The device according to claim 1, wherein, The first one or more compensation elements are connected in series on the second access line.

6. The device according to claim 1, wherein, The total resistance of the second parasitic resistance and the first compensation resistance is proportional to the resistance of the parasitic resistance associated with the full length of the first current path of the first access line.

7. The device according to claim 1, wherein, The first access line includes one or more second compensation elements disposed on the first access line, the second or more compensation elements being configured to provide a second compensation resistance when providing access to the target memory cell.

8. The device according to claim 7, wherein the resistance value of the second compensation resistor of the first access line is proportional to the resistance value of the second parasitic resistance of the second access line.

9. The device according to claim 8, wherein, The total resistance of the first parasitic resistance and the second compensation resistance is proportional to the resistance of the parasitic resistance associated with the entire length of the second current path.

10. The device according to claim 1, wherein, The memory array includes a cross-point memory array, which comprises a plurality of consecutive memory cells disposed between the intersecting layers of the plurality of access lines.

11. The device of claim 1, wherein the memory array includes a first decoder, wherein a first side of the first decoder is coupled to the first access line, wherein the first decoder is configured to provide access signals for accessing the target memory cell.

12. The device of claim 11, wherein the memory array includes a second decoder, wherein the second decoder is coupled to a second side of the first decoder, and wherein the second decoder is configured to drive the first decoder.

13. The device of claim 1, wherein the one or more compensation elements comprise one or more resistors.

14. The device of claim 1, wherein the one or more compensation elements comprise one or more transistors.

15. A method for applying a uniform resistance when accessing memory cells of a memory array, comprising: The first parasitic resistance of the second access line associated with the second side of the memory cell is compensated by a first one or more compensation elements arranged between the at least two memory cells coupled to a first access line associated with a first side of the memory cell that accesses at least two memory cells. as well as The second parasitic resistance of the first access line is compensated by a second one or more compensation elements arranged between at least two memory cells coupled to the second access line.

16. The method of claim 15, wherein the total resistance of the first parasitic resistance and the first one or more compensating elements is equal to the parasitic resistance of the second access line associated with accessing the furthest memory cell on the second access line.

17. The method of claim 15, wherein the total resistance of the second parasitic resistance and the second one or more compensating elements is equal to the parasitic resistance of the first access line associated with accessing the furthest memory cell on the first access line.

18. A semiconductor device comprising: A memory array comprising: a plurality of memory cells; and one or more compensation elements disposed between at least two first memory cells of the plurality of memory cells; A plurality of access lines, wherein a first access line of the plurality of access lines is configured to provide a first voltage to access a first side of a first memory cell of at least two first memory cells of the plurality of memory cells, wherein the first voltage is independent of the location of the first memory cell in the memory array due to the first access line having a first resistance associated with accessing the first memory cell, the first resistance being independent of the location of the first memory cell in the memory array, and is at least in part caused by the arrangement of the first one or more compensation elements of the plurality of memory cells between the at least two first memory cells.

19. The semiconductor device of claim 18, wherein a second access line of the plurality of access lines is configured to provide the first voltage to access a first side of a second memory cell of the plurality of memory cells, based on the second access line having a first resistance associated with accessing the second memory cell, the first resistance being caused at least in part by a second one or more compensating elements disposed between at least two second memory cells of the plurality of memory cells.

20. The semiconductor device according to claim 18, wherein, The first access line is coupled to the first side of the first-stage decoder via a first decoder resistor.

21. The semiconductor device of claim 20, wherein the second-stage decoder is coupled to a second side of the first-stage decoder via a second decoder resistor.

22. The semiconductor device according to claim 21, wherein, The second decoder resistor is programmable.

Images