Semiconductor package structure and method of forming the same

Abstract

The present application relates to a semiconductor package structure and a forming method thereof. The semiconductor package structure comprises a first substrate, an electronic component embedded in the first substrate, a second substrate above the first substrate, and the electronic component is electrically connected to the first substrate through the second substrate.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor technology, and more particularly, to a semiconductor package structure and a forming method thereof. BACKGROUND

[0002] With the evolution of packaging technology, various kinds of package structures are also emerging, and the overall package size is getting smaller and smaller, and the function is getting more and more, so usually a package structure is needed to control various components.

[0003] At present, the embedded substrate required by high-level applications must increase the number of embedded layers as the number of I / O increases, but the problems such as substrate expansion and warpage accompanied by the increase in the number of layers will reduce the yield of the product. For example, the yield of each layer of the embedded substrate is about 95% to 97%, and the yield of the basic four-layer board is about 90%. If the number of layers is increased to increase the number of I / O, the yield will be further reduced to about 80%. In this way, there will be no economic benefit, and most importantly, the die in the die first process will also be scrapped. SUMMARY

[0004] In view of the above problems in the related art, the present application provides a semiconductor package structure and a forming method thereof.

[0005] According to an aspect of an embodiment of the present application, a semiconductor package structure is provided, comprising: a first substrate comprising an electronic component embedded in the first substrate; and a second substrate located above the first substrate. The electronic component is electrically connected to the first substrate through the second substrate.

[0006] In the above semiconductor package structure, the second substrate has a first surface opposite to the first substrate, and the first substrate and the electronic component are both electrically connected to the first surface of the second substrate.

[0007] In the above semiconductor package structure, further comprising an electrical connecting member electrically connected between the second substrate and the first substrate, and electrically connected between the electronic component and the second substrate.

[0008] In the above semiconductor package structure, further comprising a solder disposed at the electrical connecting member, and the first substrate is further electrically connected to the second substrate through the solder.

[0009] In the above semiconductor package structure, the electrical connecting member comprises a conductive pillar.

[0010] In the above semiconductor package structure, further comprising a dielectric material disposed between the first substrate and the second substrate and covering the electrical connecting member.

[0011] In the semiconductor package structure, the dielectric material can include a first dielectric material adjacent to the first substrate and a second dielectric material adjacent to the second substrate, and the portion of the electrical connector in the first dielectric material is interfaced with the portion of the electrical connector in the second dielectric material by the solder.

[0012] In the semiconductor package structure, the first substrate has a cavity and a first surface opposite to the second substrate, and the electronic component is disposed in the cavity.

[0013] In the semiconductor package structure, the electronic component is exposed by the first surface of the first substrate.

[0014] In the semiconductor package structure, a dielectric material is further included and disposed between the first substrate and the second substrate, and the dielectric material covers the first substrate and the electronic component.

[0015] In the semiconductor package structure, the first substrate has a second surface facing away from the second substrate, and the second surface of the first substrate is coplanar with a bottom surface of the electronic component.

[0016] According to an aspect of an embodiment of the present application, a method of forming a semiconductor package structure is also provided, including: providing a first substrate and forming a cavity in the first substrate; placing an electronic component in the cavity of the first substrate; and electrically connecting the first substrate and the electronic component to a second substrate such that the electronic component is electrically connected to the first substrate through the second substrate.

[0017] In the method of forming a semiconductor package structure, the forming of the cavity includes forming the cavity through the first substrate by a via process.

[0018] In the method of forming a semiconductor package structure, a dielectric material is formed between the first substrate and the second substrate, and the dielectric material covers the first substrate and the electronic component.

[0019] In the method of forming a semiconductor package structure, the second substrate has a first surface opposite to the first substrate, and the electrically connecting of the first substrate and the electronic component to the second substrate includes electrically connecting both the first substrate and the electronic component to the first surface of the second substrate.

[0020] In the method of forming a semiconductor package structure, the electrically connecting of the first substrate and the electronic component to the second substrate includes electrically connecting the first substrate and the electronic component to the second substrate by an electrical connector.

[0021] In the method of forming a semiconductor package structure, an electrical connector is further provided on the first substrate and the electronic component, and the electrical connector is connected to the second substrate by solder.

[0022] In the method of forming a semiconductor package structure described above, the second substrate has electrical connectors on a surface opposite the first substrate, and electrically connecting the first substrate and the electronic component to the first surface of the second substrate includes: aligning the electrical connectors on the first substrate and the electronic component with the electrical connectors on the second substrate with solder.

[0023] In the method of forming a semiconductor package structure described above, further comprising: forming a dielectric material between the first substrate and the second substrate, the dielectric material covering the electrical connectors and covering the first substrate and the electronic component.

[0024] In the method of forming a semiconductor package structure described above, placing the electronic component in the cavity includes: placing the electronic component such that a bottom surface of the electronic component is coplanar with a bottom surface of the first substrate, and a top surface of the electronic component is recessed relative to a top surface of the first substrate. BRIEF DESCRIPTION OF DRAWINGS

[0025] Various aspects of the application can be best understood from the following detailed description when read with the accompanying drawings in which: It should be noted that various components were not drawn to scale. Indeed, the dimensions of the various components can be arbitrarily increased or decreased for clarity sake.

[0026] Figure 1 is a schematic diagram of a semiconductor package structure 100 according to an embodiment of the application.

[0027] Figures 2A to 2F is a schematic diagram showing various stages of a method of forming a semiconductor package structure according to an embodiment of the application. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Each example should be taken not to limit the present application as having a dependency, or requirement, on one or more particular features unless explicitly stated as such. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and second component are in direct contact, and can also include embodiments where one or more additional components are formed between the first component and second component such that the first component and second component can not be in direct contact. Further, the present application makes reference to various examples that can be repeated herein. Such repetition is for the purpose of simplification and clarity and does not imply a relationship between the examples referred to and the related examples and / or configuration discussed herein.

[0029] A semiconductor package structure is provided according to an embodiment of the application. Figure 1 is a schematic diagram of a semiconductor package structure 100 according to an embodiment of the application. As Figure 1As shown, the semiconductor package structure 100 includes a first substrate 110 and a second substrate 120 positioned above the first substrate 110. An electronic component 130 is embedded within the first substrate 110. The electronic component 130 can be, for example, a die. The electronic component 130 is electrically connected to the first substrate 110 through the second substrate 120.

[0030] In contrast to prior art Die first processes in which the active component (e.g., a die) is embedded in the center of the overall package structure, the semiconductor package structure of the present application includes an upper substrate (second substrate 120) and a lower substrate (first substrate 110) and employs a Die last process to embed the die within the first substrate 110. As a result of employing a Die last process, the die is not discarded due to substrate processing. On the other hand, because the upper and lower substrates are fabricated separately, the yield of the overall structure can be greatly improved. For example, the yield of a single layer substrate is 95%, the yield of a four layer substrate is 0.95*0.95*0.95*0.95 = 0.8145, and after splitting the four layer substrate into an upper and lower substrate, the yield of one of the upper and lower substrates is 0.95*0.95 = 0.9025, and the overall yield of the structure is 0.95*0.95 + 0.95*0.95.

[0031] With continued reference to Figure 1 As shown, the first substrate 110 has a cavity 115 and a first surface 111 opposite the second substrate 120. The first substrate 110 also has a second surface 112 facing away from the second substrate 120. The second substrate 120 has a first surface 121 opposite the first substrate 110. The electronic component 130 is disposed within the cavity 115. The second surface 112 of the first substrate 110 can be substantially coplanar with a bottom surface of the electronic component 130. The electronic component 130 is exposed by the first surface 111 of the first substrate 110. By exposing the electronic component 130, the heat dissipation function of the electronic component 130 can be enhanced. In some embodiments, a heat dissipation material (not shown) can be applied to the surface of the electronic component 130 to enhance the heat dissipation function of the electronic component 130, and in such embodiments, the heat dissipation material can be substantially coplanar with the second surface 112 of the first substrate 110.

[0032] The first substrate 110 and the electronic component 130 are both electrically connected to the first surface 121 of the second substrate 120. As shown, the first substrate 110 is electrically connected to the second substrate 120 by a first set of electrical connections 140. The electronic component 130 is electrically connected to the second substrate 120 by a second set of electrical connections 150. Figure 1As shown, the electronic components 130 are electrically connected to the second substrate 120 through a plurality of electrical connectors 140 located between the second substrate 120 and the first substrate 110 and the electronic components 130. In some embodiments, the electrical connectors 140 over the electronic components 130 can include conductive pillars 141. The electrical connectors 140 can further include solder 142 located at the top of the conductive pillars 141. Some of the plurality of electrical connectors 140 are electrically connected between the second substrate 120 and the first substrate 110, and others of the plurality of electrical connectors 140 are electrically connected between the electronic components 130 and the second substrate 120.

[0033] In some embodiments, the critical dimension (CD) of the electrical connectors 140 over the first substrate 110 can be in the range of 20 pm to 60 pm. In some embodiments, the height of the electrical connectors 140 over the first substrate 110 can be in the range of 2 pm to 30 pm. The height of the electrical connectors 140 over the electronic components 130 can be greater than 120 pm.

[0034] In some embodiments, the first substrate 110 is a core substrate. In embodiments where the first substrate 110 is a core substrate, the core substrate can have a through-hole 119 therein, and the end of the through-hole 119 can create a dimple 1195. The width of the dimple 1195 can be in the range of 20 pm to 60 pm. The depth of the dimple 1195 can be in the range of 2 pm to 30 pm.

[0035] A dielectric material 160 is disposed between the first substrate 110 and the second substrate 120 and encapsulates the plurality of electrical connectors 140. The dielectric material 160 also covers the first substrate 110 and the electronic components 130. In some embodiments, the dielectric material 160 can include a first dielectric material 161 adjacent to the first substrate 110 and a second dielectric material 162 adjacent to the second substrate 120. In some embodiments, the first dielectric material 161 can be an electrical overstress (EOS) protection film, and the second dielectric material 162 can be an underfill, such as a polymer. In some embodiments, a glue river can be provided in the first substrate 110 in order to avoid the underfill from not being able to fill the entire strip.

[0036] Solder 190 is disposed at the junction of the first dielectric material 161 and the second dielectric material 162. Solder 190 may be located at the electrical connector 140 above the corresponding first substrate 110. Solder 190 is also disposed between the electrical connector 140 above the electronic component 130 and the first substrate 110. In some embodiments, the first substrate 110 and the electronic component 130 can be electrically connected to the second substrate 120 via the electrical connector 140 and solder 190. In embodiments, solder 190 can also be used for mating two portions of the electrical connector 140. For example, the portion of the electrical connector 140 located in the first dielectric material 161 and the portion of the electrical connector 140 located in the second dielectric material 162 are mated via solder 190.

[0037] refer to Figure 1 As shown, some dimensional configurations of the various components are also illustrated. In some embodiments, the ratio of the width Y of the semiconductor package structure 100 to the width X of the die can satisfy: 1 ​​≤ |Y / X| ≤ 15. The height h of the second dielectric material 162 can satisfy: 10 ≤ h ≤ 2000 μm, for example, 10 ≤ h ≤ 50 μm. The ratio of the height p1 of the electrical connector 140 located above the first substrate 110 in the second dielectric material 162 to the height h of the second dielectric material 162 can satisfy: 50% ≤ p1 / h ≤ 90%. The ratio of the height B of the solder 190 located above the die in the second dielectric material 162 to p1 can satisfy: 60 ≤ B / p1 ≤ 100%. The ratio of the height p1 of the electrical connector 140 located above the first substrate 110 in the second dielectric material 162 to its width a (not shown) can satisfy: 30 ≤ p1 / a ≤ 65%. The dimensional configurations described above are merely exemplary, and the invention is not limited thereto.

[0038] Figures 2A to 2F Schematic diagrams illustrating various stages of a method for forming a semiconductor package structure according to an embodiment of the present invention are shown. First, as Figure 2A As shown, a first substrate 110 is formed, and an electrical connector 140 is provided on a first surface of the first substrate 110. The electrical connector 140 may be, for example, a conductive post. In the illustrated embodiment, a through hole 119 is also provided in the first substrate 110. Figure 2B This forms an electronic component 130, such as a die. The surface of the electronic component 130 may also have an electrical connector 140. The electrical connector 140 above the electronic component 130 may include a conductive post 141. The electrical connector 140 may also include solder 142 located at the top of the conductive post 141.

[0039] like Figure 2C As shown, for example, a cavity 115 is formed through the first substrate 110 via a punching process. Then, as...Figure 2D As shown, the electronic component 130 is placed in the cavity 115 of the first substrate 110. In some embodiments, the electronic component 130 can be placed such that a bottom surface of the electronic component 130 is coplanar with a bottom surface of the first substrate 110, and a top surface of the electronic component 130 is recessed with respect to a top surface of the first substrate 110.

[0040] As shown, a first dielectric material 161 is formed on the first substrate 110, covering the first substrate 110 and the electronic component 130. The first dielectric material 161 also covers a lower portion of the electrical connectors 140, and can expose the solder 142 of the electrical connectors 140 for subsequent interfacing with the second substrate 120. Figure 2E As shown, the first substrate 110 and the electronic component 130 are electrically connected to the second substrate 120 above the first substrate 110, resulting in a semiconductor package structure 100'. The electronic component 130 is electrically connected to the first substrate 110 through the second substrate 120. Both the first substrate 110 and the electronic component 130 can be electrically connected to the second substrate 120 using the electrical connectors 140. In the illustrated embodiment, both the electrical connectors 140 on the first substrate 110 and the electrical connectors 140 on the electronic component 130 are connected to the first surface 121 of the second substrate 120 through the solder 190.

[0041] Figure 2F In other embodiments, the electrical connectors 140 can be provided at the first surface 121 of the second substrate 120, and the end surface of the electrical connectors 140 exposed by the first dielectric material 161, and the end surface of the electrical connectors 140 exposed by the second dielectric material 162. In such embodiments, the electrical connectors 140 are interfaced through the solder 190 at the interface of the first dielectric material 161 and the second dielectric material 162 (as shown).

[0042] In other embodiments, the electrical connectors 140 can be provided at the first surface 121 of the second substrate 120, and the end surface of the electrical connectors 140 exposed by the first dielectric material 161, and the end surface of the electrical connectors 140 exposed by the second dielectric material 162. In such embodiments, the electrical connectors 140 are interfaced through the solder 190 at the interface of the first dielectric material 161 and the second dielectric material 162 (as shown). Figure 1

[0043] The above technical solution of the present application first separately manufactures the upper and lower substrates, and then uses a through-hole process to manufacture a cavity with an embedded electronic component in the lower substrate. The electronic component is placed in the cavity, and finally the upper substrate is interfaced with the lower substrate through solder. In some embodiments, electrical connectors such as conductive pillars can be provided on the lower substrate and the electronic component in advance to facilitate subsequent connection, and on the other hand, the height difference between the upper substrate and the electronic component can be reduced. The present application splits the original multi-layer board into two-stage processes, which can greatly improve the yield.

[0044] ​​The foregoing summary broadly summarizes several embodiments so that a better understanding can be made of the various aspects of the disclosure. It being understood that the person skilled in the art will readily be able to use the application as a basis to design or modify other processes and structures for achieving the same objectives and / or attaining the same advantages without departing from the spirit and scope of the application. The person skilled in the art will also realize that these equivalent constructions do not depart from the framework and scope of the application, and that numerous changes, substitutions and modifications can be made to it without departing from the spirit and scope of the application.

Claims

1. A semiconductor packaging structure, characterized in that, include: The first substrate includes electronic components embedded in the first substrate and through holes; A second substrate is located above the first substrate, and the second substrate has a first surface opposite to the first substrate; An electrical connector, electrically connected between a second substrate and a first substrate, includes a first electrical connector electrically connected between the electronic component and the second substrate and a second electrical connector electrically connected between the first substrate and the second substrate. The second electrical connector includes a second upper electrical connector and a second lower electrical connector. The first electrical connector and the second electrical connector include conductive posts. Solder is disposed at the first electrical connector and the second electrical connector, and the first substrate is also electrically connected to the second substrate through the solder; as well as A dielectric material is disposed between the first substrate and the second substrate and covers the first electrical connector and the second electrical connector, wherein the electronic component is electrically connected to the first substrate through the second substrate, and the second electrical connector is electrically connected to the through hole. The first substrate has a top surface and a bottom surface, and a cavity passing through the first substrate to connect the top surface and the bottom surface. The bottom surface of the first substrate is coplanar with the bottom surface of the electronic component, and the electronic component is disposed within the cavity. The dielectric material includes a first dielectric material adjacent to a first substrate and a second dielectric material adjacent to a second substrate. The second lower electrical connector located in the first dielectric material and the second upper electrical connector located in the second dielectric material are connected at the junction of the first dielectric material and the second dielectric material by the solder.

2. The semiconductor packaging structure according to claim 1, characterized in that, Both the first substrate and the electronic component are electrically connected to the first surface of the second substrate.

3. The semiconductor packaging structure according to claim 1, characterized in that, The top surface of the first substrate is opposite to the second substrate.

4. The semiconductor packaging structure according to claim 3, wherein: The dielectric material covers the first substrate and the electronic components.

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