ReRAM memory cell with dual wordline control

Abstract

The present invention discloses a ReRAM memory cell, comprising a ReRAM device including a solid electrolyte layer disposed between a first ion source electrode and a second electrode; and a selection circuit including two series-connected selection transistors connected in series with the ReRAM device, each of the two series-connected selection transistors having a gate connected to a separate control line.

Description

Background Art

[0001] The present invention relates to a Resistive Random Access Memory (ReRAM) cell and more particularly to a ReRAM cell having individually controlled series-connected word line select transistors.

[0002] ReRAM memory cells are increasingly used in the semiconductor industry. ReRAM memory cells employing two series-connected word line select transistors sharing a common gate connection to a word line have been used to alleviate the high voltage stress that exists between the bit line and the source line during programming of the ReRAM cell.

[0003] First reference Figure 1 , a schematic diagram shows an exemplary prior art ReRAM memory cell depicted within dashed line 10. ReRAM memory cell 10 includes a ReRAM device 12 connected in series with a first select transistor 14 and a second select transistor 16 connected in series. The ReRAM device includes a first conductive metal electrode serving as an ion source, a layer of solid electrolyte material, and a second conductive electrode. The ReRAM device can be programmed by applying a programming potential across the first electrode and the second electrode, the programming potential having a magnitude sufficient to cause ions of the material forming the first electrode to migrate from the first electrode into the solid electrolyte material layer to form a conductive path between the first electrode and the second electrode. The ReRAM device can be erased by applying an erase potential across the first electrode and the second electrode, the erase potential having a polarity opposite to the programming potential and having a magnitude sufficient to cause ions to migrate from the conductive path in the solid electrolyte material layer back to the ion source electrode. The wide end of the symbol representing a ReRAM device in all figures herein represents the ion source electrode.

[0004] The memory cell 10 is coupled between a bit line (BL) 18 to which one terminal of the ReRAM device 12 is connected and a source line (SL) 20 to which the source of the select transistor 16 is connected. The source line 20 is common to all memory cells in the array. The gates of both the select transistors 14 and 16 are connected together to a word line 22. In an array of such memory cells 10, the bit line 18 and the source line 20 typically run in the column direction of the array, while the word line 22 typically runs in the row direction of the array.

[0005] The use of two series connected select transistors 14 and 16 presents no additional complexity compared to a single transistor select arrangement and effectively alleviates the high voltage stress present between the bit line (BL) 18 node and the source line (SL) 20 node during program and erase operations.

[0006] exist Figure 1One problem encountered in the prior art ReRAM memory cell 10 is the problem of gate-induced drain leakage (GIDL) in the select transistors in the unselected memory cells during ReRAM memory cell programming and erase operations. GIDL is leakage current that occurs due to a high electric field between the gate and drain terminals. Because the gates of transistors 14 and 16 are connected together, a gate voltage of 0V is required to turn off both transistors 14 and 16 for the unselected memory cells. This places the entire programming voltage across the gate to drain of transistor 14. This results in GIDL. Summary of the Invention

[0007] According to one aspect of the present invention, a ReRAM memory cell includes a ReRAM device including a solid electrolyte layer disposed between a first ion source electrode and a second electrode; and two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line.

[0008] According to an aspect of the present invention, the two series-connected selection transistors are two series-connected n-channel selection transistors connected in series to the second electrode of the ReRAM device.

[0009] According to one aspect of the present invention, a ReRAM memory cell includes a first node, a second node, a ReRAM device, and a first n-channel selection transistor, the ReRAM device including a solid electrolyte layer disposed between a first ion source electrode and a second electrode, the first ion source electrode being connected to the first node, the first n-channel selection transistor being connected in series with a second n-channel selection transistor between the second electrode and the second node of the ReRAM device, the first n-channel selection transistor having a gate connected to the first selection node, and the second n-channel selection transistor having a gate connected to the second selection node.

[0010] According to an aspect of the present invention, the first node is connected to a bit line, the second node is connected to a source line, the first selection node is connected to a first word line, and the second selection node is connected to a second word line.

[0011] According to an aspect of the invention, the source line is a decoded source line.

[0012] According to an aspect of the present invention, the first word line and the second word line are decoded word lines.

[0013] According to an aspect of the invention, the bit lines are decoded bit lines.

[0014] According to one aspect of the present invention, a ReRAM memory array is arranged to form interleaved rows and columns and includes a plurality of ReRAM memory cells, each ReRAM memory cell including a ReRAM device having a solid electrolyte layer disposed between a first ion source electrode and a second electrode; and a selection circuit having two series-connected selection transistors connected in series with the ReRAM device, each of the two series-connected selection transistors having a gate connected to a separate control line.

[0015] According to one aspect of the present invention, each row of the array includes a first word line connected to a control line of a first of the series-connected select transistors of each ReRAM memory cell in the row; and a second word line connected to a control line of a second of the series-connected select transistors of each ReRAM memory cell in the row.

[0016] According to one aspect of the present invention, each column of the array includes a bit line connected to a first node of each ReRAM memory cell in the row; and a decoded source line connected to a second node of each ReRAM memory cell in the row, each ReRAM device having a solid electrolyte layer disposed between a first ion source electrode and a second electrode, the first ion source electrode being connected to the first node, and two series-connected select transistors including a first n-channel select transistor connected in series with a second n-channel select transistor between a second electrode and the second node of the ReRAM device, the first n-channel select transistor having a gate connected to the first select node, and the second n-channel select transistor having a gate connected to the second select node.

[0017] According to one aspect of the invention, each row of the array includes a first word line connected to the gate of a first n-channel select transistor of each ReRAM memory cell in the row; and a second word line connected to the gate of the first n-channel select transistor of each ReRAM memory cell in the row.

[0018] According to one aspect of the invention, each column of the array includes a bit line connected to a first node of each ReRAM memory cell in the row and a decoded source line connected to a second node of each ReRAM memory cell in the row.

[0019] According to one aspect of the present invention, a method for programming a ReRAM memory cell is disclosed, the ReRAM memory cell comprising a ReRAM device including a solid electrolyte layer disposed between a first ion source electrode and a second electrode at a bit line node; and a selection circuit including two series-connected selection transistors connected in series with the ReRAM device at the second electrode of the ReRAM device to a source line node, each of the two series-connected selection transistors having a gate connected to a separate control line. The method includes determining whether a ReRAM cell is selected for programming; if the ReRAM cell is selected for programming, biasing a bit line node at a first voltage potential, biasing a source line node at a second voltage potential less than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to program a ReRAM device in the ReRAM cell, and providing a positive voltage pulse having a first magnitude to a gate of one of the series-connected transistors having its source connected to the source line node, and providing a positive voltage pulse having a second magnitude greater than the first magnitude to a gate of another of the series-connected transistors; and if the ReRAM cell is not selected for programming, providing a voltage potential insufficient to turn on the gate of one of the series-connected transistors having its source connected to the source line node.

[0020] According to one aspect of the present invention, a method for erasing a ReRAM memory cell is disclosed, the ReRAM memory cell comprising a ReRAM device including a solid electrolyte layer disposed between a first ion source electrode and a second electrode at a bitline node; and a selection circuit comprising two series-connected selection transistors connected in series with the ReRAM device at the second electrode of the ReRAM device to a source line node, each of the two series-connected selection transistors having a gate connected to a separate control line. The method comprises: determining whether the ReRAM cell is selected for erasure; if the ReRAM cell is selected for erasure, biasing the bitline node at a first voltage potential, biasing the source line node at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device in the ReRAM cell, and providing a positive voltage pulse to the gates of the series-connected transistors; and if the ReRAM cell is not selected for erasure, providing a voltage potential insufficient to turn on the gate of one of the series-connected transistors, having its drain connected to the second electrode of the ReRAM device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The invention will now be explained in more detail with reference to embodiments and the accompanying drawings, in which:

[0022] Figure 1 is a schematic diagram of an exemplary prior art ReRAM memory cell;

[0023] Figure 2 is a schematic diagram of an exemplary ReRAM memory cell according to an aspect of the present invention;

[0024] Figure 3 is a schematic diagram of an exemplary ReRAM memory cell array according to an aspect of the present invention;

[0025] Figure 4 is a table showing exemplary voltage potentials applied to a ReRAM memory cell of the present invention during its various operating modes;

[0026] Figure 5A is a waveform diagram illustrating an exemplary programming pulse sequence for programming a ReRAM memory cell; and

[0027] Figure 5B is a waveform diagram illustrating an exemplary erase pulse sequence for erasing a ReRAM memory cell. DETAILED DESCRIPTION

[0028] Those skilled in the art will recognize that the following description is illustrative only and not limiting in any way. Other embodiments will readily occur to those skilled in the art.

[0029] Now refer to Figure 2 , a schematic diagram shows an exemplary ReRAM memory cell according to an aspect of the present invention depicted within dashed line 30. The ReRAM memory cell 30 includes a ReRAM device 32 connected in series with a first select transistor 34 and a second select transistor 36 connected in series. The memory cell 30 is coupled between a bit line (BL) 38 to which one terminal (“bit line node”) of the ReRAM device 32 is connected and a source line (SL) 40 to which the source of the select transistor 36 is connected (“source line node”). The source line (SL) 40 is a decoded source line and is addressed by a source line decoder, as will be described with reference to FIG. Figure 3The reason for decoding the source line (SL) 40 is to avoid stressing the ReRAM memory cells 30 that are not being programmed or erased and are connected to the bit lines in the columns of the array during programming or erasing operations. The gate of the select transistor 34 is connected to the word line (WLA) 42. The gate of the select transistor 36 is connected to the word line (WLB) 44. Providing separate control of the gates of the select transistors 34 and 36 in accordance with the present invention provides significant advantages. In an array of such memory cells 30, the bit lines 38 and source lines 40 typically run in the column direction of the array, while the word lines 42 and 44 typically run in the row direction of the array.

[0030] Now refer to Figure 3 , a schematic diagram depicts an exemplary array 50 of ReRAM memory cells according to an aspect of the present invention. For illustrative purposes, the array 50 is shown as having three rows and three columns. One of ordinary skill in the art of arrays will understand that arrays of any size are within the scope of the present invention.

[0031] The first row of array 50 includes ReRAM memory cells 30-00, 30-01, and 30-02, as shown within the dashed lines. The second row of array 50 includes ReRAM memory cells 30-10, 30-11, and 30-12, as shown within the dashed lines. The third row of array 50 includes ReRAM memory cells 30-20, 30-21, and 30-22, as shown within the dashed lines. The first column of the array includes ReRAM memory cells 30-00, 30-10, and 30-20. The second column of the array includes ReRAM memory cells 30-01, 30-11, and 30-21. The third column of the array includes ReRAM memory cells 30-02, 30-12, and 30-22.

[0032] The ReRAM memory cells 30-00, 30-10, and 30-20 in the first column of the array are connected between a bit line (BL0) 38-0 and a source line (SL0) 40-0. The ReRAM memory cells 30-01, 30-11, and 30-21 in the second column of the array are connected between a bit line (BL1) 38-1 and a source line (SL1) 40-1. The ReRAM memory cells 30-02, 30-12, and 30-22 in the third column of the array are connected between a bit line (BL2) 38-2 and a source line (SL2) 40-2.

[0033] The gates of the select transistors 34-00, 34-01, and 34-02 in the ReRAM memory cells 30-00, 30-01, and 30-02 in the first row of the array are respectively connected to a word line (WLA0) 42-0. The gates of the select transistors 36-00, 36-01, and 36-02 in the ReRAM memory cells 30-00, 30-01, and 30-02 in the first row of the array are respectively connected to a word line (WLB0) 44-0.

[0034] The gates of the select transistors 34-10, 34-11, and 34-12 in the ReRAM memory cells 30-10, 30-11, and 30-12 in the second row of the array are respectively connected to a word line (WLA1) 42-1. The gates of the select transistors 36-10, 36-11, and 36-12 in the ReRAM memory cells 30-10, 30-11, and 30-12 in the second row of the array are respectively connected to a word line (WLB1) 44-1.

[0035] The gates of the select transistors 34-20, 34-21, and 34-22 in the ReRAM memory cells 30-20, 30-21, and 30-22 in the third row of the array are respectively connected to a word line (WLA2) 42-2. The gates of the select transistors 36-20, 36-21, and 36-22 in the ReRAM memory cells 30-20, 30-21, and 30-22 in the third row of the array are respectively connected to a word line (WLB2) 44-2.

[0036] The source line decoder 52 drives the source lines 40-0, 40-1, and 40-2 to the voltages necessary to enable the memory cells in the array to operate in various operating modes. The operation of the source line decoder 52 is directed by the memory controller 54. The address provided to the source line decoder 52 can be the same address provided to the bit line decoder 56, which is used to drive and sense the bit lines 38-0, 38-1, and 38-2. The word line decoder 58 drives the word lines 42-0, 42-1, 42-2, 44-0, 44-1, and 44-2 to the voltages necessary to enable the memory cells in the array to operate in various operating modes. The operation of the bit line decoder 56 and the word line decoder 58 are directed by the memory controller 54 (connections omitted for simplicity). The circuitry within the source line decoder 52, the memory controller 54, the bit line controller 56, and the word line controller 58 is readily configured by one of ordinary skill in the art who understands the memory array control circuitry and the various potentials that need to be applied to the memory cells during the various operating modes described herein. Exemplary potentials are shown in FIG. Figure 4 The table below describes the

[0037] Now refer to Figure 4, shows exemplary voltage potentials applied to the memory cell during various operating modes (including read, program, program inhibit, erase, and erase inhibit) of the ReRAM memory cell of the present invention. One of ordinary skill in the art will understand that Figure 4 The voltage values ​​given in the table provide a general guide to the operation of the ReRAM memory cell of the present invention, and the exact values ​​for any actual array of ReRAM memory cells according to the present invention will depend on the device geometry and design considerations as well as the specific fabrication steps and processes.

[0038] Figure 5A and Figure 5B are waveform diagrams illustrating exemplary programming pulse sequences for programming and erasing, respectively, a ReRAM memory cell. Figure 5A An exemplary programming pulse sequence for programming a ReRAM memory cell is shown, and Figure 5B An exemplary pulse sequence for erasing a ReRAM memory cell is shown. Different voltages applied to word lines WLA (42) and WLB (44) during programming are shown. Figure 5A Shown as a solid line (WLA) and a dashed line (WLB). Figure 5B The single trace in reflects the fact that both word lines WLA (42) and WLB (44) are driven to the same voltage (1.8V) during erase.

[0039] Figure 4 The read column of the table shows exemplary potentials applied to various inputs of a ReRAM memory cell during a read operation. The decoded source line 40 is set to 0V. The word lines WLA42 and WLB44 that select the row for reading are both driven to 1V. The voltage at the bit line 38 is sensed. The bit line 38 is clamped to a voltage limited to approximately 0.3V. If the ReRAM device in the memory cell is in the programmed (low impedance) state, the voltage at the bit line 38 will be pulled down to near 0V because the select transistors are both in the on state. If the ReRAM device in the memory cell is in the erased (high impedance) state, the voltage at the bit line 38 will remain at a level close to the 0.3V clamp value. The word lines WLA42 and WLB44 for the unselected rows are both driven to 0V to keep the corresponding select transistors 34, 36 in the off state.

[0040] Figure 4 The Program column of the table shows exemplary potentials applied to the various inputs to the ReRAM memory cells during a programming operation. Programming is controlled row by row in the array. There are a variety of ways to program ReRAM devices. FIG5 illustrates a particular exemplary method in which a series of programming pulses is supplied to both word lines WLA42 and WLB44 of a selected row. Figure 45 , the bit line 38 is driven to 2.4V and the decoded source line is set to 0V. The word line WLA 42 of the selected row is driven by a series of 2.4V programming pulses interleaved with 1V read pulses, during which the resistance of the ReRAM device is measured. The word line WLB 44 of the selected row is driven by a series of 2.0V programming pulses interleaved with 1V read pulses, during which the resistance of the ReRAM device is measured. Figure 5A In the example shown, the programming pulses continue until the resistance of the ReRAM device 12 reaches a predetermined level to indicate that it has been successfully programmed. Measuring the actual resistance of the ReRAM device 12 is not required, and a comparison with a predetermined threshold is sufficient, with a resistance less than the predetermined threshold being used to indicate that it has been successfully programmed. By applying different programming pulse voltages to the word lines WLA 42 and WLB 44 in the cell to be programmed, the impedances of transistors 34 and 36 remain approximately equal, and both transistors 34 and 36 dissipate approximately the same power. In other words, the magnitude of the pulse voltage is selected so that each of transistors 34 and 36 dissipates approximately the same power.

[0041] Figure 4 The program inhibit column of the table shows exemplary potentials applied to various inputs of ReRAM memory cell 30 during a programming operation to inhibit ReRAM memory cell 30 from being programmed. Programming is controlled row by row in the array, and word line WLB 44 in the row containing the ReRAM device to remain unprogrammed is set to 0V to inhibit programming. Word line WLA 42 is set to 1.2V, which, as will be described further, is a non-limiting embodiment of a voltage that ensures that the gate-drain voltages of both transistors 34 and 36 are approximately equal and approximately half the applied programming voltage. The bit line voltage and source line voltage are set to the same levels as in the programming column. Transistor 36 is turned off due to its gate being at 0V. The drain voltage at transistor 36 is set by the gate voltage at transistor 34 and is limited to the gate-source voltage of transistor 34, which, in this non-limiting embodiment, is less than approximately 0.2V. Under these conditions, the gate-drain voltages of both transistors 34 and 36 are approximately equal and approximately half the applied programming voltage. This reduces the electric field which makes GIDL approximately equal in both transistors 34 and 36 and thus in Figure 1 The GIDL on transistor 14 in the prior art cell is about half that of the GIDL on transistor 14 in the prior art cell.

[0042] Figure 4 The Erase column of the table shows exemplary potentials applied to various inputs of a ReRAM memory cell during an erase operation. Similar to programming, erasure is controlled row by row in the array. Figure 4In the example in the table of , bit line 38 is driven to 0 V and the decoded source line is set to 1.8 V. Word lines WLA 42 and WLB 44 in the row selected for erasure are each driven with a series of 1.8 V erase pulses to provide maximum current through both transistors 34 and 36. The erase pulses are interleaved with 1 V read pulses during which the resistance of the ReRAM device is measured. Figure 5B In the example shown, the erase pulse continues until the resistance of the ReRAM device 12 reaches a predetermined level to indicate that it has been successfully erased. Measuring the actual resistance of the ReRAM device 12 is not required, and a comparison with a predetermined threshold is sufficient, with a resistance greater than the predetermined threshold being used to indicate that it has been successfully erased. There is no reason to apply different voltages to the gates of the two transistors 34 and 36 because there is no GIDL condition when the ReRAM memory cell is erased, as the gate-drain voltage of both transistors 34 and 36 in the erased ReRAM memory cell in this embodiment is approximately 0.6V.

[0043] Figure 4 The Erase Inhibit column of the table shows exemplary potentials applied to various inputs of a ReRAM memory cell during an erase operation to inhibit the ReRAM memory cell from being erased. Erasure is controlled row by row in the array, and the word line WLA 42 in the row containing the ReRAM device to be inhibited from being erased is set to 0V to inhibit erasure. In this non-limiting embodiment, the word line WLB in the row containing the ReRAM device to be inhibited from being erased is set to 1.2V. The bit line and source line voltages are set to the same levels as in the Erase column. By setting word line WLB2 to 1.2V, the erase voltage is divided approximately equally between transistors 34 and 36, and GIDL is disabled in transistor 36. The specific voltage to be applied to WLB2 during erase is selected so that the erase voltage is divided approximately equally between transistors 34 and 36.

[0044] The use of two series-connected NMOS transistors 34 and 36 whose gates are driven to different voltages by separate word lines reduces the GIDL problem during program inhibit and erase inhibit. By applying different programming pulse voltages to word lines WLA 42 and WLB 44 in the cells to be programmed, the impedances of transistors 34 and 36 remain approximately equal and dissipate approximately the same power.

[0045] The use of two series-connected NMOS transistors driven by separate word lines also provides a reduction in gate-induced drain leakage (GIDL) in the select transistor during program-inhibit and erase-inhibit operations. This allows for targeted gate voltage control for the unselected off path to significantly reduce GIDL. Lower GIDL translates into lower overall power consumption during program and erase operations and higher sensing accuracy during read operations.

[0046] In the programming inhibit condition, Figure 1 Setting the WLA voltage to 1.2V reduces the Figure 2 The magnitude of the electric field between the gate and drain of NMOS transistor 34 is reduced, which results in a significantly lower GIDL. In addition, this biasing scheme effectively divides the voltage between bit line (BL) 38 and source line (SL) 40, thereby limiting the maximum voltage exposure of each transistor in the series-connected transistors 34 and 36.

[0047] In the case of erasure prohibition, Figure 1 Setting the WLB voltage to 1.2V reduces the magnitude of the electric field between the gate and source of NMOS transistor 36, which also results in a significantly lower GIDL, compared to the depicted prior art cell. As in the program inhibit case, this biasing scheme effectively divides the voltage between bit line (BL) 38 and source line (SL) 40, thereby limiting the maximum voltage exposure of each of the series-connected transistors 34 and 36.

[0048] As noted above, the specific voltages utilized are not intended to be limiting and are provided merely as specific examples of suitable voltages for certain currently available transistors.

[0049] While the embodiments and applications of the present invention have been shown and described, it will be apparent to those skilled in the art that many more modifications than those described above may be made without departing from the inventive concepts herein. Accordingly, the present invention is not to be restricted except in the spirit of the appended claims.

Claims

1. A ReRAM memory cell, comprising: a ReRAM device comprising a solid electrolyte layer disposed between a first ion source electrode and a second electrode; two series-connected select transistors connected in series with the ReRAM device, each of the two series-connected select transistors having a gate connected to a separate control line, When the ReRAM memory cell is not selected for programming, the gate-drain voltages of the two series-connected selection transistors are equal and are half of the applied programming voltage. 2 . The ReRAM memory cell of claim 1 , wherein the two series-connected select transistors comprise two series-connected n-channel select transistors connected in series to the second electrode of the ReRAM device.

3. A ReRAM memory cell, comprising: First node; Second node; a ReRAM device comprising a solid electrolyte layer disposed between a first ion source electrode and a second electrode, the first ion source electrode being connected to the first node; a first n-channel selection transistor, wherein the first n-channel selection transistor is connected to the a second n-channel selection transistor connected in series between the second electrode and the second node of the ReRAM device, the first n-channel selection transistor having a gate connected to the first selection node, and the second n-channel selection transistor having a gate connected to the second selection node, When the ReRAM memory cell is not selected for programming, the gate-drain voltages of the first n-channel selection transistor and the second n-channel selection transistor are equal and half of an applied programming voltage.

4. The ReRAM memory cell according to claim 3, wherein: The first node is connected to a bit line; The second node is connected to a source line; The first selection node is connected to a first word line; and The second selection node is connected to a second word line.

5. The ReRAM memory cell of claim 4, wherein the source line is a decoded source line. 6 . The ReRAM memory cell of claim 4 , wherein the first word line and the second word line are decoded word lines.

7. The ReRAM memory cell of claim 4, wherein the bit line is a decoded bit line.

8. A ReRAM memory array, the ReRAM memory array being arranged to form interleaved rows and columns, the ReRAM memory array comprising: a plurality of ReRAM memory cells, each ReRAM memory cell comprising a ReRAM device having a solid electrolyte layer disposed between a first ion source electrode and a second electrode; and a selection circuit having two series-connected selection transistors connected in series with the ReRAM device, each of the two series-connected selection transistors having a gate connected to a separate control line, When one of the plurality of ReRAM memory cells is not selected for programming, gate-drain voltages of two series-connected selection transistors of the ReRAM memory cell are equal and are half of an applied programming voltage. 9 . The ReRAM memory array of claim 8 , wherein the two series-connected select transistors are n-channel transistors.

10. The ReRAM memory array of claim 8 , wherein each row of the array comprises a first word line connected to the control line of a first of the two series-connected select transistors of each ReRAM memory cell in the row; and a second word line connected to the control line of a second of the two series-connected select transistors of each ReRAM memory cell in the row.

11. The ReRAM memory array of claim 8 , wherein each column of the array comprises a bit line connected to a first node of each ReRAM memory cell in the row and a decoded source line connected to a second node of each ReRAM memory cell in the row.

12. The ReRAM memory array according to claim 8, wherein: Each ReRAM device has a solid electrolyte layer disposed between a first ion source electrode and a second electrode, the first ion source electrode being connected to a first node; and The two series-connected selection transistors include a first n-channel selection transistor connected in series with a second n-channel selection transistor between the second electrode and a second node of the ReRAM device, the first n-channel selection transistor having a gate connected to the first selection node, and the second n-channel selection transistor having a gate connected to the second selection node.

13. The ReRAM memory array of claim 12 , wherein each row of the array comprises a first word line connected to the gate of the first n-channel select transistor of each ReRAM memory cell in the row; and a second word line connected to the gate of the second n-channel select transistor of each ReRAM memory cell in the row.

14. The ReRAM memory array of claim 12 , wherein each column of the array comprises a bit line connected to the first node of each ReRAM memory cell in the row; and a decoded source line connected to the second node of each ReRAM memory cell in the row.

15. A method for programming a ReRAM memory cell, the ReRAM memory cell comprising a ReRAM device including a solid electrolyte layer disposed between a first ion source electrode and a second electrode at a bit line node; and a selection circuit comprising two series-connected selection transistors connected in series with the ReRAM device at a second electrode to a source line node, each of the two series-connected selection transistors having a gate connected to a separate control line, the method comprising: determining whether the ReRAM memory cell is selected for programming; if the ReRAM memory cell is selected for programming, biasing the bit line node at a first voltage potential, biasing the source line node at a second voltage potential that is less than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to program the ReRAM device in the ReRAM memory cell, and providing a positive voltage pulse having a first magnitude to the gate of one of the series-connected transistors having its source connected to the source line node, and providing a positive voltage pulse having a second magnitude that is greater than the first magnitude to the gate of another of the series-connected transistors; as well as If the ReRAM memory cell is not selected for programming, a voltage potential insufficient to turn the gate of the one of the series-connected transistors having its source connected to the source line node is provided to the gate.

16. The method according to claim 15, further comprising: If the ReRAM memory cell is not selected for programming, providing a voltage potential to the gate of the one of the series-connected transistors having its drain connected to the ReRAM device at the second electrode of the ReRAM device such that the gate-drain voltages of the two series-connected select transistors are equal.

17. A method for erasing a ReRAM memory cell, the ReRAM memory cell comprising a ReRAM device including a solid electrolyte layer disposed between a first ion source electrode and a second electrode at a bit line node; and a selection circuit comprising two series-connected selection transistors connected in series with the ReRAM device at the second electrode to a source line node, each of the two series-connected selection transistors having a gate connected to a separate control line, the method comprising: determining whether the ReRAM memory cell is selected for erasure; if the ReRAM memory cell is selected for erasure, biasing the bit line node at a first voltage potential, biasing the source line node at a second voltage potential greater than the first voltage potential, the difference between the first voltage potential and the second voltage potential being sufficient to erase the ReRAM device in the ReRAM memory cell, and providing a positive voltage pulse to the gates of the series-connected transistors; as well as If the ReRAM memory cell is not selected for erasing, a voltage potential insufficient to turn on one of the series-connected transistors having its drain connected to the second electrode of the ReRAM device is provided to the gate.

18. The method according to claim 17, further comprising: If the ReRAM memory cell is not selected for erasure, a voltage potential is provided to the gate of another series-connected transistor, the voltage potential being selected to evenly divide the voltage between the two series-connected select transistors.

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