Semiconductor device with a camouflage design, multiplexer unit, and method of forming the same

Abstract

Embodiments of the present invention relate to a semiconductor device with a camouflage design, a multiplexer unit, and a method of forming the same. The semiconductor device includes a semiconductor substrate, a conductive segment, a conductive layer, a first contact element, and a second contact element. The semiconductor substrate includes an active region. The conductive segment is formed on the semiconductor substrate and extends across the active region. The conductive layer is formed over the semiconductor substrate and the conductive segment. The first contact element formed between the conductive segment and a first conductive portion of the conductive layer is arranged to electrically connect the conductive segment to the first conductive portion. The second contact element is formed between the conductive segment and a second conductive portion of the conductive layer. The first contact element and the second contact element are formed on the conductive segment and spaced apart from each other. The second contact element is arranged to electrically isolate the conductive segment from the second conductive portion.

Description

Technical Field

[0001] Embodiments of the present invention relate to a multiplexer unit and a semiconductor device having a camouflage design, and a method of forming a multiplexer unit. Background Art

[0002] This disclosure relates to semiconductor device design, and more particularly, this disclosure relates to a multiplexer unit, a semiconductor device having a camouflage design, and a method of forming a semiconductor device.

[0003] Reverse engineering (RE) of an electronic chip is a process of inspecting and analyzing circuit components contained in an integrated circuit (IC) to reveal the structure and function of each circuit component. Using reverse engineering techniques, an attacker can steal design intellectual property (IP). The reverse engineering process associated with circuit extraction may include package removal, delayer, and image processing. Package removal can etch the package without damaging the die. Delayer can extract physical interconnection information layer by layer. Image processing can obtain an optical image of each circuit layer and reconstruct the structure of circuit components. Summary of the Invention

[0004] Embodiments of the present invention relate to a multiplexer unit, comprising: a semiconductor substrate; a conductive layer formed over the semiconductor substrate; a plurality of pairs of transistors formed on the semiconductor substrate, each pair of transistors including a p-channel transistor and an n-channel transistor, a gate structure, a first source / drain structure, and a second source / drain structure of each of the p-channel transistor and the n-channel transistor being electrically connected to the conductive layer, the gate structure including: a conductive segment formed on the semiconductor substrate and extending across an active region of the semiconductor substrate, the first source / drain structure and the second source / drain structure being formed on the active region and located at opposite sides of the conductive segment, a first conductive portion and a second conductive portion of the conductive layer crossing a first portion and a second portion of the conductive segment respectively; a first contact element and a second contact element formed on the first portion and the second portion of the conductive segment respectively, the first contact element being arranged to electrically connect the conductive segment to the first conductive portion, the second contact element being arranged to electrically isolate the conductive segment from the second conductive portion; and an interconnect structure located between each pair of transistors and electrically connected to the conductive layer, wherein the transistor pairs include a first pair of transistors, a second pair of transistors, and a third pair of transistors, the interconnect structure being arranged to electrically connect each gate structure of the first pair of transistors, each first source / drain structure of the second pair of transistors, and each first source / drain structure of the third pair of transistors to a selection terminal, a first input terminal, and a second input terminal of the multiplexer unit respectively.

[0005] Embodiments of the present invention relate to a semiconductor device, which includes: a conductive layer formed over a semiconductor substrate; a transistor structure formed on a first region of the semiconductor substrate, the transistor structure including: a polysilicon gate segment, a first conductive wire and a second conductive wire of the conductive layer respectively crossing a first portion and a second portion of the polysilicon gate segment; a first contact element formed on the first portion of the polysilicon gate segment and in contact with the first conductive wire; and a second contact element formed on the second portion of the polysilicon gate segment and in contact with the second conductive wire; and an interconnect structure formed on a second region of the semiconductor substrate different from the first region, the interconnect structure including: a third conductive wire and a fourth conductive wire respectively coupled to the first conductive wire and the second conductive wire, each of the third conductive wire and the fourth conductive wire extending in a first direction; a plurality of fifth conductive wires formed at a level different from each of the third conductive wire and the fourth conductive wire, each fifth conductive wire extending in a second direction different from the first direction; a plurality of third contact elements respectively formed on different portions of the third conductive wire crossed by the fifth conductive wires, wherein one of the third contact elements is arranged to electrically connect the third conductive wire to the fifth conductive wire; and a plurality of fourth contact elements respectively formed on different portions of the fourth conductive wire crossed by the fifth conductive wires, wherein one of the fourth contact elements is arranged to electrically isolate the fourth conductive wire from the fifth conductive wire.

[0006] Embodiments of the present invention relate to a method for forming a multiplexer unit, which includes: forming a plurality of polysilicon segments of a plurality of transistors on a semiconductor substrate, the transistors including a plurality of p-channel transistors located on an upper portion of the semiconductor substrate and a plurality of n-channel transistors located on a lower portion of the semiconductor substrate, each polysilicon segment extending across an active region of the semiconductor substrate to define a first source / drain region and a second source / drain region; forming a plurality of contact elements on the polysilicon segments, the first source / drain region, and the second source / drain region of each transistor; forming a conductive layer on the contact elements, the conductive layer including a first conductive portion and a second conductive portion separated from each other, wherein the polysilicon segment is electrically isolated from the first conductive portion through a first contact element of the contact elements and electrically connected to the second conductive portion through a second contact element of the contact elements; interconnecting a first p-channel transistor and a first n-channel transistor of the transistors through the conductive layer to form an inverter; interconnecting a second p-channel transistor and a second n-channel transistor of the transistors through the conductive layer to form a first transmission gate, wherein the respective polysilicon segments of the second p-channel transistor and the second n-channel transistor are electrically connected to an input and an output of the inverter respectively; and interconnecting a third p-channel transistor and a third n-channel transistor of the transistors through the conductive layer to form a second transmission gate, wherein the respective polysilicon segments of the second p-channel transistor and the second n-channel transistor are electrically connected to the output and the input of the inverter respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various components are not drawn to scale. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 Illustrate an example semiconductor structure that utilizes dummy contacts to provide a camouflage design in accordance with some embodiments of the present invention.

[0009] Figure 2 is a circuit diagram of an example multiplexer unit in accordance with some embodiments of the present invention.

[0010] Figures 3A to 3G Illustrate the use in accordance with some embodiments of the present invention Figure 2 of different logic gates implemented by the multiplexer unit shown in

[0011] Figure 4A Illustrate an example layout design of a semiconductor device in accordance with some embodiments of the present invention.

[0012] Figures 4B to 4D Illustrate in accordance with some embodiments of the present invention alongFigure 4A Cross-sectional views taken along different lines in

[0013] Figure 5 is a circuit diagram of an example multiplexer unit according to some embodiments of the present invention.

[0014] Figures 6A to 6G Illustrates the use according to some embodiments of the present invention Figure 5 different logic gates implemented by the multiplexer unit shown in

[0015] Figure 7 Illustrates an example layout design of a semiconductor device according to some embodiments of the present invention.

[0016] Figure 8 Illustrates an example semiconductor device according to some embodiments of the present invention.

[0017] Figure 9 is a flowchart of a method for forming a semiconductor device according to some embodiments of the present invention.

[0018] Figures 10A to 10F Illustrates the corresponding structures in different manufacturing stages according to some embodiments of the present invention along Figure 4A the cross-section taken along the line in

[0019] Figure 11 is a flowchart of a method for forming a multiplexer unit according to some embodiments of the present invention. Detailed Description

[0020] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, forming a first member above or on a second member may include embodiments in which the first member and the second member are formed in direct contact, and may also include embodiments in which additional members may be formed between the first member and the second member such that the first member and the second member do not directly contact. Additionally, the disclosure may repeat element symbols and / or letters in various examples. This repetition is for simplicity and clarity and does not itself indicate a relationship between each of the discussed embodiments and / or configurations.

[0021] Furthermore, it should be understood that when an element is referred to as "connected to" or "coupled to" another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.

[0022] In addition, for ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper" and the like may be used herein to describe the relationship of an element or component to another element or component, as illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may thus be interpreted accordingly.

[0023] To guard against reverse engineering attacks, different types of logic gates can be made to look similar to hide the circuit function thereby. For example, groups of logic gates that look similar can be constructed. Some of the logic gates in a circuit design can be replaced by groups of logic gates that look similar to disguise the actual circuit function. However, since the number of logic gates that can be replaced by groups of logic gates that look similar is limited, an attacker may have a slim chance of guessing the actual function of the circuit design. One or more algorithms will be used to analyze which logic gates in the replaceable circuit design can be used to reduce the risk of information leakage through reverse engineering.

[0024] This disclosure describes semiconductor devices each having a camouflage design implemented using a universal gate such as a multiplexer unit. Each logic circuit included in the semiconductor device can be constructed by utilizing the universal gate. When an attacker attempts to reverse engineer the semiconductor device, it is difficult to decrypt the actual design of the semiconductor device because the logic circuit has a universal layout structure in each de-layering stage. For example, the universal gate can include a plurality of contact elements formed between different layers (such as a transistor layer, a conductive layer, or other types of semiconductor layers). At least one of the contact elements (referred to as a true contact point) is arranged to electrically connect the layers to each other. At least one of the contact elements (referred to as a false contact point) is arranged to electrically isolate the layers from each other. By using the false contact points, the logic circuit can be implemented as a plurality of camouflage circuits respectively. The camouflage circuits can have the same arrangement of contact elements, while the arrangement of the false contact points in one camouflage circuit can be different from the arrangement of the false contact points in another camouflage circuit. Therefore, when viewed from the top of the semiconductor substrate, it is difficult to identify whether a contact element is a true contact point or a false contact point in each de-layering stage. An attacker cannot easily see the actual function of the semiconductor device.

[0025] Reference Figure 1, illustrate an example semiconductor structure providing a camouflage design using dummy contacts according to some embodiments of the present invention. The semiconductor structure 100 may include (but is not limited to) a transistor layer 110, a conductive layer 120, and a plurality of interconnect structures 103.1 and 103.2. In this embodiment, the transistor layer 110 may include a plurality of transistor structures 102.1 to 102.4. Each of the transistor structures 102.1 and 102.2 may be implemented to include an n-channel transistor formed on a semiconductor substrate 101. Each of the transistor structures 102.3 and 102.4 may be implemented to include a p-channel transistor formed on an n-well region 101.1 in the semiconductor substrate 101.

[0026] The transistor structure 102.1 includes a gate dielectric GD1, a polysilicon gate segment PG1, a plurality of source / drain regions SD11 and SD12, and a plurality of contact elements 122.1 to 122.3. The conductive layer 120 (which may be a first metal layer (M0) formed on the transistor layer 110) includes a plurality of conductive portions 120.1 to 120.3 formed on the transistor structure 102.1. In this embodiment, the gate dielectric GD1, the polysilicon gate segment PG1, and the contact element 122.1 may be used to implement at least a part of the gate structure of the transistor structure 102.1. The source / drain region SD11 and the contact element 122.2 may be used to implement at least a part of the source / drain structure of the transistor structure 102.1. The source / drain region SD12 and the contact element 122.3 may be used to implement at least a part of another source / drain structure of the transistor structure 102.1.

[0027] The gate dielectric GD1 is formed on the semiconductor substrate 101. The gate dielectric GD1 may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or a combination thereof. A polysilicon segment or a polysilicon-germanium segment may be used to implement the polysilicon gate segment PG1 formed on the gate dielectric GD1. In some embodiments, the polysilicon gate segment PG1 may be replaced by other types of conductive segments (such as metal segments). In some embodiments, the polysilicon gate segment PG1 may be replaced by a plurality of conductive segments stacked on top of each other. The source / drain regions SD11 and SD12 located on opposite sides of the polysilicon gate segment PG1 may be doped with an n-type dopant to form N+ doped regions in the semiconductor substrate 101.

[0028] The contact element 122.1 (which is formed on the polysilicon gate segment PG1 and contacts the conductive part 120.1) is arranged to electrically connect the polysilicon gate segment PG1 to the conductive part 120.1 so as to act as a gate contact thereby. The contact element 122.2 (which is formed on the source / drain region SD11 and contacts the conductive part 120.2) is arranged to electrically connect the source / drain region SD11 to the conductive part 120.2 so as to act as a source / drain contact thereby. At least one of the contact elements 122.1 and 122.2 can be implemented as a conductive via or other type of conductive structure. A conductive material such as Cu, Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti / W, Ti / TiN, any other known conductive or semiconductive material, or a combination thereof can be used to form each of the contact elements 122.1 and 122.2.

[0029] The contact element 122.3 (which is formed on the source / drain region SD12 and contacts the conductive part 120.3) is arranged to electrically isolate the source / drain region SD12 from the conductive part 120.3. The contact element 122.3 can pretend to be a source / drain contact placed on the source / drain region SD12. For example, the contact element 122.3 can include a conductive segment 122.3a and a non-conductive segment 122.3b stacked on top of each other. The height of the non-conductive segment 122.3b is much smaller than the height of the conductive segment 122.3a. Therefore, when viewed from the top of the conductive layer 120 or through the plane of the contact elements 122.1 to 122.3, in the layer-removing stage of the reverse engineering process, the contact element 122.3 seems to be a real source / drain contact similar or identical to the contact element 122.2.

[0030] In this embodiment, the conductive segment 122.3a can be stacked on the non-conductive segment 122.3b. For example, the conductive segment 122.3a can be implemented as a conductive via or other type of conductive structure formed on the non-conductive segment 122.3b. A conductive material such as Cu, Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti / W, Ti / TiN, any other known conductive or semiconductive material, or a combination thereof can be used to form the conductive segment 122.3a. The non-conductive segment 122.3b can be implemented as an insulating film or other type of insulating structure. The insulating film can be a single-layer insulating film or a laminated insulating film. For example (but not limited to), the non-conductive segment 122.3b can be implemented as a thin insulating film having a thickness of 10 nm to 30 nm. An insulating material such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, other types of insulating materials, or a combination thereof can be used to form the non-conductive segment 122.3b. A deposition process such as thermal oxidation deposition or chemical vapor deposition (CVD) can be used (but not limited to) to form the non-conductive segment 122.3b.

[0031] In some embodiments, a non-conductive segment 122.3b may be formed between the conductive portion 120.3 and the conductive segment 122.3a such that the non-conductive segment 122.3b is stacked on the conductive segment 122.3a. In some embodiments, the contact element 122.3 may include at least one conductive segment and at least one non-conductive segment stacked on top of each other. Associated modifications and alternatives are also within the scope of the present invention.

[0032] The transistor structure 102.2 may be similar or identical to the transistor structure 102.1 except that the actual design of the transistor structure 102.2 is disguised by a dummy gate contact. The transistor structure 102.2 includes a gate dielectric GD2, a polysilicon gate segment PG2, a plurality of source / drain regions SD21 and SD22, and a plurality of contact elements 122.4 to 122.6. The gate dielectric GD2, the polysilicon gate segment PG2, and the contact element 122.4 may be used to implement at least a part of the gate structure of the transistor structure 102.2. The source / drain region SD21 and the contact element 122.5 may be used to implement at least a part of the source / drain structure of the transistor structure 102.2. The source / drain region SD22 and the contact element 122.6 may be used to implement at least a part of another source / drain structure of the transistor structure 102.2. Additionally, a plurality of conductive portions 120.4 to 120.6 of the conductive layer 120 may be formed on the transistor structure 102.2.

[0033] In the present embodiment, the contact element 122.5 may act as a source / drain contact arranged to electrically connect the source / drain region SD21 to the conductive portion 120.5. The contact element 122.6 may act as a source / drain contact arranged to electrically connect the source / drain region SD22 to the conductive portion 120.6. The contact element 122.4 (which is arranged to electrically isolate the polysilicon gate segment PG2 from the conductive portion 120.4) may pretend to be a gate contact placed on the polysilicon gate segment PG2. For example, the height of the non-conductive segment 122.4b is much smaller than the height of the conductive segment 122.4a. When viewed from the top of the conductive layer 120 or through the plane of the contact elements 122.4 to 122.6, during the layer-removal stage of a reverse-engineering process, the contact element 122.4 appears to be a real gate contact similar or identical to the contact element 122.1.

[0034] Except that the actual design of the transistor structure 102.3 is disguised by dummy gate contacts and dummy source / drain contacts, the transistor structure 102.3 may be similar or identical to the transistor structures 102.1 / 102.2. For example, the transistor structure 102.3 may be implemented to include a p-channel transistor. The transistor structure 102.3 includes a gate dielectric GD3, a polysilicon gate segment PG3, a plurality of source / drain regions SD31 and SD32, and a plurality of contact elements 122.7 to 122.9. The source / drain regions SD31 and SD32 (which are located at opposite sides of the polysilicon gate segment PG3) may be doped with a p-type dopant to form P+ doped regions in the semiconductor substrate 101. The gate dielectric GD3, the polysilicon gate segment PG3, and the contact element 122.7 may be used to implement at least a part of the gate structure of the transistor structure 102.3. The source / drain region SD31 and the contact element 122.8 may be used to implement at least a part of the source / drain structure of the transistor structure 102.3. The source / drain region SD32 and the contact element 122.9 may be used to implement at least a part of another source / drain structure of the transistor structure 102.3.

[0035] In this embodiment, a plurality of conductive portions 120.7 to 120.9 of the conductive layer 120 may be formed on the transistor structure 102.3. The contact element 122.8 may act as a source / drain contact arranged to electrically connect the source / drain region SD31 to the conductive portion 120.8. The contact element 122.7 (which is arranged to electrically isolate the polysilicon gate segment PG3 from the conductive portion 120.7) may pretend to be a gate contact placed on the polysilicon gate segment PG3. The contact element 122.9 (which is arranged to electrically isolate the source / drain region SD32 from the conductive portion 120.9) may pretend to be a source / drain contact placed on the source / drain region SD32. For example, the height of the non-conductive segment 122.7b is much smaller than the height of the conductive segment 122.7a, and the height of the non-conductive segment 122.9b is much smaller than the height of the conductive segment 122.9a. When viewed from the top of the conductive layer 120 or through a plane passing through the contact elements 122.7 to 122.9, during the subtractive layer stage of a reverse engineering process, the contact element 122.7 appears to be a real gate contact similar or identical to the contact element 122.1, and the contact element 122.9 appears to be a real source / drain contact similar or identical to the contact element 122.8.

[0036] Except that each contact element can act as a true contact point, the transistor structure 102.4 can be similar to or the same as the transistor structure 102.3. The transistor structure 102.4 includes a gate dielectric GD4, a polysilicon gate segment PG4, a plurality of source / drain regions SD41 and SD42, and a plurality of contact elements 122.10 to 122.12. The gate dielectric GD4, the polysilicon gate segment PG4, and the contact element 122.10 can be used to implement at least a part of the gate structure of the transistor structure 102.3. The source / drain region SD41 and the contact element 122.11 can be used to implement at least a part of the source / drain structure of the transistor structure 102.4. The source / drain region SD42 and the contact element 122.12 can be used to implement at least a part of another source / drain structure of the transistor structure 102.4. Additionally, a plurality of conductive portions 120.10 to 120.12 of the conductive layer 120 can be formed on the transistor structure 102.4. In this embodiment, the contact element 122.10 can act as a gate contact point arranged to electrically connect the polysilicon gate segment PG4 to the conductive portion 120.10. The contact element 122.11 can act as a source / drain contact point arranged to electrically connect the source / drain region SD41 to the conductive portion 120.11. The contact element 122.12 can act as a source / drain contact point arranged to electrically connect the source / drain region SD42 to the conductive portion 120.12.

[0037] In this embodiment, at least one of the interconnect structures 103.1 and 103.2 can include one or more dummy contact points to disguise its actual design. For example, the interconnect structure 103.1 can include a plurality of conductive portions 130.1 and 140.1 and a plurality of contact elements 132.1 and 142.1. The conductive portion 130.1 is located in the conductive layer 130, and the conductive layer 130 can be a second metal layer (M1) formed above the transistor layer 110. The conductive portion 140.1 is located in the conductive layer 140, and the conductive layer 140 can be a third metal layer (M2) formed above the transistor layer 110. The contact element 132.1 (which acts as a true interlayer contact point placed between the conductive portion 120.6 and the conductive portion 130.1) can be implemented as a conductive via or other type of conductive structure. A conductive material such as Cu, Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti / W, Ti / TiN, any other known conductive or semi-conductive material, or a combination thereof can be used to form the contact element 132.1.

[0038] The contact element 142.1 (which is formed on the conductive portion 130.1 and contacts the conductive portion 140.1) is arranged to electrically isolate the conductive portion 130.1 from the conductive portion 140.1. The contact element 142.1 may pretend to be an interlayer contact between the conductive layers 130 and 140. For example, the contact element 142.1 may include conductive segments 142.1a and non-conductive segments 142.1b stacked on top of each other. The height of the non-conductive segment 142.1b is much smaller than the height of the conductive segment 142.1a. Thus, when viewed from the top of the conductive layer 140 or a plane between the conductive layers 130 and 140, during the layer-removal stage of a reverse-engineering process, the contact element 142.1 appears to be a genuine interlayer contact. In some embodiments, the structure of the contact element 142.1 may be similar or identical to the structure of the contact elements 122.3 / 122.4 / 122.7 / 122.9. Thus, for the sake of brevity, similar descriptions are not repeated herein.

[0039] The interconnect structure 103.2 may include a plurality of conductive portions 130.2, 130.3, and 140.2 and a plurality of contact elements 132.2, 132.3, and 142.2. Each of the conductive portions 130.2 and 130.3 is located in the conductive layer 130. The conductive portion 140.2 is located in the conductive layer 140. The contact element 132.2 (which serves as a genuine interlayer contact placed between the conductive portion 120.11 and the conductive portion 130.2) may be implemented as a conductive via or other type of conductive structure. The contact element 142.2 (which serves as a genuine interlayer contact placed between the conductive portion 130.3 and the conductive portion 140.2) may be implemented as a conductive via or other type of conductive structure. Each of the contact elements 132.2 and 142.2 may be formed using a conductive material such as Cu, Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti / W, Ti / TiN, any other known conductive or semiconductive material, or a combination thereof.

[0040] The contact element 132.3, which is formed on the conductive portion 120.12 and contacts the conductive portion 130.3, is arranged to electrically isolate the conductive portion 120.12 from the conductive portion 130.3. The contact element 132.3 can be pretended to be an interlayer contact between the conductive layers 130 and 140. For example, the contact element 132.3 can include conductive segments 132.3a and non-conductive segments 132.3b stacked on top of each other. The height of the non-conductive segment 132.3b is much smaller than the height of the conductive segment 132.3a. Therefore, when viewed from the top of the conductive layer 130 or the plane between the conductive layers 120 and 130, during the layer-removing stage of the reverse engineering process, the contact element 132.3 appears to be a true interlayer contact. In some embodiments, the structure of the contact element 132.3 can be similar or identical to the structure of the contact elements 122.3 / 122.4 / 122.7 / 122.9 / 142.1. Therefore, for the sake of brevity, similar descriptions are not repeated here.

[0041] It should be noted that when Figure 1 showing a cross-sectional view of the semiconductor structure 100, the semiconductor substrate 101 can be considered to extend along the XY plane, and each contact element can be considered to extend in a direction substantially perpendicular to the XY plane (e.g., a direction parallel to the Z axis).

[0042] Figure 1 The semiconductor structure 100 shown in is for illustrative purposes only and is not intended to limit the scope of the present invention. In some embodiments, one or more interlayer dielectrics can be formed between two adjacent layers of the transistor layer 110 and the conductive layers 120 to 140. In some embodiments, at least one of the transistor structures 102.1 to 102.4 can be implemented as a planar transistor structure or a three-dimensional transistor structure. In some embodiments, at least one true contact and at least one false contact can be formed on the same polysilicon gate segment, the same source / drain region, or the same conductive portion in the conductive layer to thereby disguise the actual design and function of the semiconductor device. In some embodiments, at least a part of the semiconductor structure 100 shown in Figure 1 can be used to implement a semiconductor device using a general-purpose gate design to thereby make it more difficult for an attacker to identify the actual design and function of the semiconductor device. The general-purpose gate design can be (but is not limited to) a NAND ("not and") gate design, a NOR ("not or") gate design, a NOT ("not") gate, a multiplexer design, or other types of general-purpose gate designs.

[0043] To facilitate the understanding of the present disclosure, some embodiments associated with the multiplexer unit are given below to further describe the semiconductor device with a disguised design. Those skilled in the art should understand that a disguised design using true and false contacts can be used to implement other types of general-purpose gates without departing from the scope of the present invention.

[0044] First, refer to Figure 2 FIG. 1, which illustrates a circuit diagram of an example multiplexer unit according to some embodiments of the present invention. In this embodiment, the multiplexer unit 200 may be implemented as a 2:1 multiplexer, which includes a plurality of input terminals IN0 and IN1, a selection terminal S, and an output terminal OUTX. The multiplexer unit 200 is configured to select one of the input signal at the input terminal IN0 and the input signal at the input terminal IN1 as the output signal at the output terminal OUTX according to the input signal at the selection terminal S.

[0045] The multiplexer unit 200 may further include a plurality of transistors PU0, PD0, TA0, TA1, TB0, and TB1. Each of the transistors PU0, TA0, and TB0 may be implemented using a p-channel transistor. Each of the transistors PD0, TA1, and TB1 may be implemented using an n-channel transistor. In this embodiment, the transistors PU0 and PD0 may be implemented as a pair of transistors. The respective gates of the transistors PU0 and PD0 are coupled to the selection terminal S. The respective sources of the transistors PU0 and PD0 are coupled to the supply voltage VDD and the supply voltage VSS, respectively. The respective drains of the transistors PU0 and PD0 are coupled to the connection terminal SB. Thus, the transistors PU0 and PD0 may act as an inverter.

[0046] The transistors TA0 and TA1 may be implemented as a pair of transistors. In this embodiment, the respective gates of the transistors TA0 and TA1 are coupled to the selection terminal S and the connection terminal SB, respectively. The respective sources of the transistors TA0 and TA1 are coupled to the input terminal IN1. The respective drains of the transistors TA0 and TA1 are coupled to the connection terminal OT, and the connection terminal OT is coupled to the output terminal OUTX. Thus, the transistors TA0 and TA1 may act as a transmission gate. Similarly, the transistors TB0 and TB1 may be implemented as a pair of transistors. The respective gates of the transistors TB0 and TB1 are coupled to the connection terminal SB and the selection terminal S, respectively. The respective sources of the transistors TB0 and TB1 are coupled to the input terminal IN0. The respective drains of the transistors TB0 and TB1 are coupled to the connection terminal OT. Thus, the transistors TB0 and TB1 may act as a transmission gate.

[0047] It should be noted that the multiplexer unit 200 may act as a universal gate capable of implementing various standard logic gates in different operation schemes. Figures 3A to 3G Illustrate different logic gates implemented using the multiplexer unit 200 shown in Figure 2 above. First, in Figure 3AIn the illustrated embodiment, the select terminal S, the input terminal IN1, and the input terminal IN0 are respectively coupled to the input signal B, the input signal A, and the input signal at the logic low level. The Boolean expression of the output signal of the multiplexer unit 200 will be A·B. Thus, the multiplexer unit 200 can act as an AND gate. In Figure 3B In the illustrated embodiment, the select terminal S, the input terminal IN1, and the input terminal IN0 are respectively coupled to the input signal B, the input signal A, and the input signal at the logic high level. The Boolean expression of the output signal will be A+B. Thus, the multiplexer unit 200 can act as an OR ("inclusive OR") gate. In Figure 3C In the illustrated embodiment, the select terminal S, the input terminal IN1, and the input terminal IN0 are respectively coupled to the input signal A, the input signal at the logic low level, and the input signal at the logic high level. The Boolean expression of the output signal of the multiplexer unit 200 will represent the inverted signal of the input signal A. Thus, the multiplexer 200 can act as a NOT gate or an inverter.

[0048] In Figure 3D In the illustrated embodiment, the select terminal S, the input terminal IN1, and the input terminal IN0 are respectively coupled to the input signal A, the inverted signal B# of the input signal B, and the input signal at the logic high level. The Boolean expression of the output signal of the multiplexer unit 200 will represent Figure 3A the inversion of the Boolean expression of the AND gate illustrated in Figure 3C . It should be noted that the NOT gate illustrated in Figure 3E can be used to generate the inverted signal B# of the input signal B. In Figure 3B In the illustrated embodiment, the select terminal S, the input terminal IN1, and the input terminal IN0 are respectively coupled to the input signal A, the input signal at the logic low level, and the inverted signal B# of the input signal B. The Boolean expression of the output signal of the multiplexer unit 200 will represent Figure 3B the inversion of the Boolean expression of the OR gate illustrated in

[0049] In Figure 3F In the illustrated embodiment, the select terminal S, the input terminal IN1, and the input terminal IN0 are respectively coupled to the input signal B, the inverted signal A# of the input signal A, and the input signal A. The multiplexer unit 200 can act as an XOR ("exclusive OR") gate. It should be noted that the NOT gate illustrated in Figure 3C can be used to generate the inverted signal A# of the input signal A. In Figure 3GIn the illustrated embodiment, the select terminal S, the input terminal IN1, and the input terminal IN0 are respectively coupled to the input signal B, the input signal A, and the inverted input signal A# of the input signal A. The multiplexer unit 200 can act as an XNOR ("exclusive NOR") gate.

[0050] By means of a camouflage design implemented using the true and false contacts described with reference to Figure 1 the semiconductor structure 100 shown in, Figure 2 the multiplexer unit 200 shown in can be implemented by a semiconductor device capable of hiding its logic function. Refer to Figure 4A for an example layout design of the semiconductor device 400 according to some embodiments of the present invention. The semiconductor device 400 can employ a camouflage design implemented using at least one of the contact elements 122.1 to 122.12, 132.1 to 132.3, and 142.1 and 142.2 shown in Figure 1 to thereby implement Figure 2 the multiplexer unit 200 shown in. In this embodiment, the semiconductor device 400 can include a plurality of transistor structures SPU0, SPD0, STA0, STA1, STB0, and STB1, an interconnect structure 403, and a conductive layer 420. The transistor structures SPU0, SPD0, STA0, STA1, STB0, and STB1 can be respectively used to implement Figure 2 the transistors PU0, PD0, TA0, TA1, TB0, and TB1 shown in. The interconnect structure 403 can be coupled to Figure 2 the input terminals IN0 and IN1, the select terminal S, and the output terminal OUTX shown in. The interconnect structure 403 can be arranged to interconnect the transistor structures SPU0, SPD0, STA0, STA1, STB0, and STB1 through the conductive layer 420 (which can be an embodiment of the conductive layer 120 shown in Figure 1 ).

[0051] Each of the transistor structures SPU0, SPD0, STA0, STA1, STB0, and STB1 can be formed on the semiconductor substrate 401 of the semiconductor device 400. The semiconductor substrate 401 can be used to implement Figure 1 an embodiment of the semiconductor substrate 101 shown in. It is worth noting that Figure 1 shows a cross-sectional view of the semiconductor structure 100, while Figure 4A shows a top view layout of the semiconductor device 400. Therefore, the semiconductor substrate 401 can be regarded as extending along the XY plane, and each contact element of the semiconductor device 400 can be regarded as extending in a direction substantially perpendicular to the XY plane (e.g., a direction parallel to the Z axis). Additionally, at least a part of the layout design of the transistor structures SPU0 / STA0 / STB0 can represent Figure 1An embodiment of the layout design of the transistor structures 102.3 / 102.4 shown in []. At least a portion of the layout design of the transistor structure SPD0 / STA1 / STB1 can represent Figure 1 An embodiment of the layout design of the transistor structures 102.1 / 102.2 shown in [].

[0052] The transistor structure SPU0 includes (but is not limited to) a polysilicon gate segment 410.G1, an active region 410.X1, and a plurality of contact elements 422.11 to 422.16. The polysilicon gate segment 410.G1 (which is used to implement Figure 2 the gate of the transistor PU0 shown in []) can be Figure 1 an embodiment of the polysilicon gate segments PG3 / PG4 shown in []. In this embodiment, the polysilicon gate segment 410.G1 is formed on the semiconductor substrate 401 and extends across the active region 410.X1 in a direction parallel to the Y-axis.

[0053] The active region 410.X1 (where the channel of the transistor structure SPU0 can be formed) can include a plurality of diffusion regions 410.S1 and 410.D1 located on opposite sides of the polysilicon gate segment 410.G1. The diffusion regions 410.S1 and 410.D1 can be Figure 1 an embodiment of the source / drain regions SD31 and SD32 shown in [] or Figure 1 an embodiment of the source / drain regions SD41 and SD42 shown in []. In this embodiment, the diffusion regions 410.S1 and 410.D1 doped with p-type dopants can be used to implement Figure 2 the source and drain of the transistor PU0 shown in [].

[0054] Multiple conductive lines 420.11 to 420.14 (each of which is a conductive part of the conductive layer 420) can be formed above the polysilicon gate segment 410.G1 and the active region 410.X1. In this embodiment, the conductive line 420.11 is arranged to cross a part 412.11 of the polysilicon gate segment 410.G1. The conductive line 420.12 separated from the conductive line 420.11 is arranged to cross a part 412.12 of the polysilicon gate segment 410.G1. The parts 412.11 and 412.12 can be arranged in a direction different from the direction in which the polysilicon gate segment 410.G1 extends across the active region 410.X1. For example, the polysilicon gate segment 410.G1 can include a part 412.10 extending in a direction parallel to the Y-axis. The parts 412.11 and 412.12 can be arranged in a direction parallel to the X-axis. In this embodiment, the conductive lines 420.11 and 420.12 can further extend above a part 412.14 of the diffusion region 410.S1 and a part 412.15 of the diffusion region 410.D1, respectively. In some embodiments, each of the conductive lines 420.11 and 420.12 can extend in a direction parallel to the Y-axis.

[0055] The conductive line 420.13 is arranged to cross a part 412.13 of the diffusion region 410.S1. The conductive line 420.14 is arranged to cross a part 412.16 of the diffusion region 410.D1. Each of the conductive lines 420.13 and 420.14 can extend in a direction parallel to the Y-axis. In this embodiment, the conductive lines 420.13 and 420.14 can be electrically connected to each other through the conductive part 420.1 of the conductive layer 420. The conductive part 420.1 is coupled to Figure 2 the supply voltage VDD shown in.

[0056] Each of the contact elements 422.11 to 422.16 can be Figure 1 an embodiment of one of the contact elements 122.1 to 122.12 shown in. In this embodiment, the contact elements 422.11 and 422.12 are formed on the polysilicon gate segment 410.G1 and are spaced apart from each other. The contact elements 422.11 and 422.12 can be arranged on the polysilicon gate segment 410.G1 in a direction parallel to the X-axis (which is perpendicular to the direction in which the polysilicon gate segment 410.G1 extends across the active region 410.X1). It is worth noting that when viewed from the top of the conductive layer 420, the contact elements 422.11 and 422.12 seem to be two gate contacts placed on the polysilicon gate segment 410.G1. However, one of the contact elements 422.11 and 422.12 can be implemented as a dummy gate contact or a disguised gate contact arranged to electrically isolate the polysilicon gate segment 410.G1 from the conductive layer 420.

[0057] Figure 4B A cross-sectional view taken along line L1-L1 in accordance with some embodiments of the present invention is described. Referring to Figure 4A and also referring to Figure 4B and also referring to Figure 4A , the contact elements 422.11 and 422.12 may be implemented as a true gate contact and a dummy gate contact respectively placed on the polysilicon gate segment 410.G1. The contact element 422.11 (formed in the dielectric layer 404 between the polysilicon gate segment 410.G1 and the conductive line 420.11) is arranged to electrically connect the polysilicon gate segment 410.G1 to the conductive line 420.11. The contact element 422.11 may be implemented as a conductive via or other type of conductive structure. A conductive material such as Cu, Al, Ti, Ta, W, Nb, Mo, TiN, TiC, TaN, Ti / W, Ti / TiN, any other known conductive or semiconductive material, or a combination thereof may be used to form the contact element 422.11. The contact element 422.12 formed in the dielectric layer 404 is arranged to electrically isolate the polysilicon gate segment 410.G1 from the conductive line 420.12. The contact element 422.12 may include a conductive segment 422.12a and a non-conductive segment 422.12b stacked on top of each other. The conductive segment 422.12a may be implemented as a conductive via or other type of conductive structure formed on the non-conductive segment 422.12b. The non-conductive segment 422.12b may be implemented as an insulating film or other type of insulating structure. An insulating material such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, other types of insulating materials, or a combination thereof may be used to form the non-conductive segment 422.12b. Since the non-conductive segment 422.12b may have a height / thickness much smaller than that of the conductive segment 422.12a, when viewed from the top of the conductive layer 420, the contact element 422.12 appears to be a true gate contact similar or identical to the contact element 422.11.

[0058] Returning to the reference Figure 4A, when viewed from the top of the conductive layer 420, the contact elements 422.13 and 422.14 (which are formed on different parts of the diffusion region 410.S1 and are spaced apart from each other) appear to be two source contacts placed on the diffusion region 410.S1. However, one of the contact elements 422.13 and 422.14 (i.e., the contact element 422.14 in this embodiment) is arranged to electrically isolate the diffusion region 410.S1 from the dummy source contact of the conductive layer 420. Similarly, when viewed from the top of the conductive layer 420, the contact elements 422.15 and 422.16 (which are formed on the diffusion region 410.D1 and are spaced apart from each other) appear to be two drain contacts placed on the diffusion region 410.D1. One of the contact elements 422.15 and 422.16 (i.e., the contact element 422.16 in this embodiment) is arranged to electrically isolate the diffusion region 410.D1 from the dummy drain contact of the conductive layer 420.

[0059] Figure 4C Showing a cross-sectional view taken along Figure 4A the line L2-L2 in accordance with some embodiments of the present invention. Referring to Figure 4C and also referring to Figure 4A , the contact element 422.13 may be formed in the dielectric layer 404 between the diffusion region 410.S1 and the conductive line 420.13. The contact element 422.13 is arranged to electrically connect the diffusion region 410.S1 to the conductive line 420.13 so as to thereby act as a true source contact placed on the diffusion region 410.S1. The contact element 422.14 formed in the dielectric layer 404 is arranged to electrically isolate the diffusion region 410.S1 from the conductive line 420.11 so as to thereby act as a dummy source contact placed on the diffusion region 410.S1. In this embodiment, the contact element 422.11, the contact element 422.13, and the contact element 422.14 may be arranged in a direction parallel to the Y-axis. The contact elements 422.11 and 422.14 are in contact with different parts of the conductive line 420.11.

[0060] The contact element 422.13 may be implemented as a conductive via or other type of conductive structure. The contact element 422.14 may include a conductive segment 422.14a and a non-conductive segment 422.14b stacked on top of each other. The conductive segment 422.14a may be implemented as a conductive via or other type of conductive structure formed on the non-conductive segment 422.14b. The non-conductive segment 422.14b may be implemented as an insulating film or other type of insulating structure. Since the non-conductive segment 422.14b may have a height / thickness much smaller than that of the conductive segment 422.14a, when viewed from the top of the conductive layer 420, the contact element 422.14 appears to be a true source contact similar to or the same as the contact element 422.13.

[0061] In some embodiments, the cross-sectional views of contact elements 422.15 and 422.16 may be similar to or the same as Figure 4C the cross-sectional view shown therein. For example, contact element 422.15 may be implemented as a conductive via or other type of conductive structure. Contact element 422.16 may include conductive and non-conductive segments stacked on top of each other. As another example, contact elements 422.12, 422.15, and 422.16 may be arranged in a direction parallel to the Y-axis. Contact elements 422.12 and 422.15 contact different portions of conductive line 420.12. Those skilled in the art will appreciate that the cross-sectional structures of contact elements 422.15 and 422.16 may be similar to or the same as Figure 4C the cross-sectional structures shown therein, and for the sake of brevity, similar descriptions are not repeated herein.

[0062] Figure 4D Illustrate a cross-sectional view taken along line L3-L3 in accordance with some embodiments of the present invention. Referring to Figure 4A and also referring to Figure 4D and further referring to Figure 4A , contact elements 422.14 and 422.15 formed in dielectric layer 404 may be located at opposite sides of polysilicon gate segment 410.G1. Gate dielectric 410.GD may be formed between polysilicon gate segment 410.G1 and active region 410.X1. Contact element 422.14 acting as a dummy source contact may be formed under and in contact with conductive line 420.11. Contact element 422.15 acting as a true drain contact may be formed under and in contact with conductive line 420.12.

[0063] In some embodiments, transistor structure SPD0 may be similar to or the same as transistor structure SPU0. Referring again to Figure 4A , the corresponding layouts of transistor structures SPU0 and SPD0 may be symmetric with respect to interconnect structure 403. Transistor structure SPD0 may include polysilicon gate segment 410.G2, active region 410.X2, and a plurality of contact elements 422.21 to 422.26. Polysilicon gate segment 410.G2 (which is similar to or the same as polysilicon gate segment 410.G1) may be used to implement Figure 2 the gate of transistor PD0 shown therein. Active region 410.X2 may be similar to or the same as active region 410.X1, except that its diffusion regions 410.S2 and 410.D2 may be doped with an n-type dopant. Diffusion regions 410.S2 and 410.D2 may be used to implement Figure 2 the source and drain of transistor PD0 shown therein.

[0064] Multiple conductive lines 420.21 to 420.24 (each of which is a conductive part of the conductive layer 420) may be formed over the polysilicon gate segment 410.G2 and the active region 410.X2. The layout of the conductive lines 420.21 to 420.24 and the layout of the conductive lines 420.11 to 420.14 may be symmetric with respect to the interconnect structure 403. Additionally, the conductive lines 420.23 and 420.24 may be electrically connected to each other through the conductive part 420.2 of the conductive layer 420. The conductive part 420.2 is coupled to Figure 2 the supply voltage VSS shown in

[0065] Each of the contact elements 422.21 to 422.26 may be Figure 1 an embodiment of one of the contact elements 122.1 to 122.12 shown in

[0066] the layout of the contact elements 422.21 to 422.26 and the layout of the contact elements 422.11 to 422.16 may be symmetric with respect to the interconnect structure 403. Thus, the contact elements 422.21 and 422.22 may be the true gate contact and the false gate contact placed on the polysilicon gate segment 410.G2, respectively. The contact elements 422.23 and 422.24 may be the true source contact and the false source contact placed on the diffusion region 410.S2, respectively. The contact elements 422.25 and 422.26 may be the true drain contact and the false drain contact placed on the diffusion region 410.D2, respectively.

[0066] Additionally, in addition to the conductive line layout, the true contact layout, and the false contact layout, the transistor structure STA0 may be similar or identical to the transistor structure SPU0. In this embodiment, the transistor structure STA0 may include a polysilicon gate segment 410.G3, an active region 410.X3, and multiple contact elements 422.31 to 422.36. The polysilicon gate segment 410.G3 (which is similar or identical to the polysilicon gate segment 410.G1) may be used to implement Figure 2 the gate of the transistor TA0 shown in Figure 2 the source and drain of the transistor TA0 shown in

[0067] Multiple conductive lines 420.31 to 420.35 (each of which is a conductive part of the conductive layer 420) may be formed above the polysilicon gate segment 410.G3 and the active region 410.X3. The layout of the conductive lines 420.31 to 420.35 is similar or identical to the layout of the conductive lines 420.11 to 420.14, except that the conductive line 420.31 extending above a part of the polysilicon gate segment 410.G3 is separated from the conductive line 420.33 extending above the diffusion region 410.S3. In this embodiment, the conductive line 420.33 may extend in a direction perpendicular to the Y-axis.

[0068] Each of the contact elements 422.31 to 422.36 may be Figure 1 an embodiment of one of the contact elements 122.1 to 122.12 shown in. The layout of the contact elements 422.31 to 422.36 may be similar or identical to the layout of the contact elements 422.11 to 422.16, except for the true / false contact arrangement. In this embodiment, the contact elements 422.31 and 422.32 may be a true gate contact and a false gate contact placed on the polysilicon gate segment 410.G3, respectively. The contact elements 422.33 and 422.34 may be a false source contact and a true source contact placed on the diffusion region 410.S3, respectively. The contact elements 422.35 and 422.36 may be a true drain contact and a false drain contact placed on the diffusion region 410.D3, respectively.

[0069] The respective layouts of the transistor structures STA0 and STA1 may be symmetric with respect to the interconnect structure 403. In this embodiment, the transistor structure STA1 may include a polysilicon gate segment 410.G4, an active region 410.X4, and multiple contact elements 422.41 to 422.46. The polysilicon gate segment 410.G4 (which is similar or identical to the polysilicon gate segment 410.G2) may be used to implement Figure 2 the gate of the transistor TA1 shown in. The active region 410.X4 may be similar or identical to the active region 410.X2. The diffusion regions 410.S4 and 410.D4 may be used to implement Figure 2 the source and drain of the transistor TA1 shown in, respectively.

[0070] Multiple conductive lines 420.41 to 420.45 (each of which is a conductive part of the conductive layer 420) may be formed above the polysilicon gate segment 410.G4 and the active region 410.X4. The layout of the conductive lines 420.41 to 420.45 and the layout of the conductive lines 420.31 to 420.35 may be symmetric with respect to the interconnect structure 403. Each of the contact elements 422.41 to 422.46 may be Figure 1An embodiment of one of the contact elements 122.1 to 122.12 shown. The layout of the contact elements 422.41 to 422.46 and the layout of the contact elements 422.31 to 422.36 may be symmetric with respect to the interconnect structure 403. Thus, the contact elements 422.41 and 422.42 may be a true gate contact and a dummy gate contact placed on the polysilicon gate segment 410.G4, respectively. The contact elements 422.43 and 422.44 may be a dummy source contact and a true source contact placed on the diffusion region 410.S4, respectively. The contact elements 422.45 and 422.46 may be a true drain contact and a dummy drain contact placed on the diffusion region 410.D4, respectively.

[0071] Except for the conductive line layout, the true contact layout, and the dummy contact layout, the transistor structure STB0 may be similar or identical to the transistor structure STA0. In this embodiment, the transistor structure STB0 may include a polysilicon gate segment 410.G5, an active region 410.X5, and a plurality of contact elements 422.51 to 422.56. The polysilicon gate segment 410.G5 (which is similar or identical to the polysilicon gate segment 410.G3) may be used to implement Figure 2 the gate of the transistor TA1 shown in Figure 2 The diffusion regions 410.S5 and 410.D5 of the active region 410.X5 may be used to implement

[0072] the source and drain of the transistor TA1 shown in

[0073] Each of the contact elements 422.51 to 422.56 may be Figure 1An embodiment of one of the contact elements 122.1 to 122.12 shown. In addition to the true / false contact arrangement, the layout of the contact elements 422.51 to 422.56 can be similar or the same as the layout of the contact elements 422.31 to 422.36. In this embodiment, the contact elements 422.51 and 422.52 can be a false gate contact and a true gate contact placed on the polysilicon gate segment 410.G5, respectively. The contact elements 422.53 and 422.54 can be a false source contact and a true source contact placed on the diffusion region 410.S5, respectively. The contact elements 422.55 and 422.56 can be a true drain contact and a false drain contact placed on the diffusion region 410.D5, respectively.

[0074] The corresponding layouts of the transistor structures STB0 and STB1 can be symmetric with respect to the interconnect structure 403. In this embodiment, the transistor structure STB1 can include a polysilicon gate segment 410.G6, an active region 410.X6, and a plurality of contact elements 422.61 to 422.66. The polysilicon gate segment 410.G6 (which is similar or the same as the polysilicon gate segment 410.G4) can be used to implement Figure 2 the gate of the transistor TB1 shown. The active region 410.X6 can be similar or the same as the active region 410.X4. The diffusion regions 410.S6 and 410.D6 can be used to implement Figure 2 the source and drain of the transistor TB1 shown, respectively.

[0075] A plurality of conductive lines 420.61 to 420.66 (each of which is a conductive part of the conductive layer 420) can be formed above the polysilicon gate segment 410.G6 and the active region 410.X6. The layout of the conductive lines 420.61 to 420.66 and the layout of the conductive lines 420.51 to 420.56 can be symmetric with respect to the interconnect structure 403. Each of the contact elements 422.61 to 422.66 can be Figure 1 an embodiment of one of the contact elements 122.1 to 122.12 shown. The layout of the contact elements 422.61 to 422.66 and the layout of the contact elements 422.51 to 422.56 can be symmetric with respect to the interconnect structure 403. Thus, the contact elements 422.61 and 422.62 can be a true gate contact and a false gate contact placed on the polysilicon gate segment 410.G6, respectively. The contact elements 422.63 and 422.64 can be a false source contact and a true source contact placed on the diffusion region 410.S6, respectively. The contact elements 422.65 and 422.66 can be a true drain contact and a false drain contact placed on the diffusion region 410.D6, respectively.

[0076] The interconnect structure 403 can be positioned between each pair of transistors. For example, transistors SPU0, STA0, and STB0 are positioned at one side of the interconnect structure 403, while transistors SPD0, STA1, and STB1 are positioned at the opposite side of the interconnect structure 403. In this embodiment, the interconnect structure 403 can be arranged to electrically connect each gate structure of the transistor structures SPU0 and SPD0 to the selection terminal S. In addition, the interconnect structure 403 can be arranged to electrically connect each source / drain structure of the transistor structures STA0 and STA1 (e.g., Figure 2 each source of the transistors TA0 and TA1 shown in Figure 2 ) to the input terminal IN1. The interconnect structure 403 can be further arranged to electrically connect each source / drain structure of the transistor structures STB0 and STB1 (e.g.,

[0077] each source of the transistors TB0 and TB1 shown in

[0078] ) to the input terminal IN0.

[0077] The interconnect structure 403 can include a plurality of conductive lines 430.1 to 430.10, a plurality of contact elements 432.1 to 432.18, a plurality of conductive lines 440.1 to 440.3, and a plurality of contact elements 442.1 to 442.27. In some embodiments, each of the conductive lines 430.1 to 430.10 can extend in a first direction parallel to the Y-axis. Each of the conductive lines 440.1 to 440.3 can extend in a second direction different from the first direction. For example, the second direction can be parallel to the X-axis.

[0078] The conductive lines 430.1 to 430.10 can be formed in the same conductive layer and separated from each other. Each of the conductive lines 430.1 to 430.10 can be electrically connected to at least one conductive line in the conductive layer 420. In this embodiment, the conductive lines 430.1 to 430.10 can be formed at a level higher than the conductive layer 420. Each of the contact elements 432.1 to 432.18 (which are placed on the conductive lines in the conductive layer 420) can be formed of a conductive material to electrically connect the conductive lines in the conductive layer 420 to one of the conductive lines 430.1 to 430.10.

[0079] For example, the conductive line 430.1 can be electrically connected to the conductive lines 420.11 and 420.21 through the contact elements 432.1 and 432.2, respectively. The conductive line 430.2 can be electrically connected to the conductive lines 420.12 and 420.22 through the contact elements 432.3 and 432.4, respectively. The conductive line 430.3 can be electrically connected to the conductive lines 420.33 and 420.43 through the contact elements 432.5 and 432.6, respectively. It should be noted that in some embodiments where the conductive lines 430.1 to 430.10 can be implemented as part of the conductive layer 420, the contact elements 432.1 to 432.18 can be omitted.

[0080] The conductive lines 440.1 to 440.3 may be formed at a level different from each of the conductive lines 430.1 to 430.10. Each of the contact elements 442.1 to 442.27 may be formed between one of the conductive lines 430.1 to 430.10 and one of the conductive lines 440.1 to 440.3. In the present embodiment, each of the conductive lines 440.1 to 440.3 is formed at a level higher than each of the conductive lines 430.1 to 430.10. For example (but not limited to), each of the conductive lines 440.1 to 440.3 is formed in a conductive layer such as a third metal layer (M2), and each of the conductive lines 430.1 to 430.10 may be formed in a conductive layer such as a second metal layer (M1). Each of the contact elements 442.1 to 442.27 may be formed on one of the conductive lines 430.1 to 430.10 and in contact with one of the conductive lines 440.1 to 440.3.

[0081] Each of the contact elements 442.1 to 442.27 may be implemented as a true contact or a false contact according to the circuit topology corresponding to the semiconductor device 400. In the present embodiment, the conductive lines 440.1 to 440.3 may be respectively coupled to Figure 2 the select terminal S, the output terminal OUTX, and the connection terminal SB shown in. First, regarding the connection between the transistor structures SPU0 and SPD0, the contact elements 442.1 to 442.3 are respectively formed on different portions of the conductive line 430.1 where the conductive lines 440.1 to 440.3 cross. The contact elements 442.4 to 442.6 are respectively formed on different portions of the conductive line 430.2 where the conductive lines 440.1 to 440.3 cross. To implement an inverter including Figure 2 the transistors PU0 and PD0 shown in, each of the contact elements 442.1 and 442.6 may be formed of a conductive material to act as a true contact. Thus, each of the polysilicon gate segments 410.G1 and 410.G2 may be electrically connected to the conductive line 440.1. Each of the diffusion regions 410.D1 and 410.D2 may be electrically connected to the conductive line 440.3. Additionally, each of the contact elements 442.2 to 442.5 may be formed to include a conductive segment and a non-conductive segment stacked on top of each other to thereby act as a false contact.

[0082] Regarding the connection between transistor structures STA0 and STA1, each of contact elements 442.10, 442.12, and 442.14 can be formed of a conductive material to serve as a true contact. Each of contact elements 442.7 to 442.9, 442.11, 442.13, and 442.15 can be formed to include conductive and non-conductive segments stacked on top of each other to thereby serve as a false contact. Thus, transistor structures STA0 and STA1 can implement transmission gates including Figure 2 the transistors TA0 and TA1 shown in Figure 2 Each drain of the transistors TA0 and TA1 shown in. The interconnect structure 403 can be arranged to electrically connect each source / drain structure of structures STA0 and STA1 (e.g., Figure 2 each drain of the transistors TA0 and TA1 shown in) to the output terminal OUTX. In this embodiment, the conductive wire 430.3 electrically connected to the diffusion regions 410.S3 and 410.S4 can be coupled to

[0083] Regarding the connection between transistor structures STB0 and STB1, each of contact elements 442.19, 442.24, and 442.26 can be formed of a conductive material to serve as a true contact. Each of contact elements 442.16 to 442.18, 442.20 to 442.23, 442.25, and 442.27 can be formed to include conductive and non-conductive segments stacked on top of each other to thereby serve as a false contact. Thus, transistor structures STB0 and STB1 can implement transmission gates including Figure 2 the transistors TB0 and TB1 shown in Figure 2 each drain of the transistors TB0 and TB1 shown in. The interconnect structure 403 can be arranged to electrically connect each source / drain structure of structures STB0 and STB1 (e.g., Figure 2 each drain of the transistors TB0 and TB1 shown in) to the output terminal OUTX. In this embodiment, the conductive wire 430.7 electrically connected to the diffusion regions 410.S5 and 410.S5 can be coupled to

[0084] Figures 4A to 4D The structures shown in are for illustrative purposes only and are not intended to limit the scope of the present invention. In some embodiments, at least one of the polysilicon gate segments 410.G1 to 410.G6 can be replaced by other types of conductive segments. In some embodiments, more than two contact elements can be formed on the same polysilicon gate segment or the same source / drain region. In some embodiments, the number of conductive wires crossing the conductive wires 430.1 to 430.10 can be greater than or less than 3. In some embodiments, the layout design of transistor structures STA0 and STA1 can be the same as the layout design of transistor structures STB0 and STB1.

[0085] In some embodiments, the above-described camouflaged semiconductor structure can be used to implement a multiplexer having other possible circuit topologies. Figure 5 is a circuit diagram of an example multiplexer unit according to some embodiments of the present invention. The multiplexer unit 500 is configured to select one of the input signals at the input terminal IN0 and the input signal at the input terminal IN1 as the output signal at the output terminal OUT according to the input signal at the selection terminal S.

[0086] In addition to the plurality of transistors PU1 and PD1, the circuit topology of the multiplexer unit 500 can be the same as Figure 2 the circuit topology of the multiplexer unit 200 shown in. In this embodiment, p-channel transistors and n-channel transistors can be used to implement the transistors PU1 and PD1, respectively. The respective gates of the transistors PU1 and PD1 are coupled to the connection terminal OT. The respective sources of the transistors PU1 and PD1 are coupled to the supply voltages VDD and VSS, respectively. The respective drains of the transistors PU1 and PD1 are coupled to the output terminal OUT. It is noted that the multiplexer unit 500 can be equivalent to an inverter followed by Figure 2 the multiplexer unit 200 shown in.

[0087] Similarly, the multiplexer unit 500 can act as a universal gate capable of implementing various standard logic gates in different operating schemes. Figures 6A to 6G Illustrates different logic gates implemented using the Figure 5 multiplexer unit 500 shown in according to some embodiments of the present invention. Since those skilled in the art can understand the logic functions in the operating schemes for Figures 3A to 3G after reading the above paragraphs for Figures 6A to 6G the descriptions of the operating schemes shown in are not repeated here for the sake of brevity.

[0088] Referring to Figure 7 , an example layout design of a semiconductor device 700 according to some embodiments of the present invention is illustrated. The semiconductor device 700 can be used to implement Figure 5 the multiplexer unit 500 shown in. In addition to the plurality of transistor structures SPU1 and SPD1 and the interconnect structure 703, the semiconductor device 700 can be similar or the same as Figure 4A the semiconductor device 400 shown in. The transistor structures SPU1 and SPD1 can be used to implement Figure 5 the transistors PU1 and PD1 shown in, respectively.

[0089] Except for the contact layout, the transistor structure SPU1 may be similar or identical to the transistor structure SPU0. For example, the corresponding true / false contact arrangements of the transistor structures SPU0 and SPU1 may be symmetric with respect to the conductive line 430.7. In this embodiment, the transistor structure SPU1 may include a polysilicon gate segment 410.G7, an active region 410.X7, and a plurality of contact elements 422.71 to 422.76. The polysilicon gate segment 410.G7 may be used to implement Figure 5 the gate of the transistor PU1 shown in Figure 5 . The diffusion regions 410.S7 and 410.D7 of the active region 410.X7 may be used to implement

[0090] respectively the source and drain of the transistor PU1 shown in Figure 1 . A plurality of conductive lines 420.71 to 420.74 (each of which is a conductive part of the conductive layer 420 shown in FIG. 4) may be formed above the polysilicon gate segment 410.G7 and the active region 410.X7. The layout of the conductive lines 420.71 to 420.74 may be similar or identical to the layout of the conductive lines 420.11 to 420.14. Each of the contact elements 422.71 to 422.76 may be an embodiment of one of the contact elements 122.1 to 122.12 shown in Figure 1 . In this embodiment, the contact elements 422.71 and 422.72 may be a false gate contact and a true gate contact placed on the polysilicon gate segment 410.G7 respectively. The contact elements 422.73 and 422.74 may be a false source contact and a true source contact placed on the diffusion region 410.S7 respectively. The contact elements 422.75 and 422.76 may be a false drain contact and a true drain contact placed on the diffusion region 410.D7 respectively.

[0091] The corresponding layouts of the transistor structures SPU1 and SPD1 may be symmetric with respect to the interconnect structure 703. In this embodiment, the transistor structure SPD1 may include a polysilicon gate segment 410.G8, an active region 410.X8, and a plurality of contact elements 422.81 to 422.86. The polysilicon gate segment 410.G8 may be used to implement Figure 5 the gate of the transistor PD1 shown in Figure 5 . The active region 410.X8 may be similar or identical to the active region 410.X7. The diffusion regions 410.S8 and 410.D8 may be used to implement

[0092] Multiple conductive lines 420.81 to 420.84 (each of which is a conductive part of the conductive layer 420 shown in FIG. 4) can be formed above the polysilicon gate segment 410.G8 and the active region 410.X8. The layout of the conductive lines 420.81 to 420.84 and the layout of the conductive lines 420.71 to 420.74 can be symmetric with respect to the interconnect structure 703. Each of the contact elements 422.81 to 422.86 can be Figure 1 an embodiment of one of the contact elements 122.1 to 122.12 shown in. The layout of the contact elements 422.81 to 422.86 and the layout of the contact elements 422.71 to 422.76 can be symmetric with respect to the interconnect structure 703. Thus, the contact elements 422.81 and 422.82 can be a dummy gate contact and a true gate contact placed on the polysilicon gate segment 410.G8, respectively. The contact elements 422.83 and 422.84 can be a dummy source contact and a true source contact placed on the diffusion region 410.S8, respectively. The contact elements 422.85 and 422.86 can be a dummy drain contact and a true drain contact placed on the diffusion region 410.D8, respectively.

[0093] In addition to the interconnect structure 703 may further include multiple conductive lines 430.11 and 430.12, multiple contact elements 432.19 to 432.22 and multiple contact elements 442.28 to 442.33, the interconnect structure 703 can be similar or identical to Figure 4A the interconnect structure 403 shown in. Each of the conductive lines 430.11 and 430.12 (which are located at the same level as the conductive lines 430.1 to 430.10) can extend in a direction parallel to the Y-axis. Each of the contact elements 432.19 to 432.22 (which are placed on the conductive lines in the conductive layer 420) can be formed using a conductive material to electrically connect the conductive lines in the conductive layer 420 to one of the conductive lines 430.11 and 430.12.

[0094] In addition, the contact element 442.32 can be formed using a conductive material to act as a true contact. Each of the contact elements 442.28 to 442.31 and 442.33 can be formed to include conductive segments and non-conductive segments stacked on top of each other to thereby act as dummy contacts. Thus, each of the diffusion regions 410.D7 and 410.D8 can be electrically connected to the conductive line 440.3, and the conductive line 440.3 is coupled to Figure 5 the connection terminal OT shown in. In this embodiment, each of the diffusion regions 410.S7 and 410.S8 can be coupled to Figure 5 the output terminal OUT shown in. Thus, the transistor structures SPU1 and SPD1 can be implemented to include Figure 5The inverters of transistors PU1 and PD1 shown in. The interconnect structure 703 can be arranged to electrically connect each source / drain structure of structures SPU1 and SPD1 (e.g., Figure 5 each drain of transistors PU1 and PD1 shown in) to the output terminal OUT. Since those skilled in the art can understand after reading the above paragraphs for Figures 4A to 4D the semiconductor structure shown in, for the sake of brevity, similar descriptions are not repeated here. Figure 7 the semiconductor structure shown in.

[0095] Figure 8 Illustrate an example semiconductor device according to some embodiments of the present invention. The semiconductor device 800 can utilize the semiconductor structure described with reference to Figures 1 to 7 to hide its function. In this embodiment, the semiconductor device 800 can include K circuit units 804.1 to 804.K, K circuit units 806.1 to 806.K, and an interconnect structure 803, where K is a positive integer. At least one of the circuit units 804.1 to 804.K and 806.1 to 806.K can be implemented using a general-purpose gate with a camouflage design. For example, the semiconductor device 400 shown in Figure 4A or the semiconductor device 700 shown in Figure 7 can be used to implement each of the circuit units 804.1 to 804.K and 806.1 to 806.K.

[0096] The interconnect structure 803 can include N conductive lines 850.1 to 850.N, M conductive lines 860.1 to 860.M, and a plurality of contact elements CE. Each of N and M is a positive integer. The conductive lines 850.1 to 850.N located in the same conductive layer are connected to the circuit units 804.1 to 804.K and 806.1 to 806.K. Each circuit unit can be implemented as a logic circuit or a general-purpose logic gate. For example (but not limited to), in some embodiments where the semiconductor device 400 shown in Figure 4A is used to implement the circuit unit 804.1, Figure 4A the conductive lines 440.1 to 440.3 shown in can be electrically connected to the conductive lines 850.1 to 850.3 connected to the circuit unit 804.1. It should be noted that the number of conductive lines connected to each circuit unit can be determined according to the circuit design of the circuit unit.

[0097] The conductive lines 860.1 to 860.M can be formed at a level different from each of the conductive lines 850.1 to 850.N. Each of the contact elements CE (formed between one of the conductive lines 850.1 to 850.N and one of the conductive lines 860.1 to 860.M) can be Figure 11 to 122.12 shown in FIG. 1 . In the present embodiment, each of the conductive lines 860.1 to 860.M is formed at a level higher than each of the conductive lines 850.1 to 850.N. Each of the contact elements CE may be formed on one of the conductive lines 850.1 to 850.N and contact one of the conductive lines 860.1 to 860.M. It is noteworthy that each of the contact elements CE may be implemented as a true contact or a false contact according to the circuit topology corresponding to the semiconductor device 800. Therefore, it will be difficult for an attacker to identify the actual design and function of the semiconductor device 800.

[0098] Figure 9 is a flow chart of a method for forming a semiconductor device according to some embodiments of the present invention. Figure 4A The method 900 is described with reference to the semiconductor device 400 shown in FIG. Figures 10A to 10F To describe method 900, Figures 10A to 10F The corresponding structures in different manufacturing stages according to some embodiments of the present invention are illustrated along the Figure 4A 9. A cross section is taken along line L1-L1 in FIG. 9. Those skilled in the art will recognize that method 900 may be employed in other types of semiconductor devices to provide true and false contacts without departing from the scope of the present invention. Additionally, in some embodiments, other operations in method 900 may be performed. In some other embodiments, the operations of method 900 may be performed in a different order and / or may be varied.

[0099] In operation 902, polysilicon segments are formed on an active region of a semiconductor substrate. The active region may be a region where a channel of a transistor structure is formed. For example Figure 4A and Figure 10A As described in FIG. 4 , a polysilicon gate segment 410 .G1 is formed on an active region 410 .X1 of a semiconductor substrate 401 . Figure 10A Description Figure 4A The cross-sectional view is taken along line L1-L1 in FIG. 4 , so the active area 410.X1 is not shown.

[0100] In operation 904, a dielectric layer is formed on the polysilicon segment. Figure 10B As illustrated in FIG. 4 , a dielectric layer 404 is formed on the polysilicon gate segment 410.G1. The dielectric layer 404 may be an intermetallic dielectric layer that may include a dielectric material such as silicon oxide, silicon carbon oxide, silicon nitride, silicon carbon nitride, aluminum oxide, other types of dielectric materials, or combinations thereof.

[0101] In operation 906, a first recess is formed in the dielectric layer to expose a first portion of the polysilicon segment. Figure 10CAs described, the dielectric layer 404 is patterned and etched to create a recess 1006 to expose a portion of the polysilicon gate segment 410.G1. The patterning process may include forming a photoresist on the dielectric layer 404 and using a mask to expose portions of the photoresist and exposing a portion of the dielectric layer 404 by removing the exposed or unexposed portions of the photoresist. Subsequently, an etching process is performed to remove the exposed portion of the dielectric layer 404.

[0102] In operation 908, an insulating material is used to partially fill the first recess. For example Figure 10D As described, the non-conductive segment 422.12b is used to partially fill the recess 1006. The non-conductive segment 422.12b may include an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, metal oxide, metal nitride, other types of insulating materials, or combinations thereof. Deposition processes such as (but not limited to) thermal oxidation deposition or chemical vapor deposition (CVD) may be used to form the non-conductive segment 422.12b.

[0103] In operation 910, a second recess is formed in the dielectric layer to expose a second portion of the polysilicon segment. For example Figure 10E As described, a recess 1008 is formed in the dielectric layer 404 to expose another portion of the polysilicon gate segment 410.G1. The dielectric layer 404 may be patterned and etched to create the recess 1008 to expose another portion of the polysilicon gate segment 410.G1. The patterning process may include forming a photoresist on the dielectric layer 404 and using a mask to expose portions of the photoresist and exposing another portion of the dielectric layer 404 by removing the exposed or unexposed portions of the photoresist. Subsequently, an etching process is performed to remove the other portion of the dielectric layer 404.

[0104] In operation 912, a conductive material is used to fill the first recess and the second recess to form a first gate contact and a second gate contact of the transistor structure of the semiconductor device, respectively. The first gate contact includes a conductive material and an insulating material stacked on top of each other. For example Figure 10F As described, a conductive material is used to fill the recess 1006 and the recess 1008 to form the contact element 422.12 and the contact element 422.11 of the transistor structure SPU0, respectively. The contact element 422.12 includes a conductive segment 422.12a and a non-conductive segment 422.12b stacked on top of each other.

[0105] In some embodiments, after using a conductive material to fill the first recess and the second recess, a conductive layer may be formed on the dielectric layer. Additionally, the conductive layer may be patterned into a plurality of separate conductive portions. The first conductive portion of the conductive layer contacts the first gate contact, and the second conductive portion of the conductive layer contacts the second gate contact. For example Figure 4A and Figure 4BAs described, the conductive layer 420 may be formed on the dielectric layer 404 and patterned into a plurality of conductive lines. The conductive line 420.11 contacts the contact element 422.11, and the conductive line 420.12 contacts the contact element 422.12.

[0106] In some embodiments, when forming a first groove for a first gate contact in the dielectric layer, a third groove may be formed in the dielectric layer to expose a first portion of the source / drain region of the transistor structure. When forming a second groove for a second gate contact in the dielectric layer, a fourth groove may be formed in the dielectric layer to expose a second portion of the source / drain region. Thus, when forming the first gate contact and the second gate contact, a first source / drain contact and a second source / drain contact may be formed on the source / drain region. For example, referring to Figure 4C and Figure 10C , a groove for the contact element 422.14 may be formed in the dielectric layer 404 during the manufacturing stage in which the groove 1006 for the contact element 422.12 is formed. Referring to Figure 4C and Figure 10D , an insulating material used to partially fill the groove 1006 may be used to partially fill the groove for the contact element 422.14 to thereby form the non-conductive segment 422.14b. Referring to Figure 4C and Figure 10E , after forming the non-conductive segments 422.14b and 422.12b, a groove for the contact element 422.13 may be formed in the dielectric layer 404 during the manufacturing stage in which the groove 1008 for the contact element 422.11 is formed. Referring to Figure 4C and Figure 10F , a conductive material used to fill the grooves 1006 and 1008 may be used to partially fill the groove for the contact element 422.13 and the groove for the contact element 422.14 to thereby form the contact elements 422.13 and 422.14 on the diffusion region 410.S1. Similarly, the contact elements 422.15 and 422.16 may be formed on the diffusion region 410.D1 according to the operations described with reference to Figures 10C to 10F .

[0107] Figure 11 is a flowchart of a method for forming a multiplexer unit according to some embodiments of the present invention. For illustration, the method 1100 is described with reference to the semiconductor device 400 shown in Figure 4A . Those skilled in the art will recognize that the method may be implemented in other types of multiplexer units (e.g., Figure 5Method 1100 is employed in the multiplexer unit 500 shown in []. Additionally, in some embodiments, other operations in method 1100 may be performed. In some other embodiments, the operations of method 1100 may be executed in a different order and / or may vary.

[0108] In operation 1102, multiple polysilicon segments of multiple transistors are formed on a semiconductor substrate. The transistors include multiple p-channel transistors located on the upper portion of the semiconductor substrate and multiple n-channel transistors located on the lower portion of the semiconductor substrate. Each polysilicon segment extends across the active region of the semiconductor substrate to define a first source / drain region and a second source / drain region. For example, corresponding polysilicon gate segments 410.G1, 410.G3, and 410.G5 of transistor structures SPU0, STA0, and STB0 may be formed on the upper portion of semiconductor substrate 401. Corresponding polysilicon gate segments 410.G2, 410.G4, and 410.G6 of transistor structures SPD0, STA1, and STB1 may be formed on the lower portion of semiconductor substrate 401.

[0109] In operation 1104, multiple contact elements are formed on the polysilicon segment, the first source / drain region, and the second source / drain region of each transistor. For example, contact elements 422.11 to 422.16 are formed on polysilicon gate segment 410.G1, diffusion region 410.S1, and diffusion region 410.D1. In some embodiments, operation 1104 may be performed based on Figure 9 operations 904 to 912 shown in [].

[0110] In operation 1106, a conductive layer is formed on the contact elements. The conductive layer includes a first conductive portion and a second conductive portion separated from each other. The polysilicon segment of each transistor is electrically isolated from the first conductive portion through the first contact element of the contact element and is electrically connected to the second conductive portion through the second contact element of the contact element. For example, a conductive layer 420 including conductive wires 420.11 and 420.12 is formed, where conductive wire 420.11 is electrically connected to polysilicon gate segment 410.G1 through contact element 422.11, and conductive wire 420.12 is electrically isolated from polysilicon gate segment 410.G1 through contact element 422.12.

[0111] In operation 1108, the first p-channel transistor and the first n-channel transistor of the transistor are interconnected through the conductive layer to form an inverter. For example, an interconnect structure 403 is formed to interconnect transistor structures SPU0 and SPD0 through conductive layer 420 to form an inverter.

[0112] In operation 1110, the second p-channel transistor and the second n-channel transistor of the transistor are interconnected through a conductive layer to form a first transmission gate. The corresponding polysilicon segments of the second p-channel transistor and the second n-channel transistor are electrically connected to the input and output of the inverter, respectively. For example, the interconnect structure 403 is arranged to interconnect the transistor structures STA0 and STA1 through the conductive layer 420 to form a transmission gate. The polysilicon gate segments 410.G3 and 410.G4 are electrically connected to the polysilicon gate segments 410.G1 / 410.G2 and the diffusion regions 410.D1 / 410.D2, respectively.

[0113] In operation 1112, the third p-channel transistor and the third n-channel transistor of the transistor are interconnected through a conductive layer to form a second transmission gate. The corresponding polysilicon segments of the third p-channel transistor and the third n-channel transistor are electrically connected to the output and input of the inverter, respectively. For example, the interconnect structure 403 is arranged to interconnect the transistor structures STB0 and STB1 through the conductive layer 420 to form a transmission gate. The polysilicon gate segments 410.G5 and 410.G6 are electrically connected to the diffusion regions 410.D1 / 410.D2 and the polysilicon gate segments 410.G1 / 410.G2, respectively.

[0114] By using dummy contacts and a universal gate design, the circuit units in semiconductor devices with different logic functions can be implemented as multiple camouflaged circuits with the same universal layout design to effectively protect the design intellectual property thereby.

[0115] Some embodiments described herein may include a multiplexer unit. The multiplexer unit includes a semiconductor substrate, a conductive layer, multiple pairs of transistors, and an interconnect structure. The conductive layer is formed over the semiconductor substrate. The transistor pairs are formed on the semiconductor substrate. Each pair of transistors includes a p-channel transistor and an n-channel transistor. The gate structure, the first source / drain structure, and the second source / drain structure of each of the p-channel transistor and the n-channel transistor are electrically connected to the conductive layer. The gate structure includes a conductive segment, a first contact element, and a second contact element. The conductive segment is formed on the semiconductor substrate and extends across the active region of the semiconductor substrate. The first source / drain structure and the second source / drain structure are formed on the active region and located at opposite sides of the conductive segment. A first conductive portion and a second conductive portion of the conductive layer cross a first portion and a second portion of the conductive segment, respectively. The first contact element and the second contact element are formed on the first portion and the second portion of the conductive segment, respectively. The first contact element is arranged to electrically connect the conductive segment to the first conductive portion. The second contact element is arranged to electrically isolate the conductive segment from the second conductive portion. The interconnect structure is located between each pair of transistors and is electrically connected to the conductive layer. The transistor pairs include a first pair of transistors, a second pair of transistors, and a third pair of transistors. The interconnect structure is arranged to electrically connect each gate structure of the first pair of transistors, each first source / drain structure of the second pair of transistors, and each first source / drain structure of the third pair of transistors to a selection terminal, a first input terminal, and a second input terminal of the multiplexer unit, respectively.

[0116] Some embodiments described herein may include a semiconductor device. The semiconductor device includes a conductive layer, a transistor structure, and an interconnect structure. The conductive layer is formed over a semiconductor substrate. The transistor structure is formed on a first region of the semiconductor substrate. The transistor structure includes a polysilicon gate segment, a first contact element, and a second contact element. A first conductive wire and a second conductive wire of the conductive layer cross a first portion and a second portion of the polysilicon gate segment, respectively. The first contact element is formed on the first portion of the polysilicon gate segment and contacts the first conductive wire. The second contact element is formed on the second portion of the polysilicon gate segment and contacts the second conductive wire. The interconnect structure is formed on a second region of the semiconductor substrate different from the one region. The interconnect structure includes a third conductive wire, a fourth conductive wire, a plurality of fifth conductive wires, a plurality of third contact elements, and a plurality of fourth contact elements. The third conductive wire and the fourth conductive wire are coupled to the first conductive wire and the second conductive wire, respectively. Each of the third conductive wire and the fourth conductive wire extends in a first direction. The fifth conductive wires are formed at a level different from each of the third conductive wire and the fourth conductive wire. Each fifth conductive wire extends in a second direction different from the first direction. The third contact elements are respectively formed on different portions of the third conductive wire crossed by the fifth conductive wires. One of the third contact elements is arranged to electrically connect the third conductive wire to the fifth conductive wire. The fourth contact elements are respectively formed on different portions of the fourth conductive wire crossed by the fifth conductive wires. One of the fourth contact elements is arranged to electrically isolate the fourth conductive wire from the fifth conductive wire.

[0117] Some embodiments described herein may include a method for forming a multiplexer unit. The method includes: forming a plurality of polysilicon segments of a plurality of transistors on a semiconductor substrate, the transistors including a plurality of p-channel transistors positioned on an upper portion of the semiconductor substrate and a plurality of n-channel transistors positioned on a lower portion of the semiconductor substrate, each polysilicon segment extending across an active region of the semiconductor substrate to define a first source / drain region and a second source / drain region; forming a plurality of contact elements on the polysilicon segments, the first source / drain region, and the second source / drain region of each transistor; forming a conductive layer on the contact elements, the conductive layer including a first conductive portion and a second conductive portion separated from each other, wherein the polysilicon segment is electrically isolated from the first conductive portion by a first contact element of the contact elements and electrically connected to the second conductive portion by a second contact element of the contact elements; interconnecting a first p-channel transistor and a first n-channel transistor of the transistors through the conductive layer to form an inverter; interconnecting a second p-channel transistor and a second n-channel transistor of the transistors through the conductive layer to form a first transmission gate, wherein the respective polysilicon segments of the second p-channel transistor and the second n-channel transistor are electrically connected to an input and an output of the inverter, respectively; interconnecting a third p-channel transistor and a third n-channel transistor of the transistors through the conductive layer to form a second transmission gate, wherein the respective polysilicon segments of the third p-channel transistor and the third n-channel transistor are electrically connected to the output and the input of the inverter, respectively.

[0118] The features of several embodiments have been outlined above so that those skilled in the art may better understand aspects of the present invention. Those skilled in the art should appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures for the purpose of implementing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also realize that these equivalent constructs do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and alterations to this disclosure without departing from the spirit and scope of the present invention.

[0119] Symbol Explanation

[0120] 100: Semiconductor structure

[0121] 101: Semiconductor substrate

[0122] 101.1: n-well region

[0123] 102.1 to 102.4: Transistor structures

[0124] 103.1: Interconnect structure

[0125] 103.2: Interconnection structure

[0126] 110: Transistor layer

[0127] 120: Conductive layer

[0128] 120.1 to 120.12: Conductive portions

[0129] 122.1 to 122.12: Contact elements

[0130] 122.3a: Conductive segment

[0131] 122.3b: Non-conductive segment

[0132] 122.4a: Conductive segment

[0133] 122.4b: Non-conductive segment

[0134] 122.7a: Conductive segment

[0135] 122.7b: Non-conductive segment

[0136] 122.9a: Conductive segment

[0137] 122.9b: Non-conductive segment

[0138] 130: Conductive layer

[0139] 130.1 to 130.3: Conductive portions

[0140] 132.1 to 132.3: Contact elements

[0141] 132.3a: Conductive segment

[0142] 132.3b: Non-conductive segment

[0143] 140: Conductive layer

[0144] 140.1: Conductive portion

[0145] 140.2: Conductive portion

[0146] 142.1: Contact element

[0147] 142.1a: Conductive segment

[0148] 142.1b: Non-conductive segment

[0149] 142.2: Contact element

[0150] 200: Multiplexer unit

[0151] 400: Semiconductor device

[0152] 401: Semiconductor substrate

[0153] 403: Interconnection structure

[0154] 404: Dielectric layer

[0155] 410.D1: Diffusion region

[0156] 410.D2: Diffusion region

[0157] 410.D3: Diffusion region

[0158] 410.D4: Diffusion region

[0159] 410.D5: Diffusion region

[0160] 410.D6: Diffusion region

[0161] 410.D7: Diffusion region

[0162] 410.D8: Diffusion region

[0163] 410.G1: Polysilicon gate segment

[0164] 410.G2: Polysilicon gate segment

[0165] 410.G3: Polysilicon gate segment

[0166] 410.G4: Polysilicon gate segment

[0167] 410.G5: Polysilicon gate segment

[0168] 410.G6: Polysilicon gate segment

[0169] 410.G7: Polysilicon gate segment

[0170] 410.G8: Polysilicon gate segment

[0171] 410.GD: Gate dielectric

[0172] 410.S1: Diffusion region

[0173] 410.S2: Diffusion region

[0174] 410.S3: Diffusion region

[0175] 410.S4: Diffusion region

[0176] 410.S5: Diffusion region

[0177] 410.S6: Diffusion region

[0178] 410.S7: Diffusion region

[0179] 410.S8: Diffusion region

[0180] 410.X1: Active region

[0181] 410.X2: Active region

[0182] 410.X3: Active region

[0183] 410.X4: Active region

[0184] 410.X5: Active region

[0185] 410.X6: Active region

[0186] 410.X7: Active region

[0187] 410.X8: Active region

[0188] 412.10 to 412.16: Portion

[0189] 420: Conductive layer

[0190] 420.1: Conductive portion

[0191] 420.2: Conductive portion

[0192] 420.11 to 420.14: Conductive wire

[0193] 420.21 to 420.24: Conductive wire

[0194] 420.31 to 420.35: Conductive wire

[0195] 420.41 to 420.45: Conductive wire

[0196] 420.51 to 420.56: Conductive wire

[0197] 420.61 to 420.66: Conductive wire

[0198] 420.71 to 420.74: Conductive wire

[0199] 420.81 to 420.84: Conductive wire

[0200] 422.11 to 422.16: Contact element

[0201] 422.12a: Conductive segment

[0202] 422.12b: Non - conductive segment

[0203] 422.14a: Conductive segment

[0204] 422.14b: Non-conductive section

[0205] 422.21 to 422.26: Contact elements

[0206] 422.31 to 422.36: Contact elements

[0207] 422.41 to 422.46: Contact elements

[0208] 422.51 to 422.56: Contact elements

[0209] 422.61 to 422.66: Contact elements

[0210] 422.71 to 422.76: Contact elements

[0211] 422.81 to 422.86: Contact elements

[0212] 430.1 to 430.12: Conductive wires

[0213] 432.1 to 432.22: Contact elements

[0214] 440.1 to 440.3: Conductive wires

[0215] 442.1 to 442.33: Contact elements

[0216] 500: Multiplexer unit

[0217] 700: Semiconductor device

[0218] 703: Interconnection structure

[0219] 800: Semiconductor device

[0220] 803: Interconnection structure

[0221] 804.1 to 804.K: Circuit units

[0222] 806.1 to 806.K: Circuit units

[0223] 850.1 to 850.N: Conductive wires

[0224] 860.1 to 860.M: Conductive wires

[0225] 900: Method

[0226] 902: Operation

[0227] 904: Operation

[0228] 906: Operation

[0229] 908: Operation

[0230] 910: Operation

[0231] 912: Operation

[0232] 1006: Groove

[0233] 1008: Groove

[0234] 1100: Method

[0235] 1102: Operation

[0236] 1104: Operation

[0237] 1106: Operation

[0238] 1108: Operation

[0239] 1110: Operation

[0240] 1112: Operation

[0241] GD1: Gate Dielectric

[0242] GD2: Gate Dielectric

[0243] GD3: Gate Dielectric

[0244] GD4: Gate Dielectric

[0245] IN0: Input Terminal

[0246] IN1: Input Terminal

[0247] OT: Connection Terminal

[0248] OUT: Output Terminal

[0249] OUTX: Output Terminal

[0250] PD0: Transistor

[0251] PD1: Transistor

[0252] PG1: Polysilicon Gate Segment

[0253] PG2: Polysilicon Gate Segment

[0254] PG3: Polysilicon Gate Segment

[0255] PG4: Polysilicon Gate Segment

[0256] PU0: Transistor

[0257] PU1: Transistor

[0258] S: Select Terminal

[0259] SB: Connection terminal

[0260] SD11: Source / drain region

[0261] SD12: Source / drain region

[0262] SD21: Source / drain region

[0263] SD22: Source / drain region

[0264] SD31: Source / drain region

[0265] SD32: Source / drain region

[0266] SD41: Source / drain region

[0267] SD42: Source / drain region

[0268] SPD0: Transistor structure

[0269] SPD1: Transistor structure

[0270] SPU0: Transistor structure

[0271] SPU1: Transistor structure

[0272] STA0: Transistor structure

[0273] STA1: Transistor structure

[0274] STB0: Transistor structure

[0275] STB1: Transistor structure

[0276] TA0: Transistor

[0277] TA1: Transistor

[0278] TB0: Transistor

[0279] TB1: Transistor

[0280] VDD: Supply voltage

[0281] VSS: Supply voltage.

Claims

1. A multiplexer unit, comprising: A semiconductor substrate; A conductive layer formed over the semiconductor substrate; Multiple pairs of transistors formed on the semiconductor substrate, each pair of transistors including a p-channel transistor and an n-channel transistor; a gate structure, a first source / drain structure, and a second source / drain structure of each of the p-channel transistor and the n-channel transistor are electrically connected to the conductive layer, and the gate structure includes: A conductive segment formed on the semiconductor substrate and extending across an active region of the semiconductor substrate, the first source / drain structure and the second source / drain structure are formed on the active region and located on opposite sides of the conductive segment, and a first conductive portion and a second conductive portion of the conductive layer cross a first portion and a second portion of the conductive segment respectively; A first contact element and a second contact element formed on the first portion and the second portion of the conductive segment respectively, the first contact element is arranged to electrically connect the conductive segment to the first conductive portion, and the second contact element is arranged to electrically isolate the conductive segment from the second conductive portion; and An interconnect structure located between each pair of transistors and electrically connected to the conductive layer, wherein the transistor pairs include a first pair of transistors, a second pair of transistors, and a third pair of transistors; the interconnect structure is arranged to electrically connect each gate structure of the first pair of transistors, each first source / drain structure of the second pair of transistors, and each first source / drain structure of the third pair of transistors to a selection terminal, a first input terminal, and a second input terminal of the multiplexer unit respectively.

2. The multiplexer unit according to claim 1, wherein the conductive segment extends across the active region in a first direction; the first contact element and the second contact element are arranged on the conductive segment in a second direction perpendicular to the first direction.

3. The multiplexer unit according to claim 1, wherein the second contact element includes a conductive segment and a non-conductive segment stacked on top of each other.

4. The multiplexer unit according to claim 1, wherein at least one of the first source / drain structure and the second source / drain structure includes: A diffusion region formed in the active region, wherein a third conductive portion and a fourth conductive portion of the conductive layer are formed over a first portion and a second portion of the diffusion region respectively; And A third contact element and a fourth contact element formed on the first portion and the second portion of the diffusion region respectively, the third contact element is arranged to electrically connect the diffusion region to the third conductive portion, and the fourth contact element is arranged to electrically isolate the diffusion region from the fourth conductive portion.

5. The multiplexer unit according to claim 4, wherein the conductive segment extends across the active region in a first direction; one of the first contact element and the second contact element, the third contact element, and the fourth contact element are arranged in the first direction.

6. The multiplexer unit according to claim 4, wherein the first conductive portion and the fourth conductive portion are different portions of the same conductive wire and are electrically connected to each other.

7. The multiplexer unit according to claim 4, wherein the second conductive portion and the third conductive portion are different portions of the same conductive wire and are electrically connected to each other.

8. The multiplexer unit according to claim 1, wherein the interconnect structure is further arranged to electrically connect each second source / drain structure of the second pair of transistors and each second source / drain structure of the third pair of transistors to the output terminal of the multiplexer unit.

9. The multiplexer unit according to claim 1, wherein the pair of transistors further includes a fourth pair of transistors; the interconnect structure is further arranged to electrically connect each second source / drain structure of the second pair of transistors and each second source / drain structure of the third pair of transistors to each gate structure of the fourth pair of transistors and to electrically connect each first source / drain structure of the fourth pair of transistors to the output terminal of the multiplexer unit.

10. The multiplexer unit according to claim 1, wherein the interconnect structure includes: a third conductive portion electrically connected to the first conductive portion; a fourth conductive portion electrically connected to the second conductive portion, the fourth conductive portion being separated from the third conductive portion; a fifth conductive portion formed at a level higher than each of the third conductive portion and the fourth conductive portion, the fifth conductive portion crossing the third conductive portion and the fourth conductive portion; a third contact element formed on the third conductive portion and in contact with the fifth conductive portion; and a fourth contact element formed on the fourth conductive portion and in contact with the fifth conductive portion.

11. The multiplexer unit according to claim 10, wherein the third contact element is arranged to electrically connect the third conductive portion to the fifth conductive portion, and the fourth contact element is arranged to electrically isolate the fourth conductive portion from the fifth conductive portion.

12. The multiplexer unit according to claim 10, wherein the third contact element is arranged to electrically isolate the third conductive portion from the fifth conductive portion, and the fourth contact element is arranged to electrically connect the fourth conductive portion to the fifth conductive portion; the second conductive portion is electrically connected to one of the first source / drain structure and the second source / drain structure.

13. The multiplexer unit according to claim 10, wherein the interconnect structure further includes: a sixth conductive portion electrically connected between corresponding first source / drain structures of one of the pairs of transistors, the sixth conductive portion being separated from each of the third conductive portion and the fourth conductive portion, the fifth conductive portion crossing the sixth conductive portion; and a sixth contact element formed on the sixth conductive portion and in contact with the fifth conductive portion.

14. The multiplexer unit according to claim 10, wherein the interconnect structure further comprises: a sixth conductive portion electrically connected between corresponding second source / drain structures of one of the transistor pairs, the sixth conductive portion being separated from each of the third conductive portion and the fourth conductive portion, and the fifth conductive portion crossing the sixth conductive portion; and a sixth contact element formed on the sixth conductive portion and in contact with the fifth conductive portion.

15. A semiconductor device, comprising: a conductive layer formed over a semiconductor substrate; a transistor structure formed on a first region of the semiconductor substrate, the transistor structure comprising: a polysilicon gate segment, with a first conductive line and a second conductive line of the conductive layer crossing a first portion and a second portion of the polysilicon gate segment respectively; a first contact element formed on the first portion of the polysilicon gate segment and in contact with the first conductive line; and a second contact element formed on the second portion of the polysilicon gate segment and in contact with the second conductive line; and an interconnect structure formed on a second region of the semiconductor substrate different from the first region, the interconnect structure comprising: a third conductive line and a fourth conductive line respectively coupled to the first conductive line and the second conductive line, each of the third conductive line and the fourth conductive line extending in a first direction; a plurality of fifth conductive lines formed at a level different from each of the third conductive line and the fourth conductive line, each fifth conductive line extending in a second direction different from the first direction; a plurality of third contact elements respectively formed on different portions of the third conductive line crossed by the fifth conductive lines, wherein one of the third contact elements is arranged to electrically connect the third conductive line to the fifth conductive line; and a plurality of fourth contact elements respectively formed on different portions of the fourth conductive line crossed by the fifth conductive lines, wherein one of the fourth contact elements is arranged to electrically isolate the fourth conductive line from the fifth conductive line.

16. The semiconductor device according to claim 15, wherein the first portion and the second portion of the polysilicon gate segment are arranged in the second direction; the polysilicon gate segment further comprises a third portion extending in the first direction; and the transistor structure further comprises a first source / drain region and a second source / drain region located on opposite sides of the third portion of the polysilicon gate segment.

17. The semiconductor device according to claim 15, wherein the transistor structure further comprises: a source / drain region located at one side of the polysilicon gate segment; a fifth contact element formed on a first portion of the source / drain region, the fifth contact element being arranged to electrically connect the first portion of the source / drain region to the conductive layer; and A sixth contact element is formed on a second portion of the source / drain region, and the sixth contact element is arranged to electrically isolate the second portion of the source / drain region from the conductive layer.

18. A method for forming a multiplexer unit, comprising: forming a plurality of polysilicon segments of a plurality of transistors on a semiconductor substrate, the transistors including a plurality of p-channel transistors positioned on an upper portion of the semiconductor substrate and a plurality of n-channel transistors positioned on a lower portion of the semiconductor substrate, each polysilicon segment extending across an active region of the semiconductor substrate to define a first source / drain region and a second source / drain region; forming a plurality of contact elements on the polysilicon segments, the first source / drain region, and the second source / drain region of each transistor; forming a conductive layer on the contact elements, the conductive layer including a first conductive portion and a second conductive portion separated from each other, wherein the polysilicon segment is electrically isolated from the first conductive portion by a first contact element of the contact elements and electrically connected to the second conductive portion by a second contact element of the contact elements; interconnecting a first p-channel transistor and a first n-channel transistor of the transistors through the conductive layer to form an inverter; interconnecting a second p-channel transistor and a second n-channel transistor of the transistors through the conductive layer to form a first transmission gate, wherein the respective polysilicon segments of the second p-channel transistor and the second n-channel transistor are electrically connected to an input and an output of the inverter, respectively; and interconnecting a third p-channel transistor and a third n-channel transistor of the transistors through the conductive layer to form a second transmission gate, wherein the respective polysilicon segments of the third p-channel transistor and the third n-channel transistor are electrically connected to the output and the input of the inverter, respectively.

19. The method according to claim 18, wherein forming the contact elements on the polysilicon segments, the first source / drain region, and the second source / drain region includes: forming a dielectric layer on the polysilicon segment; forming a first groove in the dielectric layer to expose a first portion of the polysilicon segment; partially filling the first groove with an insulating material; forming a second groove in the dielectric layer to expose a second portion of the polysilicon segment; and filling the first groove and the second groove with a conductive material to form the first contact element and the second contact element, respectively, wherein the first contact element includes the conductive material and the insulating material stacked on top of each other.

20. The method according to claim 19, wherein forming the contact elements on the polysilicon segments, the first source / drain region, and the second source / drain region further includes: forming a third groove in the dielectric layer to expose a first portion of the first source / drain region; partially filling the third groove with the insulating material; forming a fourth groove in the dielectric layer to expose a second portion of the first source / drain region; and Use the conductive material to fill the third groove and the fourth groove to form a third contact element and a fourth contact element on the first source / drain region respectively, wherein the third contact element includes the conductive material and the insulating material stacked on top of each other.

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