Display device

Abstract

The present application relates to a display device. The display device includes: a display panel including a hole area, a display area around the hole area, and a non-display area around the display area; a first-first insulating layer arranged in the hole area; a sensing electrode arranged on the display area; a crack detection pattern arranged on the first-first insulating layer in the hole area; a crack detection line arranged on the non-display area; and a connection pattern arranged in a first sensing electrode among the sensing electrodes arranged on the display area to be insulated from the sensing electrode and connected to the crack detection pattern and the crack detection line, the first sensing electrode being arranged between the hole area and the non-display area. The edge of the first-first insulating layer arranged at the boundary between the display area and the hole area has a stepped structure with at least two steps.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority from Korean Patent Application No. 10-2020-0060182, filed on May 20, 2020, which is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure herein relates to a display device, and more particularly, to a display device having a crack detection pattern. Background Art

[0004] Electronic devices such as smartphones, digital cameras, laptop computers, navigation devices, and smart TVs, which generally provide images to users, include a display device for displaying images. The display device generates images and provides the generated images to the user through a display screen.

[0005] The display device includes a display panel for generating an image, an input sensing portion disposed on the display panel to sense external input, and functional elements for providing a variety of functions to a user. The input sensing portion includes a plurality of sensing electrodes for sensing external input. The functional elements include a speaker, a camera, a sensor, and the like. A plurality of apertures are defined in the display panel and the input sensing portion, and the functional elements are disposed in the apertures. Summary of the Invention

[0006] The present disclosure provides a display device with improved reliability.

[0007] According to an exemplary embodiment of the present inventive concept, a display device includes: a display panel including a hole region, a display region surrounding the hole region, and a non-display region surrounding the display region; a first-first insulating layer disposed in the hole region; a plurality of sensing electrodes disposed on the display region; a crack detection pattern disposed on the first-first insulating layer in the hole region; a crack detection line disposed on the non-display region; and a connection pattern disposed insulated from the plurality of sensing electrodes disposed on the display region in a first sensing electrode disposed between the hole region and the non-display region, and connected to the crack detection pattern and the crack detection line. An edge of the first-first insulating layer disposed at a boundary between the display region and the hole region has a stepped structure having at least two steps.

[0008] According to an exemplary embodiment of the present inventive concept, a display device includes: a display panel including a first region, a second region surrounding the first region, and a third region surrounding the second region; an insulating layer disposed in the first region; a plurality of sensing electrodes disposed on the second region; and a crack detection portion disposed on the insulating layer in the first region, insulated from the plurality of sensing electrodes, and extending to the second region and the third region. An edge of the insulating layer disposed at a boundary between the first region and the second region has a stepped structure having at least two steps.

[0009] According to an exemplary embodiment of the present invention, a display device includes: a display panel including a first area, a second area around the first area, and a third area around the second area; an insulating layer disposed in the first area; a plurality of sensing electrodes disposed on the second area; a crack detection pattern disposed on the insulating layer in the first area; a crack detection line disposed on the third area; a connecting pattern disposed in a first sensing electrode among the plurality of sensing electrodes disposed on the second area to be insulated from the plurality of sensing electrodes and configured to connect the crack detection pattern and the crack detection line, wherein the first sensing electrode is disposed between the first area and the third area; and a capping layer disposed on the insulating layer to cover an edge of the insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to describe the principles of the inventive concept. In the drawings:

[0011] Figure 1 is a perspective view of a display device according to an exemplary embodiment of the present inventive concept;

[0012] Figure 2 According to an exemplary embodiment of the present invention Figure 1 A block diagram of the display device shown in ;

[0013] Figure 3 According to the exemplary embodiment of the present invention Figure 1 A cross-sectional view taken along line II' shown in FIG.

[0014] Figure 4 Schematically shows an exemplary embodiment according to the present inventive concept Figure 3 A cross section of the display panel shown in ;

[0015] Figure 5 According to an exemplary embodiment of the present invention Figure 4 A plan view of the display panel shown in ;

[0016] Figure 6 According to an exemplary embodiment of the present invention Figure 5 An enlarged view of the periphery of the hole area shown in;

[0017] Figure 7 Schematically shows an exemplary embodiment according to the present inventive concept Figure 5 a cross-sectional configuration of any one of the pixels shown in ;

[0018] Figure 8 According to an exemplary embodiment of the present invention, Figure 3 A plan view of the input sensing portion shown in ;

[0019] Figure 9 is an enlarged view of a first sensor and a second sensor disposed around a hole area according to an exemplary embodiment of the present inventive concept;

[0020] Figure 10 According to an exemplary embodiment of the present invention, Figure 9 A cross-sectional view taken along line II-II' shown in FIG.

[0021] Figure 11 According to an exemplary embodiment of the present invention, Figure 9 A cross-sectional view taken along line III-III' shown in FIG.

[0022] Figure 12 The exemplary embodiment according to the present invention is shown as follows. Figure 9 The hole area and crack detection pattern shown in Figure 9 The cross-sectional configuration of the first connection pattern shown in ;

[0023] Figure 13 The exemplary embodiment according to the present invention is shown as follows. Figure 9 The hole area and crack detection pattern shown in Figure 9 The cross-sectional configuration of the second connection pattern shown in ;

[0024] Figure 14 The exemplary embodiment according to the present invention is shown as follows. Figure 9 The hole area shown in the figure and one of the bypass lines to Figure 9 A cross-sectional configuration of a first sensor adjacent to the aperture region shown in ;

[0025] Figure 15 An exemplary embodiment according to the present inventive concept is shown. Figure 9 The upper end of the hole area shown in FIG is adjacent to the connection pattern and the grid structure of the sensing electrode;

[0026] Figure 16According to an exemplary embodiment of the present invention Figure 9 An enlarged view of the first connection pattern, the first extension line, and the first crack detection line shown in FIG;

[0027] Figure 17 According to an exemplary embodiment of the present invention, Figure 16 A cross-sectional view taken along line IV-IV' shown in FIG.

[0028] Figure 18 According to an exemplary embodiment of the present invention, Figure 16 A sectional view taken along line V-V' shown in FIG.

[0029] Figure 19 According to an exemplary embodiment of the present invention Figure 9 An enlarged view of the second connection pattern, the second extension line, and the second crack detection line shown in FIG;

[0030] Figure 20 According to an exemplary embodiment of the present invention, Figure 19 A cross-sectional view taken along line VI-VI' shown in FIG.

[0031] Figure 21 According to an exemplary embodiment of the present invention Figure 9 Magnified view of the well area shown in;

[0032] Figure 22 According to an exemplary embodiment of the present invention, Figure 21 A cross-sectional view taken along line VII-VII' shown in FIG.

[0033] Figure 23 According to an exemplary embodiment of the present invention, Figure 21 A sectional view taken along line VIII-VIII' shown in FIG.

[0034] Figure 24 According to an exemplary embodiment of the present invention, Figure 21 A cross-sectional view taken along line IX-IX' shown in FIG.

[0035] Figures 25 to 30 is used to describe the manufacturing process according to an exemplary embodiment of the present inventive concept. Figure 21 A view of the capping layer and the second connecting line shown in ; and

[0036] Figures 31 to 35 A method of manufacturing a display device is shown as a comparative method of the present inventive concept. DETAILED DESCRIPTION

[0037] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or intervening elements or layers may be present.

[0038] Throughout this specification, the same reference numerals denote the same elements. In the accompanying drawings, the thickness, proportions, and sizes of elements are exaggerated in order to effectively describe the technical content.

[0039] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] It will be understood that although the terms first, second, etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, first component, first area, first layer or first part discussed below can be referred to as second element, second component, second area, second layer or second part. As used herein, the singular "one", "an" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise.

[0041] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0043] It will also be understood that when used in this specification, the terms “comprising” or “having” specify the presence of stated features, integers, steps, operations, elements and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups thereof.

[0044] Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 is a perspective view of a display device according to an embodiment of the inventive concept.

[0046] Reference Figure 1 The display device DD may include a hole area HA, a display area DA disposed around the hole area HA, and a non-display area NDA around the display area DA. The hole area HA may be defined as a first area, the display area DA may be defined as a second area, and the non-display area NDA may be defined as a third area.

[0047] The display area DA may surround the hole area HA, and the non-display area NDA may surround the display area DA. The display area DA may display an image, and the non-display area NDA may not display an image. The non-display area NDA may define the edge of the display device DD. In an exemplary embodiment, the edge of the display device DD may be printed in a predetermined color during the manufacturing process of the display device DD.

[0048] The camera can be set in the hole area HA as a functional element. The camera will be Figure 3 The hole area HA may be exemplarily provided in a portion of the display area DA adjacent to the upper end and right side (eg, upper right corner) of the display device DD, but the position of the hole area HA is not limited thereto.

[0049] The display device DD may have a rectangular shape having long sides extending in a first direction DR1 and short sides extending in a second direction DR2 intersecting the first direction DR1. However, the display device DD is not limited thereto and may have various shapes, such as a circle and a polygon. The vertices of the rectangular shape of the display device DD may be formed into curved lines.

[0050] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. In this specification, "when viewed in a plane" may mean a state viewed in the third direction DR3.

[0051] The top surface of the display device DD may be defined as a display surface and may be parallel to a plane defined by the first direction DR1 and the second direction DR2. Images generated in the display device DD may be provided to a user via the display surface. When a user touches an icon image IM displayed on the display surface, a primary image corresponding to each icon image IM may be provided to the user.

[0052] exist Figure 1In the embodiment, the display device DD is shown as a mobile phone by way of example. However, the display device DD can be used in small and medium-sized electronic devices (such as personal computers, laptop computers, car navigation devices, game consoles, and tablet computers) as well as large electronic devices (such as televisions and outdoor digital signage). Furthermore, these are presented merely as embodiments, and the display device DD can also be used in other electronic devices as long as it does not deviate from the concept of the present invention.

[0053] Figure 2 yes Figure 1 Block diagram of the display device shown in .

[0054] Reference Figure 2 The display device DD according to an embodiment of the present inventive concept may include a display module DM, a power module PM, a first electronic module EM1, and a second electronic module EM2. The display module DM, the power module PM, the first electronic module EM1, and the second electronic module EM2 may be electrically connected to each other.

[0055] The power module PM may provide power required for overall operation of the display device DD. The power module PM may include a battery module.

[0056] The first electronic module EM1 and the second electronic module EM2 may include various functional modules for operating the display device DD. The first electronic module EM1 may be mounted directly on a main board electrically connected to the display module DM, or may be mounted on a separate board electrically connected to the main board via a connector (not shown) or the like.

[0057] The first electronic module EM1 may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, and an external interface IF. Some of the modules described above may not be mounted on the mainboard but may be electrically connected to the mainboard via a flexible circuit board.

[0058] The control module CM may control the overall operation of the display device DD. The control module CM may activate or deactivate the display module DM. The control module CM may control other modules such as the image input module IIM and the sound input module AIM based on a touch signal received from the display module DM.

[0059] The wireless communication module TM can send and receive wireless signals to and from another terminal using Bluetooth or Wi-Fi channels. The wireless communication module TM can also send and receive voice signals using universal communication channels. The wireless communication module TM includes a transmitting section TM1 for modulating and transmitting a signal to be transmitted, and a receiving section TM2 for demodulating received signals.

[0060] The image input module IIM can process the image signal to convert the processed image signal into image data that can be displayed on the display module DM. The sound input module AIM can receive an external sound signal by using a microphone in a recording mode, a voice recognition mode, etc., and can convert the received external sound signal into electrical voice data.

[0061] The external interface IF may be used as an interface for connection with an external charger, a wired / wireless data port, a card (eg, a memory card and a SIM / UIM card) slot, and the like.

[0062] The second electronic module EM2 may include an acoustic output module AOM, a light transmitting module LM, a light receiving module LRM, a camera module CMM, etc. The above components may be directly mounted on the main board, may be mounted on a separate board to be electrically connected to the display module DM via a connector (not shown), etc., or may be electrically connected to the first electronic module EM1.

[0063] The sound output module AOM can convert sound data received from the wireless communication module TM or stored in the memory MM and output the converted sound data to the outside. The light transmission module LM can generate and output light. The light transmission module LM can output infrared light. The light transmission module LM can include an LED element. The light receiving module LRM can sense infrared light. When infrared light with a predetermined level of intensity or higher is sensed, the light receiving module LRM can be activated. The light receiving module LRM can include a CMOS sensor.

[0064] After the infrared rays generated in the light emitting module LM are output, the infrared rays may be reflected by an external object (e.g., a user's finger or face), and the reflected infrared rays may be incident on the light receiving module LRM. The camera module CMM may include a camera provided in the hole area HA to capture external images.

[0065] The display module DM may include a display panel DP and an input sensing part ISP. The display panel DP may display an image using image data provided from the control module CM.

[0066] The input sensing portion ISP may sense an external input (e.g., a user's hand or a touch pen), and the sensing signal may be converted into an input signal to be transmitted to the control module CM. The input sensing portion ISP may sense the external input using a capacitive method. The control module CM may control the operation of the display panel DP in response to the input signal from the input sensing portion ISP.

[0067] Figure 3 It is along Figure 1 A cross-sectional view taken along line II' shown in FIG.

[0068] Reference Figure 3 The display module DM of the display device DD may include a display panel DP, an input sensing portion ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, a cushion layer CSL, and first to fourth adhesive layers AL1 to AL4. The input sensing portion ISP, the anti-reflection layer RPL, and the window WIN may be disposed on the display panel DP. The panel protection film PPF and the cushion layer CSL may be disposed below the display panel DP.

[0069] The display module DM may include Figure 1 , the hole area HA, the display area DA, and the non-display area NDA shown in FIG. The hole HO may be defined in the hole area HA. ​​The hole area HA may be defined around the hole HO. The hole HO may be defined in the anti-reflection layer RPL, the input sensing part ISP, the display panel DP, the panel protection film PPF, the cushion layer CSL, and the first to fourth adhesive layers AL1 to AL4. The camera CAM may be disposed in the hole HO. In an exemplary embodiment, the hole HO may penetrate the anti-reflection layer RPL, the input sensing part ISP, the display panel DP, the panel protection film PPF, the cushion layer CSL, and the first to fourth adhesive layers AL1 to AL4. The window WIN may cover the hole HO, and the camera CAM may be disposed in the hole HO below the window WIN.

[0070] The display panel DP may be a flexible display panel. Furthermore, the display panel DP according to embodiments of the present inventive concept may be a light-emitting display panel, without particular limitation. For example, the display panel DP may be an organic light-emitting display panel or a quantum dot light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of a quantum dot light-emitting display panel may include quantum dots, quantum rods, or the like. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0071] The input sensing portion ISP may be provided on the display panel DP. The input sensing portion ISP may include a plurality of sensors (not shown) for sensing external input. The sensors may sense external input using a capacitive method. When manufacturing the display panel DP, the input sensing portion ISP may be directly manufactured on the display panel DP. However, the input sensing portion ISP is not limited thereto and may be manufactured as a panel separate from the display panel DP so as to be attached to the display panel DP via an adhesive layer.

[0072] An anti-reflection layer (RPL) may be provided on the input sensing portion ISP. The anti-reflection layer (RPL) may be defined as a film that prevents reflection of external light. The anti-reflection layer (RPL) may reduce the degree of reflection of external light incident on the display panel DP from above the display device DD. For example, the anti-reflection layer (RPL) may include a phase retarder and / or a polarizer.

[0073] A window WIN may be provided on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing portion ISP, and the anti-reflection layer RPL from external scratches and / or impacts. The window WIN may be optically transparent. External light may be provided to the camera CAM through the window WIN.

[0074] A panel protection film (PPF) may be disposed below the display panel DP. The panel protection film (PPF) may be defined as a protective substrate. The panel protection film (PPF) may protect the lower portion of the display panel DP. The panel protection film (PPF) may include a flexible plastic material. For example, the panel protection film (PPF) may include polyethylene terephthalate (PET).

[0075] The cushion layer CSL may be disposed under the panel protection film PPF. The cushion layer CSL may protect the display panel DP by absorbing external impact applied to the lower portion of the display panel DP. The cushion layer CSL may include a foam sheet having a predetermined elastic force.

[0076] A first adhesive layer AL1 may be provided between the display panel DP and the panel protection film PPF. The display panel DP and the panel protection film PPF may be bonded to each other via the first adhesive layer AL1. A second adhesive layer AL2 may be provided between the anti-reflection layer RPL and the input sensing part ISP. The anti-reflection layer RPL and the input sensing part ISP may be bonded to each other via the second adhesive layer AL2.

[0077] A third adhesive layer AL3 may be provided between the window WIN and the anti-reflection layer RPL. The window WIN and the anti-reflection layer RPL may be bonded together via the third adhesive layer AL3. A fourth adhesive layer AL4 may be provided between the panel protection film PPF and the cushion layer CSL. The panel protection film PPF and the cushion layer CSL may be bonded together via the fourth adhesive layer AL4.

[0078] Figure 4 It is shown as an example Figure 3 A cross section of a display panel is shown in FIG.

[0079] Reference Figure 4 The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OLED.

[0080] The substrate SUB may include a display area DA and a non-display area NDA around the display area DA. The substrate SUB may include a flexible plastic material. For example, the substrate SUB may include polyimide (PI). Although not shown, Figure 3The hole HO shown in FIG may be defined in the substrate SUB, the circuit element layer DP-CL, and the display element layer DP-OLED. In an exemplary embodiment, the hole HO may penetrate the substrate SUB, the circuit element layer DP-CL, and the display element layer DP-OLED.

[0081] The display element layer DP-OLED may be disposed in the display area DA. The thin film encapsulation layer TFE may be disposed on the circuit element layer DP-CL to cover the display element layer DP-OLED.

[0082] Multiple pixels can be arranged in the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel can include a transistor arranged in the circuit element layer DP-CL and a light-emitting element arranged in the display element layer DP-OLED to be connected to the transistor. The configuration of the pixel will be described in detail below.

[0083] Figure 5 yes Figure 4 A plan view of the display panel is shown in FIG.

[0084] Reference Figure 5 According to an embodiment of the present inventive concept, a display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, and an emission driver EDV. The scan driver SDV, the data driver DDV, and the emission driver EDV may be provided in the display panel DP.

[0085] The display panel DP may have long sides extending in a first direction DR1 and short sides extending in a second direction DR2. The display panel DP may include a hole area HA in which a hole HO is defined, a display area DA surrounding the hole area HA, and a non-display area NDA surrounding the display area DA. The hole area HA may correspond to a plurality of sensing electrodes SE1 and SE2 provided in the display area DA (to be referred to later). Figure 8 and Figure 9 The cutout area of ​​at least one of the holes HO and the crack detection pattern CDP and the bypass line ARL extending around the hole HO is formed. The crack detection pattern CDP and the bypass line ARL will be referred to later. Figure 9 Describe. Figure 9 In an exemplary embodiment, to form the hole area HA, one first sensing electrode may be cut away, and four sensing electrodes surrounding the first sensing electrode may be partially cut away. In an exemplary embodiment, a plurality of pixels PX may not be disposed in the hole area HA and may surround the hole area HA in the display area DA.

[0086] The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL, a plurality of data lines DL, and a plurality of emission lines EL. The pixels PX may be arranged in the display area DA and may be connected to the scan lines SL, the data lines DL, and the emission lines EL. The pixels PX may be arranged around the aperture area HA. ​​The pixels PX may not be arranged in the aperture area HA.

[0087] The scan driver SDV, the data driver DDV, and the emission driver EDV may be disposed in the non-display area NDA. The scan driver SDV and the emission driver EDV may be disposed adjacent to the long sides of the display panel DP, respectively. The data driver DDV may be manufactured in the form of an integrated circuit chip and disposed adjacent to one of the short sides of the display panel DP.

[0088] The scan lines SL may extend in the second direction DR2 to be connected to the scan driver SDV, the data lines DL may extend in the first direction DR1 to be connected to the data driver DDV, and the emission lines EL may extend in the second direction DR2 to be connected to the emission driver EDV.

[0089] The scan driver SDV may generate a plurality of scan signals, and the scan signals may be applied to the pixels PX via the scan lines SL. The scan signals may be sequentially applied to the pixels PX. The data driver DDV may generate a plurality of data voltages, and the data voltages may be applied to the pixels PX via the data lines DL. The emission driver EDV may generate a plurality of emission signals, and the emission signals may be applied to the pixels PX via the emission lines EL.

[0090] Although not shown, a timing controller (not shown) for controlling operations of the scan driver SDV, the data driver DDV, and the emission driver EDV may be included in the display device DD.

[0091] The pixel PX may receive a data voltage in response to a scan signal. The pixel PX may display an image by emitting light of brightness corresponding to the data voltage in response to an emission signal. The emission time of the pixel PX may be controlled by the emission signal.

[0092] Figure 6 is Figure 5 Magnified view of the periphery of the hole area shown in .

[0093] Reference Figure 6 A groove GV may be defined between the boundary of the hole area HA and the hole HO. The groove GV may be arranged along the boundary of the hole HO to surround the hole HO. A plurality of grooves GV may be provided. Figure 12 Describe the cross-sectional structure of the groove GV in detail, Figure 12 A cross section of the periphery of the hole HO is shown.

[0094] The groove GV may have a circular ring shape. However, this is only exemplarily shown, and the groove GV may be formed as a closed line of a polygonal shape or an elliptical shape. In addition, the groove GV may be formed in a shape including a plurality of partially disconnected patterns. In an exemplary embodiment, the groove GV may accommodate the deposition pattern ELP therein. This will be referred to later. Figure 12 Describe the deposition pattern ELP.

[0095] The pixels PX may be arranged to surround the hole area HA. ​​The pixels PX around the hole area HA among the pixels PX may be connected to the scan line SL, the data line DL, and the emission line EL extending through the hole area HA. ​​The rows described below may correspond to the second direction DR2, and the columns described below may correspond to the first direction DR1.

[0096] The pixels PX of the h-th row ROW_h, between which the aperture area HA is disposed, may be connected to the scan line SL extending in the second direction DR2 and along the boundary of the aperture area HA in the aperture area HA. ​​The pixels PX of the h-th row ROW_h may be connected to the emission line EL extending in the second direction DR2 and along the boundary of the aperture area HA in the aperture area HA. ​​Here, h is a natural number.

[0097] The pixels PX of the k-th column COL_k between which the hole area HA is disposed may be connected to the data line DL extending in the first direction DR1 and extending along a boundary of the hole area HA in the hole area HA. ​​Here, k is a natural number.

[0098] Figure 7 It is shown as an example Figure 5 The cross-sectional configuration of any one of the pixels shown in .

[0099] Reference Figure 7 Each pixel PX may be disposed on a substrate SUB and may include a light-emitting element OLED and a transistor TR connected to the light-emitting element OLED. The light-emitting element OLED may include a first electrode E1, a second electrode E2, and a light-emitting layer EML. The first electrode E1 may be an anode, and the second electrode E2 may be a cathode. The light-emitting element OLED may be defined as an organic light-emitting element.

[0100] A barrier layer BR may be provided on the substrate SUB, and a buffer layer BF may be provided on the barrier layer BR. The barrier layer BR and the buffer layer BF may prevent oxygen or moisture introduced through the substrate SUB from penetrating the pixel PX. Furthermore, the barrier layer BR and the buffer layer BF may reduce the surface energy of the substrate SUB, allowing the pixel PX to be stably formed on the substrate SUB.

[0101] Although a barrier layer BR and a buffer layer BF are exemplarily provided on the substrate SUB, embodiments of the present inventive concept are not limited thereto. For example, at least one of the barrier layer BR and the buffer layer BF may be omitted. Alternatively, in addition to the barrier layer BR and the buffer layer BF, another layer may be further stacked on the substrate SUB.

[0102] The semiconductor layer SM of the transistor TR may be provided on the buffer layer BF. The semiconductor layer SM may be formed of an inorganic semiconductor material such as amorphous silicon and polycrystalline silicon, or may be formed of an organic semiconductor material. In addition, the semiconductor layer SM may include an oxide semiconductor. Figure 7 Although not shown in the figure, a source region, a drain region, and a channel region between the source region and the drain region may be included in the semiconductor layer SM.

[0103] A first insulating layer IL1 may be provided on the buffer layer BF to cover the semiconductor layer SM. A gate electrode GE of the transistor TR overlapping the semiconductor layer SM may be provided on the first insulating layer IL1. The gate electrode GE may be provided to overlap the channel region of the semiconductor layer SM. A second insulating layer IL2 may be provided on the first insulating layer IL1 to cover the gate electrode GE.

[0104] The upper electrode UE may be disposed on the second insulating layer IL2. When viewed in a planar manner, the upper electrode UE may overlap the gate electrode GE. The pixel PX may include a capacitor, and the upper electrode UE may function as one electrode of the capacitor by receiving an electrical signal different from that of the gate electrode GE. However, this is described as an example, and the upper electrode UE may be omitted in embodiments of the present invention. A third insulating layer IL3 may be disposed on the second insulating layer IL2 to cover the upper electrode UE.

[0105] The source electrode SE and drain electrode DE of the transistor TR may be disposed spaced apart from each other on the third insulating layer IL3. The source electrode SE may be connected to the source region of the semiconductor layer SM via a first contact hole CH1 defined in the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3. In an exemplary embodiment, the first contact hole CH1 may penetrate the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 to expose a portion of the source region of the semiconductor layer SM. The drain electrode DE may be connected to the drain region of the semiconductor layer SM via a second contact hole CH2 defined in the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3. In an exemplary embodiment, the second contact hole CH2 may penetrate the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 to expose a portion of the drain region of the semiconductor layer SM.

[0106] A fourth insulating layer IL4 may be disposed on the third insulating layer IL3 to cover the source electrode SE and the drain electrode DE of the transistor TR.

[0107] The first electrode E1 may be disposed on the fourth insulating layer IL4. The first electrode E1 may be connected to the drain electrode DE through a third contact hole CH3 defined in the fourth insulating layer IL4. In an exemplary embodiment, the third contact hole CH3 may penetrate the fourth insulating layer IL4 to expose a portion of the drain electrode DE.

[0108] A pixel defining film PDL exposing a predetermined portion of the first electrode E1 may be disposed on the first electrode E1 and the fourth insulating layer IL4. An opening PX_OP for exposing the predetermined portion of the first electrode E1 may be defined in the pixel defining film PDL. In an exemplary embodiment, the opening PX_OP may penetrate the pixel defining film PDL to expose the predetermined portion of the first electrode E1.

[0109] The light-emitting layer (EML) may be disposed on the first electrode E1 and the pixel-defining layer (PDL). The second electrode E2 may be disposed on the light-emitting layer (EML). The light-emitting layer (EML) and the second electrode (E2) may be disposed on the first electrode E1 and the pixel-defining layer (PDL). The light-emitting layer (EML) may include at least one material that emits red, green, and blue light, and may include a fluorescent material or a phosphorescent material. The light-emitting layer (EML) may include an organic light-emitting material or an inorganic light-emitting material.

[0110] In an embodiment of the present inventive concept, the light-emitting layer EML is shown as a layer having a unitary shape on the first electrode E1 and the pixel-defining layer PDL. However, this is shown by way of example, and the light-emitting layer EML may be provided only in the region corresponding to the opening PX_OP. The light-emitting layer EML may further include a charge control layer. The charge control layer may control the movement of charges to increase the luminous efficiency and lifespan of the light-emitting element OLED. The charge control layer may include at least one of a hole transport material, a hole injection material, an electron transport material, and an electron injection material.

[0111] A thin film encapsulation layer TFE may be provided on the second electrode E2. The thin film encapsulation layer TFE may include a first encapsulation layer EN1 provided on the second electrode E2, a second encapsulation layer EN2 provided on the first encapsulation layer EN1, and a third encapsulation layer EN3 provided on the second encapsulation layer EN2. The first encapsulation layer EN1 and the third encapsulation layer EN3 may be inorganic insulating layers, and the second encapsulation layer EN2 may be an organic insulating layer.

[0112] The first encapsulation layer EN1 and the third encapsulation layer EN3 can protect the pixel PX from moisture / oxygen. The second encapsulation layer EN2 can protect the pixel PX from foreign matter such as dust particles. The input sensing part ISP described above can be provided on the thin film encapsulation layer TFE.

[0113] The layer from the barrier layer BR to the fourth insulating layer IL4 may be defined as a circuit element layer DP-CL. The layer from the first electrode E1 to the second electrode E2 may be defined as a display element layer DP-OLED.

[0114] A first voltage may be applied to the first electrode E1, and a second voltage lower than the first voltage may be applied to the second electrode E2. Holes and electrons injected into the light-emitting layer EML may combine with each other to generate excitons, and the light-emitting element OLED may emit light when the excitons transition to a ground state. The light-emitting element OLED may emit light and thus may display an image.

[0115] Figure 8 is Figure 3 A plan view of the input sensing portion shown in FIG.

[0116] Reference Figure 8 The input sensing part ISP may be provided on the display panel DP. The input sensing part ISP may include a plurality of sensing electrodes SE1 and SE2, a plurality of sensing lines SNL1, SNL2, and SNL3, a plurality of sensing pads SPD1, SPD2, and SPD3, first to fourth pads PD1 to PD4, and a crack detection part CDT.

[0117] The input sensing portion ISP may include a hole area HA in which a hole HO is defined, an active area AA surrounding the hole area HA, and a non-active area NAA surrounding the active area AA. The active area AA may overlap with the display area DA, and the non-active area NAA may overlap with the non-display area NDA. The active area AA may be defined as a second area, and the non-active area NAA may be defined as a third area.

[0118] The sensing electrodes SE1 and SE2 may be disposed in the active area AA. The sensing electrodes SE1 and SE2 may not be disposed in the aperture area HA. ​​The sensing lines SNL1, SNL2, and SNL3 may be connected to one end of the sensing electrodes SE1 and SE2 and the other end of the sensing electrode SE1, respectively, and may extend to the non-active area NAA to be connected to the sensing pads SPD1, SPD2, and SPD3, respectively.

[0119] The crack detection portion CDT may be disposed in the hole area HA and may extend to the active area AA and be insulated from the sensing electrodes SE1 and SE2 . The crack detection portion CDT may extend to the non-active area NAA to be connected to the first to fourth pads PD1 to PD4 .

[0120] The sensing pads SPD1 , SPD2 , and SPD3 and the first to fourth pads PD1 to PD4 may be connected to an input sensing control unit (not shown) for controlling the input sensing part ISP through a flexible printed circuit board (not shown).

[0121] The sensing electrodes SE1 and SE2 may include a plurality of first sensing electrodes SE1 extending in the first direction DR1 and arranged in the second direction DR2, and a plurality of second sensing electrodes SE2 extending in the second direction DR2 and arranged in the first direction DR1. The second sensing electrodes SE2 may extend in an insulated manner to intersect with the first sensing electrodes SE1. The first sensing electrodes SE1 may be defined as output sensing electrodes, and the second sensing electrodes SE2 may be defined as input sensing electrodes.

[0122] The sensing lines SNL1, SNL2, and SNL3 may include a plurality of first sensing lines SNL1, a plurality of second sensing lines SNL2, and a plurality of third sensing lines SNL3. The first sensing line SNL1 may be connected to the lower end of the first sensing electrode SE1 to extend to the non-active area NAA. The second sensing line SNL2 may be connected to one end of the second sensing electrode SE2 to extend to the non-active area NAA. The third sensing line SNL3 may be connected to the upper end of the first sensing electrode SE1 to extend to the non-active area NAA.

[0123] The sensing pads SPD1, SPD2, and SPD3 may include a plurality of first sensing pads SPD1, a plurality of second sensing pads SPD2, and a plurality of third sensing pads SPD3. When viewed in a plane, the first sensing pads SPD1, the second sensing pads SPD2, and the third sensing pads SPD3 may be disposed adjacent to the lower end of the input sensing portion ISP. When viewed in a plane, the first sensing pads SPD1, the second sensing pads SPD2, and the third sensing pads SPD3 may be disposed with a region in which the data driver DDV is disposed interposed therebetween.

[0124] The data driver DDV may be disposed between the second sensing pad SPD2 and the first and third sensing pads SPD1 and SPD3. For example, the first and third sensing pads SPD1 and SPD3 may be disposed on the right side of the data driver DDV, and the second sensing pad SPD2 may be disposed on the left side of the data driver DDV. The first sensing pad SPD1 may be disposed between the third sensing pad SPD3 and the data driver DDV.

[0125] The first sensing line SNL1 may extend to the non-active area NAA to connect to the first sensing pad SPD1, the second sensing line SNL2 may extend to the non-active area NAA to connect to the second sensing pad SPD2, and the third sensing line SNL3 may extend to the non-active area NAA to connect to the third sensing pad SPD3.

[0126] The input sensing part ISP may be driven in a mutual sensing mode. For example, a driving signal may be applied to the second sensing electrode SE2 through the second sensing line SNL2, and a sensing signal may be output from the first sensing electrode SE1 through the first and third sensing lines SNL1 and SNL3.

[0127] Each of the first sensing electrodes SE1 may include a plurality of first sensors SP1 (i.e., first sensing electrode patterns) arranged in a first direction DR1 and a plurality of connection portions CP connecting the first sensors SP1. In an exemplary embodiment, the first sensors SP1 may be spaced apart from each other in the first direction DR1. Each connection portion CP may be provided between two first sensors SP1 adjacent to each other in the first direction DR1 to electrically connect the two first sensors SP1.

[0128] Each of the second sensing electrodes SE2 may include a plurality of second sensors SP2 (i.e., a second sensing electrode pattern) arranged in the second direction DR2 and a branch portion BP disposed between the second sensors SP2. The second sensors SP2 may be spaced apart from each other in the second direction DR2. Each branch portion BP may be disposed between two second sensors SP2 adjacent to each other in the second direction DR2 to extend from the two second sensors SP2. The branch portion BP may be integrally formed with the second sensors SP2.

[0129] The first sensor SP1 and the second sensor SP2 may be spaced apart from each other without overlapping and may be alternately arranged. A capacitance may be formed by the first sensor SP1 and the second sensor SP2. The connection portion CP may extend in an insulating manner to intersect the branch portion BP.

[0130] The first and second sensors SP1 and SP2 and the branch portions BP may be provided in the same layer. The connection portion CP may be provided in a layer different from the layer of the first and second sensors SP1 and SP2 and the branch portions BP. The connection portion CP may be provided below the first and second sensors SP1 and SP2 and the branch portions BP. The description "A and B may be provided in the same layer" or "A and B may be provided in the same layer" may mean that elements A and B are formed or patterned starting from the same layer (which may be provided on an insulating layer) using a photolithography process. The description "A and B may be provided in different layers" may mean that the two elements are formed starting from different layers (which are insulated from each other) using at least one insulating layer. For example, element A may be formed starting from a first layer on the upper surface of the insulating layer, and element B may be formed starting from a second layer on the lower surface of the insulating layer.

[0131] The first and second sensors SP1 and SP2 adjacent to the hole area HA of the first and second sensors SP1 and SP2 may have shapes different from those of the other first and second sensors SP1 and SP2. For example, the four second sensors SP2 may surround the hole area HA. ​​A portion of each of the four second sensors SP2 adjacent to the hole area HA may be modified to have a shape corresponding to the boundary of the hole area HA. ​​However, embodiments of the present inventive concept are not limited thereto, and a portion of each of the four first sensors SP1 adjacent to the hole area HA may be modified depending on the location of the hole area HA.

[0132] The crack detection portion CDT may include a crack detection pattern CDP, a crack detection line CDL, and a connection portion CPT. The crack detection pattern CDP, the crack detection line CDL, and the connection portion CPT may include a conductive material.

[0133] The crack detection pattern CDP may be provided in the hole area HA. ​​The crack detection pattern CDP may be formed as an open curve (eg, an open circle) including one end and the other end. The crack detection pattern CDP may be provided in the hole area HA to surround the hole HO.

[0134] The crack detection line CDL may be disposed in the non-active area NAA and extend along the edge of the input sensing portion ISP. The crack detection line CDL may be connected to the first to fourth pads PD1 to PD4. The crack detection line CDL may be disposed further outward than the first, second, and third sensing lines SNL1, SNL2, and SNL3.

[0135] The crack detection lines CDL may include a first crack detection line CDL1 and a second crack detection line CDL2, the second crack detection line CDL2 being positioned further outward than the first crack detection line CDL1 and adjacent to an edge of the input sensing portion ISP. The first crack detection line CDL1 and the second crack detection line CDL2 may be positioned in the non-active area NAA to extend along the upper end and left and right sides of the input sensing portion ISP. The first crack detection line CDL1 and the second crack detection line CDL2 may extend toward the lower end of the input sensing portion ISP.

[0136] The first pad PD1 and the second pad PD2 may be disposed on the left side of the second sensing pad SPD2. The first pad PD1 may be disposed between the second pad PD2 and the second sensing pad SPD2. The third pad PD3 and the fourth pad PD4 may be disposed on the right side of the third sensing pad SPD3. The third pad PD3 may be disposed between the fourth pad PD4 and the third sensing pad SPD3.

[0137] The first crack detection line CDL1 may be connected to the first pad PD1 and the third pad PD3. One end of the first crack detection line CDL1 may be connected to the first pad PD1, and the other end of the first crack detection line CDL1 may be connected to the third pad PD3.

[0138] The second crack detection line CDL2 may be connected to the second pad PD2 and the fourth pad PD4. One end of the second crack detection line CDL2 may be connected to the second pad PD2, and the other end of the second crack detection line CDL2 may be connected to the fourth pad PD4.

[0139] The connection portion CPT may be connected to the crack detection pattern CDP and extend in the first direction DR1. The connection portion CPT may extend to the non-active area NAA through the first and second sensing electrodes SE1 and SE2 between the hole area HA and the non-active area NAA. The connection portion CPT may be insulated from the first and second sensing electrodes SE1 and SE2. The connection portion CPT may be connected to the crack detection line CDL in the non-active area NAA.

[0140] The connection portion CPT may include a first connection portion CPT1 and a second connection portion CPT2, which extend in the first direction DR1 and are spaced apart from each other in the second direction DR2. The first connection portion CPT1 may be connected to one end of the crack detection pattern CDP and the first crack detection line CDL1. In an exemplary embodiment, one end of the crack detection pattern CDP and the first crack detection line CDL1 may be connected to each other via the first connection portion CPT1. The second connection portion CPT2 may be connected to the other end of the crack detection pattern CDP and the second crack detection line CDL2. In an exemplary embodiment, the other end of the crack detection pattern CDP and the second crack detection line CDL2 may be connected to each other via the second connection portion CPT2.

[0141] Damage to the display device DD, such as a crack in the hole area HA or the non-active area NAA, may be detected by the crack detection portion CDT. The first and third pads PD1 and PD3 may be input terminals, and the second and fourth pads PD2 and PD4 may be output terminals.

[0142] The electrical signal received through the first pad PD1 may be output to the second pad PD2 after passing through the first crack detection line CDL1, the crack detection pattern CDP, and the second crack detection line CDL2. Furthermore, the electrical signal received through the third pad PD3 may be output to the fourth pad PD4 after passing through the first crack detection line CDL1, the crack detection pattern CDP, and the second crack detection line CDL2.

[0143] When the level of the signal detected at each of the second pad PD2 and the fourth pad PD4 is lower than the level of the reference signal or is at zero level, both the first crack detection line CDL1 and the second crack detection line CDL2 may be damaged, or the crack detection pattern CDP may be damaged. Therefore, it is possible to detect whether a crack has occurred in the hole area HA.

[0144] Furthermore, when a signal detected at only either one of the second pad PD2 and the fourth pad PD4 is determined to be defective, the crack detection line CDL may be damaged. Therefore, it is possible to detect whether a crack has occurred in the non-active area NAA.

[0145] In an embodiment of the present inventive concept, a crack detection unit (CDT) can easily detect whether a display device (DD) has cracks. Therefore, it is possible to detect whether a display device (DD) has defects without a separate inspection circuit or inspection equipment. A more detailed configuration of the crack detection unit (CDT) will be described below.

[0146] Figure 9 is an enlarged view of the first sensor and the second sensor disposed around the hole area. Figure 10 It is along Figure 9 A cross-sectional view taken along line II-II' shown in FIG. Figure 11 It is along Figure 9 A cross-sectional view taken along line III-III' shown in FIG.

[0147] By way of example, in Figure 10 and Figure 11 , the first sensor SP1 and the second sensor SP2 provided on the thin film encapsulation layer TFE are shown, and elements under the thin film encapsulation layer TFE are omitted.

[0148] Reference Figure 9 and Figure 10 Each of the first sensing electrodes SE1 may include a plurality of first sensors SP1, a plurality of first dummy patterns DPT1, and a plurality of connection portions CP. The first dummy patterns DPT1 may be disposed in a plurality of first openings OP1 defined in each of the first sensors SP1. In an exemplary embodiment, the plurality of first openings OP1 may penetrate each of the first sensors SP1 to provide a space for accommodating the first dummy patterns DPT1 therein. The connection portions CP may connect the first sensors SP1.

[0149] exist Figure 9 In order to simplify the drawing, the boundary BAL1 between the first dummy pattern DPT1 and the first sensor SP1 in which the first opening OP1 is defined is exemplarily shown as a line. Figure 10 As shown in FIG, the first sensor SP1 and the first dummy pattern DPT1 may be spaced apart from and insulated from each other at a boundary BAL1 between the first sensor SP1 and the first dummy pattern DPT1.

[0150] The first insulating layer T_INS1 may be disposed on the thin film encapsulation layer TFE. A connection portion CP may be disposed on the first insulating layer T_INS1. A second insulating layer T_INS2 may be disposed on the first insulating layer T_INS1 to cover the connection portion CP. The first sensor SP1, the branch portion BP, and the first dummy pattern DPT1 may be disposed on the second insulating layer T_INS2. The first sensor SP1 may be connected to the connection portion CP via a plurality of first contact holes T_CH1 defined in the second insulating layer T_INS2. In an exemplary embodiment, the first contact holes T_CH1 may penetrate the second insulating layer T_INS2 to expose a portion of the connection portion CP.

[0151] The third insulating layer T_INS3 may be disposed on the second insulating layer T_INS2 to cover the first sensors SP1, the branch portions BP, and the first dummy pattern DPT1. Each of the first, second, and third insulating layers T_INS1, T_INS2, and T_INS3 may include an inorganic film and / or an organic film.

[0152] Reference Figure 9 and Figure 11 Each of the second sensing electrodes SE2 may include a plurality of second sensors SP2, a plurality of second dummy patterns DPT2, and a plurality of branch portions BP. The second dummy patterns DPT2 may be disposed in a plurality of second openings OP2 defined in each of the second sensors SP2. In an exemplary embodiment, the second openings OP2 may penetrate each of the second sensors SP2 to provide a space for accommodating the second dummy patterns DPT2 therein.

[0153] exist Figure 9 In order to simplify the drawing, the boundary BAL2 between the second dummy pattern DPT2 and the second sensor SP2 in which the second opening OP2 is defined is exemplarily shown as a line. Figure 11 As shown in , the second sensor SP2 and the second dummy pattern DPT2 may be spaced apart from and insulated from each other at a boundary BAL2 between the second sensor SP2 and the second dummy pattern DPT2 .

[0154] The second sensors SP2, the branch portions BP, and the second dummy pattern DPT2 may be disposed on the second insulating layer T_INS2. Each of the branch portions BP may extend from two adjacent second sensors SP2. The branch portions BP may be integrally formed with the second sensors SP2. The branch portions BP may extend to intersect with the connection portion CP. The branch portions BP may be insulated from the connection portion CP by the second insulating layer T_INS2.

[0155] A third insulating layer T_INS3 may be disposed on the second insulating layer T_INS2 to cover the second sensors SP2 , the branch portions BP, and the second dummy pattern DPT2 .

[0156] Reference Figure 9 In order to simplify the drawing, a boundary BAL3 between the first sensor SP1 and the second sensor SP2 is shown as a line. However, the first sensor SP1 and the second sensor SP2 may be spaced apart from each other and insulated from each other at the boundary BAL3.

[0157] Each of the first sensor SP1 and the second sensor SP2 may have a shape that is approximately rhombus-shaped. Furthermore, a plurality of protruding patterns PT may be defined at the edge of each of the first sensor SP1 and the second sensor SP2. For example, the protruding patterns PT may be configured to have a corrugated edge on each of the first sensor SP1 and the second sensor SP2, so that one first sensor SP1 and another adjacent second sensor SP2 can be adapted to each other via their corrugated edges.

[0158] The first connection portion CPT1 may include an extension line EXL, a first connection line CNL1, a first connection pattern CT1, and a first extension line EXL1. The second connection portion CPT2 may include a second connection line CNL2, a second connection pattern CT2, and a second extension line EXL2. The first connection pattern CT1 and the second connection pattern CT2 may be defined as connection patterns.

[0159] The first connection pattern CT1 and the second connection pattern CT2 may be insulated from the sensing electrodes SE1 and SE2. For example, some of the first openings OP1 provided between the hole area HA and the non-active area NAA (or the non-display area NDA) may be open toward the non-active area NAA. Some of the openings open toward the non-active area NAA may be defined as first sub-openings SOP1 and second sub-openings SOP2. In an exemplary embodiment, the first connection pattern CT1 and the second connection pattern CT2 may be formed in one of the first sensors SP1 having the first sub-opening SOP1 and the second sub-opening SOP2. The first sub-opening SOP1 may have a shape of at least two first openings OP1 connected to each other in the first sensor SP1 formed with the first dummy pattern DPT1 (rather than the first sensor SP1 formed with the first connection pattern CT1 and the second connection pattern CT2).

[0160] The first connection pattern CT1 may be disposed in the first sub-opening SOP1. The second connection pattern CT2 may be disposed in the second sub-opening SOP2. Since the first connection pattern CT1 and the second connection pattern CT2 are disposed in the first sub-opening SOP1 and the second sub-opening SOP2, respectively, the first connection pattern CT1 and the second connection pattern CT2 may be spaced apart from and insulated from the first sensor SP1.

[0161] The crack detection pattern CDP may be provided in the same layer as the first sensor SP1, the branch portion BP, and the second sensor SP2. The first connection pattern CT1 may be provided in a different layer from the second connection pattern CT2. The first connection pattern CT1 may be provided in the same layer as the crack detection pattern CDP, and the second connection pattern CT2 may be provided in a different layer from the crack detection pattern CDP. The second connection pattern CT2 may be provided in the same layer as the connection portion CP.

[0162] The first and second connection patterns CT1 and CT2 may be connected to the crack detection pattern CDP through the first and second connection lines CNL1 and CNL2 and the extension line EXL. The first and second connection patterns CT1 and CT2 may be connected to the first and second crack detection lines CDL1 and CDL2 through the first and second extension lines EXL1 and EXL2, respectively.

[0163] The first connection pattern CT1 may be connected to one end of the crack detection pattern CDP via an extension line EXL and a first connection line CNL1. Specifically, the extension line EXL may be provided in the same layer as the crack detection pattern CDP and may extend from one end of the crack detection pattern CDP toward the first connection pattern CT1. The first connection line CNL1 may be provided in the same layer as the second connection pattern CT2 and may connect the first connection pattern CT1 and the extension line EXL.

[0164] The first crack detection line CDL1 may be connected to the first connection pattern CT1 using a first extension line EXL1. For example, the first extension line EXL1 may be provided in the same layer as the first connection pattern CT1 and may extend from the first connection pattern CT1 to the first crack detection line CDL1. The first extension line EXL1 may be provided in the non-active area NAA (or non-display area NDA) to extend in the first direction DR1. The first crack detection line CDL1 may be provided in the same layer as the first extension line EXL1 and may extend from the first extension line EXL1. In an exemplary embodiment, the first crack detection line CDL1 may be connected to the first extension line EXL1 and extend along the boundary between the display area DA and the non-display area NDA.

[0165] The second connection pattern CT2 may be connected to the other end of the crack detection pattern CDP through a second connection line CNL2. Specifically, the second connection line CNL2 may be provided in the same layer as the second connection pattern CT2 and may extend from the second connection pattern CT2 to the hole area HA. ​​The second connection line CNL2 may be connected to the other end of the crack detection pattern CDP.

[0166] The second crack detection line CDL2 may be connected to the second connection pattern CT2 using a second extension line EXL2. For example, the second extension line EXL2 may be provided in the same layer as the second connection pattern CT2 and may extend from the second connection pattern CT2 to the second crack detection line CDL2. The second extension line EXL2 may be provided in the non-active area NAA (or non-display area NDA) to extend in the first direction DR1. The second crack detection line CDL2 may be provided in the same layer as the second extension line EXL2 and may extend from the second extension line EXL2. In an exemplary embodiment, the second crack detection line CDL2 may be connected to the second extension line EXL2 and extend along the boundary between the display area DA and the non-display area NDA.

[0167] The first and second connection lines CNL1 and CNL2 may extend to intersect the branch portions BP disposed between the hole area HA and the non-active area NAA in the branch portions BP. Since the first and second connection lines CNL1 and CNL2 are disposed in the same layer as the connection portion CP, the first and second connection lines CNL1 and CNL2 may be insulated from the branch portions BP.

[0168] The first sensor SP1 disposed on the upper side of the hole area HA and the first sensor SP1 disposed on the lower side of the hole area HA may be connected by a bypass line ARL. The bypass line ARL may extend along the periphery of the hole HO and may be disposed in the same layer as the first sensor SP1. The bypass line ARL may be disposed further outward than the crack detection pattern CDP.

[0169] The first sensor SP1 disposed on the upper side of the hole area HA and the first sensor SP1 disposed on the lower side of the hole area HA can be connected to the bypass line ARL through a connection portion CP (which is disposed so that the extension line EXL and the second connection line CNL2 are interposed therebetween). For example, the bypass line ARL can be connected to the connection portion CP through a contact hole (not shown) defined in the second insulating layer T_INS2. In an exemplary embodiment, the contact hole may penetrate the second insulating layer T_INS2 to expose a portion of the connection portion CP. However, this is described as an example, and the bypass line ARL may be disposed in the same layer as the connection portion CP and may extend from the connection portion CP.

[0170] Figure 12 It is shown as an example from Figure 9 The hole area and crack detection pattern shown in Figure 9 The cross-sectional configuration of the first connection pattern is shown in FIG.

[0171] Reference Figure 12 , the groove GV may be defined between the hole HO and the boundary of the hole area HA. ​​The groove GV may be provided in plurality. For example, the groove GV may include a first groove GV1, a second groove GV2, and a third groove GV3. The first groove GV1, the second groove GV2, and the third groove GV3 may have a shape of a closed line surrounding the hole HO. However, embodiments of the present inventive concept are not limited thereto, and the first groove GV1, the second groove GV2, and the third groove GV3 may also have a shape of a dotted line surrounding some portion of the edge of the hole HO.

[0172] Each of the first, second, and third grooves GV1, GV2, and GV3 may be recessed downward by a predetermined depth from the top surface of the substrate SUB. Each of the first, second, and third grooves GV1, GV2, and GV3 may be formed by removing a portion of the substrate SUB. The first groove GV1 may be adjacent to the boundary between the hole area HA and the display area DA. The third groove GV3 may be adjacent to the hole HO. The second groove GV2 may be disposed between the first and third grooves GV1 and GV3.

[0173] The deposition pattern ELP may be disposed in the first groove GV1, the second groove GV2, and the third groove GV3. The deposition pattern ELP may be aligned with the light emitting layer EML and the second electrode E2 (see FIG. Figure 7 ) include the same material and may be formed together when forming the light emitting layer EML and the second electrode E2. In an exemplary embodiment, the deposition pattern ELP may include a patterned light emitting layer and a patterned second electrode stacked on each other. The deposition pattern ELP may be covered by the first encapsulation layer EN1.

[0174] Because the deposition pattern ELP is disposed in the first, second, and third grooves GV1, GV2, and GV3 in an embodiment of the present inventive concept, the deposition pattern ELP may not be disposed continuously with the light-emitting layer EML. The continuity between the deposition pattern ELP and the light-emitting layer EML may be interrupted by the first, second, and third grooves GV1, GV2, and GV3. In an exemplary embodiment, the deposition pattern ELP may not be disposed continuously but may be disposed spaced apart from each other.

[0175] In order to form the hole HO, a portion of the display panel DP in the hole area HA may be cut away During the cutting process, external moisture or oxygen may be introduced into the display panel DP through the cut surface of the hole HO.

[0176] The deposition pattern ELP may be formed to extend from the light emitting layer EML, and the deposition pattern ELP may be continuously provided until the hole HO. In this case, external moisture or oxygen introduced through the hole HO may penetrate into the active area AA through the deposition pattern ELP. Elements provided in the active area AA may be damaged by the moisture or oxygen penetrating into the active area AA.

[0177] However, in an embodiment of the present inventive concept, the deposition pattern ELP is spaced apart from the light-emitting layer EML of the display element layer DP-OLED, and the deposition patterns ELP are arranged to be spaced apart from each other, thereby blocking external moisture or oxygen introduced through the hole HO. As a result, damage to the elements provided in the active area AA can be prevented.

[0178] Although three grooves GV (ie, first, second, and third grooves GV1, GV2, and GV3) are illustrated by way of example, embodiments of the present inventive concept are not limited thereto, and a single groove may be provided around the hole HO, or the groove may be omitted.

[0179] A plurality of dams DAM1 and DAM2 may be disposed on the substrate SUB between the first groove GV1, the second groove GV2, and the third groove GV3. The dams DAM1 and DAM2 may include a first dam DAM1 disposed between the first groove GV1 and the second groove GV2 on the substrate SUB, and a second dam DAM2 disposed between the second groove GV2 and the third groove GV3 on the substrate SUB. A deposition pattern ELP may be further disposed on the first dam DAM1 and the second dam DAM2.

[0180] The first dam portion DAM1 may be formed of a barrier layer BR, a buffer layer BF, first to fourth insulating layers IL1 to IL4, and a pixel defining layer PDL. The second dam portion DAM2 may be formed of a barrier layer BR, a buffer layer BF, and first to third insulating layers IL1 to IL3. However, this is shown as an example, and the first dam portion DAM1 and the second dam portion DAM2 may also have a single-layer structure.

[0181] The barrier layer BR may be disposed on the substrate SUB between the hole HO and the third groove GV3. The buffer layer BF may be disposed on the barrier layer BR between the hole HO and the third groove GV3. The deposition pattern ELP may be further disposed on the buffer layer BF between the hole HO and the third groove GV3.

[0182] The width of each of the first dam portion DAM1 and the second dam portion DAM2 may be gradually reduced toward the upper portion thereof. Figure 12 In the figure, the width is measured relative to the horizontal direction. The widths of the barrier layer BR and buffer layer BF of the first dam portion DAM1 and the widths of the barrier layer BR and buffer layer BF of the second dam portion DAM2 can each be greater than the width of the portion of the substrate SUB between the first groove GV1, the second groove GV2, and the third groove GV3. This is because the etching amount of the substrate SUB and the etching amount of the barrier layer BR and buffer layer BF differ during the etching process due to the difference between the materials of the substrate SUB and the barrier layer BR and buffer layer BF.

[0183] In the cross-sectional structure, the widths of the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 disposed in each of the first dam portion DAM1 and the second dam portion DAM2 may be smaller than the widths of the barrier layer BR and the buffer layer BF disposed in each of the first dam portion DAM1 and the second dam portion DAM2. Furthermore, the width of the fourth insulating layer IL4 disposed in the first dam portion DAM1 may be smaller than the widths of the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3 disposed in each of the first dam portion DAM1 and the second dam portion DAM2. Furthermore, the width of the pixel defining layer PDL disposed in the first dam portion DAM1 may be smaller than the width of the fourth insulating layer IL4 disposed in the first dam portion DAM1. The deposition pattern ELP may further be disposed on a portion of the buffer layer BF that does not overlap with the first insulating layer IL1, the second insulating layer IL2, and the third insulating layer IL3. In example embodiments, the deposition pattern ELP may be disposed in the first to third grooves GV1 to GV3, on the first and second dams DAM1 and DAM2, and on portions of the buffer layer BF that do not overlap with the first, second, and third insulating layers IL1, IL2, and IL3.

[0184] The wiring pattern LN may be provided on the second insulating layer IL2 and the third insulating layer IL3. Figure 5 The data line DL shown in FIG or the power line supplied by the transistor TR.

[0185] The first encapsulation layer EN1 and the third encapsulation layer EN3 may extend to the hole area HA. ​​The first dam portion DAM1 and the second dam portion DAM2 may define an area in which the second encapsulation layer EN2 including an organic material is formed. For example, the second encapsulation layer EN2 may extend to the hole area HA and may be provided up to the first dam portion DAM1.

[0186] The first encapsulation layer EN1 may be disposed on the substrate SUB and the first and second dams DAM1 and DAM2 in the hole area HA. ​​As described above, the first encapsulation layer EN1 may be disposed on the substrate SUB in the hole area HA to cover the deposition pattern ELP. The third encapsulation layer EN3 may be disposed on the first encapsulation layer EN1 in the hole area HA.

[0187] When manufacturing the display device DD, the fluid organic material may be cured to form the second encapsulation layer EN2. Even when the fluid organic material flows into the hole area HA, the first dam DAM1 may block the organic material. The second dam DAM2 may also block the organic material from overflowing the first dam DAM1.

[0188] The sensing electrodes SE1 and SE2 may be provided in the display area DA. An insulating layer INS (i.e., a first insulating layer) may be provided in the display panel DP in the aperture area HA. ​​The insulating layer INS may be provided on the third encapsulation layer EN3 in the aperture area HA. ​​An edge of the insulating layer INS provided at the boundary between the display area DA and the aperture area HA may have a stepped structure having at least two steps.

[0189] The crack detection pattern CDP may be provided in the hole area HA. ​​The crack detection pattern CDP may be provided on the insulating layer INS in the hole area HA. ​​When viewed in a plane, by way of example, a crack detection pattern CDP having an open curved shape (e.g., an open circle) may overlap with the second groove GV2, but embodiments of the present invention are not limited thereto. For example, when viewed in a plane, the crack detection pattern CDP may overlap with the first groove GV1 or may overlap with the third groove GV3. When viewed in a plane, optionally, the crack detection pattern CDP may be provided between the first groove GV1 and the second groove GV2, or between the second groove GV2 and the third groove GV3, and thereby may not overlap with the first groove GV1, the second groove GV2, and the third groove GV3.

[0190] The first insulating layer T_INS1 disposed on the thin film encapsulation layer TFE in the display area DA may extend across the insulating layer INS disposed in the hole area HA. ​​The second insulating layer T_INS2 may extend to the hole area HA to be disposed on the first insulating layer T_INS1 in the hole area HA. ​​The third insulating layer T_INS3 may extend to the hole area HA to be disposed on the second insulating layer T_INS2 in the hole area HA.

[0191] The crack detection pattern CDP, the extension line EXL extending from the crack detection pattern CDP, and the first connection pattern CT1 may be disposed on the second insulating layer T_INS2. The first connection line CNL1 may be disposed on the first insulating layer T_INS1. The second insulating layer T_INS2 may be disposed on the first connection line CNL1.

[0192] The extension line EXL and the first connection pattern CT1 may be connected to the first connection line CNL1 through a plurality of second contact holes T_CH2 defined in the second insulating layer T_INS2. In an exemplary embodiment, the second contact holes T_CH2 may penetrate the second insulating layer T_INS2 to expose a portion of the first connection line CNL1. The first connection line CNL1 may be insulated from the branch portions BP and the first sensor SP1 by the second insulating layer T_INS2.

[0193] A third insulating layer T_INS3 may be disposed on the second insulating layer T_INS2 to cover the crack detection patterns CDP, the extension lines EXL, and the first connection patterns CT1 .

[0194] Figure 13 It is shown as an example from Figure 9 The hole area and crack detection pattern shown in Figure 9 The cross-sectional configuration of the second connection pattern is shown in FIG. Figure 14 It is shown as an example from Figure 9 The hole area shown in the figure and one of the bypass lines to Figure 9 A cross-sectional configuration of a first sensor adjacent to the hole area is shown in FIG.

[0195] In the following, for Figure 13 and Figure 14 , will not be given with reference Figure 12 The elements described are the same as the description of the elements.

[0196] Reference Figure 13 The second connection patterns CT2 and the second connection lines CNL2 extending from the second connection patterns CT2 may be disposed on the first insulating layer T_INS1. The second insulating layer T_INS2 may be disposed on the second connection patterns CT2 and the second connection lines CNL2.

[0197] The crack detection pattern CDP may be connected to the second connection line CNL2 through a third contact hole T_CH3 defined in the second insulating layer T_INS2. In an exemplary embodiment, the third contact hole T_CH3 may penetrate the second insulating layer T_INS2 to expose a portion of the second connection line CNL2. The second connection line CNL2 may be insulated from the branch portion BP and the first sensor SP1 by the second insulating layer T_INS2.

[0198] Reference Figure 14 , the bypass line ARL may be provided on the second insulating layer T_INS2. The bypass line ARL and the first sensor SP1 may be connected to the connection portion CP corresponding to the bypass line ARL through a plurality of fourth contact holes T_CH4 defined in the second insulating layer T_INS2. In an exemplary embodiment, the fourth contact holes T_CH4 may penetrate the second insulating layer T_INS2 to expose a portion of the connection portion CP. A third insulating layer T_INS3 may be provided on the second insulating layer T_INS2 to cover the bypass line ARL.

[0199] Figure 15 Shown with Figure 9 The upper end of the hole area shown in FIG is adjacent to the grid structure of the connection pattern and the sensing electrode.

[0200] Reference Figure 15Each of the first and second sensors SP1 and SP2, the first and second dummy patterns DPT1 and DPT2, and the first and second connection patterns CT1 and CT2 may have a grid shape. For example, each of the first and second sensors SP1 and SP2, the first and second dummy patterns DPT1 and DPT2, and the first and second connection patterns CT1 and CT2 may include a plurality of first grid lines MSL1 extending in a first diagonal direction DDR1 and a plurality of second grid lines MSL2 extending in a second diagonal direction DDR2.

[0201] The first diagonal direction DDR1 may intersect the first and second directions DR1 and DR2 in a plane defined by the first and second directions DR1 and DR2. The second diagonal direction DDR2 may be substantially orthogonal to the first diagonal direction DDR1 in a plane defined by the first and second directions DR1 and DR2.

[0202] The first mesh line MSL1 and the second mesh line MSL2 may be formed integrally. The mesh opening MOP may be defined by the first mesh line MSL1 and the second mesh line MSL2 formed integrally. Figure 5 The pixel PX shown in FIG can be arranged to overlap the mesh opening MOP. The first and second mesh lines MSL1 and MSL2 can be disconnected and spaced apart from each other at the boundaries BAL1, BAL2, and BAL3 shown by the bold lines. Therefore, the first and second connection patterns CT1 and CT2 can be disconnected from and spaced apart from the first sensor SP1. As a result, the first and second connection patterns CT1 and CT2 can be insulated from the first sensor SP1.

[0203] The first connection line CNL1 and the second connection line CNL2 may extend along the first mesh lines MSL1 and the second mesh lines MSL2 in the active area AA. The first connection line CNL1 may be connected to at least one of the intersections of the first mesh lines MSL1 and the second mesh lines MSL2. The second connection line CNL2 may extend from some of the first mesh lines MSL1 and the second mesh lines MSL2 of the second connection pattern CT2.

[0204] The connection portion CP may extend along the first and second mesh lines MSL1 and MSL2 in the active area AA. The connection portion CP may be connected to at least one of the intersections of the first and second mesh lines MSL1 and MSL2. The dotted portion represents a portion of the connection portion CP connected to at least one of the intersections of the first and second mesh lines MSL1 and MSL2, and a portion of the first connection line CNL1 connected to the at least one intersection.

[0205] Each of the connection portions CP may extend in at least one line in the hole area HA. ​​Although each of the connection portions CP extends in two lines in the hole area HA by way of example, the number of extended lines may not be limited thereto.

[0206] Figure 16 yes Figure 9 An enlarged view of the first connection pattern, the first extension line and the first crack detection line shown in FIG. Figure 17 It is along Figure 16 A cross-sectional view taken along line IV-IV' shown in FIG. Figure 18 It is along Figure 16 A cross-sectional view taken along line VV' shown in FIG.

[0207] By way of example, the first connection pattern CT1 is Figure 16 It is shown in a grid shape and in Figure 17 and Figure 18 The components below the thin film encapsulation layer TFE are omitted.

[0208] Reference Figure 16 and Figure 17 The first extension line EXL1 extending from the first connection pattern CT1 may be disposed on the second insulating layer T_INS2 to extend to the non-active area NAA (or non-display area NDA). The first crack detection line CDL1 may be disposed on the second insulating layer T_INS2 and may extend from the first extension line EXL1. That is, the first connection pattern CT1, the first extension line EXL1, and the first crack detection line CDL1 may be integrally formed.

[0209] The third sensing line SNL3 and the second crack detection line CDL2 may be disposed on the first insulating layer T_INS1. The second insulating layer T_INS2 may be disposed on the first insulating layer T_INS1 to cover the third sensing line SNL3 and the second crack detection line CDL2.

[0210] The first extension line EXL1 may extend to intersect the third sensing line SNL3. The first extension line EXL1 may be insulated from the third sensing line SNL3 by the second insulating layer T_INS2. The third insulating layer T_INS3 may be disposed on the second insulating layer T_INS2 to cover the first extension line EXL1 and the first crack detection line CDL1.

[0211] Reference Figure 16 and Figure 18The guard ring line GDR may be disposed in the non-active area NAA (or non-display area NDA). The guard ring line GDR may be disposed between the first crack detection line CDL1 and the second crack detection line CDL2 and the active area AA (or display area DA). The guard ring line GDR may be disposed between the first crack detection line CDL1 and the second crack detection line CDL2 and the third sensing line SNL3.

[0212] The guard ring line GDR may be disposed on the first insulating layer T_INS1, and the second insulating layer T_INS2 may be disposed on the first insulating layer T_INS1 to cover the guard ring line GDR. The guard ring line GDR may be disposed in the same layer as the second connection pattern CT2. The guard ring line GDR may include a conductive material.

[0213] The guard ring line GDR may be used to prevent static electricity introduced from outside from being transmitted to the sensing electrodes SE1 and SE2 . The width of the guard ring line GDR may be greater than the width of each of the third sensing line SNL3 and the first and second crack detection lines CDL1 and CDL2 .

[0214] The guard ring line GDR may not overlap with the first extension line EXL1. When viewed in a plane, for example, the guard ring line GDR may not be disposed in a region where the guard ring line GDR intersects with the first extension line EXL1. The guard ring line GDR may be spaced apart from the first extension line EXL1.

[0215] When the guard ring line GDR is disposed below the first extension line EXL1 so as to overlap with the first extension line EXL1, the first extension line EXL1 and the guard ring line GDR may be short-circuited through the second insulating layer T_INS2 during the manufacturing process. In an embodiment of the present inventive concept, since the guard ring line GDR is spaced apart from the first extension line EXL1 and does not overlap with the first extension line EXL1, the short circuit between the first extension line EXL1 and the guard ring line GDR can be prevented during the manufacturing process.

[0216] Figure 19 yes Figure 9 An enlarged view of the second connection pattern, the second extension line, and the second crack detection line shown in FIG. Figure 20 It is along Figure 19 A cross-sectional view taken along line VI-VI' shown in FIG.

[0217] By way of example, the second connection pattern CT2 is Figure 19 It is shown in a grid shape and in Figure 20 The components below the thin film encapsulation layer TFE are omitted.

[0218] Reference Figure 19 and Figure 20, the second extension line EXL2 extending from the second connection pattern CT2 can be disposed on the first insulating layer T_INS1 to extend to the non-active area NAA (or non-display area NDA). The second crack detection line CDL2 can be disposed on the first insulating layer T_INS1 to extend from the second extension line EXL2. That is, the second connection pattern CT2, the second extension line EXL2, and the second crack detection line CDL2 can be formed integrally.

[0219] The second extension line EXL2 may extend to intersect the third sensing line SNL3. In the region where the third sensing line SNL3 overlaps the second extension line EXL2, the third sensing line SNL3 may be connected by a line connector LCN. The line connector LCN may be provided on the second insulating layer T_INS2.

[0220] Although contact holes defined in the second insulating layer T_INS2 are not shown, the wire connector LCN may be connected to the third sensing line SNL3 through the contact holes. A third insulating layer T_INS3 may be disposed on the second insulating layer T_INS2 to cover the wire connector LCN.

[0221] The guard ring line GDR may not overlap with the second extension line EXL2. When viewed in a plane, for example, the guard ring line GDR may not be disposed in a region where the guard ring line GDR and the second extension line EXL2 intersect. The guard ring line GDR may be spaced apart from the second extension line EXL2.

[0222] Figure 21 yes Figure 9 Magnified view of the well area shown in . Figure 22 It is along Figure 21 A cross-sectional view taken along line VII-VII' shown in FIG. Figure 23 It is along Figure 21 A cross-sectional view taken along line VIII-VIII' shown in FIG. Figure 24 It is along Figure 21 A cross-sectional view taken along line IX-IX' shown in FIG.

[0223] By way of example, in Figures 22 to 24 The components below the thin film encapsulation layer TFE are omitted.

[0224] Reference Figure 21 and Figure 22 A capping layer CPL may be provided at a boundary between the active area AA (or display area DA) and the hole area HA. ​​The capping layer CPL may be spaced apart from the crack detection pattern CDP and may be provided on the insulating layer INS to cover an edge of the insulating layer INS having a stepped structure with at least two steps. The capping layer CPL may include a conductive material.

[0225] The capping layer CPL may be disposed on a portion of the insulating layer INS adjacent to a boundary of the hole area HA and a portion of the thin film encapsulation layer TFE adjacent to a boundary of the hole area HA. ​​The capping layer CPL may be disposed further outward than the bypass line ARL.

[0226] Reference Figure 21 、 Figure 22 and Figure 23 , the capping layer CPL may be provided on the first insulating layer T_INS1. The capping layer CPL may be provided in the same layer as the second connection line CNL2. That is, the capping layer CPL may be provided in the same layer as the second connection pattern CT2. Although the connection portion CP is not shown, the capping layer CPL and the connection portion CP may be provided in the same layer. The second insulating layer T_INS2 may be provided on the first insulating layer T_INS1 to cover the capping layer CPL. The extension line EXL may be provided on the capping layer CPL.

[0227] Reference Figure 21 and Figure 23 , the capping layer CPL may not overlap with the second connection line CNL2 and may be provided in the same layer as the second connection line CNL2. The capping layer CPL may be spaced apart from the second connection line CNL2 by a gap GAP greater than zero and less than about 15 micrometers. Similarly, the capping layer CPL may not overlap with the connection portion CP passing through the boundary of the hole area HA. ​​The capping layer CPL may be spaced apart from the connection portion CP by a gap GAP greater than zero and less than about 15 micrometers.

[0228] Reference Figure 24 , the second connection line CNL2 may extend across an edge of the insulating layer INS formed in a stepped structure having at least two steps.

[0229] Figures 25 to 30 is used to describe the manufacturing Figure 21 A view of the capping layer and the second connecting line method shown in FIG.

[0230] By way of example, Figure 25 and Figure 28 Shown with Figure 22 The cross section corresponding to the diagram of Figure 26 and Figure 29 Shown with Figure 23 In addition, Figure 27 and Figure 30 Shown with Figure 24 The cross section corresponding to the diagram.

[0231] Reference Figure 25 、 Figure 26 and Figure 27, a first conductive layer CON1 may be disposed on the first insulating layer T_INS1. The first conductive layer CON1 may be disposed on the first insulating layer T_INS1 to form a capping layer CPL and a second connection line CNL2. Although not shown, a connection portion CP may be formed of the first conductive layer CON1.

[0232] A photoresist PR may be provided on the first conductive layer CON1. ​​The photoresist PR may be provided on a region of the first conductive layer CON1 where the capping layer CPL will be formed and a region of the first conductive layer CON1 where the second connection line CNL2 will be formed. Although not shown, the photoresist PR may be provided on a region of the first conductive layer CON1 where the connection portion CP will be formed.

[0233] The photoresist PR may be used as a mask. A portion of the plasma PLM used in the dry etching process may be provided to a portion of the first conductive layer CON1 not covered by the photoresist PR. Another portion of the plasma PLM provided toward the portion of the first conductive layer CON1 covered by the photoresist PR may be blocked by the photoresist PR.

[0234] Reference Figure 28 、 Figure 29 and Figure 30 , portions of the first conductive layer CON1 not covered by the photoresist PR may be removed by a dry etching process. The photoresist PR may be removed after the etching process. Thus, a capping layer CPL and a second connection line CNL2 may be formed on the first insulating layer T_INS1. Although not shown, a connection portion CP may be formed on the first insulating layer T_INS1 by patterning the first conductive layer CON1.

[0235] Thereafter, a second insulating layer T_INS2 and a third insulating layer T_INS3 may be sequentially stacked on the capping layer CPL and the second connection line CNL2 .

[0236] Figures 31 to 35 A method of manufacturing a display device is shown as a comparative method of the present inventive concept.

[0237] By way of example, Figure 31 and Figure 32 Shown with Figure 24 The cross section corresponding to the diagram of Figures 33 to 35 Shown with Figure 22 In the following description, when necessary, it will be used together with Figures 21 to 30 Describe some of them together Figures 31 to 35 .

[0238] Figure 31 and Figure 32 is with Figure 21IX-IX' corresponds to a cross-sectional view and is a view for describing a method of manufacturing the second connection line CNL2. Figures 33 to 35 When the capping layer CPL is not formed Figure 21 The cross-sectional view corresponding to the line VII-VII'.

[0239] Reference Figure 31 and Figure 32 , the edge of the insulating layer INS' may have a single step structure. The height of the top surface of the insulating layer INS' may be Figure 24 The heights of the top surfaces of the insulating layers INS shown in FIG. 5 are the same.

[0240] A first conductive layer CON1 for forming the second connection line CNL2 may be disposed on the first insulating layer T_INS1. A photoresist PR may be disposed on the first conductive layer CON1. ​​The photoresist PR may be disposed on a region of the first conductive layer CON1 where the second connection line CNL2 will be formed.

[0241] The photoresist PR having fluidity may be disposed thinner at the edge of the upper end of the insulating layer INS' than on the periphery of the edge. The larger the step of the edge of the insulating layer INS' is, the thinner the portion of the photoresist PR disposed at the edge of the upper end of the insulating layer INS' may be.

[0242] During the dry etching process, the photoresist PR may be damaged by the plasma PLM. If the photoresist PR is thick enough, the first conductive layer CON1 may not be exposed even when the photoresist PR is damaged. However, if the photoresist PR is thin, the photoresist PR may be damaged by the plasma PLM, and the first conductive layer CON1 may be exposed.

[0243] Therefore, a portion of the first conductive layer CON1 may be removed undesirably. For example, a portion of the photoresist PR disposed on the edge of the upper end of the insulating layer INS' is damaged, and thus a portion of the first conductive layer CON1 disposed on the edge of the upper end of the insulating layer INS' may be removed. In this case, as Figure 32 As shown in FIG, the second connection line CNL2 formed on the insulating layer INS' may be broken on the edge of the upper end of the insulating layer INS'. That is, the crack detection portion CDT may be damaged during the manufacturing process.

[0244] Although the second connection line CNL2 has been described by way of example, the above-described problem may also occur in the connection portion CP and the extension line EXL extending through a single step of the insulating layer INS′.

[0245] The photoresist PR has the following characteristics on the insulating layer INS: Figure 27The thickness of the edge of the step structure having at least two steps shown in FIG may be greater than the thickness of the photoresist PR on the insulating layer INS′ having at least two steps as shown in FIG. Figure 31 The thickness on the edge of the step structure with a single step shown in FIG. Figure 27 The photoresist PR shown in FIG. 4 may have a thickness sufficient to protect the first conductive layer CON1 from the plasma PLM.

[0246] Therefore, if Figure 30 As shown in FIG, the second connection line CNL2 formed of the first conductive layer CON1 may not be broken on the edge of the upper end of the insulating layer INS. In other words, damage to the crack detection portion CDT can be prevented.

[0247] Reference Figure 22 and Figure 25 , since the photoresist PR is provided on the region of the first conductive layer CON1 where the capping layer CPL is formed, the first conductive layer CON1 where the capping layer CPL is formed can be protected. Figure 25 In the embodiment, when the capping layer CPL is not formed, the photoresist PR may not be used.

[0248] Reference Figure 33 When the capping layer CPL is not formed on the first insulating layer T_INS1, the first conductive layer CON1 may be exposed because the photoresist PR is not used. The first conductive layer CON1 may be removed by plasma PLM during the manufacturing process.

[0249] When the edge of the insulating layer INS' has a single step, the first insulating layer T_INS1 and the first conductive layer CON1 may have a smaller thickness at the lower end of the edge of the insulating layer INS' than on the periphery of the edge of the insulating layer INS'. For example, during the deposition process for forming the first insulating layer T_INS1 and the first conductive layer CON1, the deposited material may not be sufficient to provide to the lower end of the edge of the insulating layer INS'.

[0250] Reference Figure 33 and Figure 34 , a portion of the lower end of the first insulating layer T_INS1 disposed to the edge of the insulating layer INS' and a portion of the lower end of the first conductive layer CON1 disposed to the edge of the insulating layer INS' may be damaged by the plasma PLM provided in various directions. Figure 34 As shown in FIG, the lower end of the edge of the insulating layer INS' may be exposed. During the cleaning process, a cleaning liquid CLN may be supplied to the lower end of the edge of the insulating layer INS'.

[0251] Reference Figure 35During the cleaning process, the lower end of the edge of the insulating layer INS' may be peeled off by the cleaning liquid CLN supplied to the lower end of the edge of the insulating layer INS'. As a result, a defective display device may be manufactured.

[0252] Reference Figure 25 , a photoresist PR may be provided on a portion of the first conductive layer CON1 from which the capping layer CPL is formed. A portion of the first insulating layer T_INS1 disposed at a lower end of the edge of the insulating layer INS and a portion of the first conductive layer CON1 disposed at a lower end of the edge of the insulating layer INS may be protected by the photoresist PR and thus may not be damaged by the plasma PLM during the manufacturing process.

[0253] Reference Figure 28 Since the capping layer CPL is formed on the insulating layer INS to cover the edge of the insulating layer INS, the cleaning liquid CLN may be blocked by the capping layer CPL during the cleaning process. Therefore, the lower end of the edge of the insulating layer INS may not be peeled off.

[0254] According to embodiments of the inventive concept, defects in the display device DD may be reduced, and the reliability of the display device DD may be improved.

[0255] According to an embodiment of the inventive concept, by providing a crack detection portion in a display device, it may be easily detected whether the display device has a crack.

[0256] Furthermore, the edge of the insulating layer in which the crack detection portion is provided is formed in a stepped structure having at least two steps, and thereby damage to the crack detection portion can be prevented.

[0257] Furthermore, since the capping layer is provided to cover the edge of the insulating layer provided in the hole region, peeling of the edge of the insulating layer can be prevented.

[0258] Although exemplary embodiments of the present invention have been described herein, it should be understood that those skilled in the art can make various changes and modifications within the spirit and scope of the present invention as defined by the appended claims or their equivalents. The exemplary embodiments described herein are not intended to limit the technical spirit and scope of the present invention, and all technical spirits within the scope of the appended claims or their equivalents will be interpreted as being included within the scope of the present invention.

Claims

1. A display device comprising: a display panel comprising a hole area, a display area around the hole area, and a non-display area around the display area; a first insulating layer disposed in the hole region; A plurality of sensing electrodes are arranged on the display area; a crack detection pattern provided on the first-first insulating layer in the hole region; a crack detection line, arranged on the non-display area; as well as a connection pattern provided in a first sensing electrode among the plurality of sensing electrodes provided on the display area to be insulated from the plurality of sensing electrodes and connected to the crack detection pattern and the crack detection line, wherein the first sensing electrode is provided between the hole area and the non-display area; The edge of the first-first insulating layer disposed at the boundary between the display area and the hole area has a stepped structure with at least two steps.

2. The display device according to claim 1, in, The crack detection pattern includes a first end and a second end and surrounds a hole defined in the hole region, and The hole penetrates the first-first insulating layer.

3. The display device according to claim 2, in, The connection pattern includes: a first connection pattern provided in the same layer as the crack detection pattern and connected to the first end of the crack detection pattern; and a second connection pattern provided in a layer different from that of the crack detection pattern and connected to the second end of the crack detection pattern, and Wherein, the crack detection line includes: a first crack detection line connected to the first connection pattern; and A second crack detection line is connected to the second connection pattern.

4. The display device according to claim 3, further comprising: A capping layer is spaced apart from the crack detection pattern and disposed on the first-first insulating layer to cover the edge of the first-first insulating layer.

5. The display device according to claim 4, in, The capping layer includes a conductive material.

6. The display device according to claim 4, in, The capping layer and the second connection pattern are provided in the same layer.

7. The display device according to claim 4, further comprising: an extension line extending from the first end of the crack detection pattern across the step structure of the hole region toward the first connection pattern; a first connection line provided in the same layer as the second connection pattern and configured to connect the first connection pattern and the extension line to each other; as well as A second connection line extends from the second connection pattern across the step structure of the hole area to the hole area and is connected to the second end of the crack detection pattern.

8. The display device according to claim 7, in, The capping layer is disposed in the same layer as the second connection line and is spaced apart from the second connection line.

9. The display device according to claim 8, in, The capping layer is spaced apart from the second connecting line by a gap greater than zero and less than 15 micrometers.

10. The display device according to claim 7, in, The plurality of sensing electrodes include: a plurality of first sensing electrode patterns spaced apart from each other in a first direction; a plurality of first dummy patterns disposed in a plurality of first openings defined in each of the plurality of first sensing electrode patterns; a plurality of connection portions disposed between the plurality of first sensing electrode patterns such that each of the plurality of connection portions connects two adjacent first sensing electrode patterns among the plurality of first sensing electrode patterns to each other; a plurality of second sensing electrode patterns spaced apart from each other in a second direction intersecting the first direction; and a plurality of branch portions formed integrally with the plurality of second sensing electrode patterns; wherein each of the plurality of branch portions connects two adjacent second sensing electrode patterns among the plurality of second sensing electrode patterns to each other, wherein the plurality of branch portions are insulated from the plurality of connection portions, and each of the plurality of branch portions extends to intersect with a corresponding one of the plurality of connection portions, and The first sensing electrode corresponds to a first sensing electrode pattern among the plurality of first sensing electrode patterns.

11. The display device according to claim 10, wherein the plurality of sensing electrodes further comprise: A plurality of second dummy patterns are disposed in a plurality of second openings defined in each of the plurality of second sensing electrode patterns.

12. The display device according to claim 10, in, The first connecting line and the second connecting line are insulated from a first branch portion among the plurality of branch portions, wherein the first branch portion of the plurality of branch portions is disposed between the hole area and the non-display area, and Each of the first connection line and the second connection line extends to intersect with the first branch portion of the plurality of branch portions.

13. The display device according to claim 10, in, The plurality of first sensing electrode patterns, the plurality of branch portions, and the plurality of second sensing electrode patterns are disposed in the same layer as the crack detection pattern, and The plurality of connection portions and the second connection pattern are provided in the same layer.

14. The display device according to claim 10, in, A first sub-opening and a second sub-opening are defined in the one first sensing electrode pattern among the plurality of first sensing electrode patterns, and the first sub-opening and the second sub-opening are open toward the non-display area, and The first connection pattern and the second connection pattern are respectively arranged in the first sub-opening and the second sub-opening.

15. The display device according to claim 10, further comprising: a first insulating layer, disposed on the display area to extend across the first-first insulating layer; as well as a second insulating layer, disposed on the first insulating layer; The crack detection pattern is disposed on the second insulating layer, the second connection pattern is disposed on the first insulating layer, and the second insulating layer is disposed on the first insulating layer to cover the second connection pattern.

16. The display device according to claim 3, further comprising: A guard ring line is provided between the first crack detection line, the second crack detection line and the display area, The guard ring line and the second connection pattern are arranged in the same layer.

17. The display device according to claim 16, further comprising: a first extension line extending from the first connection pattern to the first crack detection line and disposed on the non-display area; as well as a second extension line extending from the second connection pattern to the second crack detection line and disposed on the non-display area; The guard ring line does not overlap with the first extension line and the second extension line.

18. The display device according to claim 1, in, The crack detection pattern, the crack detection line, and the connection pattern include a conductive material.

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