Data storage device and data processing method

Abstract

The present invention relates to a memory controller, coupled to a memory device, for controlling access operations of the memory device, comprising a data protection engine and a microprocessor. The data protection engine is used to generate corresponding protection information according to data received from a host device. The microprocessor detects a state of the memory device in response to one or more write operations of writing data into the memory device, determines whether the data protection engine needs to exclude a part of the data when generating protection information according to the state, generates a decision result, and stores the protection information and the decision result together in the memory device, wherein the decision result indicates which parts of the data the protection information is generated according to.

Description

Technical Field

[0001] The present invention relates to a data processing method, and in particular to a data processing method which can effectively protect data stored in a memory device. Background Art

[0002] As the technology of data storage devices has grown rapidly in recent years, many data storage devices, such as memory cards, solid state drives, embedded Multi Media Cards (eMMC) and Universal Flash Storage (UFS) that comply with Secure Digital (SD) / Multi Media Card (MMC) specifications, Compact Flash (CF) specifications, Memory Stick (MS) specifications and Extreme Digital (XD) specifications, have been widely used in a variety of applications. Therefore, efficient access control has become an important issue for these data storage devices.

[0003] In order to improve the access performance of a data storage device and protect the data stored in the memory device, the present invention proposes a novel data processing method, which can effectively protect the data stored in the memory device and avoid reducing the access performance of the data storage device due to the implementation of an error protection mechanism. Summary of the invention

[0004] One purpose of the present invention is to effectively protect data stored in a memory device and to avoid reducing the access performance of the data storage device due to the implementation of an error protection mechanism.

[0005] According to one embodiment of the present invention, a memory controller is coupled to a memory device and used to control access operations of the memory device, including a data protection engine and a microprocessor. The data protection engine is used to generate corresponding protection information according to data received from a host device. The microprocessor detects a state of the memory device in response to one or more write operations of writing data to the memory device, determines whether the data protection engine needs to exclude a part of the data when generating protection information according to the state, generates a decision result, and stores the protection information and the decision result together in the memory device, wherein the decision result indicates which parts of the data the protection information is generated according to.

[0006] According to another embodiment of the present invention, a data processing method is performed by a memory controller coupled to a memory device, including: detecting a state of the memory device in response to one or more write operations of writing data received from a host device into the memory device; determining whether to exclude a portion of the data when generating protection information corresponding to the data based on the state, and generating a decision result; generating protection information corresponding to the data based on the decision result and the data; and storing the protection information and the decision result together in the memory device, wherein the decision result indicates based on which portions of the data the protection information is generated. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic diagram showing a data storage device 100 according to an embodiment of the present invention.

[0008] Figure 2 It is a flow chart showing a data processing method according to an embodiment of the present invention.

[0009] Figure 3 It is a schematic diagram showing the generation of protection information corresponding to a plurality of multi-plane data pages according to the first embodiment of the present invention.

[0010] Figure 4 Is displayed according to Figure 3 An example of a bit table created for protection information is shown.

[0011] Figure 5 It is a schematic diagram showing the generation of protection information corresponding to a plurality of multi-plane data pages according to the second embodiment of the present invention.

[0012] Figure 6 Is displayed according to Figure 5 An example of a bit table created for protection information is shown.

[0013] Explanation of symbols

[0014] 100: Data storage device

[0015] 110: memory controller

[0016] 112: Microprocessor

[0017] 112C: Program code

[0018] 112M: Read-only memory

[0019] 114: Memory interface

[0020] 116: Buffer memory

[0021] 115:Data Protection Engine

[0022] 118:Host Interface

[0023] 120: memory device

[0024] 130: Host device

[0025] 132: Encoder

[0026] 134:Decoder

[0027] 136: Voltage detection circuit

[0028] 310,510,520,530,540,550,LP_Parity,MP_Parity,P_S0~P_S383,Pj_S0~Pj_S7,S0_L,S0_M,S0_U,UP_Pairty: Protection Information

[0029] 410,610:Bit table

[0030] 710: Spare area

[0031] 720: Data area

[0032] Die[0], Die[1], Die[2], Die[n-1]: memory die

[0033] Lower_Page,Middle_Page,Page[0],Page[1],Page[2],Upper_Page: data page

[0034] META: Metadata

[0035] Plane[0],Plane[1]: plane

[0036] WL_0~WL_95: character line DETAILED DESCRIPTION

[0037] In the following, many specific details are described to provide a thorough understanding of the embodiments of the present invention. However, those skilled in the art will still understand how to implement the present invention in the absence of one or more specific details or relying on other methods, elements or materials. In other cases, well-known structures, materials or operations are not shown or described in detail to avoid obscuring the main concepts of the present invention.

[0038] References throughout this specification to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one of the multiple embodiments of the present invention. Thus, the phrases "in one embodiment," "in an embodiment," "in an example," or "in an example" appearing in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples.

[0039] In addition, in order to make the purpose, features and advantages of the present invention more clearly understood, the following specific embodiments of the present invention are specifically cited and described in detail with the accompanying drawings. The purpose is to illustrate the spirit of the present invention rather than to limit the scope of protection of the present invention. It should be understood that the following embodiments can be implemented via software, hardware, firmware, or any combination thereof.

[0040] Figure 11 is a schematic diagram showing a data storage device 100 according to an embodiment of the present invention. The data storage device 100 includes a memory device 120, such as a flash memory module, and a memory controller 110. The memory controller 110 is used to access the memory device 120. According to an embodiment of the present invention, the memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a memory interface 114, a data protection engine 115, a buffer memory 116, and a host interface 118. The read-only memory 112M is used to store a program code 112C. The program code 112C may include one or more program modules, such as a boot loader code. When the host device 130 supplies power to the data storage device 100, the microprocessor 112 may execute the program code 112C to perform an initialization operation to load a group of In-System Programming (ISP) codes (not shown) from the memory device 120. The microprocessor 112 may execute the group of ISP codes to enable the data storage device 100 to have various functions. According to the present embodiment, the group of ISP codes may include (but not limited to) a plurality of program modules related to access (e.g., reading, writing, and erasing), such as a read operation module, a table lookup module, a wear leveling module, a read refresh module, a read reclaim module, a garbage collection module, a sudden power off recovery (SPOR) module, and an uncorrectable error correction code (UECC) module for respectively performing reading, table lookup, wear leveling, read refresh, read reclaim, garbage collection, sudden power off recovery, and error handling for UECC errors. The memory interface 114 includes an encoder 132, a decoder 134, and a voltage detection circuit 136. The encoder 132 is used to encode the data written into the memory device 120 to generate a corresponding check code (or error correction code, ECC). The decoder 134 is used to decode the data read from the memory device 120. The voltage detection circuit 136 is used to detect a voltage level of the memory device 120, such as the power supply voltage level, and generate a corresponding detection result. The microprocessor 112 can determine whether the memory device 120 has a power supply voltage change (e.g., the power supply voltage is unstable), or an unexpected or sudden power off (SPO) occurs, etc. according to the detection result.The data protection engine 115 is used to generate corresponding protection information according to data received from a host device, and to recover damaged or lost data according to the protection information, wherein the protection information can be coded information generated according to the data to be protected, such as parity bit information. When a portion of the data protected by a given protection information is damaged or lost, the data protection engine 115 can perform a corresponding decoding operation according to the given protection information and the remaining portion of the data protected by the given protection information, thereby deriving the damaged or lost portion.

[0041] In a typical case, the memory device 120 includes a plurality of flash memory chips or dies, and each flash memory chip or dies includes a plurality of memory blocks, and the memory controller 110 performs an erase operation on the memory device 120 in units of blocks. In addition, a memory block may record (include) a specific number of data pages, i.e., physical data pages, and the memory controller 110 performs a write operation on the memory device 120 in units of data pages.

[0042] In practice, the memory controller 110 can use its own internal components to perform a variety of control operations, such as: using the memory interface 114 to control the access operation of the memory device 120 (especially the access operation to at least one block or at least one data page), using the buffer memory 116 to perform the required buffer processing, and using the host interface 118 to communicate with a host device (Host Device) 130. Among them, the host interface 118 can also be regarded as a front-end controller engine, which is used to transmit communication signals between the memory controller 110 and the host device 130, transmit write / read data, and control task scheduling, etc.

[0043] In one embodiment, the memory controller 110 communicates with the host device 130 via the host interface 118 using a standard communication protocol. For example, the above-mentioned standard communication protocols include (but are not limited to): Universal Serial Bus (USB) standard, Secure Digital (SD) interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, Compact flash (CF) interface standard, Multimedia Card (MMC) interface standard, Embedded Multimedia Card (eMMC) interface standard, Universal Flash Storage (UFS) interface standard, Advanced Technology Attachment (ATA) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PAT) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PAT) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PAT) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PAT) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PAT) standard, Attachment, abbreviated as PATA) standard.

[0044] In one embodiment, the buffer memory 116 is implemented as a random access memory (RAM). For example, the buffer memory 116 may be a static random access memory (SRAM), but the present invention is not limited thereto. In other embodiments, the buffer memory 116 may be a dynamic random access memory (DRAM).

[0045] In one embodiment, the data storage device 100 may be a portable memory device (e.g., a memory card that complies with SD / MMC, CF, MS, XD, or UFS standards), and the host device 130 may be an electronic device that can be connected to the data storage device, such as a mobile phone, a notebook computer, a desktop computer, etc. In another embodiment, the data storage device 100 may be a solid state drive or an embedded storage device that complies with UFS or eMMC specifications, and may be disposed in an electronic device, such as a mobile phone, a notebook computer, or a desktop computer, and the host device 130 may be a processor of the electronic device.

[0046] The host device 130 may issue commands, such as read commands or write commands, to the data storage device 100 to access data stored in the memory device 120 , or to further control and manage the data storage device 100 .

[0047] According to an embodiment of the present invention, the multiple memory blocks included in the memory device 120 may include a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, and / or a triple-level cell (TLC) memory block. Each memory cell of the SLC memory block stores one bit of data, each memory cell of the MLC memory block stores two bits of data, and each memory cell of the TLC memory block stores three bits of data. According to an embodiment of the present invention, the memory device 120 is a 3D NAND-type flash memory.

[0048] Generally speaking, in order to protect the memory device from losing valid data due to damage to the memory unit, the memory device can use the error protection mechanism adopted in the redundant array of independent disks (RAID) technology to protect the data. In the error protection mechanism adopted by RAID, the memory controller can calculate the protection information based on the data written to the memory device. When it is found that the valid data is lost, the protection information can be used to reversely deduce the content of the lost valid data.

[0049] However, in some cases, the data is damaged when it is written to the memory device. If the memory controller learns that part of the data that has been written is damaged, it is usually necessary to trigger a data migration procedure to reorganize the remaining undamaged data (i.e., the correct data) into a predetermined memory area, and then calculate protection information for the data in this predetermined memory area to protect the remaining undamaged data. However, since the protection information must be calculated before it can have a protective effect on the data, if a data error occurs during the data migration process, the erroneous data cannot be recovered because the data has not been protected during the migration process. Therefore, there is a risk of data errors during the data migration process. In addition, data migration and reorganization are also very time-consuming operations.

[0050] To solve the above problems, the present invention proposes a novel data processing method, which can effectively protect the data stored in the memory device and effectively avoid the access performance of the data storage device being reduced due to the implementation of the error protection mechanism.

[0051] According to one embodiment of the present invention, in addition to storing protection information, the memory controller 110 also stores relevant information indicating which parts of the data the protection information is generated based on in the memory space storing the protection information. In this way, when the memory controller 110 finds that a part of the data does not need or cannot be encrypted or protected, it can directly skip this part of the data and only perform encryption or protection operations on the remaining part of the data without having to perform data movement operations in order to collect a predetermined number of correct data. The relevant information on which parts of the data the protection information stored by the memory controller 110 is generated based on can be used when it is necessary to decode the data. For example, when the memory controller 110 finds that another part of the protected data has been lost or damaged, it can know which parts of the data the protection information is generated based on through the stored information, and correctly access the required data to perform data repair operations.

[0052] Figure 2 1 is a flow chart showing a data processing method according to an embodiment of the present invention. The data processing method of the present invention may be executed by the memory controller 110 or one or more components included in the memory controller, and includes the following steps:

[0053] Step S202: Detecting a state of the memory device 120 in response to one or more write operations of writing data received from the host device 130 into the memory device 120 or detecting a state of data written into the memory device 120 according to the one or more write operations.

[0054] Step S204: Determine whether to exclude a portion of the data when generating protection information corresponding to the data according to the state, and generate a decision result accordingly.

[0055] Step S206: Generate protection information corresponding to the data according to the determination result and the data. For example, the memory controller 110 (or the microprocessor 112) may instruct the data protection engine 115 which parts of the data should be used or which parts of the data should be excluded when generating the protection information corresponding to the data according to the determination result. The data protection engine 115 generates corresponding protection information according to the data that is not excluded according to the content indicated by the memory controller 110.

[0056] Step S208: Store the protection information and the determination result in a memory device.

[0057] Please note that these steps do not have to be followed if substantially the same results are achieved. Figure 2 1 and 120. The data protection engine 115 is configured to execute the data protection information of the super page according to the content of the super page, wherein the basic protection unit of the data protection engine 115 is a data page, and a super page includes a first number of data pages. When a super page temporarily stored in the buffer memory 116 is written into the memory device 120, the data protection engine 115 can generate protection information according to all data pages of the super page stored in the buffer memory 116 by default. That is, the data protection engine 115 can first generate protection information according to the data stored in the buffer memory 116. If the microprocessor 112 determines in step S204 that one or more data pages in this super data page need to be excluded, it can instruct the data protection engine 115 to perform a corresponding data exclusion operation to remove the relevant content of the one or more data pages from the protection information. This result is equivalent to the data protection engine 115 generating corresponding protection information based on other data pages in this super data page that do not include the one or more data pages. Alternatively, the microprocessor 112 instructs the data protection engine 115 to exclude the one or more data pages in this super data page and then regenerate the corresponding protection information, that is, the data protection engine 115 ultimately regenerates the corresponding protection information based on other data pages in this super data page that do not include the one or more data pages. Therefore, in the case where one or more data pages need to be excluded, the protection information of this super data page is actually generated based on data pages that are less than the first number.

[0058] In an embodiment of the present invention, the determination result may be used to indicate which parts of the data the protection information is generated based on (e.g., which data pages in a super data page). In addition, according to an embodiment of the present invention, in step S208, the memory controller 110 may represent the determination result in multiple bits. For example, the memory controller 110 may establish a bit map for the protection information based on the determination result to record which parts of the corresponding data the protection information is generated based on, and store the protection information and the bit map in the same memory space, such as a data page (e.g., a physical data page), wherein the size of a physical data page may be, for example but not limited to, 16K bytes, and a physical data page may include a data area and a spare area, and the memory controller 110 may store the protection information in the data area, and store the determination result or the bit map in the spare area as part of the metadata of this memory space.

[0059] When the memory controller 110 (or, the microprocessor 112) determines that a portion of the data stored in the memory device 120 is damaged or lost, the memory device 120 can be accessed to obtain the protection information and the decision result (or, the bit table) corresponding to the damaged or lost portion, and according to the decision result (or, the bit table), the data protection engine 115 is instructed to use which parts of the data to decode the corresponding protection information to deduce the damaged or lost portion.

[0060] As described above, in one embodiment of the present invention, the determination result can be represented by multiple bits, and one bit is used to indicate whether the data of a predetermined storage unit is excluded, wherein the predetermined storage unit can be set to be the same as the basic protection unit of the data protection engine 115, or the size of the predetermined storage unit can be larger than the basic protection unit of the data protection engine 115.

[0061] For example, assuming that the currently set basic protection unit is a data page, the size of the protection information generated by the data protection engine 115 may be the size of a data page. For example, the protection information may be a parity bit of a data page.

[0062] In one embodiment of the present invention, the size of the predetermined storage unit can also be set to the size of a data page, so one bit is used to indicate whether the data of a corresponding data page is excluded when generating the corresponding protection information. In this embodiment, when the data protection engine 115 generates protection information based on all data pages of a single-plane super data page, the determination result corresponding to the single-plane super data page can include the aforementioned first number of bits.

[0063] Alternatively, in another embodiment of the present invention, the size of the predetermined storage unit may be set to the size of a multi-plane data page, wherein a multi-plane data page may include, for example but not limited to, two data pages located in different planes. Therefore, in this embodiment, one bit is used to indicate whether the data of a corresponding multi-plane data page (for example, two data pages) is excluded when generating corresponding protection information. In this embodiment, when the data protection engine 115 generates protection information based on all data pages of a multi-plane super data page, the determination result corresponding to the multi-plane super data page may include the aforementioned first number of bits, and each bit may be compressed information, which is used to indicate whether the data of multiple data pages is excluded when generating corresponding protection information.

[0064] It is worth noting that in the embodiment of the present invention, the data protection engine 115 can flexibly generate corresponding protection information for data of different sizes, and the basic protection unit of the data protection engine 115 is not limited to a data page. For example, the data protection engine 115 can generate protection information corresponding to a single-plane or multi-plane super data page according to the content of the super data page, generate protection information corresponding to a memory block according to the content of the memory block, generate protection information corresponding to a super memory block according to the content of the super memory block (wherein a super memory block may include multiple memory blocks), or other. The basic protection unit of the data protection engine 115 can be a data page, a multi-plane data page, a super data page, a memory block, etc.

[0065] Figure 31 is a schematic diagram showing the generation of protection information corresponding to a plurality of multi-plane data pages according to the first embodiment of the present invention. In this embodiment, the memory device 120 may include a plurality of flash memory chips (or memory dies), and the data protection engine 115 may bind n of the memory dies together for encoding to generate corresponding protection information, such as the memory dies Die[0] to Die[n-1] shown in the figure, where n is a positive integer. Each memory die may include one or more planes, such as the planes Plane[0] and Plane[1] shown in the figure. Each plane may include a plurality of data pages, such as data pages Page[0], Page[1], Page[2], etc. In this embodiment, assuming that the memory device 120 is written using a triple-level cell (TLC) storage method, a physical data page may correspond to three logical data pages, such as the low, middle, and high data pages (logical data pages) shown in the figure: Lower_Page, Middle_Page, and Upper_Page. Among them, data pages Page[0], Page[3], Page[6], Page[9], etc. of each plane can be low data pages, data pages Page[1], Page[4], Page[7], Page

[10] , etc. can be medium data pages, data pages Page[2], Page[5], Page[8], Page

[11] , etc. can be high data pages, and so on.

[0066] At Figure 3 In the illustrated embodiment, the data protection engine 115 can classify n memory dies into a protection group, and generate corresponding protection information according to the data corresponding to each data page of each plane of the n memory dies. For example, assuming n=8, the data protection engine 115 can classify every 8 memory dies into a protection group, wherein one protection group includes Figure 3 The memory dies Die[0] to Die[7] are shown. The data pages of the memory dies Die[0] to Die[7] can form multiple super data pages, wherein one super data page includes a first number of data pages, for example, 8 data pages. It is worth noting that the super data page can be a single-plane super data page, or a multi-plane super data page. For example, the first data page Page[0] of the first plane Plane[0] of the memory dies Die[0] to Die[7] can constitute a single-plane super data page, the first data page Page[0] of the second plane Plane[1] of the memory dies Die[0] to Die[7] can constitute another single-plane super data page, or the first data page Page[0] of the two planes of the memory dies Die[0] to Die[7] can constitute a multi-plane super data page.

[0067] In an embodiment of the present invention, a set of low, medium, and high data pages may form a string. The data protection engine 115 may perform exclusive or (XOR) operations on the data corresponding to the low, medium, and high data pages of the memory die Die[0] to Die[7] to obtain a string of corresponding protection information, for example, Figure 3 The protection information 310 corresponding to the first string shown, wherein the protection information 310 may include protection information S0_L obtained by the data protection engine 115 performing an XOR operation on the data corresponding to the first data page Page[0] (low data page) of the memory die Die[0]~Die[7], protection information S0_M obtained by performing an XOR operation on the data corresponding to the second data page Page[1] (middle data page) of the memory die Die[0]~Die[7], and protection information S0_U obtained by performing an XOR operation on the data corresponding to the third data page Page[2] (high data page) of the memory die Die[0]~Die[7]. The protection information S0_L, S0_M, and S0_U of the first plane Plane[0] and the second plane Plane[1] are respectively used to protect the data corresponding to the low, middle, and high data pages included in the first string of the memory die Die[0]~Die[7] on the plane.

[0068] Figure 4 Is displayed according to Figure 3 In this embodiment, it is assumed that the memory controller 110 determines that all data can be used to generate the protection information corresponding to the first string (i.e., the data protection engine 115 does not need to exclude the first string when generating the protection information corresponding to the first string) based on the state of the memory device 120 when executing the write operation corresponding to the first string or the state of the first string of data written to the memory device 120. Figure 3 ), the memory controller 110 may set each bit included in the bit table 410 to a corresponding value (e.g., 1) to indicate that all data pages are protected by the protection information 310. Wherein, one byte of the bit table 410 corresponds to one super data page of one plane, and one bit of one byte may be used to indicate whether a data page included in the corresponding super data page is excluded. On the other hand, if the memory controller 110 determines that a data page needs to be excluded, the memory controller 110 may set the corresponding bit in the bit table 410 to another corresponding value (e.g., 0) to indicate that the data page is not protected by the protection information 310, and may further instruct the data protection engine 115 to exclude this data page when generating protection information corresponding to a super data page including this data page.

[0069] It is worth noting that, as described above, the protection information may also be compressed information. For example, in another embodiment of the present invention, the content recorded in each bit in the bit group corresponding to the first plane Plane[0] and the second plane Plane[1] in the bit table 410 may be compressed and represented by one bit to indicate whether the multi-plane super data page corresponding to the bit is protected by the protection information 310. That is, the bit table 410 may be compressed into one bit group.

[0070] In addition, in addition to being applied to a multi-plane architecture, the data processing method and error protection mechanism of the present invention can also be applied to a single-plane architecture. For example, in yet another embodiment of the present invention, each memory die may include a single plane, such as Figure 3 and Figure 4 The content shown can be simplified to include only data pages of one plane. The data protection engine 115 can classify n memory dies into a protection group, and generate protection information corresponding to each data page according to the data corresponding to each data page of the n memory dies.

[0071] Figure 5 is a schematic diagram showing the generation of protection information corresponding to a plurality of multi-plane data pages according to the second embodiment of the present invention. The second embodiment of the present invention may be an extension of the first embodiment. As described above, a set of low, medium, and high data pages may form a string. Data pages Page[0], Page[1], and Page[2] may form a first string S0, data pages Page[3], Page[4], and Page[5] may form a second string S1, data pages Page[6], Page[7], and Page[8] may form a third string S2, and so on.

[0072] In the second embodiment of the present invention, the data protection engine 115 may repeatedly execute the operations described in the first embodiment to obtain protection information corresponding to different strings.

[0073] like Figure 5 As shown, the protection information P_S0 is the protection information corresponding to the first string S0, which may further include the following Figure 3The protection information S0_L, S0_M and S0_U shown, the protection information P_S1 is the protection information corresponding to the second string S1, which may further include the protection information corresponding to the low, middle and high data pages of the second string, and so on. In addition, in the second embodiment of the present invention, a set of four strings may form a word line (abbreviated as WL), so the protection information 510 may include the protection information corresponding to the word lines WL_0 and WL_1, the protection information 520 may include the protection information corresponding to the word lines WL_2 and WL_3, the protection information 530 may include the protection information corresponding to the word lines WL_4 and WL_5, the protection information 540 may include the protection information corresponding to the word lines WL_94 and WL_95, and so on. In this embodiment, each memory chip may include 1152 data pages, which is equivalent to 384 strings, and also equivalent to 96 word lines.

[0074] In the second embodiment of the present invention, after obtaining the protection information P_S0-P_S383 corresponding to the 384 strings, the data protection engine 115 can further form a set of protection information corresponding to the two word lines, such as the protection information 510-540 shown in the figure, and perform exclusive OR (XOR) operations on each set to obtain protection information 550 corresponding to a super memory block, wherein the protection information 550 can include protection information Pj_S0-Pj_S7 of two planes, protection information Pj_S0-Pj_S7 of the first plane Plane[0] / the second plane Plane[1] j_S0 is the protection information obtained by the data protection engine 115 based on the protection information P_S0, P_S8, P_S16…P_S376 of the first plane Plane[0] / the second plane Plane[1] by performing an XOR operation. The protection information Pj_S1 of the first plane Plane[0] / the second plane Plane[1] is the protection information obtained by the data protection engine 115 based on the protection information P_S1, P_S9, P_S17…P_S377 of the first plane Plane[0] / the second plane Plane[1] by performing an XOR operation, and so on.

[0075] Figure 6 Is displayed according to Figure 5 An example of a bit table established by protection information is shown. One byte of the bit table 610 corresponds to one super data page of one plane, and one bit of a byte can be used to indicate whether a data page included in the corresponding super data page is excluded. Similarly, if the memory controller 110 determines that a data page needs to be excluded, the memory controller 110 can set the corresponding bit in the bit table 610 to a corresponding value (e.g., 0) to indicate that the data page is not protected by the protection information 550.

[0076] According to an embodiment of the present invention, the memory controller 110 may store the protection information and its corresponding bit table (determination result) together in a physical data page, wherein the protection information is stored in the data area and the bit table is stored in the spare area as part of the metadata (e.g., META in the figure) of the physical data page. Figure 6 As shown, the data area 720 stores the content of the protection information Pj_S2 on the first plane Plane[0], which is the protection information obtained by the data protection engine 115 performing an XOR operation based on the protection information P_S2, P_S10, P_S18…P_S378 of the first plane Plane[0], and may further include protection information LP_Parity, MP_Parity and UP_Pairty corresponding to the low, medium and high data pages. The bit table associated with each protection information is stored in the corresponding spare area. As shown in the figure, the spare area 710 is used to store the bit table corresponding to the protection information LP_Parity of the low data page of the first plane Plane[0] of the protection information Pj_S2, wherein the bit corresponding to the protection information LP_Parity of the low data page of the first plane Plane[0] of the protection information Pj_S2 is Figure 6 The content is highlighted with a box and points to the spare area 710 to indicate that the content is stored in the spare area 710 .

[0077] According to an embodiment of the present invention, the determination result or bit table may be temporarily stored in the buffer memory 116 during the encoding process of the data protection engine 115, and written into the memory device 120 after the protection information is generated. In addition, in an embodiment of the present invention, the data protection engine 115 may generate the final protection information according to a predetermined number of data pages and / or protection information by default. For example, in the first embodiment, the data protection engine 115 may generate the protection information according to a first number of data pages by default, for example, Figure 3 In the second embodiment, the data protection engine 115 can further generate the following information according to the set of the second amount of protection information: Figure 5 The protection information of the hyper memory block shown. Since the predetermined number is known, when a part of the data is damaged or lost, the data protection engine 115 can infer the storage location of the protection information corresponding to the data according to the information of the predetermined number (e.g., the first number, the second number, etc.), and access the metadata according to the location to obtain the bit table corresponding to the protection information. Then, the data protection engine 115 can perform corresponding decoding operations according to the obtained protection information and the content indicated by the bit table, thereby inferring the damaged or lost data.

[0078] In addition, in the embodiment of the present invention, the data exclusion operation may be a reverse operation of generating protection information. For example, when the data protection engine 115 generates protection information by performing an exclusive OR (XOR) operation, the data exclusion operation may be a reverse exclusive OR operation. It should be noted that the data protection engine 115 may also generate protection information by performing other operations. Therefore, the present invention is not limited to using an exclusive OR (XOR) operation to generate protection information.

[0079] In addition, in the embodiment of the present invention, since the memory controller 110 can determine whether one or more data pages need to be excluded according to a state of the memory device 120 or detect the state of the data written into the memory device 120, when the data protection engine 115 generates the protection information of the super data page according to the first number of data pages by default and one or more data pages need to be excluded, the protection information of the super data page is actually generated according to the data pages less than the first number.

[0080] Reference Figure 2 According to one embodiment of the present invention, in step S202 , in response to one or more write operations of writing data received from the host device 130 into the memory device 120 , the microprocessor 112 may detect a status of the memory device 120 .

[0081] For example, the microprocessor 112 may detect a status message sent back by the memory device 120 after executing a write operation to learn whether the write operation is successful or failed. When the status message indicates that the write operation of the first portion of the data fails, the microprocessor 112 may decide to instruct the data protection engine 115 to exclude the first portion when generating protection information, and set the corresponding information of the decision result or the corresponding bit in the bit table to a corresponding value (e.g., 0).

[0082] For another example, the voltage detection circuit 136 may send a message to notify the microprocessor 112 when detecting a power supply voltage change of the memory device (e.g., voltage drop, voltage instability, or power failure of the memory device, etc.), so that the microprocessor 112 can know the status of the memory device 120 in executing the write operation. When the status indicates that the power supply voltage of the memory device 120 changes during the execution of the write operation corresponding to the first part of the data, the unstable voltage may cause a write data error or the data cannot be written. The microprocessor 120 may decide to instruct the data protection engine 115 to exclude the first part when generating protection information, and set the corresponding information of the decision result or the corresponding bit in the bit table to a corresponding value (e.g., 0).

[0083] For another example, the microprocessor 120 may also determine the state of the memory device 120 in executing a write operation according to the state of the data storage device 100. If the data storage device 100 suddenly loses power during the process of the memory device 120 executing a write operation, the memory device 120 also experiences a sudden power failure. Since a sudden power failure may damage the data being written, when the state indicates that a sudden power failure occurs in the memory device 120 during the process of executing a write operation corresponding to the first portion of the data, the microprocessor 120 may decide to instruct the data protection engine 115 to exclude the first portion when generating protection information, and set the corresponding information of the decision result or the corresponding bit in the bit table to a corresponding value (e.g., 0).

[0084] According to another embodiment of the present invention, in step S202, in response to one or more write operations of writing data received from the host device 130 into the memory device 120, the microprocessor 112 may also detect the status of the data written into the memory device 120 according to the one or more write operations. For example, the microprocessor 112 may read the data written into the memory device 120 and attempt to decode the content thereof through the decoder 134 to learn whether a data error occurs (e.g., too many error bits cause the decoder 134 to be unable to correct the error content thereof). When the status of the data written into the memory device 120 indicates that an error has occurred in the first portion of the data or includes an uncorrectable error, the microprocessor 120 may decide to instruct the data protection engine 115 to exclude the first portion when generating protection information, and set the corresponding information of the decision result or the corresponding bit in the bit table to a corresponding value (e.g., 0).

[0085] In summary, the data processing method proposed by the present invention can effectively protect the data stored in the memory device, and can effectively avoid reducing the access performance of the data storage device due to the implementation of the error protection mechanism. In the embodiment of the present invention, in addition to storing the protection information, the memory controller 110 also stores relevant information that can indicate which parts of the data the protection information is generated based on in the memory space storing the protection information. In this way, when the memory controller 110 finds that a part of the data does not need or cannot be encrypted or protected, it can directly skip this part of the data and only perform encryption or protection operations on the remaining part of the data without performing data movement operations in order to collect a predetermined number of correct data. When the memory controller 110 finds that another part of the protected data has been lost or damaged, it can know which parts of the data the protection information is generated based on through the stored information, and correctly access the required data to perform data repair operations.

[0086] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should fall within the scope of the present invention.

Claims

1. A memory controller, coupled to a memory device, for controlling access operations of the memory device, comprising: a data protection engine for generating corresponding protection information according to data received from a host device; as well as A microprocessor detects a state of the memory device when executing one or more write operations to write the data to the memory device, determines whether the data protection engine needs to exclude a portion of the data when generating the protection information based on the state, generates a determination result, and stores the protection information and the determination result together in the memory device, wherein the determination result indicates which portions of the data the protection information is generated based on, wherein when the microprocessor determines that the data protection engine needs to exclude a first portion of the data when generating the protection information based on the state, the microprocessor further instructs the data protection engine to exclude the first portion of the data when generating the protection information, and wherein when the state indicates that the write operation corresponding to the first portion of the data fails, the power supply voltage of the memory device changes during the execution of the write operation corresponding to the first portion of the data, or the memory device suddenly loses power during the execution of the write operation corresponding to the first portion of the data, the microprocessor instructs the data protection engine to exclude the first portion when generating the protection information.

2. The memory controller according to claim 1, wherein: The protection information is stored in a data area of ​​a memory space, and the determination result is stored in a spare area of ​​the memory space as meta data of the memory space.

3. The memory controller according to claim 1, wherein: The determination result is represented by a plurality of bits, one bit being used to indicate whether the data of a predetermined storage unit is excluded, and the predetermined storage unit is the same as a basic protection unit of the protection information.

4. The memory controller according to claim 1, wherein: The determination result is represented by a plurality of bits, wherein one bit is used to indicate whether the data of a given storage unit needs to be excluded, and the given storage unit is larger than a basic protection unit of the protection information.

5. The memory controller according to claim 1, wherein: The data protection engine is further used to recover damaged or lost data. When the microprocessor determines that a second part of the data is damaged or lost, the microprocessor accesses the memory device to obtain the protection information and the decision result corresponding to the data, and instructs the data protection engine according to the decision result which parts of the data to use to recover the damaged or lost second part.

6. A data processing method, executed by a memory controller coupled to a memory device, comprising: detecting a state of the memory device in performing one or more write operations in response to one or more write operations to write data received from a host device to the memory device; Determine whether to exclude a portion of the data when generating protection information corresponding to the data according to the state, and generate a determination result; generating the protection information corresponding to the data according to the determination result and the data; as well as storing the protection information together with the determination result in the memory device, wherein the determination result indicates which parts of the data the protection information is generated based on, The step of generating the protection information corresponding to the data according to the determination result and the data further includes: When it is determined based on the state that a first portion of the data needs to be excluded when generating the protection information corresponding to the data, a data protection engine is instructed to exclude the first portion of the data when generating the protection information, and wherein when the state indicates that the write operation corresponding to the first portion of the data fails, the power supply voltage of the memory device changes during the execution of the write operation corresponding to the first portion of the data, or the memory device suddenly loses power during the execution of the write operation corresponding to the first portion of the data, it is determined that the first portion of the data needs to be excluded when generating the protection information corresponding to the data.

7. The data processing method according to claim 6, characterized in that: The protection information is stored in a data area of ​​a memory space, and the determination result is stored in a spare area of ​​the memory space as meta data of the memory space.

8. The data processing method according to claim 6, characterized in that: The determination result is represented by a plurality of bits, one bit being used to indicate whether the data of a predetermined storage unit is excluded, and the predetermined storage unit is the same as a basic protection unit of the protection information.

9. The data processing method according to claim 6, characterized in that: The determination result is represented by a plurality of bits, wherein one bit is used to indicate whether the data of a given storage unit needs to be excluded, and the given storage unit is larger than a basic protection unit of the protection information.

10. The data processing method according to claim 6, characterized in that: Also includes: When it is determined that a second part of the data is damaged or lost, accessing the memory device to obtain the protection information and the determination result corresponding to the data; as well as According to the determination result, a data protection engine is instructed to use which parts of the data to restore the damaged or lost second part.

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