50 results about "Universal flash storage" patented technology

The invention relates to a word generation method and device, electronic equipment, a non-transitory storage medium and a computer program product. The word generation method comprises the steps that a query vector Q of a previous generated word of a current word to be generated and keys K and values V of a plurality of generated words are read from a universal flash memory (UFS); based on the query vector Q and the key sum value of each generated word, calculating the importance value of the generated word; selecting a target generated word based on the importance value of each generated word; loading keys and values of the target generated word from the UFS into a memory; a word is generated using the key K and the value V of the target generated word loaded into the memory.

The embodiment of the invention provides a verification method, platform and equipment for a garbage collection strategy stored by a universal flash memory and a storage medium, and belongs to the technical field of memories. The method comprises the following steps: equally partitioning a target UFS according to a garbage collection basic unit to obtain a plurality of target storage regions; obtaining single writing data and taking the initial address of each target storage area as a target writing address; a UFS preprocessing step: according to each target writing address, synchronously writing single writing data into each target storage area, and reading a garbage collection strength state of a target UFS; when the garbage collection strength state characterizes that the maximum garbage collection strength is not reached, updating each target writing address according to the length of the single writing data, and skipping to the UFS preprocessing step; and when the garbage collection strength state characterizes that the maximum garbage collection strength is reached, performing a performance test on the target UFS. The verification efficiency and the reliability of the verification result can be considered at the same time.

A channel-associated information transfer method and apparatus, and a device are related to the field of storage technologies and provide a transfer mechanism applied to channel-associated information of data of a universal flash storage (UFS). The method includes a UFS device sending a first ready-to-transfer (RTT) frame to a host, where the first RTT frame indicates to transfer first target data. The first RTT frame includes channel-associated control information. The channel-associated control information is used to control transfer of first channel-associated information of the first target data. When the host receives the first RTT frame, the host sends a first data frame to the UFS device, where the first data frame includes the first target data and the first channel-associated information. The UFS device receives the first data frame.

The invention relates to the technical field of terminals, in particular to a memory management method, electronic equipment and a storage medium, the method comprises the steps that the memory management method is written in a kernel layer in a software code mode and is separated from kernel codes, and a kernel can call the software codes through a calling function to manage memory space; according to the method, the anonymous page corresponding to the application program is compressed to the block space, the compressed page corresponding to the application program is dumped to the universal flash memory and the like, so that the memory pressure can be reduced under the condition that kernel codes are not modified.

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to interact with a host device using a Universal Flash Storage (UFS) interface protocol, provide a hint to the host device, switch between a first mode and a second mode, retrieve data from the memory device, and transfer the data to the host device. The hint includes an indication of what order data is to be received from the data storage device. After the hint is provided, the order of the data will be a different order than a requested order.

Semiconductor packaging device are described herein. In one embodiment, the device includes a substrate configured to support at least two types of Multi-Chip Package (MCP) configurations. One MCP configuration includes a Universal Flash Storage (UFS) memory controller, and another MCP configuration includes an embedded multi-media card (eMMC) controller. The substrate is configured through internal connections and signal assignments to support either of the UFS controller or the eMMC controller selected to be included in the final MCP.

The utility model discloses a universal flash memory storage circuit and a universal flash memory, and relates to the technical field of embedded semiconductor storage. Comprising a first power supply network, a second power supply network, a third power supply network, a voltage reduction module, a main control unit and a flash memory unit, the main control unit is used for bridging an upper computer and the flash memory unit, and the main control unit is used for controlling and managing erasing, writing and reading operations of the flash memory unit; the flash memory unit is used for storing user data; the input end of the step-down module is connected to the first power supply network or / and the second power supply network, the output end of the step-down module is connected to the flash memory unit, the main control unit and the third power supply network, and the voltage of the output end of the step-down module is smaller than that of the input end of the step-down module; through the above design, compatible use of a plurality of UFS power supply networks is realized.

Methods executable by a universal flash storage (UFS) system of a computing device provide a write accelerator buffer portion flush procedure and a flush recovery / retry procedure in a flash storage device. A method for managing operations of a write accelerator buffer of a flash memory device includes notifying a host controller that a flush of the write accelerator buffer has terminated, sending context information to the host controller that describes one or more data structures that have been successfully flushed. The method can include receiving a partial unmap command from the host controller to unmap the one or more data structures that have been successfully flushed, and can include resuming the flush of the write accelerator buffer.

Systems and methods for improving security of a Universal Flash Storage (UFS) device during a purge operation. If a purge operation being performed in the UFS device is interrupted prematurely, due to issuance of one or more urgent commands, the UFS device notifies the host processor that the purge operation has been interrupted. After the host processor performs the urgent command(s), it causes the UFS device to resume performance of the purge operation and the host processor delays performance of any other commands that arrive at the command queue (CQ) of the host processor until the resumed purge operation has been completed. Because the purge operation is resumed and completed before the host processor performs any of the other command(s) that have arrived at the CQ, die-level attacks seeking to access unpurged data by sending read commands to the CQ of the host processor are thwarted.

Disclosed is an operation method of a universal flash storage (UFS) device which communicates with a UFS host through a device physical layer. The operation method includes monitoring an internal operation status, changing a power mode of the device physical layer to a low-speed mode, based on the internal operation status, transmitting a first power mode change request to the UFS host, receiving a first power mode change confirmation from the UFS host, and operating based on the low-speed mode with the UFS host through the device physical layer, in response to the first power mode change confirmation.

Systems and methods for fast memory access are disclosed. In one aspect, a processor, such as a control circuit in a system-on-chip (SoC) coupled to an external memory (such as a universal flash storage (UFS) memory (e.g., NAND flash memory), where a partial logical-to-physical (L2P) mapping table is stored in the external memory and a local L2P mapping table is stored in a local memory (e.g., dynamic random access memory (DRAM))). The control circuit can evaluate the percentage of active entries compared to non-active entries in the local L2P mapping table. If the number of non-active entries exceeds the number of active entries, the control circuit can send a read command without accessing the local L2P mapping table.

Rather than waiting on a squelch to detect the difference in the state from steady to floating, this disclosure suggests using the time from when a reference clock is turned on to begin the process to exit the hibernation state. The reference clock is turned off while a data storage device is in the hibernation state to save power. Once the host is ready for the device to exit the hibernation state, the reference clock is turned on. The reference clock is monitored for the change. Once the reference clock is on, the data storage device returns to a steady state. In the ready state, the data storage device has a shortened ready time. Once the ready time is complete, the data storage device may now exit the hibernation state without waiting on squelch detection or a hibernation exit request from the host.

In a flash memory device, portions of a write buffer may be merged into a user space logical unit based on a measurement of write buffer usage. In a Universal Flash Storage (UFS) device configured with the WriteBooster feature, the write buffer may be a WriteBooster buffer. When it is determined that a user space logical unit has become full, then the write buffer usage may be determined. Portions of the write buffer that are least used or have the longest remaining lifetime may be preferentially merged into the user space logical unit.

The embodiment of the invention provides a storage system, a host, an operation method and a data processing system. An operating method of a memory system includes transmitting a logical-to-physical (L2P) mapping table using a first operation mode or a second operation mode; wherein the first operation mode comprises the steps of sending first recommendation information; the first recommendation information comprises at least one L2P mapping table; the second mode of operation includes: in response to a host performance enhancer (HPB) read buffer command, transmitting a data input universal flash memory storage protocol information unit (UPIU); the data input UPIU comprises at least two L2P mapping tables.

A method of operation of a Universal Flash Storage (UFS) device that communicates with a UFS host over a device physical layer is disclosed. The operation method comprises the following steps: monitoring an internal operation state; changing a power mode of the device physical layer to a low speed mode based on the internal operating state; sending the first power mode change request to a UFS host; receiving a first power mode change confirmation from the UFS host; and operating the UFS host based on the low speed mode through the device physical layer in response to the first power mode change confirmation.

This application discloses a testing method, storage device, and medium for Universal Flash Memory (UFS). First, a main thread and a sub-thread are created in the UFS application layer, and a queue status mapping table corresponding to the slot queue in the UFS driver layer is configured. Then, the main thread asynchronously sends an operation request containing a structure carrying the target operation instruction to the driver layer according to the mapping table. Next, the sub-thread receives the response result returned by the driver layer. Subsequently, the time taken for the target operation instruction is determined based on the response result and the corresponding structure. Then, based on a preset time threshold and the time taken, the timeout result of the target operation instruction is obtained. This application manages the slots through a queue status mapping table and traces the entire lifecycle information of commands through structures. This enables full coverage of the number of tasks in the UFS command queue to verify asynchronous read / write functionality, effectively determine whether each asynchronous command has timed out, and reduce the difficulty of analyzing device firmware problems, thereby effectively solving existing testing deficiencies.

An operation method of a universal flash storage (UFS) host configured to control a UFS device includes configuring a turbo write buffer of the UFS device; sending a first query request UFS protocol information unit (UPIU) including reconfiguration information about the turbo write buffer to the UFS device, during driving the UFS device; and receiving a first response UPIU associated with the first query request UPIU from the UFS device, wherein, the first query request UPIU is a request that causes a size of the turbo write buffer of the UFS device to be changed from a first size to a second size different from the first size.

Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a universal flash storage (UFS) host controller may access a UFS transport protocol (UTP) transfer request that includes a hash pointer (HP) indicator indicating that an HP associated with the UTP transfer request is encoded at a data structure, wherein the HP indicates a memory location where one or more hash values associated with the UTP transfer request are stored. The UFS host controller may read the HP from the data structure. The UFS host controller may access the one or more hash values in the memory location indicated by the HP. Numerous other aspects are described.

In a multi-processor computing device having a Universal Flash Storage (UFS) host controller interface operating in Multi-Circular Queue (MCQ) mode, mappings between processors and completion queues (CQs) may be dynamically changed based on one or more conditions. A condition may be detected that may impair the performance of one of the processors in accessing a CQ. When such a condition is detected, the UFS host controller system may update a queue-to-processor mapping, which may include replacing an association between a CQ and a processor with an association between the CQ and another processor.

Various aspects of the present disclosure generally relate to universal flash storage (UFS) devices. In some aspects, a UFS controller may receive, from a UFS driver, a command associated with a storage transaction for an application that runs on a processor. The UFS controller may identify, from the command, a data transfer size associated with the command. The UFS controller may identify, from a register, a power management quality of service (PM-QoS) control data transfer size. The UFS controller may send, to the processor, a PM-QoS processor vote based at least in part on the data transfer size associated with the command in relation to the PM-QoS control data transfer size, wherein the PM-QoS processor vote prevents the processor from entering a low power state until the storage transaction is completed. Numerous other aspects are described.

An operation method of a universal flash storage (UFS) host configured to control a UFS device includes configuring a turbo write buffer of the UFS device; sending a first query request UFS protocol information unit (UPIU) including reconfiguration information about the turbo write buffer to the UFS device, during driving the UFS device; and receiving a first response UPIU associated with the first query request UPIU from the UFS device, wherein, the first query request UPIU is a request that causes a size of the turbo write buffer of the UFS device to be changed from a first size to a second size different from the first size.

Systems and methods are provided for enhancing Universal Flash storage (UFS) power mode transitions by autonomously entering the sleep or power down states upon the expiration of a timer, thereby eliminating the need to reactivate the link between the UFS host and the UFS device to send sleep or power down commands from the UFS host to the UFS device. Eliminating the need to frequently reactivate the link to transition it into sleep and power down states reduces power consumption associated with reactivating the link and keeping it in the active state while the sleep and power commands are transmitted by the UFS host and responded to by the UFS device. In addition, eliminating the need to frequently reactivate the link and keep it active for these purposes reduces latencies associated with issuing the sleep and power down commands.

A Universal Flash Storage (UFS) host controller supporting input / output virtualization (IOV) is disclosed. The host controller comprises a programmable Function ID (FID) to Stream ID (SID) mapping unit configured to assign unique stream IDs to physical and virtual UFS Host Controller Interface (UFSHCI) functions. The mapping unit includes registers accessible only within the physical UFSHCI's address space, allowing exclusive control by the host operating system. When a data transfer request is received, the host controller maps it to an assigned stream ID based on the programmable mapping. A UFS device coupled to the host controller validates received stream IDs before executing data transfer requests. This mechanism enables isolation of data streams between virtual functions, enhancing security in virtualized storage environments and accommodating evolving system requirements.

A universal flash storage (UFS) device controller is provided. The UFS device controller is configured to, based on an error identified through a UFS interface, identify that a state related to the UFS interface is changed from a first state in which data is transferred based on a first data processing speed to a second state in which data is transferred based on a second data processing speed different from the first data processing speed, wherein the UFS device controller is configured to, while the second state is maintained, after a designated time for identifying whether to process cache data stored in cache memory from a time point at which a change from the first state to the second state is identified, transmit the cache data stored in cache memory from the cache memory to non-volatile memory.

Various aspects of the present disclosure generally relate to universal flash storage (UFS) devices. In some aspects, a UFS controller may receive, from a UFS driver, a command associated with a storage transaction for an application that runs on a processor. The UFS controller may identify, from the command, a data transfer size associated with the command. The UFS controller may identify, from a register, a power management quality of service (PM-QoS) control data transfer size. The UFS controller may send, to the processor, a PM-QoS processor vote based at least in part on the data transfer size associated with the command in relation to the PM-QoS control data transfer size, wherein the PM-QoS processor vote prevents the processor from entering a low power state until the storage transaction is completed. Numerous other aspects are described.

The technical scheme of the present application provides a kind of method, system, electronic equipment and storage medium for verifying eMMC function, the method comprises: loading operating system in storage device, and mounting root file system in storage device, wherein the storage device is secure digital card or universal flash memory;Access eMMC device by calling eMMC character device driver, and the function of eMMC device is verified by executing eMMC protocol test case, wherein eMMC character device driver is located in the kernel layer of operating system, and eMMC protocol test case is located in the application layer of operating system.Using the technical scheme of the present application can prevent other processes except test process from accessing eMMC device, ensure the normal operation of system, increase the coverage of eMMC protocol test, and accurately locate the test problem.

Methods, systems, and devices for hardware reset management for universal flash storage (UFS) are described. A UFS device may initiate a boot-up procedure that includes multiple phases. The UFS device may perform a first reset operation to reset one or more circuits based on receiving a first reset command during a first phase. The UFS device perform a second phase and may initiate a portion of a second reset operation to reset the one or more circuits during the second phase based on a likelihood that a second reset command is to be received. The UFS device may receive the second reset command during the second phase after initiating the portion of the second reset operation. The UFS device may initiate a second portion of the second reset operation based on receiving the second reset command and initiating the portion of the second reset operation.

Universal flash storage (UFS) systems are provided. In one aspect, a UFS system includes a UFS host including a first UFS interconnect (UIC) layer and a first pin, and a UFS device including a second UIC layer configured to communicate with the first UIC layer and a second pin electrically connected to the first pin. The UFS host drives a voltage of the first pin based on first information indicating whether a high speed-link startup sequence (HS-LSS) is supported by the UFS host, and the UFS device drives a voltage of the second pin based on second information indicating whether the HS-LSS is supported by the UFS device.

The invention discloses an image processing method and device, and relates to the technical field of image processing. The method comprises the following steps: generating a preview RAW graph according to preset preview image parameters; splitting the preview RAW graph in a downsampling mode to obtain sub-graphs and original image data corresponding to each sub-graph, and storing the original image data based on a universal flash memory storage mode; analyzing the current performance index to determine the number of subgraphs which can be processed in parallel; and reading the original image data, and performing parallel processing and fusion on the sub-images according to the number of the sub-images which can be processed in parallel to obtain a preview image. Compared with the prior art, after the preview RAW graph is generated according to the preset preview image parameters, through the UFS data storage strategy based on the down-sampling mode, the memory and performance requirements are reduced, and meanwhile through the parallel processing strategy, the processing efficiency is improved. According to the invention, high resolution can be ensured under the condition of keeping the size of the preview image, so that the preview image is clearer.