Memory repair circuit and method

Abstract

The present invention relates to a memory repair method, which is to divide a plurality of normal bits into a plurality of first groups, and divide a plurality of redundant bits into a plurality of second groups. When any of the first groups has a bad bit, a second group is selected to replace the first group. Since the group is used as the repair unit, the repair circuit is simpler and has a smaller area, and the processing speed is also faster.

Description

Technical Field

[0001] The present invention relates to the field of memory, and in particular to a memory repair circuit and method, and in particular to a repair circuit and method based on bit groups. Background Art

[0002] The memory may produce bad bits due to various non-ideal factors in the manufacturing process. Therefore, when designing the memory, in addition to the original normal bits, some of the internal space is used to set up redundant bits. When the memory is tested and found to have bad bits in the normal bits, the redundant bits can be used to replace these bad bits to exert the repair efficiency and improve the manufacturing yield of the memory. The traditional way to repair the memory is to add redundant row (rowredundancy) or redundant column (columnredundancy) auxiliary circuits during the design, so that when the memory is found to have bad bits, the row or column containing the bad memory bit can be replaced.

[0003] However, the conventional method is to replace an entire row or column of bits, so in addition to replacing bad bits, good bits in a row or column will also be replaced, resulting in waste. In addition, as the memory size decreases and the memory capacity increases, the density of the memory bit array increases, so the number of bad memory bits also increases, and the space required to set up extra rows or columns also increases, resulting in a large amount of additional area required to configure enough extra rows or columns of memory bits for replacement. Therefore, the method of replacing an entire row or column of memory bits is no longer applicable to small-volume and large-capacity memories. Summary of the invention

[0004] The object of the present invention is to provide a repair circuit and method based on bit groups.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] According to the present invention, a memory repair method includes dividing a plurality of normal bits into a plurality of first groups and dividing the plurality of redundant bits into a plurality of second groups, and finally determining whether to select one of the second groups to replace the first group according to the repair data corresponding to the first group. The repair data may include relevant data of the second group to be selected. The first group and the second group both have t bits, and t is an integer greater than or equal to 2.

[0007] According to the present invention, a memory repair circuit includes a decoder and a selection circuit. The decoder decodes the corresponding first group of repair data to generate a selection signal. The selection circuit selects one of a plurality of second groups to replace the first group according to the selection signal. The repair data may include relevant data of the second group to be selected. The first group and the second group both have t bits, where t is an integer greater than or equal to 2.

[0008] According to the specific embodiment provided by the present invention, the present invention discloses the following technical effects: the repair method based on bit groups of the present invention can reduce the area of ​​the repair circuit and also speed up the processing speed of the repair circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0010] Figure 1 A circuit diagram of the bit-by-bit method of the present invention;

[0011] Figure 2 For the present invention Figure 1 A circuit diagram of an embodiment of a repair circuit;

[0012] Figure 3 For the present invention Figure 2 A circuit diagram of an embodiment of a decoder;

[0013] Figure 4 A circuit diagram of a first embodiment of a repair method based on bit groups according to the present invention;

[0014] Figure 5 A circuit diagram of a second embodiment of the repair method based on bit groups of the present invention;

[0015] Figure 6 A circuit diagram of a third embodiment of the repair method based on bit groups of the present invention;

[0016] Figure 7 For the present invention Figure 6 A circuit diagram of an embodiment of a repair circuit;

[0017] Figure 8 For the present invention Figure 7 Implementation circuit diagram of a decoder.

[0018] Explanation of symbols:

[0019] 10. memory; 11. register; 12. repair circuit; 14. redundant bit sorting circuit; 20. decoder; 21. selection circuit; 22. decoder; 23. selection circuit; 24. decoder; 25. selection circuit; 26. decoder; 27. selection circuit; 30. memory; 301. register; 302. first group; 304. first group; 306. first group; 308. first group; 310. second group; 312. second group; 314. second group; 3 16. repair circuit; 318. input and output terminal; 320. input and output terminal; 322. input and output terminal; 324. input and output terminal; 326. input and output terminal; 328. input and output terminal; 330. input and output terminal; 332. input and output terminal; 334. second group; 336. second group; 340. decoder; 342. decoder; 344. decoder; 346. decoder; 348. selection circuit; 350. selection circuit; 352. selection circuit; 354. selection circuit. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] The object of the present invention is to provide a repair circuit and method based on bit groups.

[0022] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] In order to improve the shortcomings of traditional methods, Figure 1 The circuit diagram of the bit-by-bit replacement method is shown in FIG. 1 . The memory 10 includes a register 11, a repair circuit 12, and a plurality of input and output terminals I / O1 to I / Om. The register 11 is connected to a plurality of memory bits G1 to Gm and R1 to Rn selected from a memory array (not shown). Figure 1Placing the memory bits G1-Gm and R1-Rn in the register 11 is only to express that these memory bits are connected to the register 11. In fact, the memory bits G1-Gm and R1-Rn are not inside the register 11. The register 11 is used to temporarily store the data DG1-DGm and DR1-DRn output by the memory bits G1-Gm and R1-Rn or to temporarily store the data to be written into the memory bits G1-Gm and R1-Rn. Since the selected memory bits G1-Gm and R1-Rn are on the same row, the register 11 is also called a row buffer. Memory bits G1-Gm are general bits, and memory bits R1-Rn are redundant bits. Data DG1 to data DGm are data stored in memory bits G1-Gm, and data DR1 to data DRn are data stored in memory bits R1-Rn. Memory bits G1-Gm and R1-Rn are selected simultaneously in the same internal access. Internal access means that the memory 10 selects the memory bits to be used from the memory array. For example, each internal access selects all memory bits on the same column. After selecting memory bits G1-Gm and R1-Rn through internal access and connecting them to the register 11, the repair circuit 12 selects memory bits to correspond to multiple input and output terminals I / O1-I / Om from the memory bits G1-Gm and R1-Rn. After detection, the memory 10 generates a plurality of repair data RPG1-RPGm and RPR1-RPRn, wherein the repair data RPG1-RPGm correspond to the general bits G1-Gm respectively, and the repair data RPR1-RPRn correspond to the redundant bits R1-Rn respectively. The plurality of repair data RPG1-RPGm and RPR1-RPRn are used to mark whether the corresponding memory bits are bad bits. The repair data RPG1-RPGm and RPR1-RPRn can be provided by the register 11 to the repair circuit 12, but are not limited to being provided by the register 11. Figure 1In the example, bit G2, bit Gm-1 and bit R1 are bad bits. When the repair circuit 12 is to correspond the memory bits to the input / output terminals I / O1 to I / Om, the repair circuit 12 determines that the first general bit G1 is a good memory bit according to the repair data RPG1, and thus couples the bit G1 to the first input / output terminal I / O1, so that the data DG1 of the bit G1 can be accessed from the input / output terminal I / O1. Then the repair circuit 12 knows from the repair data RPG2 that the second general memory bit G2 is a bad bit, so it discards the bit G2 and selects one from the redundant bits R1 to Rn to replace the bit G2. At this time, the repair circuit 12 can know from the repair data RPR1 and RPR2 that the first redundant bit R1 is a bad bit and the second redundant bit R2 is a good memory bit, so the repair circuit 12 will select the second redundant bit R2 to replace the bit G2 and couple it to the second input / output terminal I / O2. Similarly, the repair circuit 12 determines whether the bits G3 to Gm are good bits in sequence according to the repair data RPG3 to RPGm. If so, they are coupled to the input and output terminals I / O3 to I / Om. If they are bad bits, such as bit Gm-1, a good and unused bit R3 is selected from the redundant bits and coupled to the input and output terminal I / Om-1. The method of generating the repair data RPG1 to RPGm and RPR1 to RPRn can refer to US20190220350.

[0024] exist Figure 1 In the embodiment, the register 11 is used to access the memory bits G1-Gm and R1-Rn, but in another embodiment, the register 11 may be omitted, and the memory bits G1-Gm and R1-Rn are coupled to the repair circuit 12 after being selected by internal access.

[0025] Figure 2 for Figure 1The circuit diagram of the embodiment of the repair circuit 12 in FIG. 1 includes a plurality of decoders 20, 22, 24, 26, a plurality of selection circuits 21, 23, 25, 27 and a redundant bit sorting circuit 14. The first decoder 20 generates a selection signal Se1 and an accumulation signal Sol according to the repair data RPG1. The second decoder 22 generates a selection signal Se2 and an accumulation signal So2 according to the repair data RPG2 and the accumulation signal So1. The third decoder 24 generates a selection signal Se3 and an accumulation signal So3 according to the repair data RPG3 and the accumulation signal So2. By analogy, multiple decoders 20, 22, 24 and 26 each receive a patch data RPG1~RPGm and each output a selection signal Se1~Sem. Except for the first decoder 20, the remaining decoders 22, 24 and 26 generate selection signals Se2~Sem based on the received patch data and the cumulative signals So1~Som-1 output by the previous decoder, wherein the multiple cumulative signals So1~Som-1 record the next redundant bit that can be used or the number of redundant bits that have been used. The redundant bit sorting circuit 14 connects the good bits in the redundant bits R1~Rn (DR1~DRn) to each selection circuit 21, 23, 25 and 27 according to the multiple patch data RPR1~RPRn. Figure 1 In this embodiment, bit R1 is defective, so the redundant bit sorting circuit 14 excludes bit R1, so that the output RI of the redundant bit sorting circuit 14 is DR2~DRn (R2~Rn). The output ends of the plurality of selection circuits 21, 23, 25 and 27 are respectively connected to an input / output end I / O1~I / Om, and the selection circuits 21, 23, 25 and 27 can be implemented by a multiplexer (MUX). The first selection circuit 21 determines to couple one of the normal bit G1 or the redundant bit R2 to the bit Rn (DG1 or DR2~DRn) to the first input / output end I / O1 according to the repair data RPG1 and the selection signal Se1. In this embodiment, the normal bit G1 is a good bit, so the selection circuit 21 selects to couple the normal bit G1 (DG1) to the input / output end I / O1. The second selection circuit 23 couples the normal bit G2 or one of the redundant bits R2 to Rn to the second input / output terminal I / O2 according to the repair data RPG2 and the selection signal Se2. In this embodiment, the normal bit G2 is a bad bit, so the selection circuit 23 selects the bit R2 (DR2) from the redundant bits R2 to Rn (DR2 to DRn) and couples it to the input / output terminal I / O2. Similarly, each selection circuit 21, 23, 25 and 27 couples a memory bit to the corresponding input / output terminal I / O1 to I / Om.

[0026] Figure 3 for Figure 21 is a circuit diagram of an embodiment of a decoder in FIG. 1 . Each decoder 20, 22 and 24 is composed of a plurality of logic circuits. Taking decoder 20 as an example, in decoder 20, NAND gates 202, 206 and 208 and inverter 204 form a basic circuit. Decoder 20 is composed of more than n basic circuits stacked together, where n is the number of redundant bits. The signals RENB11, RENB12 and RENB13 output by the NAND gate 208 of each basic circuit in decoder 20 form Figure 2 The selection signal Se1 in the NAND gate 206 and the signals Sa11, Sa12, Sa13, RENB11, RENB12 and RENB13 outputted by the NAND gates 206 and 208 constitute Figure 2 The accumulated signal So1 of the judgment circuit 20 is used in the selection signal Se1. In this embodiment, the response data is GND=“0”, so the position of “0” in the selection signal Se1 represents the redundant bit to be selected. For example, when the selection signal is “101”, the second good redundant bit R3 is selected to be coupled to the input / output terminal I / O, and when the selection signal is “110”, the third good redundant bit R4 is selected to be coupled to the input / output terminal I / O. In this embodiment, when the Mth normal bit is a bad bit, the Mth selection signal SeM is determined by the first patch data RPG1 to the Mth patch data RPGM, and one of the multiple redundant bits is selected to replace the Mth normal bit, where M is an integer greater than 0.

[0027] Figure 3 Only part of the circuits of the judgment circuits 20, 22 and 24 are shown, and those skilled in the art can understand the circuits of the judgment circuits 20, 22 and 24 from the following. Figure 5 The disclosed content can be used to infer the complete circuit of the judgment circuits 20, 22 and 24. Figure 3 In the embodiment of the present invention, the judgment circuits 20, 22 and 24 are implemented by a plurality of NAND gates 202, 206 and 208. However, the judgment circuits 20, 22 and 24 are not limited to being implemented by NAND gates, but may also be implemented by a plurality of NOR gates or other logic gate elements. For example, when the preset response data is "1 (VDD)", the NAND gates 202, 206 and 208 may be replaced by NOR gates.

[0028] However, Figure 1 In the repair circuit 12, each of the repair data RPG1-RPGm requires a decoder 20, 22 and 24 to decode and determine the normal bits to be replaced and the redundant bits to be replaced, such as Figure 2 As shown, therefore Figure 1The repair circuit will occupy a larger area, and each decoder 20 will provide its output to the next decoder 22 to count the redundant bits that have been used. Therefore, there will be a delay time between the completion of the operation of the first decoder and the completion of the operation of the last decoder. The more the number of decoders, the longer the delay time, resulting in a slower processing speed of the repair circuit 12.

[0029] Figure 4 FIG. 1 is a circuit diagram of a first embodiment of a repair method based on bit groups according to the present invention. Figure 4 The memory 30 includes a register 301, a repair circuit 316, and a plurality of input and output terminals 318, 320, 322, 324, 326, 328, 330, and 332. The register 301 is connected to a plurality of normal bits G1-G8 and a plurality of redundant bits R1-R6 selected from a memory array (not shown). Figure 4 The memory bits G1-G8 and R1-R6 are placed in the register 301 only to express that these memory bits are connected to the register 301. In fact, the memory bits G1-G8 and R1-R6 are not inside the register 11. The memory bits G1-G8 and R1-R6 are selected at the same time in the same internal access. The plurality of general bits G1-G8 and the plurality of redundant bits R1-R6 can be on the same row of the memory array. In this embodiment, 2 bits are grouped together, so the 8 general bits G1-G8 connected to the register 301 are divided into 4 first groups 302, 304, 306 and 308, and the 6 redundant bits R1-R6 connected to the register 301 are divided into 3 second groups 310, 312 and 314. Then, it is detected whether there are bad bits in the first groups 302, 304, 306 and 308 and the second groups 310, 312 and 314 to generate the group's repair data RPG1-RPG4 and RPR1-RPR3, wherein the repair data RPG1-RPG4 respectively mark whether there are bad bits in the first groups 302, 304, 306 and 308, and the repair data RPR1-RPR3 respectively mark whether there are bad bits in the second groups 310, 312 and 314. In this embodiment, the repair data RPG1-RPG4 and RPR1-RPR3 are provided by the register 301 to the repair circuit 316, but are not limited to being provided by the register 301. The repair circuit 316 can eliminate the second group 310 with bad bits in the second groups 310, 312 and 314 according to the repair data RPR1-RPR3 to avoid the second group 310 being used to replace the first group with bad bits, for example, by using Figure 2The repair circuit 316 determines whether the first groups 302, 304, 306 and 308 have bad bits according to the repair data RPG1-RPG4. When there are bad bits in the first groups 302, 304, 306 or 308, the repair circuit 316 selects one of the remaining second groups 312 and 314 to replace the first group with bad bits, for example, by Figure 2 The decoder and selection circuit in the embodiment select the second group. Figure 4 As shown in the embodiment, the repair circuit 316 determines that there are no bad bits in the first group 302 according to the repair data RPG1, and thus connects the normal bits G1 and G2 in the first group 302 to the input-output terminals 318 and 320, respectively. The repair circuit 316 determines that there are bad bits in the first group 304 according to the repair data RPG2, and thus selects the second group 312 to replace the first group 304, and connects the redundant bits R3 and R4 in the second group 312 to the input-output terminals 322 and 324, respectively. The repair circuit 316 determines that there are no bad bits in the first group 306 according to the repair data RPG3, and thus connects the normal bits G5 and G6 in the first group 306 to the input-output terminals 3326 and 328, respectively. The repair circuit 316 determines that there are bad bits in the first group 308 according to the repair data RPG4, so the second group 314 is selected to replace the first group 308, and the redundant bits R5 and R6 in the second group 314 are connected to the input and output terminals 330 and 332 respectively. The circuit structure of the repair circuit 316 can be referred to Figure 2 .

[0030] exist Figure 4 In the embodiment, the patch data RPG1-RPG4 and RPR1-RPR3 of the group are determined based on the patch data of all the bits in the group. For example, in the first group 302, the patch data of bits G1 and G2 are both "0", indicating that the first group 302 is all good bits, so the patch data RPG1 of the group is set to "0", and in the first group 304, the patch data of bits G3 and G4 are "1" and "0" respectively, indicating that there are bad bits in the first group 304, so the patch data RPG2 of the group is set to "1". The patch data RPG1-RPG4 and RPR1-RPR3 of the group can be preset, or can be obtained by calculating the patch data of bits G1-G8 and R1-R6, for example, using an OR gate to process the patch data of bits G1 and G2 to generate the patch data RPG1 of the group. In other embodiments, the patch data of the group with bad bits can also be marked as "0", and the patch data of the group without bad bits can be marked as "1".

[0031] exist Figure 4In the embodiment, the register 301 is used to access the normal bits G1-G8 and the redundant bits R1-R6, but in another embodiment, the register 301 can be omitted, and the selected memory bits G1-G8 and R1-R6 are coupled to the repair circuit 316 after being internally accessed.

[0032] exist Figure 1 In the repair method with one bit as the unit, if the number of general bits is 8, the repair circuit 12 needs 8 decoders 20, 22 or 24 to process the repair data of the 8 general bits G1 to G8 respectively. Figure 4 In the method of repairing in bit groups, the repair circuit 316 only needs four decoders 20, 22 or 24 to process the repair data RPG1 to RPG4 of the four first groups 302, 304, 306 and 308. Figure 4 The repair circuit 316 can reduce the number of decoders by half, making the circuit architecture simpler, and can reduce the area of ​​the repair circuit 316, and also reduce the delay time caused by data transmission between decoders, thereby speeding up the processing speed of the repair circuit 316. Figure 4 In the embodiment, 2 bits are used as a group, but the present invention is not limited to this. The present invention can also use more than 2 bits as a group. In other embodiments, each group can be composed of t bits, and t is an integer greater than or equal to 2.

[0033] Figure 5 A circuit diagram showing a second embodiment of the repair method based on bit groups of the present invention, Figure 5 The memory 30 also includes a register 301 connected to the normal bits G1-G8 and the redundant bits R1-R6, a repair circuit 316 and a plurality of input and output terminals 318, 320, 322, 324, 326, 328, 330 and 332. The normal bits G1-G8 are divided into a plurality of first groups 302, 304, 306 and 308. Figure 4 The difference is that Figure 5 The redundant bits R1 to R6 are first detected, and then the bad bit R2 is removed. Finally, the good redundant bits R1, R3 to R6 are divided into a plurality of second groups 334 and 336. The repair circuit 316 determines whether the first groups 302, 304, 306 and 308 have bad bits according to the repair data RPG1 to RPG4. When there are bad bits in the first groups 302, 304, 306 or 308, the repair circuit 316 selects one from the remaining second groups 334 and 336 to replace the first group with bad bits. Figure 5As shown in the embodiment of FIG. 3 , the repair circuit 316 determines that there are no bad bits in the first group 302 according to the repair data RPG1, and thus connects the normal bits G1 and G2 in the first group 302 to the input-output terminals 318 and 320, respectively. The repair circuit 316 determines that there are bad bits in the first group 304 according to the repair data RPG2, and thus selects the second group 334 to replace the first group 304, and connects the redundant bits R1 and R3 in the second group 334 to the input-output terminals 322 and 324, respectively. The repair circuit 316 determines that there are no bad bits in the first group 306 according to the repair data RPG3, and thus connects the normal bits G5 and G6 in the first group 306 to the input-output terminals 3326 and 328, respectively. The repair circuit 316 determines that there are bad bits in the first group 308 according to the repair data RPG4, and thus selects the second group 336 to replace the first group 308, and connects the redundant bits R5 and R6 in the second group 336 to the input and output terminals 330 and 332, respectively.

[0034] Figure 6 A circuit diagram showing a third embodiment of the repair method based on bit groups of the present invention, Figure 6 The memory 30 and Figure 4 The present invention also has a register 301 connected to normal bits G1-G8 and redundant bits R1-R6, a repair circuit 316 and a plurality of input and output terminals 318, 320, 322, 324, 326, 328, 330 and 332. The normal bits G1-G8 are divided into four first groups 302, 304, 306 and 308, and the plurality of redundant bits R1-R6 are divided into two second groups 334 and 336. Figure 6 The memory 30 detects the plurality of general bits G1-G8 to determine whether there are bad bits in the general bits G1-G8 and generates corresponding repair data RPG1-RPG8. If the general bits in the first group are all good bits, the repair data is marked as "00". If there is at least one bad bit in the first group, the repair data is marked as "01", "10" or "11". The repair data RPG1-RPG8 can be provided to the repair circuit 316 by the register 301, but is not limited to being provided by the register 301. Figure 6For example, in which the general bits G3, G7, and G8 are bad bits, it can be determined that the first group 304 where the general bit G3 is located is the first group where the bad bits appear, and the first group 308 where the general bits G7 and G8 are located is the second group where the bad bits appear. Therefore, the repair data RPG3 and RPG4 of the first group 304 can be set to "01", so that the repair circuit 316 can select the first second group 334 to replace the first group 304 through the repair data "01" corresponding to the first group 304. Similarly, the repair data RPG7 and RPG8 of the general bits G7 and G8 in the first group 308 are set to "10", so that the repair circuit 316 can select the second second group 336 to replace the first group 308 through the repair data "10" corresponding to the first group 308. When there is a third first group with bad bits and a third second group in the memory 30, the repair data corresponding to the third first group with bad bits can be set to "11" so that the repair circuit selects the third second group to replace the third first group with bad bits. On the other hand, the first groups 302 and 306 are all good bits, so the repair data RPG1 and RPG2 and the repair data RPG5 and RPG6 are all set to "00". In this embodiment, since two bits form a group, only three different repair data "01", "10" and "11" can be set to correspond to the three second groups. If three bits form a group, seven different repair data "001" to "111" can be set to correspond to the seven second groups. As the number of bits in the group increases, more second groups can be set. In this embodiment, the data "00" is used to indicate that the bits in the group are all good bits, but in other embodiments, other data can be used to indicate, such as the data "11".

[0035] Figure 7 for Figure 6 The circuit diagram of the embodiment of the repair circuit 316 includes decoders 340, 342, 344 and 346 and selection circuits 348, 350, 352 and 354, wherein the selection circuits 348, 350, 352 and 354 can be implemented by multiplexers. Figure 8 for Figure 7 The circuit diagram of the decoder 340 in the embodiment of FIG. 3 is the same as that of the decoder 340. Figure 7 and Figure 8 , the decoder 340 receives the corresponding patch data "00" of the first group 302, Figure 8The input terminal In1 receives the first data “0” in the patch data “00”, and the input terminal In2 receives the second data “0” in the patch data “00”, so the decoder 340 generates a selection signal “1000” according to the patch data “00”. The selection circuit 348 can connect the first group 302 to the input and output terminals 318 and 320 according to the selection signal “1000” provided by the decoder 340. The decoder 342 receives the patch data “01” of the corresponding first group 304 to generate a selection signal “0100” so that the selection circuit 350 selects the first second group 334 to connect to the input and output terminals 322 and 324. The decoder 344 receives the patch data “00” of the corresponding first group 306 to generate a selection signal “1000” so that the selection circuit 352 connects the third first group 306 to the input and output terminals 326 and 328. The decoder 346 receives the patch data “10” of the corresponding first group 308 to generate a selection signal “0010”, so that the selection circuit 354 selects the second second group 336 to be connected to the input and output terminals 330 and 332 .

[0036] Compared to Figure 3 The decoder 20 of the present invention Figure 8 The decoder 340 circuit is simpler and requires a smaller area. Figure 7 There is no data transmission between the decoders 340, 342, 344 and 346, so the processing speed of the repair circuit 316 will not be slowed down as the number of decoders increases.

[0037] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0038] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for repairing a memory, characterized in that: The memory includes a plurality of normal bits and a plurality of redundant bits. The repair method includes the following steps: A. dividing the plurality of general bits into a plurality of first groups, wherein each of the plurality of first groups has t general bits, where t is an integer greater than or equal to 2; B. dividing the plurality of redundant bits into a plurality of second groups, wherein each of the plurality of second groups has t redundant bits; C. detecting the plurality of first groups to generate a plurality of first patch data, wherein the plurality of first patch data are used to respectively mark whether the plurality of first groups have bad bits; as well as D. using one of the plurality of second groups to replace the first group having bad bits; wherein the plurality of normal bits and the plurality of redundant bits are selected simultaneously during internal access; The plurality of normal bits and the plurality of redundant bits are located in the same row.

2. The repair method according to claim 1, characterized in that: The method further includes connecting the plurality of normal bits and the plurality of redundant bits to a register and then performing steps A and B.

3. The repair method according to claim 1, characterized in that: Also includes: Detecting the plurality of second groups to generate a plurality of second patch data, wherein the plurality of second patch data are used to respectively mark whether the plurality of second groups have bad bits; as well as The second group with bad bits is excluded according to the plurality of second patch data to prevent the second group with bad bits from being used to replace the first group with bad bits.

4. The repair method according to claim 1, characterized in that: The step B includes grouping good bits in the plurality of redundant bits into the plurality of second groups.

5. The repair method according to claim 1, characterized in that: The step D includes selecting one of the second groups from the plurality of second groups to replace the Mth first group according to the first patch data corresponding to the first first group to the Mth first group when the Mth first group among the plurality of first groups has bad bits, where M is an integer greater than 0.

6. The repair method according to claim 1, characterized in that: The step D includes selecting one of the second groups from the plurality of second groups to replace the Mth first group according to the Mth first patch data corresponding to the Mth first group in the plurality of first patch data when the Mth first group in the plurality of first groups has bad bits, where M is an integer greater than 0.

7. The repair method according to claim 6, characterized in that: The Mth first patch data includes information of the second group to be selected.

8. The repair method according to claim 6, characterized in that: The method also includes decoding the Mth first patch data to generate a selection signal to select a second group to replace the Mth first group.

9. A method for repairing a memory, characterized in that: The memory includes a plurality of normal bits and a plurality of redundant bits. The repair method includes the following steps: A. dividing the plurality of general bits connected to the register into a plurality of first groups, wherein each of the plurality of first groups has t general bits, and t is an integer greater than or equal to 2; B. dividing the plurality of redundant bits connected to the register into a plurality of second groups, wherein each of the plurality of second groups has t redundant bits; C. detecting the plurality of first groups to generate a plurality of first patch data, wherein the plurality of first patch data are used to respectively mark whether the plurality of first groups have bad bits; as well as D. using one of the plurality of second groups to replace the first group having bad bits; The plurality of normal bits and the plurality of redundant bits are located in the same row.

10. The repair method according to claim 9, characterized in that: Also includes: Detecting the plurality of second groups to generate a plurality of second patch data, wherein the plurality of second patch data are used to respectively mark whether the plurality of second groups have bad bits; as well as The second group with bad bits is excluded according to the plurality of second patch data to prevent the second group with bad bits from being used to replace the first group with bad bits.

11. The repair method according to claim 9, characterized in that: The step B includes grouping good bits in the plurality of redundant bits into the plurality of second groups.

12. The repair method according to claim 9, characterized in that: The step D includes selecting one of the second groups from the plurality of second groups to replace the Mth first group according to the first patch data corresponding to the first first group to the Mth first group when the Mth first group among the plurality of first groups has bad bits, where M is an integer greater than 0.

13. The repair method according to claim 9, characterized in that: The step D includes selecting one of the second groups from the plurality of second groups to replace the Mth first group according to the Mth first patch data corresponding to the Mth first group in the plurality of first patch data when the Mth first group in the plurality of first groups has bad bits, where M is an integer greater than 0.

14. The repair method according to claim 13, characterized in that: The Mth first patch data includes information of the second group to be selected.

15. The repair method according to claim 13, characterized in that: The method also includes decoding the Mth first patch data to generate a selection signal to select a second group to replace the Mth first group.

16. A memory repair circuit, characterized in that: The memory includes a plurality of normal bits and a plurality of redundant bits, and the repair circuit includes: a decoder, for decoding patch data of an Mth first group among a plurality of first groups to generate a selection signal, wherein the plurality of first groups each have t normal bits, M is an integer greater than 0, and t is an integer greater than or equal to 2; and a selection circuit connected to the decoder and a plurality of input and output terminals of the memory, for selecting a group from the Mth first group and a plurality of second groups to be connected to the plurality of input and output terminals according to the selection signal, wherein each of the plurality of second groups has t redundant bits; wherein the plurality of normal bits and the plurality of redundant bits are selected simultaneously during internal access; The plurality of normal bits and the plurality of redundant bits are located in the same row.

17. The repair circuit according to claim 16, characterized in that: A register is also included which is connected to the decoder and is used for connecting the plurality of normal bits and the plurality of redundant bits.

18. The repair circuit according to claim 16, characterized in that: The decoder includes a plurality of logic gates.

19. The repair circuit according to claim 16, characterized in that: The selection circuit includes a multiplexer.

20. The repair circuit according to claim 16, characterized in that: The repair data is provided by the Mth first group.

21. A memory repair circuit, characterized in that: The memory includes a plurality of normal bits and a plurality of redundant bits, and the repair circuit includes: A register for connecting the plurality of normal bits and the plurality of redundant bits; a decoder connected to the register, for decoding patch data of an Mth first group among a plurality of first groups to generate a selection signal, wherein the plurality of first groups each have t normal bits, M is an integer greater than 0, and t is an integer greater than or equal to 2; and a selection circuit connected to the decoder and a plurality of input and output terminals of the memory, for selecting a group from the Mth first group and a plurality of second groups to be connected to the plurality of input and output terminals according to the selection signal, wherein each of the plurality of second groups has t redundant bits; The plurality of normal bits and the plurality of redundant bits are located in the same row.

22. The repair circuit according to claim 21, characterized in that: The decoder includes a plurality of logic gates.

23. The repair circuit according to claim 21, characterized in that: The selection circuit includes a multiplexer.

24. The repair circuit according to claim 21, characterized in that: The repair data is provided by the Mth first group.

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