Method and apparatus for improving performance in reading one-time programmable memory

Abstract

Methods, apparatus, systems, and articles of manufacture are disclosed to improve performance when reading one-time programmable memory. An example apparatus includes a boost circuit (236) including a first output (215a), a second output (215b), a first input (213) configured to be coupled to a controller (234), a second input (221) coupled to a first output of a decoder (246), a third input (223) coupled to a second output of the decoder (246), and a multiplexer (206) including a first input coupled to the first output (215a) of the boost circuit (236), a second input coupled to the second output (215b) of the boost circuit (236), a third input coupled to a memory array (202 / 204), and an output coupled to a sense circuit (208).

Description

Technical Field

[0001] This disclosure relates generally to memory, and more specifically to methods and apparatus for improving performance when reading one-time programmable memory. Background Technology

[0002] Memory typically comprises an array of memory cells, each accessible via a corresponding word line and bit line pair. Therefore, a memory cell typically includes word line switching devices and storage elements. In one-time programmable (OTP) memory, the word line switching devices are metal-oxide-semiconductor field-effect transistors (MOSFETs), and the storage elements are floating-gate MOSFETs (FGMOS). Attached Figure Description

[0003] Figure 1 This is a schematic diagram of the first OTP memory array, the second OTP memory array, the multiplexer, and the sensing circuit.

[0004] Figure 2 These are schematic diagrams of an example first OTP memory array, an example second OTP memory array, an example multiplexer, an example sensing circuit, and an example boost circuit, to improve performance when reading one or more of the first OTP memory array 202 and / or the second OTP memory array 204.

[0005] Figure 3 It is shown Figure 2 A block diagram of an example implementation of the controller.

[0006] Figure 4 It is shown Figure 2 A schematic diagram of an example implementation of a boost circuit.

[0007] Figure 5 It is shown Figure 4 A schematic diagram showing further details of an example implementation of a level shifter.

[0008] Figure 6 It is a description Figure 2 and / or Figure 3 A diagram illustrating the operation of the boost circuit.

[0009] Figure 7 It describes based on a more concentrated time scale Figure 2 and / or Figure 3 A diagram illustrating the operation of the boost circuit.

[0010] Figure 8 This is a flowchart illustrating a process that can be implemented by example machine-readable instructions, which can be executed to carry out... Figure 2 and Figure 3 The controller.

[0011] Figure 9 This is a flowchart illustrating a process that can be implemented by example machine-readable instructions, which can be executed to carry out... Figure 2 , Figure 4 and Figure 5 The boost circuit.

[0012] Figure 10 It is constructed to execute Figure 8 and Figure 9 A block diagram of an example processing platform for implementing the instructions. Figure 2 and Figure 3 Example controller, Figure 2 and Figure 4 Example boost circuit, and / or Figure 4 and Figure 5 Example level shifter.

[0013] These figures are not drawn to scale. Generally, the same reference numerals will be used throughout the figures(s) and accompanying written description to refer to the same or similar parts. Unless otherwise stated, connection references (e.g., attachment, coupling, connection, and joining) should be interpreted broadly and may include intermediate members between sets of elements and relative movement between elements. Therefore, connection references do not necessarily imply that two elements are directly connected and have a fixed relationship with each other.

[0014] When identifying multiple elements or components that can be individually mentioned, this document uses descriptors such as “first,” “second,” “third,” etc. Unless otherwise specified or understood in the context of their use, such descriptors are not intended to assign any meaning to priority, physical order, arrangement, or chronological order in the list, but are merely labels used to refer to multiple elements or components separately to facilitate understanding of the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in a particular embodiment, while different descriptors (e.g., “second” or “third”) may be used in the claims to refer to the same element. In such cases, it should be understood that such descriptors are only used for convenience in referring to multiple elements or components. Detailed Implementation

[0015] Memory cells are used to store binary digital data (e.g., bit values ​​1 or 0, logic high or logic low values, etc.) in computing devices and / or any suitable computing architecture (e.g., microcontrollers, etc.). Memory cells may be contained in an array of memory cells located in volatile memory (e.g., random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), etc.) or non-volatile memory (e.g., read-only memory (ROM), mask ROM, programmable read-only memory (PROM), OTP memory (e.g., one-time programmable memory array), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, etc.).

[0016] As previously described, OTP memory is a type of non-volatile memory that can be programmed by the end user. An OTP memory array may include one or more memory cells, each memory cell including one or more storage devices (e.g., FGMOS). Non-volatile memory (e.g., OTP memory) stores binary data representing firmware code and / or low-level programs for read-only access. When such firmware code and / or any low-level programs are to be used, the corresponding memory bits stored in the memory cell can be sensed and / or otherwise read for use in volatile memory within the computing system and / or computing device, or elsewhere.

[0017] Some types of non-volatile memories (e.g., OTP memories) are programmed using hot carrier injection. When hot carrier injection is used, a voltage higher than the memory device's (e.g., FGMOS) rating (e.g., 5V) (e.g., 8 volts (V)) is applied to the memory device for a period of time. To avoid damaging and / or destroying the memory device, the rated voltage of the memory device is selected such that the rated voltage is high enough to withstand the higher voltage for the duration of that period. Non-volatile memories and memories in general typically include multiplexers or other circuitry to read and / or otherwise sense the bit values ​​stored in the memory cells. Because these multiplexers and / or other circuitry are coupled to the memory cells, they are similarly rated for higher voltages.

[0018] However, when reading non-volatile memory cells (e.g., OTP memory cells), a voltage lower than the rated voltage (e.g., 5V) (e.g., 1.5V) is used to save power. However, due to the higher rated voltage of the memory device (e.g., FGMOS), the read operation is slower, especially under the limitation of the memory's operating area.

[0019] Figure 1This is a schematic diagram 100 of the first OTP memory array 102, the second OTP memory array 104, the multiplexer 106, and the sensing circuit 108. Figure 1 In the first OTP memory array 102, there are first OTP memory cells 110 and second OTP memory cells 112. Similarly, in... Figure 1 In the second OTP memory array 104, there are a third OTP memory unit 114 and a fourth OTP memory unit 116.

[0020] exist Figure 1 In this configuration, the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, and the fourth OTP memory cell 116 include corresponding positive channel (P-channel) MOSFETs (PMOS) 118, 120, 122, and 124 (e.g., one or more positive channel switches). Furthermore, the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, and the fourth OTP memory cell 116 include corresponding FGMOS switches 126, 128, 130, and 132. Figure 1 In this context, the controller 134 is operable to load a corresponding memory bit in any one of the first OTP memory unit 110, the second OTP memory unit 112, the third OTP memory unit 114, and / or the fourth OTP memory unit 116 via a first word line (line 105) or a second word line (line 107).

[0021] exist Figure 1 In this configuration, multiplexer 106 is a pair of direct-through multiplexers comprising a first array of PMOS switches 136, a first array of (negative channel) n-channel MOSFET (NMOS) switches 138 (e.g., negative channel switches), a second array of PMOS switches 140, a second array of NMOS switches 142, and a decoder 144. Multiplexer 106 can operate based on memory address values ​​associated with control signals (line 113) decoded by decoder 144, to conduct current through the first array of PMOS switches 136 and the first array of NMOS switches 138, or to conduct current through the second array of PMOS switches 140 and the second array of NMOS switches 142.

[0022] To read a bit value stored in one of the selected OTP memory cells 110, 112, 114, or 116, controller 134 generates a control signal (line 113) for use by multiplexer 106 to enable and / or disable the corresponding first array PMOS switch 136, first array NMOS switch 138, second array PMOS switch 140, or second array NMOS switch 142. Essentially simultaneously (e.g., within a few microseconds), a reference signal (line 115) is transmitted to reference current generator 146. In operation, the reference signal (line 115) instructs reference current generator 146 to generate a reference current (I0) for sensing circuit 108. REF Similarly, multiplexer 106 conducts bit current (I) based on the memory address value associated with the control signal (line 113) and whether the memory bit is stored in one of the following: first OTP memory cell 110, second OTP memory cell 112, third OTP memory cell 114, or fourth OTP memory cell 116. BIT ).

[0023] exist Figure 1 In this context, the rated voltage of each of the multiplexer 106, the first OTP memory unit 110, the second OTP memory unit 112, the third OTP memory unit 114, and the fourth OTP memory unit 116 is much higher than the voltage of the sensing circuit 108, the reference current generator 146, and the computing system 148 (e.g., 5V versus 1.5V).

[0024] exist Figure 1 In the process of performing a read operation on a memory bit stored in one or more of the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, or the fourth OTP memory cell 116, the controller 134 generates a control signal (line 113) for use by the decoder 144. Based on the control signal (line 113), the decoder 144 generates at least one signal to operate the multiplexer 106 at a voltage much lower than the rated voltage of the multiplexer 106 (e.g., 1.5V vs. 5V). Due to the fabrication process of one or more of the first array PMOS switch 136, the first array NMOS switch 138, the second array PMOS switch 140, and the second array NMOS switch 142, the threshold voltage (V) of one or more of the first array PMOS switch 136, the first array NMOS switch 138, the second array PMOS switch 140, and the second array NMOS switch 142 is... t The voltage is higher than the threshold voltage of the lower rated component. Therefore, in order to make the potential current (I) higher than the threshold voltage of the lower rated component, the potential current (I) is higher than the threshold voltage of the lower rated component. BITThe voltage levels of the control signal (line 113) and / or the resulting signal generated by the decoder 144, which can be conducted through the multiplexer 106, should be high enough to saturate one or more of the first array PMOS switch 136, the first array NMOS switch 138, the second array PMOS switch 140, and the second array NMOS switch 142.

[0025] exist Figure 1 In this case, because the voltage of the control signal (line 113) and one or more resulting signals generated by the decoder 144 are not high enough to saturate one or more of the first array PMOS switches 136, the first array NMOS switches 138, the second array PMOS switches 140, and the second array NMOS switches 142 of the multiplexer 106, the speed of the read operation is affected. For example, especially under the limitation of the operating region of the multiplexer 106, the read operation can be so greatly affected that it hinders the function of the multiplexer. More specifically, the access time (e.g., the time spent reading and / or sensing data, instructions, and information stored in the first OTP memory array 102 or the second OTP memory array 104) and the cycle time (e.g., the time between one access to the first OTP memory array 102 or the second OTP memory array 104 and a subsequent access to the first OTP memory array 102 or the second OTP memory array 104) depend on the bit current (I0) that the first OTP memory array 102 or the second OTP memory array 104 can cause. BIT The speed of conduction. For example, the conduction speed of... Figure 1 As shown, read operations (e.g., access times above (e.g., satisfying) a threshold, and loop times) may be limited to a voltage of 1.35V or lower for the control signal (line 113) and / or the voltage of one or more signals generated by the decoder 144. Figure 1 As shown, read operations (e.g., access time and loop time above (e.g., satisfying) a threshold) can be limited to temperatures equal to or below -40°C.

[0026] The examples disclosed herein include methods and apparatuses for improving performance while reading and / or otherwise detecting memory bits stored in memory. In the examples disclosed herein, read operations on the OTP memory are improved within its reliable operating area. Furthermore, when utilizing the examples disclosed herein, memory bits, instructions, and / or other information stored in the first OTP memory cell 110, the second OTP memory cell 112, the third OTP memory cell 114, and / or the fourth OTP memory cell 116 can be read by a processor, CPU, and / or other computing system without the use of additional volatile memory architecture.

[0027] Figure 2 This is a schematic diagram 200 of an example first OTP memory array 202, an example second OTP memory array 204, an example multiplexer 206, an example sensing circuit 208, and an example boost circuit 236, to improve performance when reading one or more of the first OTP memory array 202 and / or the second OTP memory array 204. Figure 2 In the first OTP memory array 202, there are example first OTP memory cells 210 and example second OTP memory cells 212. Similarly, in... Figure 2 In this example, the second OTP memory array 204 includes an example third OTP memory cell 214 and an example fourth OTP memory cell 216. Figure 2 Schematic diagram 200 also includes an example controller 234, an example boost circuit 236, an example decoder 246, an example inverter 247, an example reference current generator 248, and an example computing system 250. In other examples disclosed herein, any number of OTP memory arrays may be configured in schematic diagram 200.

[0028] exist Figure 2 In this configuration, the first OTP memory cell 210, the second OTP memory cell 212, the third OTP memory cell 214, and the fourth OTP memory cell 216 include corresponding PMOS transistors 218, 220, 222, and 224. Furthermore, the first OTP memory cell 210, the second OTP memory cell 212, the third OTP memory cell 214, and the fourth OTP memory cell 216 include corresponding FGMOS switches 226, 228, 230, and 232. Figure 2 In this configuration, controller 234 is operable to load corresponding memory bits into any one of the first OTP memory unit 210, the second OTP memory unit 212, the third OTP memory unit 214, and / or the fourth OTP memory unit 216 via an example first word line (line 205) or an example second word line (line 207). Figure 2 In the example shown, in response to generating a logic low on either the first word line (line 205) or the second word line (line 207), charge is stored in the floating gate of the corresponding FGMOS switches 226, 228, 230, 232.

[0029] exist Figure 2 In the example, the rated voltage (e.g., 5 volts) of the first OTP memory array 202, the second OTP memory array 204, and the multiplexer 206 is higher than the rated voltage (e.g., 1.5 volts) of the sensing circuit 208 and the reference current generator 248. Although Figure 2The illustration shows that the rated voltage (e.g., 5 volts) of the first OTP memory array 202, the second OTP memory array 204, and the multiplexer 206 is higher than the rated voltage (e.g., 1.5 volts) of the sensing circuit 208 and the reference current generator 248, but any suitable rated voltage can be used to implement the first OTP memory array 202, the second OTP memory array 204, the multiplexer 206, the sensing circuit 208, and / or the reference current generator 248.

[0030] exist Figure 2 In this example, multiplexer 206 is two pairs of continuous multiplexers, including an example first array PMOS switch 238, an example first array NMOS switch 240, an example second array PMOS switch 242, and an example second array NMOS switch 244. The first array PMOS switch 238 includes a gate (e.g., a control terminal) coupled to the output of decoder 246 (e.g., a first select signal (line 221)), a source (e.g., a current terminal) coupled to the first OTP memory cell 210 and the second OTP memory cell 212, and a drain (e.g., a current terminal) coupled to sensing circuit 208. The first array NMOS switch 240 includes a gate (e.g., a control terminal) coupled to the output of boost circuit 236 (e.g., a boosted control signal (line 215a)), a drain (e.g., a current terminal) coupled to the first OTP memory cell 210 and the second OTP memory cell 212, and a source (e.g., a current terminal) coupled to sensing circuit 208. The second array PMOS switch 242 includes a gate (e.g., a control terminal) coupled to the output of inverter 247, a source (e.g., a current terminal) coupled to the third OTP memory cell 214 and the fourth OTP memory cell 216, and a drain (e.g., a current terminal) coupled to sensing circuit 208. The second array NMOS switch 244 includes a gate (e.g., a control terminal) coupled to the output of boost circuit 236 (e.g., a supplemented boost control signal (line 215b)), a drain (e.g., a current terminal) coupled to the third OTP memory cell 214 and the fourth OTP memory cell 216, and a source (e.g., a current terminal) coupled to sensing circuit 208.

[0031] exist Figure 2In this example, multiplexer 206 may operate based on the polarity of the example selection signal (lines 221, 223) generated by decoder 246 and / or the example boost control signal (line 215a) and / or the example supplement boost control signal (line 215b) generated by boost circuit 236. In operation, controller 234 transmits the example control signal (line 213) to boost circuit 236, and boost circuit 236 generates the example boost control signal (line 215a) and / or the example supplement boost control signal (line 215b) based on the polarity of the selection signals (lines 221, 223) and transmits them to multiplexer 206. Furthermore, controller 234 transmits the example decode signal (line 231) to decoder 246. As a result, decoder 246 generates selection signals (lines 221, 223) based on the decoding signal (line 231) to combine with the boosted control signal (line 215a) and / or the supplementary boosted control signal (line 215b) to cause current conduction through the first array PMOS switch 238 and the first array NMOS switch 240 or to cause current conduction through the second array PMOS switch 242 and the second array NMOS switch 244.

[0032] For example, if the first word line (line 205) is logic low, the second word line (line 207) is logic high, the first select signal (line 221) is logic high, the second select signal (line 223) is logic low, and the control signal (line 213) is logic high, then the boosted control signal (line 215a) is logic low, the voltage level of the supplementary boosted control signal (line 215b) is boosted, and the memory bit (if any) stored in the third OTP memory cell 214 will be sensed and / or otherwise read. Further in this example, if the memory bit is stored in the third OTP memory cell 214 and the select signal (lines 221, 223) and / or the control signal (line 213) indicate sensing and / or otherwise reading the memory bit stored in the third OTP memory cell 214, then the example bit current (I0) BIT The conduction will be carried through the second array PMOS switch 242 and the second array NMOS switch 244.

[0033] Alternatively, in another example disclosed herein, if the first word line (line 205) is logic high, the second word line (line 207) is logic low, the first select signal (line 221) is logic low, the second select signal (line 223) is logic high, and the control signal (line 213) is logic high, then the voltage level of the boosted control signal (line 215a) is boosted, the supplementary boosted control signal (line 215b) is logic low, and the memory bits stored in the second OTP memory cell 212 (if any) are sensed and / or otherwise read. Further in this example, if the memory bits are stored in the second OTP memory cell 212, and the select signals (lines 221, 223) and / or the control signal (line 213) indicate sensing and / or otherwise reading the memory bits stored in the second OTP memory cell 212, then the bit current (I0) BIT The current (I) will be conducted through the first array PMOS switch 238 and the first array NMOS switch 240. In the example disclosed herein, if the memory bit is stored in one of the first OTP memory cell 210, the second OTP memory cell 212, the third OTP memory cell 214, or the fourth OTP memory cell 216, the bit current (I) will be conducted through the first array PMOS switch 238 and the first array NMOS switch 240. BIT The amplitude can be 0.5 mA, 1.0 mA, etc. Table 1 below illustrates example voltage values ​​when reading memory cells of the first OTP memory array 202.

[0034] Signal Voltage level (volts) Control signal (line 213) 1.5 Control signal for boosting (line 215a) 2.4 Supplemental boost control signal (line 215b) 0 First selection signal (line 221) 0 Second selection signal (line 223) 1.5 Decoding signal (line 231) 0

[0035] Table 1

[0036] Table 2 below illustrates example voltage values ​​when reading memory cells of the second OTP memory array 204.

[0037] Signal Voltage level (volts) Control signal (line 213) 1.5 Control signal for boosting (line 215a) 0 Supplemental boost control signal (line 215b) 2.4 First selection signal (line 221) 1.5 Second selection signal (line 223) 0 Decoding signal (line 231) 1

[0038] Table 2

[0039] exist Figure 2 In the example shown, the sensing circuit 208 is operable to sense and / or otherwise read memory bits (if any) stored in one of the selected first OTP memory units 210, second OTP memory units 212, and first OTP memory unit 210. Figure 2In the example, if a memory bit is stored in one of the selected first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216, and such a corresponding memory cell is selected to be sensed and / or otherwise read via a selection signal (line 221, 223) and / or a control signal (line 213), then the bit current (I0) BIT The transmission is carried out through multiplexer 206.

[0040] exist Figure 2 In the example shown, controller 234 is coupled to a first OTP memory cell 210, a second OTP memory cell 212, a third OTP memory cell 214, a fourth OTP memory cell 216, a boost circuit 236, a decoder 246, and a reference current generator 248. In the example disclosed herein, controller 234 is implemented as a single controller operable to at least: load memory bits in any one of the first OTP memory cell 210, the second OTP memory cell 212, the third OTP memory cell 214, and / or the fourth OTP memory cell 216; select, via a control signal (line 213) and / or a decoding signal (line 231), which of the first OTP memory cell 210, the second OTP memory cell 212, the third OTP memory cell 214, or the fourth OTP memory cell 216 is used for sensing and / or otherwise reading; and / or generate and / or otherwise cause the generation of a reference current via a reference signal (line 217). Figure 2 In the example, controller 234 is a CPU that includes a memory controller. In other examples disclosed herein, any number of suitable controllers can be configured to perform the operations of controller 234.

[0041] exist Figure 2In this configuration, controller 234 is operable to load memory bits into any one of the first OTP memory unit 210, the second OTP memory unit 212, the third OTP memory unit 214, and / or the fourth OTP memory unit 216 based on logic values ​​on either the first word line (line 205) or the second word line (line 207). In this example, a user can instruct certain program and / or low-level code to be converted into binary digital data by controller 234 and stored in one of the selected first OTP memory unit 210, the second OTP memory unit 212, the third OTP memory unit 214, and / or the fourth OTP memory unit 216. Controller 234 is operable to generate control signals (line 213) and / or decode signals (line 231) and / or otherwise provide control signals (line 213) and / or decode signals (line 231) to boost circuit 236 and / or decoder 246 to indicate which of the first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216 should be sensed and / or otherwise read (e.g., sense memory bits, if any). Furthermore, controller 234 is operable to generate a reference signal (line 217) and / or otherwise provide the reference signal (line 217) to reference current generator 248 to generate a reference current (I0). REF Further operation of controller 234 will be described below. Figure 3 To explain.

[0042] exist Figure 2 In the example shown, the boost circuit 236 is the voltage level (V) of the control signal (line 213) and / or selection signal (lines 221, 223). CONTROL A boost circuit applies a voltage increase. For example, if the voltage level of the control signal (line 213) is 1.5V, the boost circuit 236 applies a boost of approximately 500-900 millivolts (mV) to the control signal (line 213). The resulting control signal is selected based on the polarity of the selection signals (lines 221, 223), i.e., the boosted control signal (line 215a) or the supplementary boosted control signal (line 215b). The voltage level of the resulting control signal (e.g., the boosted control signal (line 215a) and / or the supplementary boosted control signal (line 215b)) is between 2.0V and 2.4V. BOOST ). The following is combined with Figure 4 Explain the further operation of boost circuit 236.

[0043] exist Figure 2In this example, a reference current generator 248 senses circuitry 208 and a controller 234. In the example disclosed herein, the reference current generator 248 is implemented externally to the controller 234. Alternatively, in other examples disclosed herein, the reference current generator 248 may be implemented internally to the controller 234. The reference current generator 248 is configured to acquire and / or otherwise receive an indication reference current (I0). REF The reference signal (line 217) indicates the desired amplitude of the reference current. For example, the reference signal (line 217) can indicate a desired reference current (I) of 0.1 mA. REF Therefore, the reference current generator 248 is configured to generate a reference current (I0.1mA) with a desired current. REF In some of the examples disclosed herein, sensing circuitry 208 may be included in controller 234.

[0044] exist Figure 2 In the example shown, computing system 250 is coupled to the output of sensing circuitry 208. In the examples disclosed herein, computing system 250 may be volatile memory configured to receive indications of sensed and / or otherwise read memory bits. In such an example disclosed herein, computing system 250 may download and / or otherwise load memory bits from any of the first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and / or fourth OTP memory cell 216 for reprogramming, use, and / or any other suitable application. In other examples disclosed herein, computing system 250 may be a processor and / or a suitable processing device configured to access memory bits stored in any of the first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and / or fourth OTP memory cell 216.

[0045] In some of the examples disclosed herein, sensing circuit 208, boost circuit 236, reference current generator 248, and / or decoder 246 may be included in controller 234.

[0046] Figure 3 It is a diagram. Figure 2 The example controller 234 is shown in block diagram 300. Figure 3 The controller 234 includes an example signal analyzer 302, an example signal generator 304, and an example sensing interface 306. In the examples disclosed herein, any one of the signal analyzer 302, the signal generator 304, and / or the sensing interface 306 can transmit wired and / or wireless communication to corresponding devices inside and / or outside the controller 234 via any suitable method.

[0047] exist Figure 3In the example shown, signal analyzer 302 is configured to determine whether an indication of sensing and / or reading memory bits has been obtained and / or otherwise received. Figure 3 In this embodiment, signal analyzer 302 operates within controller 234 based on a pre-initialized command instructing the sensing and / or otherwise reading of memory bits. For example, during the boot-up of controller 234, signal analyzer 302 may respond to a pre-initialized command instructing the sensing and / or otherwise reading of memory bits stored in non-volatile memory (e.g., first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216). In other examples disclosed herein, signal analyzer 302 may be configured to determine whether an instruction to sense and / or read a memory bit is received based on communication with a user interface and / or any suitable input device. In response to the instruction to sense and / or read a memory bit, signal analyzer 302 analyzes the instruction to determine which of the first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, or fourth OTP memory cell 216 will be accessed for sensing and / or reading. In the examples disclosed herein, signal analyzer 302 may be a signal analyzer controller.

[0048] exist Figure 3 In the example shown, signal generator 304 is configured to receive an instruction and / or determination from signal analyzer 302 to generate a corresponding logic value on a signal associated with a word line of the selected memory cell to be read. For example, signal generator 304 may generate a logic low value on example word lines (e.g., the first word line (line 205) and / or the second word line (line 207)) to store memory bits in any one of the first OTP memory cell 210, the second OTP memory cell 212, the third OTP memory cell 214, and / or the fourth OTP memory cell 216, respectively. Furthermore, signal generator 304 may generate... Figure 2 Example reference signal (line 217) for use Figure 2 The reference current generator 248 is used. In the examples disclosed herein, the signal generator 304 may be a signal generator controller.

[0049] exist Figure 3 In the example shown, the sensing interface 306 is configured to generate Figure 2 Example control signal (line 213) for use Figure 2 The boost circuit 236 is used. Furthermore, the sensing interface 306 is configured to generate... Figure 2 Example decoded signal (line 231) for use Figure 2The decoder 246 is used. In the examples disclosed herein, the sensing interface 306 is configured to generate a control signal (line 213) that causes the boost circuit 236 to generate a boosted control signal (line 215a) and / or a supplementary boosted control signal (line 215b). In the examples disclosed herein, the sensing interface 306 may be a sensing interface controller.

[0050] In some of the examples disclosed herein, signal generator 304 and / or sensing interface 306 may be included in the memory controller. Alternatively, in other examples disclosed herein, controller 234 may include Figure 2 The boost circuit 236 and / or the reference current generator 248.

[0051] Figure 4 It is shown Figure 2 A schematic diagram of an example implementation of the boost circuit 236. Figure 4 The boost circuit 236 includes an example boost network 402, an example first level shifter 404a, an example second level shifter 404b, and a voltage input 406. The example boost network 402 includes an example first input 408, an example second input 410, an example output 412, an example first inverter 414, an example second inverter 416, an example third inverter 418, an example fourth inverter 420, an example fifth inverter 422, an example first switch 424, an example second switch 426, an example third switch 428, and an example capacitor 430. The example first level shifter 404a includes an example first input 432a, an example second input 434a, an example third input 436a, an example fourth input 437a, and an example output 438a. Example second level shifter 404b includes example first input 432b, example second input 434b, example third input 436b, example fourth input 437b, and example output 438b.

[0052] exist Figure 4 In the examples, example first switch 424 is an NMOS transistor, which includes example gate 440 (e.g., a control terminal), example source 442 (e.g., a current terminal), and example drain 444 (e.g., a current terminal). Example second switch 426 is a PMOS transistor, which includes example gate 446 (e.g., a control terminal), example source 448 (e.g., a current terminal), and example drain 450 (e.g., a current terminal). Example third switch 428 is a PMOS transistor, which includes example gate 452 (e.g., a control terminal), example source 454, and example drain 456. Example capacitor 430 includes example first terminal 458 (e.g., a first plate) and example second terminal 460 (e.g., a second plate).

[0053] exist Figure 4In the example, the boost network 402 receives the control signal (line 213) at the first input 408 and the input voltage V at the voltage input 406. DD The circuit. For example, the voltage level at voltage input 406 could be 1.5 volts (e.g., V). DD =1.5V). In operation, boost network 402 boosts the voltage level of control signal (line 213) to improve the operating area of ​​the memory that the controller can sense. For example, boost network 402 can increase the voltage level of control signal (line 213) by 500mV. In operation, boost network 402 outputs the boosted signal at output 412. For example, when the controller (e.g., controller 234) sends control signal (line 213) and / or the decoder (e.g., decoder 246) transmits select signals (lines 221, 223) to read bits from memory arrays (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the logic value of control signal (line 213) and the logic value of select signals (lines 221, 223) can vary depending on which memory array is selected (e.g., first OTP memory array 202 versus second OTP memory array 204). Furthermore, when the controller (e.g., controller 234) sends a control signal (line 213) to avoid reading bits from the memory array, the logic value of the control signal (line 213) can be a logic low value.

[0054] exist Figure 4 In the example shown, the first level shifter 404a is a device that receives a first input signal and shifts the voltage level of the output signal to a voltage level specified by a second input signal. Figure 4 In this circuit, the first level shifter 404a receives a second selection signal (line 223) at the first input 432a and a first selection signal (line 221) at the second input 434a. For example, the first input 432a and the second input 434a are coupled to the output of the decoder 246. Figure 4In the example, the third input 436a is coupled to the output 412, the fourth input 437a is coupled to a reference voltage node (e.g., GND, zero volts, etc.), and the output 438a is coupled to the first array NMOS switch 240. In operation, the first level shifter 404a receives a first select signal (line 221) at the second input 434a, a second select signal (line 223) at the first input 432a, and a signal at the output 412 of the boost network 402. In operation, when the logic value at the first input 432a (e.g., the second selection signal (line 223)) and the logic value at the second input 434a (e.g., the first selection signal (line 221)) are logic high and logic low respectively, the first level shifter 404a shifts the voltage level of the signal at output 438a (e.g., the boosted control signal (line 215a)) from the voltage level of the signal at the first input 432a (e.g., logic high or logic low) to the voltage level of the signal at the third input 436a (e.g., the voltage level of the signal at output 412).

[0055] exist Figure 4 In the example shown, the second level shifter 404b is a device that receives the first input signal and shifts the voltage level of the output signal to the voltage level specified by the second input signal. Figure 4 In this circuit, the second level shifter 404b receives a first selection signal (line 221) at the first input 432b and a second selection signal (line 223) at the second input 434b. For example, the first input 432b and the second input 434b are coupled to the output of the decoder 246. Figure 4 In the example, the third input 436b is coupled to the output 412, the fourth input 437b is coupled to a reference voltage node (e.g., GND, zero volts, etc.), and the output 438b is coupled to the second array NMOS switch 244. In operation, the second level shifter 404b receives a first select signal (line 221) at the first input 432b, a second select signal (line 223) at the second input 434b, and a signal at the output 412 of the boost network 402. In operation, when the logic value at the first input 432b (e.g., the first select signal line 221) and the logic value at the second input 434b (e.g., the second select signal (line 223)) are logic high and logic low respectively, the second level shifter 404b shifts the voltage level of the signal at output 438b (e.g., the supplementary boost control signal (line 215a)) from the voltage level of the signal at the first input 432b (e.g., logic high or logic low) to the voltage level of the signal at the third input 436b (e.g., the voltage level of the signal at output 412).

[0056] exist Figure 4In the example shown, each of the first inverter 414, the second inverter 416, the third inverter 418, the fourth inverter 420, and the fifth inverter 422 is a NOT gate that includes both an input and an output. The input of the first inverter 414 is coupled to a first input 408, and the output of the first inverter 414 is coupled to the input of the second inverter 416. In operation, the first inverter 414 receives a control signal (line 213) and inverts the logic value of the control signal (line 213).

[0057] exist Figure 4 In the example shown, the input of the second inverter 416 is coupled to the output of the first inverter 414, and the output of the second inverter 416 is coupled to the input of the third inverter 418 and the input of the fourth inverter 420. In operation, the second inverter 416 receives the signal at the output of the first inverter 414 and inverts the logic value of the signal at the output of the first inverter 414.

[0058] exist Figure 4 In the example, the input of the third inverter 418 is coupled to the output of the second inverter 416, and the output of the third inverter 418 is coupled to the gate 440 of the first switch 424 and the gate 452 of the third switch 428. In operation, the third inverter 418 receives the signal at the output of the second inverter 416 and inverts the logic value of the signal at the output of the second inverter 416.

[0059] exist Figure 4 In the example shown, the input of the fourth inverter 420 is coupled to the output of the second inverter 416, and the output of the fourth inverter 420 is coupled to the input of the fifth inverter 422. In operation, the fourth inverter 420 receives the signal at the output of the second inverter 416 and inverts the logic value of the signal at the output of the second inverter 416.

[0060] exist Figure 4 In the example shown, the input of the fifth inverter 422 is coupled to the output of the fourth inverter 420, and the output of the fifth inverter 422 is coupled to the second terminal 460 of the capacitor 430. In operation, the fifth inverter 422 receives the signal at the output of the fourth inverter 420 and inverts the logic value of the signal at the output of the fourth inverter 420.

[0061] exist Figure 4In the example, the gate 440 of the first switch 424 is coupled to the output of the third inverter 418 and the gate 452 of the third switch 428. The source 442 of the first switch 424 is coupled to a reference voltage node (e.g., GND, zero volts, etc.). The drain 444 of the first switch 424 is coupled to the drain 456 of the third switch 428 and the gate 446 of the second switch 426. In operation, during a read operation of the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.), the logic value at the gate 440 of the first switch 424 can be a logic low value. Additionally, when no bit is read from the memory array, the logic value at the gate 440 of the first switch 424 can be a logic high value.

[0062] Therefore, before a read operation of the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.), the first switch 424 is enabled and the voltage level at the drain 450 of the first switch 424 can correspond to zero volts. During a read operation of the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204), the first switch 424 is deactivated.

[0063] exist Figure 4 In the example, the gate 446 of the second switch 426 is coupled to the drain 444 of the first switch 424 and the drain 456 of the third switch 428. The source 448 of the second switch 426 is coupled to the voltage input 406 (e.g., V) via the second input 410. DD The drain 450 of the second switch 426 is coupled to the source 454 of the third switch 428 and the first terminal 458 of the capacitor 430 (e.g., output 412). During operation, during read operations of the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.), the logic value at the gate 446 of the second switch 426 can be floating (e.g., at an indeterminate voltage level, rather than at zero voltage level, etc.). Additionally, when no bit is read from the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.), the logic value at the gate 446 of the second switch 426 can be a logic low value.

[0064] Therefore, before a read operation of the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.), the second switch 426 is enabled and the voltage level at the drain 450 of the second switch 426 can correspond to the voltage level at the voltage input 406 (e.g., V). DD During a read operation of the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.), the second switch 426 is deactivated.

[0065] exist Figure 4 In the example, the gate 452 of the third switch 428 is coupled to the output of the third inverter 418 and the gate 440 of the first switch 424. The source 454 of the third switch 428 is coupled to the drain 450 of the second switch 426 and the first terminal 458 (e.g., output 412) of the capacitor 430. The drain 456 of the third switch 428 is coupled to the gate 446 of the second switch 426 and the drain 444 of the first switch 424. In operation, during a read operation of the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.), the logic value at the gate 452 of the third switch 428 may be a logic low value. Additionally, when no bit is read from the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.), the logic value at the gate 452 of the third switch 428 may be a logic high value.

[0066] Therefore, the third switch 428 is deactivated before a read operation of the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.). During a read operation of the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.), the third switch 428 is activated and the voltage level at the source 454 of the third switch 428 can be floating and depends on the voltage level at the first terminal 458 of the capacitor 430.

[0067] exist Figure 4 In the example, capacitor 430 is a high-capacity capacitor. The first terminal 458 of capacitor 430 is coupled to the output 412, the source 454 of the third switch 428, and the drain 450 of the second switch 426. In operation, capacitor 430 is charged based on the voltage level at the drain 450 of the second switch 426. In operation, the voltage level at the second terminal 460 of capacitor 430 is used as the reference voltage level for output 412. For example, when a controller (e.g., controller 234) sends a control signal (line 213) to read a bit from a memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the logic value of the control signal (line 213) can be a logic high value. Therefore, the voltage level at the second terminal 460 of capacitor 430 can be a logic high voltage level. Additionally, when no bit is read from the memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), the logic value of the control signal (line 213) can be a logic low value. Therefore, the voltage level at the second terminal 460 of capacitor 430 can be zero volts.

[0068] Additionally, when no bits are read from the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.), the voltage value at the first terminal 458 (e.g., output 412) can be equal to the voltage level at the voltage input 406 (e.g., V). DD Furthermore, the voltage level at the second terminal 460 can be a logic low value (e.g., zero volts). Therefore, prior to a read operation of the memory array (e.g., first OTP memory array 202, second OTP memory array 204, etc.), capacitor 430 can be charged to the voltage level of voltage input 406 (e.g., V). DD When the controller (e.g., controller 234) transmits a logic high value as a control signal (line 213) (e.g., to initiate a read operation), the control signal (line 213) transitions from a logic low value to a logic high value. Before capacitor 430 discharges, the rising edge on the control signal (line 213) increases the voltage level at the second terminal 460 of capacitor 430 to a logic high value. Therefore, when capacitor 430 discharges, the voltage level at the first terminal 458 of capacitor 430 (e.g., output 412) is boosted.

[0069] Furthermore, because the voltage level of the signal at output 412 is boosted by the rising edge of the control signal (line 213), the first level shifter 404a and / or the second level shifter 404b respectively boost the voltage levels of the boosted control signal (line 215a) and / or the supplementally boosted control signal (line 215b) to the multiplexer 206. Therefore, the read operation of the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.) is improved in its reliable operating region. For example, because the voltage level of the signal at output 412 is boosted, one or more of the first array NMOS switches 240 or the second array NMOS switches 244 can be more fully saturated. Therefore, the bit current (I0) can be sensed more reliably by the sensing circuit (e.g., sensing circuit 208). BIT Furthermore, read operations on the memory array are improved within its reliable operating region. Additionally, due to the boost level at the output 412 of the boost network 402, memory bits, instructions, and / or other information stored in the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.) can be read by the processor, CPU, and / or other computing system without the need for additional volatile memory architecture.

[0070] Figure 5 It is shown Figure 4A schematic diagram illustrating further details of an example implementation of the first level shifter 404a and / or the second level shifter 404b. The example first level shifter 404a and / or the example second level shifter 404b includes an example shift network 502, an example first inverter 504, and an example second inverter 506. The example shift network 502 includes a first switch 508, a second switch 510, a third switch 512, a fourth switch 514, a fifth switch 516, and a sixth switch 518. The example first inverter 504 includes an example seventh switch 520 and an example eighth switch 522. The example second inverter 506 includes an example ninth switch 524 and an example tenth switch 526.

[0071] exist Figure 5 In the example, each of the first switch 508, the second switch 510, the eighth switch 522, and the tenth switch 526 is an NMOS transistor, which includes an example gate (e.g., a control terminal), an example drain (e.g., a current terminal), and an example source (e.g., a current terminal). Additionally, each of the third switch 512, the fourth switch 514, the fifth switch 516, the sixth switch 518, the seventh switch 520, and the ninth switch 524 is a PMOS transistor, which includes an example gate (e.g., a control terminal), an example drain (e.g., a current terminal), and an example source (e.g., a current terminal).

[0072] exist Figure 5 In the example shown, the gate of the first switch 508 is coupled to the first input 432a of the first level shifter 404a and / or the first input 432b of the second level shifter 404b and the gate of the fifth switch 516. The gate of the first switch 508 receives signals at the first input 432a (e.g., the second select signal (line 223)) and / or the first input 432b (e.g., the first select signal (line 221)). The drain of the first switch 508 is coupled to the drain of the fifth switch 516 and the gate of the third switch 512. The source of the first switch 508 is coupled to a reference voltage node (e.g., GND, zero volts, etc.) at the fourth input 437a and / or the fourth input 437b.

[0073] exist Figure 5In the example shown, the gate of the second switch 510 is coupled to the gate of the second input 434a and / or the second input 434b and the fourth switch 514. The gate of the second switch 510 receives signals at the second input 434a (e.g., the first select signal (line 221)) and / or the second input 434b (e.g., the second select signal (line 223)). The drain of the second switch 510 is coupled to the drain of the fourth switch 514, the gate of the sixth switch 518, the gate of the seventh switch 520, and the gate of the eighth switch 522. The source of the second switch 510 is coupled to a reference voltage node (e.g., GND, zero volts, etc.) at the fourth input 437a and / or the fourth input 437b.

[0074] exist Figure 5 In the example shown, the gate of the third switch 512 is coupled to the drain of the first switch 508 and the drain of the fifth switch 516. The drain of the third switch 512 is coupled to the source of the fourth switch 514, and the source of the third switch 512 is coupled to the third input 436a and / or the third input 436b and receives the signal at the output 412.

[0075] exist Figure 5 In the example shown, the gate of the fourth switch 514 is coupled to the gate of the second switch 510 and to the second input 434a and / or the second input 434b. The gate of the fourth switch 514 receives signals at the second input 434a (e.g., the first select signal (line 221)) and / or the second input 434b (e.g., the second select signal (line 223)). The drain of the fourth switch 514 is coupled to the drain of the second switch 510, the gate of the sixth switch 518, the gate of the seventh switch 520, and the gate of the eighth switch 522. The source of the fourth switch 514 is coupled to the drain of the third switch 512.

[0076] exist Figure 5 In the example, the gate of the fifth switch 516 is coupled to the gate of the first switch 508 and the first input 432a and / or the first input 432b. The gate of the fifth switch 516 receives signals at the first input 432a (e.g., the second select signal (line 223)) and / or the first input 432b (e.g., the first select signal (line 221)). The drain of the fifth switch 516 is coupled to the drain of the first switch 508 and the gate of the third switch 512. The source of the fifth switch 516 is coupled to the drain of the sixth switch 518.

[0077] exist Figure 5In the example shown, the gate of the sixth switch 518 is coupled to the drain of the second switch 510, the drain of the fourth switch 514, the gate of the seventh switch 520, and the gate of the eighth switch 522. The drain of the sixth switch 518 is coupled to the source of the fifth switch 516, and the source of the sixth switch 518 is coupled to the third input 436a and / or the third input 436b and receives the signal at the output 412.

[0078] In operation, the voltage level of the signal at the third input 436a and / or the third input 436b can correspond to the voltage level of the signal at the voltage input 406 (e.g., V). DD The voltage level is increased by the rising edge on the second terminal 460 of capacitor 430 as capacitor 430 discharges. The first switch 508 can be enabled and / or disabled based on the logic value of the signals at the first input 432a and / or the first input 432b. The second switch 510 is disabled. Additionally, the third switch 512 can be enabled and / or disabled based on the operation of the first switch 508 and / or the fifth switch 516. The fourth switch 514 is enabled. Furthermore, the fifth switch 516 can be enabled and / or disabled based on the logic value of the signals at the first input 432a and / or the first input 432b. The sixth switch 518 can be enabled and / or disabled based on the operation of the second switch 510 and / or the fourth switch 514.

[0079] For example, when shift network 502 receives a logic high value at first input 432a and / or first input 432b, first switch 508 is enabled and the logic value at the gate of third switch 512 is a logic low value, thereby enabling third switch 512. Since second switch 510 is disabled and fourth switch 514 is enabled, the voltage levels at the drain of second switch 510, the drain of fourth switch 514, the gate of sixth switch 518, the gate of seventh switch 520, and the gate of eighth switch 522 are set to the voltage levels of the signals at third input 436a and / or third input 436b.

[0080] When shift network 502 receives a logic low value at first input 432a and / or first input 432b, first switch 508 is deactivated, fifth switch 516 is activated, and the logic value at the gate of third switch 512 can be floating (e.g., at an indeterminate voltage level instead of a zero voltage level, etc.). Therefore, the voltage levels at the drain of second switch 510, the drain of fourth switch 514, the gate of sixth switch 518, the gate of seventh switch 520, and the gate of eighth switch 522 can be floating (e.g., at an indeterminate voltage level instead of a zero voltage level, etc.).

[0081] exist Figure 5In the example shown, the gate of the seventh switch 520 is coupled to the drain of the second switch 510, the drain of the fourth switch 514, the gate of the sixth switch 518, and the gate of the eighth switch 522. The drain of the seventh switch 520 is coupled to the drain of the eighth switch 522, the gate of the ninth switch 524, and the gate of the tenth switch 526. The source of the seventh switch 520 is coupled to the third input 436a and / or the third input 436b and receives the signal at the output 412.

[0082] exist Figure 5 In the example, the gate of the eighth switch 522 is coupled to the drain of the second switch 510, the drain of the fourth switch 514, the gate of the sixth switch 518, and the gate of the seventh switch 520. The drain of the eighth switch 522 is coupled to the drain of the seventh switch 520, the gate of the ninth switch 524, and the gate of the tenth switch 526. The source of the eighth switch 522 is coupled to the second input 434a and / or the second input 434b, and receives the first selection signal (line 221) and / or the second selection signal (line 223).

[0083] When the first inverter 504 receives a logic high value at the gate of the seventh switch 520 and the gate of the eighth switch 522, the eighth switch 522 is enabled, and the voltage levels at the drain of the seventh switch 520, the drain of the eighth switch 522, the gate of the ninth switch 524, and the gate of the tenth switch 526 are logic low values. When the first inverter 504 receives a logic low value at the gate of the seventh switch 520 and the gate of the eighth switch 522, the seventh switch 520 is enabled, and the voltage levels at the drain of the seventh switch 520, the drain of the eighth switch 522, the gate of the ninth switch 524, and the gate of the tenth switch 526 are the voltage levels of the signals at the third input 436a and / or the third input 436b.

[0084] exist Figure 5 In the example shown, the gate of the ninth switch 524 is coupled to the drain of the seventh switch 520 and the drain of the eighth switch 522. The drain of the ninth switch 524 is coupled to the drain of the tenth switch 526 and outputs 438a and / or 438b. The source of the ninth switch 524 is coupled to the third input 436a and / or the third input 436b and receives the signal at output 412.

[0085] exist Figure 5 In the example, the gate of the tenth switch 526 is coupled to the drain of the seventh switch 520 and the drain of the eighth switch 522. The drain of the tenth switch 526 is coupled to the drain of the ninth switch 524 and outputs 438a and / or 438b. The source of the tenth switch 526 is coupled to the second input 434a and / or the second input 434b, and receives the first selection signal (line 221) and / or the second selection signal (line 223).

[0086] When the second inverter 506 receives logic high values ​​at the gates of the ninth switch 524 and the tenth switch 526, the tenth switch 526 is enabled and the voltage levels at the drains of the ninth switch 524, the tenth switch 526, and outputs 438a and / or 438b are logic low. When the second inverter 506 receives logic low values ​​at the gates of the ninth switch 524 and the tenth switch 526, the ninth switch 524 is enabled, and the voltage levels at the drains of the ninth switch 524, the tenth switch 526, and outputs 438a and / or 438b are the voltage levels of the signals at the third inputs 436a and / or 436b.

[0087] Figure 6 It is a description Figure 2 and / or Figure 3 A schematic diagram 600 illustrates the operation of the boost circuit 236. The schematic diagram 600 includes an example first graph 602 and an example second graph 604. The example first graph 602 includes an example first line 606, and the example second graph 604 includes an example second line 608.

[0088] exist Figure 6 In the example, the first graph 602 is a graph of the control signal (line 213) versus time. The first graph 602 includes a voltage axis (V) 610 and a time axis (t) 612. The first line 606 corresponds to the voltage value of the signal (e.g., the control signal (line 213)) at the input of the boost circuit 236 (e.g., the first input 408).

[0089] exist Figure 6 In the example shown, the second graph 604 is a graph of the boost control signal (line 215a) and / or the supplementary boost control signal (line 215b) against time. The second graph 604 includes a voltage axis (V) 610 and a time axis (t) 612. The second line 608 corresponds to the voltage value of the signal (e.g., the boost control signal (line 215a) and / or the supplementary boost control signal (line 215b)) at the output of the boost circuit 236 (e.g., output 438a and / or output 438b).

[0090] exist Figure 6In the example, each of the first curve 602 and the second curve 604 includes a first time 614t1, a second time 616t2, a third time 618t3, and a fourth time 620t4. At the first time 614, the first line 606 transitions from a logic low value (e.g., zero volts) to a logic high value (e.g., 1.5 volts), and the second line 608 is at a voltage level of 1.5 volts. Due to the rising edge of the first line 606 at the first time 614, the boost network 402 of the boost circuit 236 boosts the voltage values ​​of the output 438a of the first level shifter 404a and / or the output 438b of the second level shifter 404b from 1.5 volts to 2.4049 volts. For example, the rising edge on the first line 606 causes the voltage level at the first terminal 458 (e.g., output 412) of the capacitor 430 to be boosted as the capacitor 430 discharges.

[0091] exist Figure 6 In the example shown, at the second time 616, the first line 606 is at a logic high value (e.g., 1.5 volts) and the second line 608 transitions from a voltage level of 2.4049 volts to a voltage level of 1.5 volts. For example, the second time 616 could correspond to the time when the capacitor 430 discharges due to the voltage change caused by the rising edge on the first line 606 at the first time 614.

[0092] exist Figure 6 In the example, at the third time 618, the first line 606 transitions from a logic low value (e.g., zero volts) to a logic high value (e.g., 1.5 volts) and the second line 608 is at a voltage level of 1.5 volts. Due to the rising edge of the first line 606 at the third time 618, the boost network 402 of the boost circuit 236 boosts the voltage value of the output 438a of the first level shifter 404a and / or the output 438b of the second level shifter 404b from 1.5 volts to 2.4049 volts. For example, the rising edge on the first line 606 causes the voltage level at the first terminal 458 (e.g., output 412) of the capacitor 430 to be boosted as the capacitor 430 discharges.

[0093] exist Figure 6 In the example shown, at the fourth time 620, the first line 606 is at a logic high value (e.g., 1.5 volts) and the second line 608 transitions from a voltage level of 2.4049 volts to a voltage level of 1.5 volts. For example, the fourth time 620 could correspond to the time when the capacitor 430 discharges due to the voltage change caused by the rising edge on the first line 606 at the third time 618.

[0094] exist Figure 6In the example, due to the increased voltage level of the second line 608 between the first time 614 and the second time 616, and between the third time 618 and the fourth time 620, read operations on the first memory array (e.g., the second OTP memory array 204) are improved in their reliable operating regions. Furthermore, due to the increased voltage level of the second line 608 between the first time 614 and the second time 616, and between the third time 618 and the fourth time 620, memory bits, instructions, and / or other information stored in the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.) can be read by the processor, CPU, and / or other computing systems without the need for additional volatile memory architecture.

[0095] Figure 7 Based on a more concentrated time scale Figure 2 and / or Figure 3 A diagrammatic illustration 700 illustrates the operation of the boost circuit 236. Diagram 700 includes an example graph 702. Example graph 702 includes an example first line 704 and an example second line 706.

[0096] exist Figure 7 In the example, graph 702 is a curve of the control signal (line 213) and the boosted control signal (line 215a) and / or the supplementary boosted control signal (line 215b) against time. Graph 702 includes a voltage axis (V) 708 and a time axis (t) 710. The first line 704 corresponds to the voltage value of the signal (e.g., the control signal (line 213)) at the input of the boost circuit 236 (e.g., the first input 408). The second line 706 corresponds to the voltage value of the signal (e.g., the boosted control signal (line 215a) and / or the supplementary boosted control signal (line 215b)) at the output of the boost circuit 236 (e.g., output 438a and / or output 438b).

[0097] exist Figure 7 In the example, graph 702 includes a first time 712t1, a second time 714t2, and a third time 716t3. At the first time 712, the first line 704 transitions from a logic low value (e.g., zero volts) to a logic high value (e.g., 1.5 volts) and the second line 706 is at a voltage level of 1.5 volts. Due to the rising edge of the first line 704 at the first time 712, the boost network 402 of the boost circuit 236 boosts the voltage values ​​of the output 438a of the first level shifter 404a and / or the output 438b of the second level shifter 404b from 1.5 volts to 2.4049 volts at the second time 714. For example, the rising edge on the first line 704 causes the voltage level at the first terminal 458 (e.g., output 412) of the capacitor 430 to be boosted as the capacitor 430 discharges.

[0098] exist Figure 7 In the example shown, at the third time 716, the first line 704 is at a logic high value (e.g., 1.5 volts) and the second line 706 transitions from a voltage level of 2.4049 volts to a voltage level of 1.5 volts. For example, the third time 716 could correspond to the time when the capacitor 430 discharges due to the voltage change caused by the rising edge on the first line 704 at the first time 712.

[0099] exist Figure 7 In the example, due to the increased voltage level of the second line 706 between the second time 714 and the third time 716, read operations on the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.) are improved in their reliable operating regions. Furthermore, due to the increased voltage level of the second line 706 between the second time 714 and the third time 716, memory bits, instructions, and / or other information stored in the memory array (e.g., the first OTP memory array 202, the second OTP memory array 204, etc.) can be read by the processor, CPU, and / or other computing systems without the need for additional volatile memory architecture.

[0100] When in Figure 3 , Figure 4 and Figure 5 Implementation as shown in the diagram Figure 2 When the controller 234 and / or boost circuit 236 are used in the example configuration, they can be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Figure 3 , Figure 4 and Figure 5 One or more of the components, processes, and / or devices illustrated. Furthermore, example signal analyzer 302, example signal generator 304, example sensing interface 306, and / or more generally, Figure 2 and Figure 3 Example controller 234 and / or example boost network 402, example first level shifter 404a, example second level shifter 404b, example voltage input 406, example first inverter 414, example second inverter 416, example third inverter 418, example fourth inverter 420, example fifth inverter 422, example first switch 424, example second switch 426, example third switch 428, example capacitor 430 and / or more generally, Figure 2 and Figure 4Example boost circuit 236, and / or example shift network 502, example first inverter 504, example second inverter 506, example first switch 508, example second switch 510, example third switch 512, example fourth switch 514, example fifth switch 516, example sixth switch 518, example seventh switch 520, example eighth switch 522, example ninth switch 524, example tenth switch 526 and / or more generally, Figure 4 and / or Figure 5 The example first level shifter 404a and / or the example second level shifter 404b can be implemented by hardware, software, firmware, and / or any combination of hardware, software, and / or firmware. Thus, for example, the example signal analyzer 302, the example signal generator 304, the example sensing interface 306, and / or more generally, Figure 2 and Figure 3 Example controller 234, and / or example boost network 402, example first level shifter 404a, example second level shifter 404b, example voltage input 406, example first inverter 414, example second inverter 416, example third inverter 418, example fourth inverter 420, example fifth inverter 422, example first switch 424, example second switch 426, example third switch 428, example capacitor 430, and / or more generally, Figure 2 and Figure 4 Example boost circuit 236, and / or example shift network 502, example first inverter 504, example second inverter 506, example first switch 508, example second switch 510, example third switch 512, example fourth switch 514, example fifth switch 516, example sixth switch 518, example seventh switch 520, example eighth switch 522, example ninth switch 524, example tenth switch 526, and / or more generally, Figure 4 and Figure 5 Any of the example first level shifter 404a and / or example second level shifter 404b can be implemented by one or more analog or digital circuits, logic circuits, one or more programmable processors, one or more programmable controllers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more application-specific integrated circuits (ASICs), one or more programmable logic devices (PLDs), and / or one or more field-programmable logic devices (FPLDs). When reading any of the device or system claims of this patent to cover purely software and / or firmware implementations, the example signal analyzer 302, example signal generator 304, example sensing interface 306, and / or more generally, Figure 2 and Figure 3Example controller 234, and / or example boost network 402, example first level shifter 404a, example second level shifter 404b, example voltage input 406, example first inverter 414, example second inverter 416, example third inverter 418, example fourth inverter 420, example fifth inverter 422, example first switch 424, example second switch 426, example third switch 428, example capacitor 430, and / or more generally, Figure 2 and Figure 4 Example boost circuit 236, and / or example shift network 502, example first inverter 504, example second inverter 506, example first switch 508, example second switch 510, example third switch 512, example fourth switch 514, example fifth switch 516, example sixth switch 518, example seventh switch 520, example eighth switch 522, example ninth switch 524, example tenth switch 526 and / or more generally, Figure 4 and Figure 5 At least one of the example first level shifter 404a and / or second level shifter 404b is hereby explicitly defined as including a non-transitory computer-readable storage device or storage disk containing software and / or firmware, such as a memory, digital versatile disc (DVD), compact disc (CD), Blu-ray disc, etc. Furthermore, Figure 2 and Figure 3 Example controller 234 Figure 2 and Figure 4 Example boost circuit 236, and / or Figure 4 and Figure 5 Example first level shifter 404a and / or example second level shifter 404b may include, in addition to Figure 2 , Figure 3 , Figure 4 and / or Figure 5 Other than or in place of those shown in the diagram Figure 2 , Figure 3 , Figure 4 and / or Figure 5 The elements, processes, and / or devices illustrated herein may include one or more of the illustrated elements, processes, and devices. As used herein, the phrase “communication”, including its variations, includes direct and / or indirect communication via one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or continuous communication, but additionally includes selective communication at periodic intervals, predetermined intervals, non-periodic intervals, and / or one-off events.

[0101] exist Figure 8 and Figure 9 The diagram shows the representation used for implementation. Figure 2 and Figure 3 Example controller 234 Figure 2 and Figure 4 Example boost circuit 236, and / or Figure 4 and Figure 5 The flowcharts illustrate example hardware logic, machine-readable instructions, hardware-implemented state machines, and / or any combination thereof for example first level shifter 404a and / or example second level shifter 404b. Machine-readable instructions can be generated by a computer processor (e.g., as described below in conjunction with...). Figure 10 The processor 1012 shown in the example processor platform 1000 discussed here executes one or more executable programs or portions thereof. The program may be embodied in software stored on a non-transitory computer-readable storage medium (e.g., CD-ROM, floppy disk, hard disk drive, DVD, Blu-ray disc, or memory associated with the processor 1012), but the entire program and / or portions thereof may alternatively be executed by a device other than the processor 1012 and / or embodied in firmware or dedicated hardware. Furthermore, although references... Figure 8 and Figure 9 The flowchart illustrated in the figure describes the example program, but alternative implementations can be used. Figure 2 and Figure 3 Example controller 234 Figure 2 and Figure 4 Example boost circuit 236 and / or Figure 4 and Figure 5 Examples of the first level shifter 404a and / or the second level shifter 404b, and many other methods. For example, the execution order of the blocks can be changed, and / or some of the described blocks can be changed, eliminated, or combined. Additionally or alternatively, any or all blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuits, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) configured to perform the corresponding operations without executing software or firmware.

[0102] The machine-readable instructions described herein can be stored in one or more of the following formats: compressed, encrypted, fragmented, packaged, etc. Machine-readable instructions as described herein can be stored as data (e.g., portions of instructions, code, code representations, etc.) that can be used to create, manufacture, and / or produce machine-executable instructions. For example, machine-readable instructions can be fragmented and stored on one or more storage devices and / or computing devices (e.g., servers). Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, and redistributed to make them directly readable and / or executable by computing devices and / or other machines. For example, machine-readable instructions can be stored in multiple parts that are individually compressed, encrypted, and stored on separate computing devices, where these parts, when decrypted, decompressed, and combined, form a set of executable instructions that implement programs, such as those described herein. In another example, machine-readable instructions can be stored in a state where they can be read by a computer, but require the addition of libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., to execute the instructions on a specific computing device or other device. In another example, it may be necessary to configure the machine-readable instructions (e.g., storage settings, data input, recorded network addresses, etc.) before they can be executed in whole or in part. Therefore, the disclosed machine-readable instructions and / or / one or more corresponding programs are intended to cover such machine-readable instructions and / or / one or more programs, regardless of their specific format or state when stored or otherwise at rest or in transit.

[0103] The machine-readable instructions described in this article can be represented using any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0104] As mentioned above, Figure 8 and Figure 9The example process can be implemented using executable instructions (e.g., computer and / or machine-readable instructions) stored on non-transitory computer and / or machine-readable media (e.g., hard disk drives, flash memory, read-only memory, compact disks, digital multifunction disks, caches, random access memory, and / or any other storage device or disk), where information is stored for any duration (e.g., extended time periods, permanently, for brief instances, temporary buffers, and / or cached information). As used herein, the term non-transitory computer-readable media is explicitly defined to include any type of computer-readable storage device and / or disk and excludes propagation signals and transmission media.

[0105] "Comprising" and "including" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a claim uses any form of "comprising" or "including" (e.g., including, comprising, having, etc.) as a preamble or in any type of claim statement, it should be understood that additional elements, terms, etc., may be present without exceeding the scope of the corresponding claim or statement. As used herein, when the phrase "at least" is used as a transitional term, for example, in the preamble of a claim, it is open-ended in the same way as the terms "comprising" and "including". The term "and / or" when used in the form of, for example, A, B, and / or C, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, and (7) A and B and C. As used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A and B" is intended to refer to an implementation that includes any one of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects, and / or things, the phrase "at least one of A or B" is intended to refer to an implementation that includes any one of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. As used herein in the context of describing the implementation or execution of processes, instructions, actions, activities, and / or steps, the phrase "at least one of A and B" is intended to refer to an implementation that includes any one of (1) at least one A, (2) at least one B, and (3) at least one A and at least one B. Similarly, as used herein in the context of describing the implementation or execution of processes, instructions, actions, activities and / or steps, the phrase “at least one of A or B” is intended to refer to an implementation that includes (1) at least one A, (2) at least one B and (3) at least one A and at least one B.

[0106] As used herein, singular references (e.g., "a," "an," "first," "second," etc.) do not exclude plurals. As used herein, the term "a" or "an" refers to one or more of that entity. The terms "a" (or "an"), "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple means, elements, or method actions can be implemented by, for example, a single unit or processor. Additionally, while individual features may be included in different examples or claims, they may be combined, and inclusion in different examples or claims does not imply that combining features is impractical and / or not advantageous.

[0107] Figure 8 This is a flowchart representing process 800, which can be implemented by example machine-readable instructions that can be executed to perform the process. Figure 2 and Figure 3 Controller 234. In Figure 8 In the example shown, Figure 3 Signal analyzer 302 determines whether an indication to sense and / or read memory bits is obtained and / or otherwise received (block 802). If the control at block 802 returns no (e.g., if no indication to sense and / or read memory bits is obtained or received), control proceeds to block 802 and waits. Alternatively, if the control at block 802 returns yes (e.g., if signal analyzer 302 obtains or receives an indication to sense and / or read memory bits), signal analyzer 302 determines which memory cell to access (e.g., first OTP memory cell 210, second OTP memory cell 212, third OTP memory cell 214, and / or fourth OTP memory cell 216) based on the received indication (block 804). In response to the execution of control at block 806, control proceeds to block 808.

[0108] At block 806, sensing interface 306 determines a memory array that includes selected memory cells from the memory cells. At block 808, sensing interface 306 generates control signals (e.g., control signal (line 213)) and / or decoding signals (e.g., decoding signal (line 231)) to enable the conduction of the corresponding PMOS and NMOS switches of multiplexer 206 (block 808). In response to the execution of control at block 808, control proceeds to block 810.

[0109] In response Figure 2 and Figure 3Controller 234 determines whether to continue operation (block 810). If the control at block 810 returns yes (e.g., controller 234 determines to continue operation), control returns to block 802. Alternatively, if the control at block 810 returns no (e.g., controller 234 determines not to continue operation), process 800 stops.

[0110] Figure 9 This is a flowchart representing process 900, which can be implemented by example machine-readable instructions that can be executed to perform the process. Figure 2 , Figure 4 and Figure 5 The boost circuit 236. In Figure 9 In this configuration, the boost network monitors the signal at the first input 408 (box 902). In response to a rising edge of the signal at the first input 408 (box 904: Yes), the boost network 402 boosts the voltage level of the signal to be transmitted to the first level shifter 404a and / or the second level shifter 404b (e.g., boosts the voltage level of the signal at the output 412 of the boost network 402) (box 908). When no rising edge is detected on the signal at the first input 408 (box 904: No), the boost network 402 applies a voltage input to the signal at 406 (e.g., V). DD The signal is transmitted to the first level shifter 404a and / or the second level shifter 404b, which transmits the signal to the multiplexer 206 (box 906).

[0111] After receiving a signal at output 412 of boost network 402, first level shifter 404a and / or second level shifter 404b determine whether the selection signals (lines 221, 223) indicate the transmission of a complementary boost control signal (line 215b) to the multiplexer (block 910). For example, if the first selection signal (line 221) is logic low and the second selection signal (line 223) is logic high, then first level shifter 404a can transmit the boost control signal (line 215a) to first array NMOS switch 240, and second level shifter 404b can transmit a reference voltage to second array NMOS switch 244. For example, if the first select signal (line 221) is logic high and the second select signal (line 223) is logic low, the first level shifter 404a can transmit the reference voltage to the first array NMOS switch 240, and the second level shifter 404b can transmit a supplementary boost control signal (line 215b) to the second array NMOS switch 244. In response to the select signals (lines 221, 223) indicating the transmission of the supplementary boost control signal (box 910: Yes), the second level shifter 404b transmits the supplementary boost control signal (line 215a) to the multiplexer 206 (box 914). In response to the select signals (lines 221, 223) indicating the transmission of the boost control signal (box 910: No), the first level shifter 404a transmits the boost control signal (line 215a) to the multiplexer 206 (box 912). After the signal at output 412 of boost network 402 is transmitted to multiplexer 206 (either boosted at block 914, boosted at block 912, or not boosted at block 906), boost circuit 236 determines whether to continue operation (block 916). If boost circuit 236 determines to continue operation (e.g., execution of block 916 returns to yes), control proceeds to block 902. Alternatively, in response to boost circuit 236 determining not to continue operation (e.g., execution of block 916 returns to no), process 900 stops.

[0112] Figure 10 It is constructed to execute Figure 8 and Figure 9 To implement the instructions Figure 2 and Figure 3 Example controller 234 Figure 2 and Figure 4 Example boost circuit 236 and / or Figure 4 and Figure 5The example first level shifter 404a and / or the second level shifter 404b are block diagrams of an example processing platform. For example, the processor platform 1000 may be a server, personal computer, workstation, self-learning machine (e.g., neural network), mobile device (e.g., mobile phone, smartphone, tablet computer such as iPad™), personal digital assistant (PDA), internet infrastructure, DVD player, CD player, digital video recorder, Blu-ray player, game console, personal video recorder, set-top box, headphones or other wearable device, or any other type of computing device.

[0113] The processor platform 1000 shown in the example includes a processor 1012. The processor 1012 shown in the example is hardware. For example, the processor 1012 can be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer. The hardware processor can be a semiconductor-based (e.g., silicon-based) device. In this example, the processor implements an example signal analyzer 302, an example signal generator 304, an example sensing interface 306, and / or more generally, Figure 2 and Figure 3 Example controller 234, and / or example boost network 402, example first level shifter 404a, example second level shifter 404b, example voltage input 406, example first inverter 414, example second inverter 416, example third inverter 418, example fourth inverter 420, example fifth inverter 422, example first switch 424, example second switch 426, example third switch 428, example capacitor 430, and / or more generally, Figure 2 and Figure 4 Example boost circuit 236, and / or example shift network 502, example first inverter 504, example second inverter 506, example first switch 508, example second switch 510, example third switch 512, example fourth switch 514, example fifth switch 516, example sixth switch 518, example seventh switch 520, example eighth switch 522, example ninth switch 524, example tenth switch 526 and / or more generally, Figure 4 and Figure 5 Examples include the first level shifter 404a and / or the second level shifter 404b.

[0114] The processor 1012 of the illustrated example includes local memory 1013 (e.g., cache). The processor 1012 of the illustrated example communicates via bus 1018 with main memory, which includes volatile memory 1014 and non-volatile memory 1016. Volatile memory 1014 may be synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), etc. Dynamic Random Access Memory It may be implemented using flash memory and / or any other type of random access memory device. The non-volatile memory 1016 may be implemented using flash memory and / or any other desired type of memory device. Access to the main memory 1014, 1016 is controlled by the memory controller.

[0115] The processor platform 1000 shown in the example also includes interface circuitry 1020. Interface circuitry 1020 can be implemented using any type of interface standard, such as an Ethernet interface, Universal Serial Bus (USB), etc. Interfaces, Near Field Communication (NFC) interfaces, and / or PCI Express interfaces.

[0116] In the example shown, one or more input devices 1022 are connected to interface circuitry 1020. The input devices 1022 allow users to input data and / or commands into processor 1012. The input devices may be implemented, for example, audio sensors, microphones, cameras (still or video), keyboards, buttons, mice, touchscreens, touchpads, trackballs, isopoints, and / or voice recognition systems.

[0117] One or more output devices 1024 are also connected to the interface circuitry 1020 of the illustrated example. The output devices 1024 may be implemented, for example, via display devices (e.g., light-emitting diodes (LEDs), organic light-emitting diodes (OLEDs), liquid crystal displays (LCDs), cathode ray tube displays (CRTs), in-plane switching (IPS) displays, touchscreens, etc.), haptic output devices, printers, and / or speakers. Therefore, the interface circuitry 1020 of the illustrated example typically includes a graphics driver card, a graphics driver chip, and / or a graphics driver processor.

[0118] The interface circuitry 1020 of the example shown also includes communication devices such as transmitters, receivers, transceivers, modems, residential gateways, wireless access points, and / or network interfaces to facilitate data exchange with external machines (e.g., any kind of computing device) via network 1026. Communication can be via, for example, Ethernet connections, digital subscriber line (DSL) connections, telephone line connections, coaxial cable systems, satellite systems, line-of-site wireless systems, cellular telephone systems, etc.

[0119] The processor platform 1000 shown in the example also includes one or more mass storage devices 1028 for storing software and / or data. Examples of such mass storage devices 1028 include floppy disk drives, hard disk drives, compact disk drives, Blu-ray disk drives, redundant array of independent disks (RAID) systems, and digital multifunction disk (DVD) drives.

[0120] Figure 8 and Figure 9 The machine-executable instructions 1032 can be stored in a mass storage device 1028, volatile memory 1014, non-volatile memory 1016 and / or a removable non-transitory computer-readable storage medium (such as a CD or DVD).

[0121] As can be understood from the foregoing, example methods, apparatuses, and articles of art have been disclosed to reduce the power consumption of computing devices. These example methods, apparatuses, and articles of art improve the reliable operating area of ​​a memory array for read operations. Furthermore, the example methods, apparatuses, and articles of art disclosed herein read memory bits, instructions, and / or other information stored in a memory array without using additional volatile memory architecture. The examples disclosed herein reduce the computational burden of accessing memory. The disclosed methods, apparatuses, and articles of art improve the efficiency of using computing devices by reducing power consumption and increasing the operating area on which memory can be read. The disclosed methods, apparatuses, and articles of art thus address one or more improvements in computer functionality.

[0122] Although certain example methods, apparatuses, and articles of manufacture have been disclosed herein, the scope of this patent is not limited thereto. Rather, this patent covers all methods, apparatuses, and articles of manufacture that fall fully within the scope of the claims of this patent.

Claims

1. An apparatus for operating a memory array, the apparatus comprising: A boost circuit, the boost circuit including a first output, a second output, a first input configured to be coupled to a controller, a second input coupled to a first output of a decoder, and a third input coupled to the second output of the decoder; as well as A multiplexer, the multiplexer including a first input coupled to the first output of the boost circuit, a second input coupled to the second output of the boost circuit, a third input coupled to the memory array, and an output coupled to the sensing circuit; The boost circuit includes a boost network, which includes: The first input and output of the boost circuit; A first level shifter has a first input and a second input coupled to the first output and the second output of the decoder, respectively, a third input coupled to the output of the boost network, and an output coupled to the first input of the multiplexer; and The second level shifter has a first input and a second input coupled to the first output and the second output of the decoder, respectively, a third input coupled to the output of the boost network, and an output coupled to the second input of the multiplexer; The boost network is configured as follows: The transmission includes a signal comprising voltage levels, wherein the signal is transmitted by a first level shifter to a first input of the multiplexer or by a second level shifter to a second input of the multiplexer; and In response to a rising edge on a control signal transmitted to the first input of the boost network, the voltage level of the signal is increased.

2. The apparatus of claim 1 further includes an inverter, the inverter having an output coupled to the multiplexer and an input coupled to the first output of the decoder.

3. The apparatus according to claim 2, wherein: The memory array is a first memory array; and The multiplexer includes: The first n-channel transistor includes a control terminal coupled to the first output of the boost circuit, a first current terminal coupled to the first p-channel transistor and the first current terminal of the first memory array, and a second current terminal coupled to the first p-channel transistor and the second current terminal of the sensing circuit. as well as The second n-channel transistor includes a control terminal coupled to the second output of the boost circuit, a first current terminal coupled to the second memory array and the first current terminal of the second p-channel transistor, and a second current terminal coupled to the second p-channel transistor and the second current terminal of the sensing circuit.

4. The apparatus of claim 3, wherein the multiplexer comprises: The first p-channel transistor includes a control terminal coupled to the first output of the decoder, a first current terminal coupled to the first memory array and the first current terminal of the first n-channel transistor, and a second current terminal coupled to the sensing circuit and the second current terminal of the first n-channel transistor. as well as The second p-channel transistor includes a control terminal coupled to the output of the inverter, a first current terminal coupled to the first current terminal of the second memory array and the second n-channel transistor, and a second current terminal coupled to the sensing circuit and the second current terminal of the second n-channel transistor.

5. The apparatus of claim 1, wherein the memory array comprises a one-time programmable memory array.

6. The apparatus of claim 1, wherein the multiplexer comprises an n-channel transistor coupled to a memory array.

7. The apparatus of claim 1, wherein the multiplexer is operable to select a one-time programmable memory array.

8. A method for operating a memory array performed by the apparatus of claim 1, comprising: Provide a signal with a first voltage; Receive control signals from the controller; In response to the rising edge of the control signal, the signal is boosted from the first voltage to the second voltage, and the signal is maintained at the second voltage for a first time period; Based on the selection signal, the signal is provided to the gate of the first transistor of the multiplexer; as well as During the first time period, bit current is transferred from the memory cell to the sensing circuit through the first transistor.

9. The method of claim 8, wherein the memory array is a first memory array, the first transistor is a first n-channel transistor coupled to the first memory array, and the multiplexer further includes a second n-channel transistor coupled to a second memory array.

10. The method of claim 9, wherein the first memory array and the second memory array comprise a one-time programmable memory array.

11. The method of claim 8, further comprising: The memory bits are transferred from the sensing circuit to the computing system.

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