Low power memory

Abstract

A charge transfer transistor is coupled between the bit line and a sense node for a sense amplifier. During a read operation, a charge transfer driver drives a gate voltage of the charge transfer transistor to control whether the charge transfer transistor turns on during a charge transfer period. Prior to the charge transfer period, a bit cell is coupled to the bit line to drive a bit cell influence voltage onto the bit line. The charge transfer driver drives the gate voltage such that the charge transfer transistor turns on only when the bit cell influence voltage is equal to a pre-charge voltage of the bit line.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to U.S. Nonprovisional Patent Application No. 16 / 849,616, filed April 15, 2020, and U.S. Provisional Patent Application No. 62 / 835,160, filed April 17, 2019, each of which is incorporated herein by reference in its entirety as if fully set forth below and for all applicable purposes. Technical Field

[0003] This application relates to memory, and more specifically to low-power memory. Background Technology

[0004] In conventional static random access memory (SRAM), a bit cell is connected to a pair of bit lines during a read operation. Before the read operation, the bit lines are precharged to the supply voltage for the bit cell. Depending on the binary content of the bit cell, either the true bit line or the complementary bit line in the bit line pair will slightly discharge from its precharged state. For example, a false bit cell stores a binary 1. Due to the binary 1 value, the complementary bit line will then discharge from its precharged state, which was charged to the supply voltage. However, the bit cell will retain the true bit line in its precharged state.

[0005] Therefore, a read operation will generate a voltage difference across the bit line pair. This bit line voltage difference is not a full rail difference, but rather a fraction of the supply voltage. For example, if the supply voltage is 1 volt, this voltage difference might be only 100 millivolts or less. To respond to such a relatively small voltage difference, a relatively high-power sense amplifier with reduced density is typically required.

[0006] Therefore, there is a need in the art for a memory in which the sense amplifier has increased density and improved power efficiency. Summary of the Invention

[0007] According to a first aspect of this disclosure, a memory is provided, the memory comprising: a bit line; a bit cell configured to charge the bit line to a bit cell influence voltage during a word line assertion period in response to a bit stored in the bit cell; a sense amplifier; a first sense node for the sense amplifier; a first charge transfer transistor having a source connected to the bit line and a drain connected to the first sense node; and a charge transfer driver configured to charge the gate of the first charge transfer transistor to a gate voltage during a charge transfer period to turn on the first charge transfer transistor in response to a stored bit being equal to a first binary value, and to keep the first charge transfer transistor off in response to a stored bit being equal to the complement of the first binary value.

[0008] According to a second aspect of this disclosure, a method is provided for sensing a bit stored by a bit cell using a charge transfer transistor, the method comprising: pre-charging a bit line to an amount equal to a pre-charge voltage while turning off a charge transfer transistor having a source connected to the bit line and a drain connected to a sensing node to isolate the sensing node from the bit line; after pre-charging the bit line, coupling the bit cell to the bit line while the charge transfer transistor remains off to charge the bit line to a bit cell influence voltage, the bit cell influence voltage being equal to the pre-charge voltage in response to the bit being equal to a first binary value, and the bit cell influence voltage differing from the pre-charge voltage by a bit line difference voltage in response to the bit being equal to a second binary value; charging the gate of the charge transfer transistor to a gate voltage during a charge transfer period, wherein the difference between the gate voltage and the bit cell influence voltage causes the charge transfer transistor to turn on in response to the bit being equal to the first binary value, and wherein the difference between the gate voltage and the bit cell influence voltage causes the charge transfer transistor to remain off in response to the bit being equal to the second binary value; and after the charge transfer period ends, sensing the bit in response to inverting the voltage of the sensing node.

[0009] According to a third aspect of this disclosure, a memory is provided, the memory comprising: a bit line; a bit cell configured to charge the bit line to a bit cell in response to a bit stored by the bit cell during a read operation; a sense amplifier inverter; a charge transfer transistor coupled between the bit line and a sense node for the sense amplifier inverter; and a discharge circuit configured to discharge the sense node to ground before a charge transfer period of the charge transfer transistor.

[0010] According to a fourth aspect of this disclosure, a memory is provided, the memory comprising: a bit line; a bit cell configured to charge the bit line to a bit cell influence voltage during a read operation in response to a bit stored by the bit cell; a sense amplifier inverter; a charge transfer transistor coupled between the bit line and a sense node for the sense amplifier inverter; and a charging circuit configured to charge the sense node to a power supply voltage before a charge transfer period of the charge transfer transistor.

[0011] These and other advantages can be better understood through the following detailed description. Attached Figure Description

[0012] Figure 1 A memory with single-ended PMOS charge transfer sensing according to one aspect of the present disclosure is shown.

[0013] Figure 2 This shows the source-to-gate voltage as a function of the charge transfer transistor. Figure 1 The waveform of the current conducted by the charge transfer transistor in the memory.

[0014] Figure 3 This illustrates an embodiment of the present disclosure for providing Figure 1 The charge transfer transistor in the memory is a diode-connected transistor that generates the gate voltage.

[0015] Figure 4 A memory with dual-ended charge transfer sensing according to one aspect of the present disclosure is shown.

[0016] Figure 5 A memory with single-ended NMOS charge transfer sensing according to one aspect of the present disclosure is shown.

[0017] Figure 6 This is a flowchart of a method for sensing the binary content of a bit cell using charge transfer technology according to one aspect of this disclosure.

[0018] Figure 7 Some example electronic systems are shown, each incorporating a memory according to one aspect of this disclosure.

[0019] The embodiments and advantages of this disclosure can be best understood by referring to the following detailed description. It should be understood that similar reference numerals are used to identify one or more similar elements shown in the figures. Detailed Implementation

[0020] To improve density and power efficiency, a charge-transfer transistor is disclosed for coupling the sense node of a sense amplifier to a bit line during a read operation. The source of the charge-transfer transistor is bound to the bit line, while its drain is bound to the sense node. The resulting charge transfer is highly efficient, allowing the use of only a single bit line in some implementations. Alternatively, bit line pairs can assist in the charge transfer. In column multiplexing implementations, the charge-transfer transistor can be used as a column multiplexer transistor. Although the sense amplifier is typically coupled to the bit line via a column multiplexer transistor, note that the conventional column multiplexer transistor is controlled as a switch, such that it is fully turned on during the read operation while the sense node is coupled to the bit line.

[0021] Compared to this conventional all-on operation, the gate of the charge-transfer transistor is charged to a gate voltage that causes the charge-transfer transistor to conduct with only one polarity for the binary value stored in the accessed bit cell. Before the assertion word line voltage during the read operation, the bit line is charged to a pre-charge voltage while the charge-transfer transistor remains off. Then, while the charge-transfer transistor is still off, the assertion word line voltage is applied to couple the bit cell to the pre-charged bit line. The bit cell then charges the pre-charged bit line to the bit cell's influence voltage, which depends on the bit cell's binary content.

[0022] If the bit cell stores the first binary value, the bit cell influence voltage equals the bit line precharge voltage. However, if the bit cell stores the second binary value (the complement of the first binary value), the bit cell influence voltage differs from the precharge voltage by the bit line voltage difference (dvbl). As the bit cell influence voltage increases, the charge transfer period can begin while the word line voltage is still asserted. During the charge transfer period, the charge transfer driver charges the gate voltage of the charge transfer transistor so that its amplitude is between ground and the supply voltage VDD. Since the source voltage of the charge transfer transistor equals the bit cell influence voltage, during the charge transfer period, the gate-to-source voltage of the charge transfer transistor equals the difference between the gate voltage and the bit cell influence voltage. If the accessed bit cell stores the first binary value such that the bit cell influence voltage equals the bit line precharge voltage, the gate-to-source voltage of the charge transfer transistor satisfies the threshold voltage of the charge transfer transistor, causing the charge transfer transistor to conduct charge to change the sense node voltage from the default voltage established before the charge transfer period. However, if the accessed bit cell stores a second binary value (the complement of the first binary value), the gate-to-source voltage will change the bit line voltage difference, thus failing to meet the threshold voltage during the charge transfer period.

[0023] A surprising result is that the charge transfer depends on the binary state stored in the bit cell. If the binary state equals a first binary value, the charge transfer transistor turns on to change the sense node voltage from its default value. However, if the binary state equals a second binary value, the charge transfer transistor does not charge, allowing the sense node voltage to remain at its default value. Note that the capacitance of the sense node is relatively small compared to the bit line capacitance. The charge conduction of the charge transfer transistor thus rapidly changes its state from the default state to a state substantially equal to the bit cell influence voltage. The charge transfer obtained through this charge transfer is therefore used to amplify the bit line difference voltage in a substantially full-track manner. In conventional SRAM, the sense amplifier must be relatively sensitive to the bit line voltage difference. In stark contrast, a simple inverter can be used in this paper to sense the sense node voltage because the sense node voltage swings dramatically from its default voltage due to the amplification provided by the charge transfer function.

[0024] Note that the preceding discussion is generalized to the polarity of charge-transfer transistors. It can be either a p-type metal-oxide-semiconductor (PMOS) transistor or an n-type metal-oxide-semiconductor (NMOS) transistor. In both cases, the source is bonded to the bit line, and the drain is bonded to the sense node. However, the polarity is reversed. In a PMOS implementation, the bit line is pre-charged to the supply voltage VDD, while the default voltage of the sense node is ground. But in an NMOS implementation, the bit line is pre-charged through ground, and the default voltage of the sense node will be equal to the supply voltage. The following discussion will focus on the PMOS implementation, followed by the NMOS implementation.

[0025] In a PMOS charge-transfer embodiment, the bit line is pre-charged to the supply voltage VDD before the word line is activated. The sense node discharges to ground to its default state, and the sense node is isolated from the pre-charged bit line by a PMOS charge-transfer transistor. As the word line is asserted, the bit cell can then drive the pre-charged bit line to be equal to the bit cell effect voltage. If the binary content stored in the bit cell is equal to a first binary value, the bit cell effect voltage is equal to the supply voltage VDD. However, if the binary content is equal to a second binary value, the bit cell effect voltage decreases from the supply voltage to the bit line voltage difference. The following discussion will assume that the first binary value is a binary 1 (logic 1) value and the second binary value is a binary 0 (logic 0) value, but these values ​​may be reversed in alternative implementations.

[0026] As previously mentioned, the bit line voltage difference can be a relatively small value, such as 100 millivolts or even lower. However, this small difference becomes significant due to the charge transfer amplification achieved by the PMOS charge transfer transistor. Because the word line is asserted, creating a bit cell influence voltage on the bit line, the PMOS charge transfer transistor does not simply turn on fully as in conventional memory. Instead, the gate voltage of the PMOS charge transfer transistor charges such that the difference between the supply voltage and the gate voltage is equal to or slightly less than the absolute value of the PMOS charge transfer transistor's threshold voltage. If the bit cell stores a binary 1 value, the bit cell influence voltage is equal to the supply voltage VDD. Therefore, the source-to-gate voltage of the PMOS charge transfer transistor is slightly greater than the absolute value of the threshold voltage, causing the PMOS charge transfer transistor to turn on to transfer charge from the bit line to the discharge sensing node. However, if the bit cell stores a binary 0 value, the source-to-gate voltage of the PMOS charge transfer transistor will be slightly less than the supply voltage because the bit cell voltage value decreases. Therefore, when the bit cell stores a binary 0 due to the threshold voltage not being met, the PMOS charge transfer transistor continues to isolate the discharge sensing node.

[0027] The charge transfer amplification resulting from the difference between the bit line capacitance and the sensing node capacitance is highly advantageous because the sensing amplifier can simply be an inverter. Such an inverter-sensing amplifier then senses the binary content of the bit cell by inverting the sensing node voltage. If the binary content of the bit cell is binary 0, the inverter output will therefore be equal to the supply voltage. Conversely, if the binary content of the bit cell is binary 1, the inverter output will be equal to ground. In stark contrast, conventional memories cannot use inverters as sensing amplifiers because conventional sensing amplifiers must make bit decisions based on relatively small bit line voltage differences.

[0028] The NMOS implementation complements the PMOS implementation by discharging the bit line before a read operation instead of pre-charging it. Before the read operation, the sense node is charged to the supply voltage instead of discharging. The gate voltage of the NMOS charge transfer transistor is then charged to substantially equal to the threshold voltage of the NMOS charge transfer transistor at the start of the charge transfer period. If the accessed bit cell stores a binary 0 value, the NMOS charge transfer transistor conducts charge, causing the pre-charged sense node to discharge to ground. However, if the accessed bit cell stores a binary 1, the accessed bit cell raises the voltage of the discharge bit line through the bit line voltage difference, causing the NMOS charge transfer transistor to not conduct because its gate-to-source voltage is below its threshold voltage. Some example PMOS charge transfer embodiments will now be discussed in more detail, followed by NMOS charge transfer embodiments.

[0029] Figure 1 An example SRAM 100 is shown. As is known in the SRAM art, SRAM 100 includes a plurality of bit cells 105 arranged in rows according to a plurality of word lines and in columns according to a plurality of bit lines. For clarity, Figure 1Only one word line W, one bit cell 105, and one bit line B1 are shown. Before a read operation, if bit cell 105 stores a binary 1 value, the Q node of bit cell 105 is charged to the supply voltage. Conversely, if bit cell 105 stores a binary 0, the Q node is grounded. As is known in SRAM technology, a precharge circuit 115 is used to precharge bit line B1 to the supply voltage VDD before the assertion of word line W. During a read operation, the voltage of word line W is asserted to the supply voltage to turn on the NMOS access transistor M1, causing the Q node to couple to the precharged bit line B1. The bit line voltage is then charged to the bit cell influence voltage, which depends on the Q node voltage. If bit cell 105 stores a binary 1, the bit cell influence voltage will be equal to the supply voltage VDD, but if bit cell 105 stores a binary 0, the bit cell influence voltage will be less than the bit line voltage difference from the supply voltage VDD. Note that the capacitance of bit line B1 is relatively large, as indicated by the bit cell capacitance Cbl. Therefore, if bit cell 105 stores binary 0, bit cell 105 cannot discharge bit line B1 to zero during the relatively short period of time during which word line W is asserted. Instead, the bit line voltage decreases from the supply voltage by a bit line voltage difference equal to a portion of the supply voltage VDD (e.g., 100mV).

[0030] During a read operation, when bit cell 105 stores a binary 0 value, the bit cell effect voltage of bit line B1 is therefore equal to the supply voltage minus the bit line voltage difference (dvbl). It is this bit line voltage difference that prevents charge transfer on the PMOS charge transfer transistor P1, which isolates the sense node 120 from bit line B1, before the read operation. Before the read operation, a charge transfer driver (not shown, but discussed further below) charges the gate voltage Vg of charge transfer transistor P1 to the supply voltage, causing charge transfer transistor P1 to isolate the sense node 120 from bit line B1. The sense node voltage is equal to the drain voltage Vd of charge transfer transistor P1, while the bit line voltage is equal to the source voltage Vs of charge transfer transistor P1. Before the read operation, a discharge circuit, such as an NMOS transistor M2, coupled between ground and sense node 120, is turned on to discharge the sense node voltage Vd. The capacitance Cd of sense node 120 is relatively small compared to the bit line capacitance Cbl. The small capacitance Cd of sensing node 120 effectively causes charge transfer amplification, as will be discussed further in this paper.

[0031] The sense amplifier inverter 110 inverts the sense node voltage during the sense enable period following the charge transfer period of the readout operation. For example, the sense enable signal Sen can be asserted to turn on the NMOS transistor M3 coupled between ground and the ground node of inverter 110, thus turning on inverter 110 during the sense enable period. If the sense node voltage Vd is still discharging during the sense enable period, the output voltage Vout of inverter 110 will be asserted as the supply voltage. Conversely, if the sense enable voltage is charged above a threshold value of inverter 110 during the sense enable period, the output voltage Vout will discharge to ground.

[0032] To control charge transfer via charge transfer transistor P1, the charge transfer driver charges the gate voltage to voltage Vg during the charge transfer period. Voltage Vg is equal to the supply voltage VDD minus the absolute value of the threshold voltage of transistor P1 and the additional positive overdrive voltage Vx; therefore, voltage Vg equals VDD - (Abs(Vt) + Vx), where Abs represents the absolute value function. Since the bit cell influence voltage is also the source voltage of charge transfer transistor P1, the resulting source-to-gate voltage Vsg of charge transfer transistor P1 depends on the bit cell influence voltage of bit line B1. Furthermore, the bit cell influence voltage of bit line B1 depends on the binary value of bit cell 105.

[0033] By considering Figure 2 This allows for a better understanding of the charge transfer control generated by charge transfer transistor P1. Figure 2 The diagram illustrates the current i conducted by charge transfer transistor P1 as a function of its source-to-gate voltage Vsg. If the bit cell effect voltage is equal to the supply voltage VDD, then the source-to-drain voltage Vsg will be equal to VDD - Vg, which is equal to VDD - (VDD - (Abs(Vt) + Vx)), and it is also equal to Abs(Vt) + Vx, as shown. Figure 2 The voltage A is shown in the diagram. Since voltage A is greater than the absolute value of the threshold voltage, charge transfer transistor P1 turns on to conduct current I. However, if bit cell 105 stores binary 0, the source voltage of charge transfer transistor P1 (bit cell influence voltage) decreases from the supply voltage VDD by the bit line voltage difference (dvbl). Then voltage Vsg equals Abs(Vt) + Vx - dvbl, which is equal to voltage B, as shown in the diagram. Figure 2 As shown. Since voltage B is less than the absolute value of the threshold voltage, charge transfer transistor P1 remains off and the amount of charge conducted is negligible.

[0034] Therefore, if bit cell 105 stores binary 0, the sensing node voltage Vd will remain discharged, while if bit cell 105 stores binary 1, the charge transfer transistor P1 will conduct current I. Since the capacitance Cd of the sensing node is relatively small, the current I will relatively quickly charge the sensing node voltage Vd from ground to the bit cell. The bit line voltage difference dvbl is thus amplified by the charge transfer process to produce a sensing node voltage difference close to the full rail. This amplification advantageously makes it possible to use an inverter 110 to sense the sensing node voltage. Not only is the inverter 110 relatively compact and low-power compared to conventional sensing amplifiers, but each bit cell of memory 100 can use only one bit line compared to the conventional requirement for SRAM bit line pairs. The sensing of the binary content of the bit cell by the inverter 110 can therefore be represented as single-ended sensing because it uses only one bit line.

[0035] The charge transfer driver used to generate the gate voltage Vg can be, for example, Figure 3 The diode-connected PMOS transistor P2 is formed for SRAM 300. The source of the diode-connected transistor P2 is bonded to the power supply node of the power supply voltage VDD, while its gate and drain are bonded to the source of the PMOS current source transistor P3, which is turned on by a low-level active charge transfer enable signal (cts_en) during the charge transfer period. Then, transistor P3 will conduct current Is during the charge transfer period. The gate of the diode-connected transistor P2 is connected to the gate of the charge transfer transistor P1. Therefore, if the source of the charge transfer transistor P1 is also charged to the power supply voltage VDD, the charge transfer transistor P1 will mirror the current Is during the charge transfer period according to the size ratio between transistors P1 and P2. As previously described, when bit cell 105 ( Figure 1 When storing a binary 1 value, the bit cell influence voltage of bit line B1 is equal to the supply voltage VDD. Therefore, when the bit cell influence voltage equals the supply voltage VDD, charge transfer transistor P1 conducts during the charge transfer period to allow current Is to pass through. However, if the bit cell influence voltage drops from the supply voltage VDD due to the binary 0 value stored in bit cell 105, causing a bit line voltage difference (bit line dvbl), the current mirror configuration is disrupted, causing charge transfer transistor P1 to conduct a negligible amount of charge. Note that diode-connected transistors (such as transistor P2) conduct a large amount of charge to ground, thus reducing efficiency.

[0036] An alternative charge transfer driver that does not have the efficiency and cost of using a diode-connected transistor can be developed from any suitable source that reduces the gate voltage relatively slowly compared to the development of the bit line voltage difference dvbl. The goal is to reduce the gate voltage Vg from the supply voltage to approximately the absolute value of the threshold voltage at the start of the charge transfer period. If the source voltage (bit cell effect voltage) of charge transfer transistor P1 is equal to the supply voltage VDD, then the Vsg voltage of charge transfer transistor P1 will be equal to the absolute value of the threshold voltage, and therefore charge transfer transistor P1 will conduct. However, if the source voltage is equal to the supply voltage minus the bit line voltage difference dvbl, then charge transfer transistor P1 will not conduct.

[0037] One method for relatively slowly reducing the gate voltage Vg is to use a small inverter to form a charge transfer driver. Due to its relatively small size, the inverter reduces the gate voltage relatively slowly during the charge transfer period. Alternatively, a dummy bit line can be used as a charge transfer driver to form the gate voltage Vg. As is known in the SRAM field, a dummy bit line is used to model when the bit line voltage has sufficiently developed to warrant the start of a sense-on period. Since the dummy bit line simulates the bit line capacitance, the rate at which the dummy bit line discharges from the pre-charge state to the threshold voltage is approximately the same as the rate at which the bit line discharges from the supply voltage to the bit line voltage difference dvbl. Both types of charge transfer drivers are... Figure 4 The diagram for memory 400 is shown. Since only one method is used in practice, the connection from inverter 415 to the gate voltage of charge transfer transistor P1 is optionally shown as a dashed line. Furthermore, unlike the single-ended method discussed for memory 100, memory 400 uses a bit line pair formed by bit line B1 and complementary bit line Blb. Although the bit line pair requires more wiring, the resulting sensing operation can be performed faster compared to the single-ended method. Therefore, memory 100 can be used for time-insensitive applications, while memory 400 provides faster operation for time-critical applications.

[0038] Prior to the assertion of word line W, precharge circuitry 420 is used to precharge bit line B1 and complementary bit line B1b, as is known in the SRAM field. As discussed with respect to memory 100, the Q node of bit cell 105 is coupled to bit line B1 via access transistor M1. Additionally, the complementary Q node (QB) of bit cell 105 in memory 400 is coupled to complementary bit line B1b via another NMOS access transistor M5. As discussed with respect to memory 100, bit line B1 is isolated from sensing node 120 via charge transfer transistor P1. Similarly, complementary bit line B1b is isolated from sensing node 402 via PMOS charge transfer transistor P4. A charge transfer driver (dummy bit line or inverter 415) controls the gate voltages of charge transfer transistors P1 and P4 during the charge transfer period. Transistors M2 and M4 serve as discharge circuits to discharge sensing nodes 120 and 402 before the charge transfer period. The source of transistor M4 is connected to ground, and its drain is connected to sensing node 402. The arrangement of transistor M2 is as discussed for SRAM 100.

[0039] The sense amplifier in memory 400 is formed by a simple reset bit (RS) latch, such as that implemented by a pair of cross-coupled NAND gates 315 and 310. NAND gate 310 has a first input node connected to sense node 120 and a second input node connected to the output node of NAND gate 315. Similarly, NAND gate 315 has a first input node connected to sense node 402 and a second input node connected to the output node of NAND gate 310. The output node of NAND gate 310 drives the output signal Dout for read operations on bit cell 105. The RS latch formed by NAND gates 310 and 315 is relatively compact and efficient compared to a conventional sense amplifier. Due to the discharge default state of sense nodes 120 and 402, the outputs of NAND gates 315 and 310 will both be logic high (charged to the supply voltage) before the charge transfer period. Each NAND gate then acts as an inverter for its sense node (the drain of charge transfer transistor P4 or charge transfer transistor P1). If bit cell 105 stores a binary 1 value, charge transfer transistor P1 will be turned on during the charge transfer period, while charge transfer transistor P4 will remain off. In this state, the RS latch formed by NAND gates 310 and 315 is reset, causing the output signal Dout to discharge to ground. Conversely, if bit cell 105 stores a binary 0 value, charge transfer transistor P4 will be turned on during the charge transfer period, while charge transfer transistor P1 will remain off. The RS latch formed by NAND gates 310 and 315 is then set, causing the output signal Dout to charge to the supply voltage VDD. Note that even when unwanted charge transfer occurs due to bit line leakage when the accessed bit cell stores a binary 0 value, the RS latch can still be read advantageously without failure.

[0040] Now refer to Figure 5 The example SRAM 500 shown discusses an NMOS charge transfer embodiment. Similar to that discussed with respect to memory 100, bit line B1 is coupled to bit cell 105 during a read operation. During the charge transfer period, bit line B1 is coupled to sensing node 505 (the drain of charge transfer transistor M6) via NMOS charge transfer transistor M6. As discussed with respect to memory 100, the sense amplifier inverter 110 in memory 500 senses the bit stored in bit cell 105 by inverting the sense node voltage (the drain voltage Vd of charge transfer transistor M6). The pre-charge state of bit line B1 is ground when discharged by pre-charge NMOS transistor M7. Conversely, the pre-charge state of sense node 505 is the supply voltage VDD when charged by a charging circuit such as pre-charge PMOS transistor P6.

[0041] Since the precharge state of bit line B1 is ground, the access transistor is a PMOS transistor as indicated by access transistor P5. The assertion of word line W of memory 500 can then be an active-low (ground) assertion. Before a read operation, the default state of the word line is the power supply voltage VDD to keep access transistor P5 off. However, during a read operation, word line W is then discharged to ground during the word line period. Depending on the bit stored in bit cell 105, if the stored bit is binary 0, bit line B1 will then remain grounded (remain in its precharge state), or if the stored bit is binary 1, bit line B1 will then be boosted by a portion of the power supply voltage VDD.

[0042] Before the charge transfer period, the gate of charge transfer transistor M6 is grounded, thus turning off transistor M6. During the charge transfer period, the gate voltage of charge transfer transistor M6 slowly rises to its threshold voltage plus a positive overdrive voltage (a portion of the supply voltage VDD). Therefore, a small inverter is suitable as a charge transfer driver to charge the gate voltage of charge transfer transistor M6. This gate drive is similar to the inverter 415 discussed with regard to memory 400, except that the gate voltage will charge memory 500 from ground during the charge transfer period, while it discharges memory 400 from the supply voltage VDD. As the gate voltage Vg is charged to the threshold voltage and bit cell 105 stores binary 0, the gate-to-source voltage of charge transfer transistor M6 will satisfy its threshold voltage, causing charge from pre-charge sensing node 505 to flow onto bit line B1. However, since the bit line capacitance Cbl is relatively large compared to the small sensing node capacitance Cd, this charge transfer does not significantly increase the bit line voltage. In contrast, the voltage of the pre-charge sensing node 505 changes significantly and discharges to ground, thereby triggering the inverter 110 to charge the output voltage Vout to the power supply voltage VDD.

[0043] If the bit stored in bit cell 105 is changed to binary 1, bit cell 105 will raise the discharge bit line voltage through the bit line voltage difference dvbl. Since the gate voltage of charge transfer transistor M6 is slightly higher than its threshold voltage, the source voltage of charge transfer transistor M6 raised by the bit line voltage difference dvbl can keep charge transfer transistor M6 off during the charge transfer period. The precharge sensing node voltage will then be held at the supply voltage VDD, causing inverter 110 to maintain the output voltage Vout discharge. In this way, charge transfer operation can be achieved regardless of the polarity of the charge transfer transistor. However, note that the operation of SRAM 500 is completely different from conventional SRAM operation because the precharge state of bit line B1 is ground and access transistor P6 is a PMOS transistor. Although such operation is very different from conventional SRAM operation, the precharge of the bit line is low-power because the precharge state is ground. SRAM 500 is single-ended, but it can be understood that this NMOS charge transfer operation can be easily extended to a double-ended implementation, as discussed similarly with regard to memory 400. However, note that in the NMOS charge transfer embodiment, the cross-coupled NAND gates will be replaced with cross-coupled NOR gates to form the sense amplifier.

[0044] Now about Figure 6 The flowchart shown discusses a method for sensing charge transfer of bits stored by bit cells. This method includes action 600: pre-charging the bit line to an amount equal to a pre-charge voltage while turning off a charge transfer transistor having a source connected to the bit line and a drain connected to the sensing node to isolate the sensing node from the bit line. An example of action 600 is the pre-charging of bit line B1 in memory 100 or 400 when charge transfer transistor P1 is turned off. Furthermore, the method includes action 605 after bit line pre-charging and includes coupling the bit cell to the bit line while the charge transfer transistor remains off to charge the bit line to a bit cell influence voltage, which is equal to the pre-charge voltage in response to the bit being equal to a first binary value, and differs from the pre-charge voltage by a bit line difference voltage in response to the bit being equal to a second binary value. Note that action 605 is general for the polarity of the charge transfer transistor. In an NMOS implementation such as that discussed for SRAM 500, the pre-charge voltage is equal to ground, while in a PMOS implementation, the pre-charge voltage is equal to the supply voltage.

[0045] The method further includes action 610: charging the gate of the charge transfer transistor to a gate voltage during the charge transfer period, wherein the difference between the gate voltage and the bit cell influence voltage causes the charge transfer transistor to turn on in response to a bit equal to a first binary value, and wherein the difference between the gate voltage and the bit cell influence voltage causes the charge transfer transistor to remain off in response to a bit equal to a second binary value. Like action 605, action 610 is universal for the polarity of the charge transfer transistor.

[0046] Finally, the method includes action 615 after the charge transfer period ends, and includes sensing the bit in response to inverting the voltage of the sensing node. This inversion can be performed by inverter 110 in a single-ended implementation, or by NAND gate 310 in a double-ended implementation.

[0047] The memory disclosed herein can be advantageously incorporated into any suitable electronic system or device. For example, such as Figure 7 As shown, according to this disclosure, a cellular phone 700, a laptop computer 705, and a tablet PC 710 can all include memory. Other exemplary electronic systems, such as music players, video players, communication devices, and personal computers, can also be configured with memory constructed according to this disclosure.

[0048] As those skilled in the art will now understand, and depending on the specific application at hand, many modifications, substitutions, and variations can be made to the materials, apparatus, configuration, and methods of use of the devices disclosed herein without departing from the scope of this disclosure. Therefore, the scope of this disclosure should not be limited to the specific embodiments shown and described herein, as they are merely examples, but rather should be fully proportionate to the scope of the appended claims and their functional equivalents.

Claims

1. A memory, comprising: Bit line; The pre-charge circuit is configured to charge the bit line to an amount equal to the pre-charge voltage during the pre-charge period. Bit cells are configured to charge the bit line to a bit cell influence voltage during a word line assertion period in response to a bit stored in the bit cell, wherein the bit cell influence voltage is equal to the pre-charge voltage in response to the bit being equal to a first binary value, and the bit cell influence voltage is different from the pre-charge voltage by a bit line difference voltage in response to the bit being equal to a second binary value. Sensing amplifier; A first sensing node is used for the sensing amplifier; A first charge transfer transistor has a source connected to the bit line and a drain connected to the first sensing node; as well as A charge transfer driver is configured to charge the gate of the first charge transfer transistor to a gate voltage during a charge transfer period, to turn on the first charge transfer transistor in response to the stored bit being equal to the first binary value, and to keep the first charge transfer transistor off in response to the stored bit being equal to the second binary value.

2. The memory according to claim 1, wherein The pre-charge circuit is configured to charge the bit line to the power supply voltage during the pre-charge period, and wherein the first charge transfer transistor is a p-type metal-oxide-semiconductor (PMOS) transistor.

3. The memory of claim 2, further comprising a transistor configured to discharge the first sensing node to ground during the precharge period.

4. The memory according to claim 1, wherein The precharge circuit is configured to discharge the bit line to ground during the precharge period, and the first charge transfer transistor is an n-type metal-oxide-semiconductor (NMOS) transistor.

5. The memory of claim 4, further comprising a transistor configured to charge the first sensing node to a power supply voltage during the precharge period.

6. The memory of claim 1, wherein the charge transfer driver includes a dummy bit line.

7. The memory of claim 1, wherein the charge transfer driver comprises an inverter.

8. The memory of claim 1, wherein the charge transfer driver comprises a diode-connected transistor having a gate connected to the gate of the first charge transfer transistor.

9. The memory of claim 1, wherein the sensing amplifier includes an inverter configured to invert the voltage of the first sensing node to sense the binary value of the stored bit.

10. The memory according to claim 1, further comprising: Complementary bit lines; The second charge transfer transistor has a source connected to the complementary bit line and a drain connected to a second sensing node for the sensing amplifier, wherein the charge transfer driver is further configured to drive the gate voltage of the second charge transfer transistor.

11. The memory of claim 10, wherein the sensing amplifier includes a reset bit latch.

12. The memory of claim 11, wherein the reset bit latch comprises a pair of cross-coupled NAND gates.

13. The memory of claim 1, wherein the memory is integrated into a cellular phone.

14. A method for sensing bits stored in bit cells using a charge transfer transistor, comprising: The bit line is precharged to an amount equal to the precharge voltage, while the charge transfer transistors connected to the source of the bit line and the drain of the sensing node are turned off to isolate the sensing node from the bit line. After the pre-charging of the bit line, the bit cell is coupled to the bit line while the charge transfer transistor remains off to charge the bit line to a bit cell influence voltage, the bit cell influence voltage being equal to the pre-charging voltage in response to the bit being equal to a first binary value, and the bit cell influence voltage being different from the pre-charging voltage by a bit line difference voltage in response to the bit being equal to a second binary value. During the charge transfer period, the gate of the charge transfer transistor is charged to a gate voltage, wherein the difference between the gate voltage and the bit cell influence voltage causes the charge transfer transistor to turn on in response to the bit being equal to the first binary value, and wherein the difference between the gate voltage and the bit cell influence voltage causes the charge transfer transistor to remain off in response to the bit being equal to the second binary value; as well as After the charge transfer period ends, the bit is sensed in response to inverting the voltage of the sensing node.

15. The method of claim 14, wherein pre-charging the bit line to an amount equal to the pre-charge voltage comprises: Charge the bit line to the power supply voltage to reach the pre-charge period.

16. The method of claim 15, further comprising discharging the sensing node to ground before the charge transfer period.

17. The method of claim 14, wherein the first binary value is logic 1 and the second binary value is logic 0.

18. The method of claim 15, wherein charging the gate of the charge transfer transistor to the gate voltage comprises: The gate of the charge transfer transistor is charged using a dummy bit line.

19. The method of claim 15, wherein charging the gate of the charge transfer transistor to the gate voltage comprises: The gate of the charge transfer transistor is discharged using an inverter.

20. A memory comprising: Bit line; A pre-charge circuit is configured to pre-charge the bit line to the power supply voltage before the charge transfer period; A bit cell is configured to charge the bit line to a bit cell influence voltage during a read operation in response to a bit stored in the bit cell, wherein the bit cell influence voltage is equal to the power supply voltage in response to the bit being equal to a first binary value, and the bit cell influence voltage is different from the power supply voltage by a bit line difference voltage in response to the bit being equal to a second binary value. Sensing amplifier inverter; A charge transfer transistor is coupled between the bit line and the sensing node for the inverter of the sensing amplifier; as well as A discharge circuit is configured to discharge the sensing node to ground before the charge transfer period of the charge transfer transistor.

21. The memory according to claim 20, further comprising: A charge transfer driver is configured to drive the gate voltage of the charge transfer transistor during the charge transfer period.

22. The memory of claim 21, wherein the charge transfer driver includes a dummy bit line.

23. The memory of claim 21, wherein the charge transfer driver includes an inverter configured to discharge the gate voltage of the charge transfer transistor during the charge transfer period.

24. A memory comprising: Bit line; A pre-charge circuit is configured to discharge the bit line to ground before the charge transfer period; A bit cell is configured to charge the bit line to a bit cell influence voltage during a read operation in response to a bit stored in the bit cell, wherein the bit cell influence voltage is equal to ground in response to the bit being equal to a first binary value, and the bit cell influence voltage is different from ground by a bit line difference voltage in response to the bit being equal to a second binary value. Sensing amplifier inverter; A charge transfer transistor is coupled between the bit line and the sensing node for the inverter of the sensing amplifier; as well as A charging circuit is configured to charge the sensing node to a power supply voltage before the charge transfer period of the charge transfer transistor.

25. The memory according to claim 24, further comprising: A charge transfer driver is configured to drive the gate voltage of the charge transfer transistor during the charge transfer period.

26. The memory of claim 25, wherein the charge transfer driver includes a dummy bit line.

27. The memory of claim 25, wherein the charge transfer driver includes an inverter configured to charge the gate voltage of the charge transfer transistor during the charge transfer period.

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