Self-aligned bit line and storage node contact for 4f2dram

Abstract

The present techniques include vertical cell dynamic random access memory (DRAM) arrays with improved bit line and storage node contact resistivity and self-alignment, and methods of making such arrays. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending in a vertical direction substantially orthogonal to the first direction and the second horizontal direction such that a plurality of bit lines intersect source / drain regions of the plurality of channels and a plurality of word lines intersect gate regions of the plurality of channels. Further, the array includes where the bit lines, the storage node contacts, or both are formed of metallized material.

Description

[0001] Cross-references to related applications

[0002] This application claims a patent filed on October 5, 2023, entitled "SELF-ALIGNED BIT LINE ANDSTORAGE NODE CONTACTS FOR 4F2 DRAM (for 4F...)". 2 The benefit and priority of U.S. Patent Application No. 63 / 588,214, entitled “Self-alignment lines and memory node contacts for DRAM,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally describes 4F 2 Design of a two-dimensional dynamic random access memory array. More specifically, this disclosure describes a 4F array with self-aligned metallized bit lines or memory node contacts. 2 Memory array. Background Technology

[0004] With advancements in computing technology, computing devices are becoming smaller while their processing power is increasing. Therefore, there is a need to increase storage and memory to meet the programming and computational demands of these devices. This is achieved by increasing the number of storage cells with smaller geometries, thus miniaturizing devices while maintaining increased storage capacity.

[0005] Dynamic random-access memory (DRAM) architectures have shrunk over time. For example, the DRAM cell structure of one transistor and one capacitor (1T-1C) has been successfully reduced from 8F. 2 Size reduced to 6F 2 Size (where F is the smallest feature size). From 6F 2 Go to 4F 2 Further design modifications could help improve the area density. In 4F 2 In DRAM designs, the memory nodes (capacitors) and bit lines are located at the top and bottom of the vertical cell transistors, completely isolating the channel from the bulk. Due to this arrangement, the floating body effect becomes 4F. 2 The main technical challenge of DRAM is that, due to the bulk interconnect of the channel, the floating body effect is not present in current 8F DRAM. 2 Or 6F 2 There are issues with the DRAM cell architecture. Furthermore, this arrangement interferes with the formation of bit lines or memory node contacts. Therefore, improvements to the current technology are necessary. Summary of the Invention

[0006] This technology generally relates to vertical cell dynamic random access memory (DRAM) precursor structures, methods of manufacturing such structures, and semiconductor devices and methods of manufacturing such devices. A DRAM precursor structure includes a substrate, one or more sacrificial layers formed over the substrate, one or more first epitaxial junction material layers formed over the sacrificial layers, an epitaxial channel material formed on the first junction material, and one or more second epitaxial junction material layers formed over the channel material.

[0007] In some embodiments, the precursor structure includes one or more sacrificial layers that are epitaxially grown silicon germanium (SiGe). In more embodiments, germanium is present in one or more sacrificial layers in an amount greater than or about 5% by weight. Furthermore, in some embodiments, the one or more sacrificial layers have a thickness greater than or about 5 nm. Additionally or alternatively, in some embodiments, one or more first epitaxial junction material layers, one or more second epitaxial junction material layers, or both one or more first epitaxial junction material layers and one or more second epitaxial junction material layers have a doping concentration greater than or about 50% of the average doping concentration of the respective layers of the junction material. In more embodiments, one or more first epitaxial junction material layers comprise n-type doped silicon, the channel material comprises silicon, and one or more second epitaxial junction material layers comprise n-type doped silicon.

[0008] This technology also generally relates to methods for forming precursor structures. Methods include growing one or more sacrificial layers over a semiconductor substrate. Methods include epitaxially growing channel material over one or more sacrificial layers while providing one or more n-type dopants to form one or more first junction layers. Methods include epitaxially growing channel material over one or more first junction layers to form one or more channel layers. Methods include epitaxially growing channel material over one or more channel layers while providing one or more n-type dopants to form one or more second junction layers.

[0009] In one embodiment, the method includes growing one or more sacrificial layers to a height greater than or about 10 nm. In more embodiments, the one or more sacrificial layers contain a greater than or about 5% by weight of germanium, based on the weight of the one or more sacrificial layers. The embodiment includes one or more first junction layers, one or more second junction layers, or both of the one or more first junction layers and one or more second junction layers having a target doping concentration, wherein the doping concentration along one or more of the first junction layers, the second junction layers, or at any point in the first junction layers, the second junction layers, or both of the first junction layers and the second junction layers is greater than or about 50% of the target doping concentration of the respective layer. Additionally or alternatively, in an embodiment, one or more channel layers are grown to a height greater than or about 10 nm.

[0010] This technology also generally relates to vertical cell DRAM arrays. The array includes multiple metallized bit lines arranged in a first horizontal direction, multiple word lines arranged in a second horizontal direction, and multiple channels extending in a vertical direction. The array includes a vertical direction that is substantially orthogonal to the first and second horizontal directions, such that the multiple metallized bit lines intersect the source / drain regions of the multiple channels, and the multiple word lines intersect the gate regions of the multiple channels. The array includes dielectric spacers disposed between adjacent bit lines.

[0011] In some embodiments, the array includes dielectric spacers comprising dielectric oxides. In more embodiments, at least a portion of the metallization bit lines is offset from the respective channels of the plurality of channels by about 10% to less than or about 90% of the width of the respective channel. Additionally or alternatively, embodiments include instances where at least a portion of the dielectric spacers at least partially intersects the source / drain regions of the plurality of channels. In still other embodiments, the bit lines are self-aligned bit lines disposed beneath a single-crystal channel. Furthermore, in embodiments, one or more metallized memory node contacts are disposed at the top of the plurality of channels.

[0012] This technology also generally relates to methods for forming vertical cell DRAM arrays. The method includes providing a substrate having a sacrificial material over a substrate material and one or more channel materials disposed over the sacrificial layer. The method includes etching the substrate to form one or more shallow trench isolations and a plurality of vertically extending channels having at least a first source / drain region. The method includes forming a dielectric material in one or more of the shallow trench isolations. The method includes removing at least a portion of the sacrificial material, forming a void space that at least partially intersects a portion of the first source / drain region of the vertically extending channel, and forming metallization bit lines in the void space.

[0013] In one embodiment, the method includes forming word lines in word line trenches, wherein the word lines intersect gate regions of a plurality of vertically extending channels. In a further embodiment, the method includes removing portions of sacrificial material through one or more access vias. In a further embodiment, the method includes removing portions of sacrificial material through exposed areas at the back or side surfaces of the substrate. In one embodiment, the method includes reducing the thickness of the substrate material before removing at least a portion of the sacrificial material. Additionally, in one embodiment, the method includes removing all sacrificial material. Additionally or alternatively, in one embodiment, one or more channel materials include doped channel material and undoped channel material. In a further embodiment, the method includes forming one or more of a plurality of vertically extending channels by depositing doped channel material over the sacrificial material, depositing undoped channel material over the doped channel material, and depositing a second doped channel material on the undoped channel material. In a further embodiment, the method includes flipping the substrate and removing all or a portion of the substrate before removing the sacrificial material. Additionally, in one embodiment, the method includes siliconizing a first source / drain region before forming metallization bit lines. In an embodiment, the metallization bit line includes tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species of the above, alloys of the above, or combinations of the above.

[0014] This technology also generally relates to vertical cell DRAM arrays. The array includes multiple bit lines arranged in a first horizontal direction, multiple word lines arranged in a second horizontal direction, and multiple channels extending in a vertical direction. The array includes a vertical direction that is substantially orthogonal to the first and second horizontal directions, such that the multiple bit lines intersect the source / drain regions of the multiple channels, and the multiple word lines intersect the gate regions of the multiple channels. The array includes multiple metallized memory node contacts.

[0015] In one embodiment, the array includes a plurality of metallized memory node contacts that are self-aligned beneath a single-crystal channel. In more embodiments, the multiple bit lines include metallized bit lines disposed at the top of the multiple channels.

[0016] This technology also generally relates to methods for forming vertical cell DRAM arrays. The method includes providing a substrate having a sacrificial layer over a substrate material and one or more channel materials disposed over the sacrificial layer. The method includes etching the substrate to form one or more shallow trench isolations and a plurality of vertically extending channels having at least one first source / drain region. The method includes forming a dielectric material in one or more of the shallow trench isolations. The method includes removing at least a portion of the sacrificial material to form a void space that at least partially intersects with a portion of the first source / drain region of the vertically extending channel. The method includes forming one or more metallized memory node contacts in the void space.

[0017] In one embodiment, the method includes forming word lines in word line trenches, wherein the word lines intersect gate regions of a plurality of channels. In further embodiments, the method includes forming one or more of a plurality of vertically extending channels by depositing a doped channel material over a sacrificial material, depositing an undoped channel material over the doped channel material, and depositing a second doped channel material over the undoped channel material. In further embodiments, the method includes flipping the substrate and removing all or a portion of the substrate before removing the sacrificial material. Furthermore, in one embodiment, the method includes siliconizing a first source / drain region before forming one or more metallized memory node contacts. Additionally or alternatively, embodiments include one or more metallized memory node contacts comprising tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species of the foregoing, alloys of the foregoing, or combinations thereof.

[0018] Compared to traditional systems and technologies, this type of technology offers numerous advantages. For example, the process and system allow for the formation of bit lines or memory node contact junctions early in the process, significantly reducing the complexity and cost of junction formation compared to traditional methods with thermal budget constraints. Furthermore, the methods and systems discussed in this paper are 4F... 2 DRAM components offer higher quality junctions. Furthermore, these processes and systems allow for the formation of metallized bit lines or memory node contacts without requiring additional overlay and patterning processes, instead providing self-aligned metallized bit lines or memory node contacts. These and other embodiments, along with their numerous advantages and features, are described in more detail below with reference to the accompanying drawings. Attached Figure Description

[0019] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of the specification and the accompanying drawings.

[0020] Figure 1A The illustration shows a top plan view of an exemplary processing chamber according to an embodiment of the present technology.

[0021] Figure 1B It shows the traditional 4F 2 Top view of the memory array.

[0022] Figure 1C It shows the traditional 4F 2 Perspective view of the memory array.

[0023] Figure 2 The illustration shows a selected operation in the formation method according to the present technical embodiment.

[0024] Figure 3AThe illustration shows a perspective view of a precursor semiconductor structure according to an embodiment of the present technology, wherein a sacrificial layer is formed over a substrate.

[0025] Figure 3B The illustration shows a perspective view of a precursor semiconductor structure according to an embodiment of the present technology, wherein a junction is formed over a sacrificial layer.

[0026] Figure 3C The illustration shows a perspective view of a precursor semiconductor structure according to an embodiment of the present technology, wherein a channel is formed above a junction.

[0027] Figure 3D The illustration shows a perspective view of a precursor semiconductor structure according to an embodiment of the present technology, wherein a junction is formed over a channel.

[0028] Figure 3E The illustration shows a perspective view of a precursor semiconductor structure according to an embodiment of the present technology, wherein a contact pad is formed above a junction.

[0029] Figure 4A The illustration shows a perspective view of a semiconductor structure having one or more separators according to an embodiment of the present technology.

[0030] Figure 4B The illustration shows a perspective view of a semiconductor structure according to an embodiment of the present technology, wherein one or more insulators are etched through a sacrificial layer.

[0031] Figure 4C The illustration shows a perspective view of a semiconductor structure according to an embodiment of the present technology, wherein one or more spacers are filled with insulating material.

[0032] Figure 4D The illustration shows a perspective view of a semiconductor structure having one or more word line trenches according to an embodiment of the present technology.

[0033] Figure 4E The illustration shows a perspective view of a semiconductor structure according to an embodiment of the present invention, wherein one or more 4F elements are formed. 2 feature.

[0034] Figure 4F The illustration shows a perspective view of a semiconductor structure according to an embodiment of the present technology, wherein the substrate is flipped 180°.

[0035] Figure 4G The illustration shows a perspective view of a semiconductor structure according to an embodiment of the present technology, which has metallization features formed after the removal of sacrificial material.

[0036] Figure 5A The illustration shows a perspective view of a semiconductor structure having one or more word line trenches according to an embodiment of the present technology.

[0037] Figure 5B The illustration shows a perspective view of a semiconductor structure according to an embodiment of the present invention, wherein one or more 4F elements are formed. 2 feature.

[0038] Figure 5C The illustration shows a perspective view of a semiconductor structure according to an embodiment of the present technology, wherein the substrate is flipped 180°.

[0039] Figure 5D The illustration shows a perspective view of a semiconductor structure according to an embodiment of the present technology, wherein metallization features are formed after the removal of sacrificial material.

[0040] The accompanying drawings include multiple figures for illustrative purposes. It should be understood that these figures are for illustrative purposes only and should not be considered to be drawn to scale unless specifically stated otherwise. Furthermore, the accompanying drawings include multiple figures for illustrative purposes and may not include all aspects or information compared to a true representation, and may also include exaggerated material for illustrative purposes.

[0041] In the accompanying drawings, similar parts and / or features may have the same reference numerals. Furthermore, various parts of the same type may be distinguished by letters following the reference numerals to differentiate between similar parts. If only the first reference numeral is used in the description, the description applies to any similar part having the same first reference numeral, regardless of the letters used. Detailed Implementation

[0042] Historically, DRAM chip bit density increased by approximately 25% per node. However, in recent generations, the increase in bit density per node has decreased to approximately 20%, primarily due to the challenges of scaling cell area. Modern DRAM technology's cell design architecture is based on 6F. 2 Geometric structure, where F is the minimum feature size for a given technology node. At the same technology node, from 6F... 2 Go to 4F 2 Switching to a different cell architecture can result in a 33% increase in bit density. Furthermore, compared to 6F... 2 Compared to 4F 2 Patterning DRAM is significantly easier. This is mainly because of the 4F... 2 In DRAM designs, capacitors and bit lines are located at the ends of vertical cell transistors, rather than as in 6F. 2 DRAMs are typically arranged close together on the same side.

[0043] However, 4F 2 DRAM design also presents its own challenges. For example, 4F 2The memory cell has a transistor channel between the bit line and the capacitor layer, thus lacking a common substrate connecting the channels, resulting in a floating body effect for the transistor. Furthermore, this design can also produce high aspect ratio structures that challenge existing doping techniques.

[0044] Furthermore, when the capacitor is positioned at the top of the vertical channel, the bit line must be formed at the bottom of the vertical channel. This can be achieved by using continuous silicon lines as bit lines. However, silicon has high resistivity, especially compared to the current 6F... 2 Compared to the metal bit lines used in DRAM, bit lines can be formed by patterning metal bit lines from the back of the wafer after front-side wafer bonding is complete and the substrate has been flipped. However, this process requires complex patterning and alignment, which is challenging for handling output volume and consistent high-quality structure formation. For example, this process requires multiple complex masking and etching steps to align the connections with the formed bit lines. An alternative is to place the bit lines on top of the vertical channel while forming capacitors via a back-side process after wafer bonding. However, similar to the problems faced with forming the back of the bit lines, this alternative requires complex alignment and patterning of the memory node contacts with the vertical channel, which requires complex masking and etching steps to align the connections with the memory node contacts.

[0045] This technology provides a self-aligned method at 4F 2 The method for forming metallized bit lines or memory node contacts in DRAM cells overcomes the aforementioned and other problems. Specifically, this technology has surprisingly discovered that by providing a substrate with a unique orientation, sacrificial material can be removed after the front-side processing is complete, allowing the area to be filled with a metallized material that provides excellent resistivity for the bit lines or memory node contacts, to name just one example. By utilizing this sacrificial material, the metallized material can self-align and fill the voids formed by the removed sacrificial material. This allows bit lines or memory node contacts to be formed on the bottom of the semiconductor structure without the need for complex masking and etching operations. Furthermore, this technology also allows for customized doping of one or more source / drain regions when the substrate is provided. Therefore, this technology can provide highly specific and consistent dopant levels, even when the resulting DRAM cell contains one or more high aspect ratios or other complex features.

[0046] Although the remaining disclosure will conventionally identify the use of vertical cell dynamic random access memory (DRAM) arrays (such as 4F) to form such arrays. 2The specific deposition and etching processes for DRAM components are described, but it is readily understood that the system and method are equally applicable to other DRAM components, other components subject to the buoyancy effect and their orientation, and to processes used to form such components. Therefore, this technology should not be considered limited to use only with that particular component or system. Before describing additional variations and modifications to the device according to embodiments of the present technology, this disclosure will discuss a possible semiconductor device that may include one or more components according to embodiments of the present technology.

[0047] Figure 1A A top plan view of a multi-chamber processing system 100 is shown, which may be specifically configured to implement aspects or operations of some embodiments according to the present technology. The multi-chamber processing system 100 may be configured to perform one or more fabrication processes on a single substrate (such as any number of semiconductor substrates) for forming a semiconductor device. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single-wafer loading latches 110 and 112 (but may also include dual loading latches), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. Single-wafer loading latches 110 and 112 may include a heating element 113 and may be attached to the buffer chamber 108. Processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. Processing chambers 122 and 124 may be attached to the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be disposed between transfer chamber 106 and buffer chamber 108, facilitating transfer between robots 126 and 128. Platforms 102 and 104 may be open to both the transfer chamber and the buffer chamber, or the platforms may be selectively isolated from or sealed to allow for different operating pressures to be maintained between transfer chamber 106 and buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105, such as those for orientation or measurement operations.

[0048] The operation of the multi-chamber processing system 100 can be controlled by a computer system 130. The computer system 130 may include any means or combination of means configured to perform the operations described below. Therefore, the computer system 130 may be a controller or controller array, and / or a general-purpose computer configured with software stored on a non-transitory computer-readable medium, which, when executed, performs the operations described with respect to embodiments of the present technology. Each processing chamber 114, 116, 118, 120, 122, and 124 may be configured to perform one or more process steps in the fabrication of a semiconductor structure. More specifically, processing chambers 114, 116, 118, 120, 122, and 124 may be assembled to perform a variety of substrate processing operations, including dry etching processes, cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, alignment, and any number of other substrate processes.

[0049] Figure 1B and Figure 1C The illustration shows the traditional 4F 2 Top and perspective views of memory array 150. Memory array 150 may include multiple word lines 152 disposed in a first layer above a substrate. Word lines 152 may be conductive traces for selecting memory cells in memory array 150. Memory array 150 may also include multiple bit lines 154 disposed in a second layer above the substrate. The multiple bit lines may be conductive traces for selecting memory cells in memory array 150. Activating one of the multiple bit lines 154 and one of the multiple word lines 152 can select a cell in memory array 150. The first and second layers may include different metal layers formed at different times during the manufacturing process. For example, the first layer with word lines 152 may be formed over the second layer with bit lines 154 such that the two layers do not intersect.

[0050] Multiple vertical memory cells can be arranged at the intersections of multiple word lines 152 and multiple bit lines 154. Each of the multiple vertical memory cells may include a vertical transistor 170, which may be referred to as a vertical pillar transistor or a vertical column transistor. The channel material for the transistor may be formed from a single-crystal silicon pillar or any other substrate, which will be discussed in more detail below. This silicon channel may be formed by etching the substrate. Each of the multiple vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may indicate the saved memory state by storing charge on the vertical capacitor 156. However, although Figure 1B and Figure 1CThe illustration depicts an arrangement of vertical transistors and capacitors within a rectangular orthogonal grid pattern; however, it should be understood that other orientations are also conceivable. For example, in one embodiment, capacitors and vertical transistors can be spaced alternately in rows offset by approximately half the distance between the vertical transistors. That is, in one embodiment, the first row of memory cells can be regularly spaced in a first direction, and the second row of memory cells can also be regularly spaced in the first direction, but the second row of memory cells can be offset from the first row of memory cells, such as being aligned at approximately half the distance between the vertical transistors and capacitors in the first row. Figure 1B and Figure 1C Compared to the square pattern shown, this pattern can be referred to as a "honeycomb" or "hexagonal pattern". Therefore, it should be understood that this technique can be used with any suitable orientation.

[0051] To characterize this conventional 4F memory array, a comparison with the following simple memory array is needed. 2 The dimensions of the unit cell region 166 of the memory array are practical. For example, the capacitor occupancy region 158 can be defined as a circular region around each vertical capacitor 156. The capacitor occupancy region 158 may include a horizontal cross-sectional region of the capacitor that extends outward until it contacts the capacitor region from the adjacent memory cell. Assume that the word line spacing 162 of the multiple word lines 152 and the bit line spacing 164 of the multiple bit lines 154 can be defined as 2F. This results in a total cross-sectional area of ​​4F for the unit cell region 166. 2 .

[0052] Figure 2 Exemplary operations in method 200 according to some embodiments of the present technology are illustrated. The method can be performed in various processing chambers, including the processing chamber 100 described above. Method 200 may include several optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many operations are described to provide a wider range of structure formations, but such operations are not critical to the present technology or may be performed by readily understood alternative methods. Furthermore, although the method may describe a formation method perpendicular from the word line side to the bit line side of the structure, it should be understood that other orientations from the bit line to the word line side may be utilized. Furthermore, it should be understood that although the precursor semiconductor structure 300 described herein can be used to advantageously form a variety of challenging structures, the precursor structure 300 and semiconductor structures 400 and / or 500 are merely exemplary structures and methods of forming such structures. Furthermore, it should be understood that the exemplary structure and methods of forming such structures are not limiting, and other structures and methods of forming such structures are contemplated.

[0053] Method 200 may include additional operations prior to initiating the listed operations. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include forming and removing material. The prior processing operations may be performed in the chamber in which method 200 is performed, or may be performed in one or more other processing chambers prior to transferring the substrate to the semiconductor processing chamber in which method 200 is performed.

[0054] Regardless, method 200 may, as appropriate, include conveying a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or other chambers that may include the aforementioned components. The substrate may be deposited on a substrate support / transfer platform, which may be a base such as substrate support 104, and may reside in a processing region of the chamber, such as the processing region of processing chamber 120 described above. Method 200 describes the operations schematically illustrated in the remaining figures, and the illustrations of these operations will be described in conjunction with the operations of method 200. It should be understood that the figures show only partial schematics, and the semiconductor substrate may include other components as shown in the figures, and alternative components of any size or configuration may still benefit from various aspects of the present technology.

[0055] Method 200 may or may not involve optional operations for forming a semiconductor structure according to specific manufacturing operations. It should be understood that method 200 can be performed on any number of semiconductor structures 300 or substrates 302, as shown, including exemplary structures on which selectively deposited materials can be formed. Figure 3A As shown, substrate 302 can be any number of materials, such as a substrate wafer or substrate made of silicon or silicon-containing materials, germanium, other substrate materials, and one or more materials can be formed over the substrate during semiconductor processing.

[0056] Furthermore, although various deposition and filling processes will be described, it should be understood that, in embodiments, semiconductor structures can be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or similar processes. Therefore, unless specifically stated otherwise, it should be understood that any one or more of the above methods can be utilized, as is known in the art. Similarly, the semiconductor structure may be transferred to one or more processing chambers 114, 116, 118, 120, 122 and 124 configured for etching (such as one or more of inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, and other etching processes known in the art), and transferred between the processing chambers.

[0057] In embodiments, substrate 302 may include a bulk substrate, an epitaxial growth substrate, and / or a silicon-on-insulator wafer. As used herein, the term "semiconductor substrate" refers to a substrate whose entire substrate is made of semiconductor material. A semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may include one or more materials, such as crystalline silicon (e.g., Si). <100> or Si <111> The semiconductor material may include silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In one embodiment, the semiconductor material is silicon (Si). In one or more embodiments, semiconductor substrate 300 comprises semiconductor materials such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, substrate 302 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although several examples of materials that can form substrates have been described herein, any material that can be used as the basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) falls within the spirit and scope of this disclosure.

[0058] In implementations, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In implementations, any suitable process, such as ion implantation, may be used to dope the substrate. As used herein, the term "n-type" refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term n-type derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers, while holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the well (or hole). In contrast to an n-type semiconductor, a p-type semiconductor has a greater hole concentration than an electron concentration. In a p-type semiconductor, holes are the majority carriers, while electrons are the minority carriers.

[0059] like Figure 3A As shown, the provided structure 300 includes a substrate 302, on which a sacrificial layer 304 is formed in operation 201. In embodiments, the sacrificial layer 304 (also referred to as a “sacrificial spacer”) can be deposited or grown on the substrate 302 in any manner known in the art. In embodiments, the sacrificial material can be any material capable of being selectively etched. For example, in embodiments where silicon is used as the substrate, the sacrificial material can be silicon germanium (SiGe), such as epitaxially grown SiGe. However, it should be understood that other combinations of materials with different etch selectivity known in the art can also be utilized.

[0060] That is, this technology has surprisingly discovered that by forming the semiconductor structure 300 according to the method and disclosure herein, the semiconductor structure 300 can be uniquely formed to allow for the self-aligned formation of one or more contacts on the bottom side of the structure 300. Specifically, by initially forming the sacrificial spacer 304, the sacrificial spacer can reserve the space required for one or more features. Furthermore, in embodiments, the sacrificial spacer can also serve as an etch stop layer, providing fully self-aligned features.

[0061] Nevertheless, when SiGe is used as the sacrificial layer 304 material, based on the weight of silicon and germanium in SiGe, the amount of germanium present can be about 5% by weight or greater, such as greater than or about 7.5% by weight, such as greater than or about 10% by weight, such as greater than or about 12.5% ​​by weight, such as greater than or about 15% by weight, such as less than or about 25% by weight, such as less than or about 22.5% by weight, such as greater than or about 25% by weight, such as greater than or about 27.5% by weight, such as greater than or about 30% by weight, such as greater than or about 32.5% by weight, such as greater than or about 35% by weight. % by weight, such as greater than or about 37.5% by weight, such as greater than or about 40% by weight, such as greater than or about 42.5% by weight, such as greater than or about 45% by weight, such as greater than or about 47.5% by weight, such as up to about 50% by weight, or such as less than or about 50% by weight, such as less than or about 40% by weight, such as less than or about 35% by weight, such as less than or about 30% by weight, such as less than or about 25% by weight, such as less than or about 20% by weight, such as less than or about 17.5% by weight, such as less than or about 15% by weight, or any range or value between these.

[0062] Nevertheless, since the sacrificial layer 304 will act as a placeholder for later-formed metallization features (such as bit lines or memory node contacts), the thickness or height of the sacrificial layer can be selected based on the desired thickness or height of the resulting features. Therefore, in embodiments, the sacrificial layer can be deposited or grown to a thickness greater than or about 5 nm, such as greater than or about 10 nm, such as greater than or about 15 nm, such as greater than or about 20 nm, such as greater than or about 25 nm, such as greater than or about 30 nm, such as greater than or about 35 nm, such as greater than or about 40 nm, or such as less than or about 60 nm, such as less than or about 55 nm, such as less than or about 50 nm, such as less than or about 45 nm, such as less than or about 40 nm, or any range or value between these.

[0063] Regardless of the material and thickness of the sacrificial layer 304, during operation 202, one or more junction materials 306 may be formed on the sacrificial layer 304, such as... Figure 3BAs shown. In an embodiment, junction material 306 may be grown or deposited over sacrificial layer 304. In an embodiment, junction material 306 may be grown or deposited directly over sacrificial layer 304 (e.g., without an interposer between sacrificial layer 304 and junction material 306), or may be grown or deposited over one or more interposers (not shown). However, in an embodiment, junction material 306 may be any one or more of the substrate materials discussed above, and may be the same as or different from the material forming substrate 302, depending on individual selection. Furthermore, in an embodiment, p-type or n-type doping may be performed by blanket doping, dopant implantation or modulated dopant distribution, and other methods known in the art.

[0064] However, in embodiments, it has been found that junctions can be doped during the epitaxial growth of the semiconductor structure 300 by including one or more dopants. This process may be advantageous because it eliminates the need to dope the junction after the formation of one or more channels (discussed in more detail below) or as part of a back-side treatment. Therefore, in embodiments, the junction material 306 may undergo blanket doping during the growth or deposition of the layer. For example, in embodiments, the junction material 306 may be epitaxial silicon and undergo P+, P-, N+, and / or N- blanket doping. Blanket doping can be performed as is generally known in the art, such as by including dopants during epitaxial growth. When the junction material 306 contains one or more dopants, the junction material 306 can be used as the source / drain region of the structure 300.

[0065] Furthermore, as described above, this technology has found that targeted and highly consistent doping levels can be achieved by utilizing blanket doping during deposition or growth without subsequent junction processing. For example, in an embodiment, the junction material 306 may have a doping concentration greater than or about 50% of the target doping concentration of the junction material 306 at any point along the junction material 306 or within the junction material 306, such as greater than or about 60%, such as greater than or about 70%, such as greater than or about 80%, such as greater than or about 85%, such as greater than or about 90%, such as greater than or about 92.5%, such as greater than or about 95%, such as greater than or about 97.5%, such as greater than or about 99%, such as greater than or about 99.5%, or any range or value between these values. However, it should be understood that in an embodiment, the target doping concentration may vary (e.g., decrease in an embodiment) as it travels in the direction from the substrate 302 toward the channel material 308. Therefore, in an embodiment, a highly consistent doping level can be compared to the target doping level in a corresponding horizontal extension layer of the junction material. For example, this technology has surprisingly discovered that by forming the junction as part of the precursor structure 300, the individual layers or portions of the junction can have highly consistent doping concentrations, and exhibit little or no variation across layers. Furthermore, due to the vertical formation of the junction, highly precise doping is exhibited within the corresponding region or portion even when the target doping concentration is changed. Therefore, in embodiments, the values ​​discussed above can be associated with points within the corresponding junction layer that have doping concentrations consistent with the target doping concentration of the corresponding layer or portion.

[0066] In this embodiment, during operation 203, channel material 308 may be deposited above the junction material 306, such as... Figure 3C As shown. In an embodiment, the channel material 308 may be deposited directly over the junction material 306 (e.g., without an interposer between the junction material 306 and the channel material 308), or it may be deposited over one or more interposers (not shown). However, in an embodiment, the channel material 308 may be any one or more of the substrate materials discussed above, and may be the same as or different from the materials forming the substrate 302 and / or the junction material 306, by individual selection.

[0067] However, in some embodiments, the channel material layer 308 may be formed of the same material as the junction material 306, except that no dopant is present or only a very small amount of dopant is present. Therefore, in this embodiment, if epitaxial growth is used, the epitaxial growth can continue uninterrupted during the formation of the junction material 306 and the channel material 308, but no dopant may be introduced during the growth of the channel material 308, or only a very small amount of dopant may be introduced. Nevertheless, as mentioned above, in some embodiments, other deposition methods may be used to allow different materials, different processes, or combinations thereof to appear between the junction material 306 and the channel material 308. In any case, in some embodiments, the channel material 308 may be epitaxially grown silicon (or any of the other substrate materials discussed above), with a small amount of dopant or no dopant present in the layer.

[0068] In this implementation, regardless of the material chosen, the trench can be deposited to a height corresponding to the desired trench length. Therefore, in an embodiment, the channel may be deposited to a height greater than or about 10 nm, such as greater than or about 15 nm, such as greater than or about 20 nm, such as greater than or about 25 nm, such as greater than or about 30 nm, such as greater than or about 35 nm, such as greater than or about 40 nm, such as greater than or about 45 nm, such as greater than or about 50 nm, such as greater than or about 55 nm, such as greater than or about 60 nm, such as greater than or about 65 nm, such as greater than or about 70 nm, such as greater than or about 75 nm, such as greater than or about 80 nm, such as greater than or about 90 nm, such as greater than or about 100 nm, such as greater than or about 120 nm, such as greater than or about 140 nm, such as greater than or about 160 nm, such as greater than or about 180 nm, such as greater than or about 200 nm, such as greater than or about 220 nm, such as greater than or about 240 nm, or such as greater than or about 250 nm. nm, or such as less than or about 250 nm, such as less than or about 200 nm, such as less than or about 150 nm, such as less than or about 100 nm, or any range or value in between.

[0069] In this embodiment, the second junction material 310 may be grown or deposited on top of the channel material 308 during operation 204, such as Figure 3DAs shown. In embodiments, the second junction material 310 may be grown or deposited directly over the channel material layer 308 (e.g., without an intermediary layer between the channel material layer 308 and the second junction material 310), or it may be grown or deposited over one or more intermediary layers (not shown). However, in embodiments, the second junction material 310 may be any one or more of the substrate materials discussed above, and may be the same as or different from the materials forming the substrate 302, junction material 306, and / or channel material layer 308, by individual selection. Furthermore, in embodiments, p-type or n-type doping may be performed by blanket doping, dopant implantation, or modulated dopant distribution, and other methods known in the art.

[0070] In embodiments, the second junction material 310 may undergo blanket doping during layer growth or deposition. For example, in embodiments, the second junction material 310 may be epitaxial silicon and undergo P+, P-, N+, and / or N- blanket doping. In embodiments, the doping of the second junction material 310 may be the same as or different from that of the junction material 306. Blanket doping may be performed as is generally known in the art, such as by including dopants during epitaxial growth. When the second junction material 310 contains one or more dopants, the second junction material 310 may be used as a second source / drain region of structure 300.

[0071] Furthermore, as described above, this technology has discovered that targeted and highly consistent doping levels can be achieved by utilizing blanket doping during deposition or growth. For example, in an embodiment, the second junction material 310 may have a doping concentration greater than or about 50% of the average doping concentration of the second junction material 310 at any point along or within the second junction material 310, such as greater than or about 60%, greater than or about 70%, greater than or about 80%, greater than or about 85%, greater than or about 90%, greater than or about 92.5%, greater than or about 95%, greater than or about 97.5%, greater than or about 99%, or greater than or about 99.5%. Moreover, the doping level may be within any one or more of the aforementioned ranges of the target doping level (e.g., the average doping concentration is one embodiment of the target concentration).

[0072] Furthermore, in this embodiment, the second junction material 310 may be formed of the same material as the junction material 306. Therefore, in this embodiment, if epitaxial growth is used, the epitaxial growth can continue uninterruptedly during the formation of the junction material 306, the channel material layer 308, and the second junction material 310, but the dopant can be introduced during the formation of the junction material 306 and the second junction material 310, rather than during the formation of the channel material layer 308. Nevertheless, as described above, in this embodiment, other deposition methods can be used so that different materials, different processes, or combinations thereof appear among one or more of the first channel material layer 306, the channel material layer 308, and the second junction material 310. In any case, in this embodiment, the second junction material 310 may be epitaxially grown silicon (or any other substrate material discussed above) with a dopant amount similar to or substantially equal to that of the junction material 306. In any case, this substrate formation process (or the substrate provided by it) allows for structures or features with high aspect ratios, or other complex features (e.g., one or more turns or bends from the center access hole), which have a high degree of consistency and target doping levels that are difficult to achieve using conventional processes.

[0073] However, in some embodiments, one or more channel material layers 306 may instead be formed of a single material, such as any or more of the substrate materials described above. In such embodiments, one or more channel material layers 306 may undergo source / drain formation known in the art, such as by forming them using one or more fabric plants after forming the trench isolation 414, as will be discussed in more detail below.

[0074] In the implementation, Figure 3D The semiconductor structure 300 shown can form the precursor structure described herein. That is, the precursor structure formed according to the present technology can be carefully formed to provide one or more self-aligned features. However, in an embodiment, the precursor semiconductor structure 300 may include a contact pad 312 formed over the second junction material 310. The contact pad 312 may include one or more dielectric materials, such as oxide-containing materials, nitride-containing materials, or other materials known in the art.

[0075] Although it should be made clear that the precursor semiconductor structure 300 can be advantageously used to form a variety of challenging structures, Figures 4A to 4G and Figures 5A to 5D Exemplary structures and methods for forming such structures are shown, illustrated using only the precursor semiconductor structure 300. However, it should be understood that this example is non-limiting, and further structures and methods for forming such structures from the aforementioned precursors are contemplated.

[0076] Nevertheless, such as Figure 4AAs shown, structure 400 may have one or more trench isolations 414 formed through junction material 406, channel material 408, and second junction material 410. Such trenches can be formed in ways known in the art, such as by patterning and etching, such as by utilizing mask 416 and any etching process known in the art. However, in embodiments, the etching of the trench isolations 414 can be as follows: Figure 4A and Figure 4B The two-step operation is illustrated. First, the trench 414 can be etched according to any one or more methods known in the art, and then a second etching operation selectively etching the sacrificial material 404 can be performed. In this way, highly aligned and uniform trenches 414 can be formed in the structure 400.

[0077] That is, in addition to the benefits mentioned above, excellent depth control can be obtained by utilizing this type of selective etching. Furthermore, if targeting... Figure 3D The text line etching is discussed in more detail, demonstrating that highly customized etching depths can be achieved without additional lithography or patterning processes by utilizing sacrificial materials with different etching selectivity than channel and / or junction materials.

[0078] like Figure 4C As shown in the exemplary embodiments, trench 414 may be filled with an insulating material 420, such as a dielectric material. In this way, the insulating material 420 can electrically insulate and support the metallization features (discussed in more detail below). However, in embodiments, the insulating material 420 may be a dielectric material, such as an oxide-containing material, a nitride-containing material, or a combination thereof. In embodiments, the insulating material 420 may include one or more of the following: silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, combinations thereof, or other dielectric materials known in the art, formed using any filling methods discussed above and known in the art.

[0079] See Figure 4D In the illustrated embodiment, one or more word line grooves 422 may be formed in operation 205. Because... Figures 4A to 4G An exemplary embodiment for forming metallized bit lines is shown, so that word line trenches 422 can advantageously extend vertically to sacrificial material 404. However, it should be understood that in the embodiment, word line trenches reaching the substrate 402 can be formed through sacrificial material 404 using one or two etching steps. In any case, in the illustrated embodiment, sacrificial material 404 can be retained during word line trench 422 formation by utilizing materials with etch selectivity to junction material 406, channel material 408, and junction material 410. This allows space to be reserved for self-aligned bit lines to be formed without the need for additional patterning or lithography operations, which will be discussed in more detail below.

[0080] In an implementation, after the trench 422 is formed, it can be formed with 4F 2 One or more additional components associated with a dynamic random access memory (DRAM) component, such as Figure 4E As shown. For example, the gate dielectric 424 may generally be formed around the periphery of the trench 422. Additionally or alternatively, if silicon is used as the channel material 408, the trench 422 may undergo in-situ vapor generation to provide silicon oxide as the gate dielectric 424 around the periphery of the trench 422. Nevertheless, in embodiments, the gate dielectric 424 may be a dielectric material such as silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, combinations thereof, or other dielectric materials known in the art, which is formed using any of the filling methods discussed above and known in the art.

[0081] In addition, such as Figure 4E As shown, in one embodiment, gate metal 426 may be formed within trench 422 along gate dielectric 424. Gate metal 426 may be a conductive material with low resistivity, such as tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species thereof, alloys thereof, or combinations thereof, deposited by any one or more methods known in the art or as described above. Nevertheless, as shown, gate metal 426 may be under-punched to remove it from the bottom surface of trench 422, thereby separating adjacent gates 426.

[0082] After stamping, insulating material 428 may be filled in the trench 422 between adjacent gates 426. Nevertheless, in embodiments, insulating material 428 may be a dielectric oxide, such as one or more of silicon oxide, silicon carbide, silicon oxynitride, silicon carbonitride, or combinations thereof, or other dielectric materials known in the art, which are formed using any filling methods discussed above and known in the art.

[0083] Furthermore, as shown, an insulating plug 430 may be formed between the gate 426 and the top surface 432 of the channel 408. The insulating plug 430 may be formed of any insulating material known in the art, such as one or more dielectric materials, including silicon nitride, silicon oxynitride, silicon dioxide, or other similar materials. Although the description herein will generally discuss silicon dioxide or silicon nitride as dielectric and / or spacer materials, it should be understood that any number of dielectric materials may be used in embodiments of the art, and the art should not be limited to any particular dielectric material in which features may be formed.

[0084] In one embodiment, junction 410 may undergo a metallization process, such as silicide, to form a metallized interface over junction 410. For example, a metal layer may be coated on junction 410, which is then exposed to a silicide process to form metallized contacts 436. In one embodiment, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species of the foregoing, alloys of the foregoing, or combinations thereof. Thus, the resulting interface may be any one or more of the metals described above, with a channel material such as silicon. Only in this example may the interface layer be titanium silicide, molybdenum silicide, hafnium silicide, or combinations thereof.

[0085] Nevertheless, one or more memory node contacts 434 may be formed above the metallized contacts 436. In embodiments, the metal may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species of the foregoing, alloys of the foregoing, or combinations thereof. The memory node contact metal may be selected to be the same as or different from the gate metal 426. As shown, in an embodiment, a memory node landing pad 438 may also be formed above the memory node contacts 434.

[0086] In one implementation, the front-side DRAM capacitor can be completed after the memory node contact features are formed. However, in another implementation, as described above, structure 400 may undergo one or more further operations, which can also be considered front-side operations.

[0087] Nevertheless, in operation 206, structure 400 is rotated 180 degrees (referred to herein as a "flip"), such that the previous top surface of structure 400 is now oriented as the bottom surface. However, as will be discussed in more detail below, in an implementation, this step may not be necessary for access to the sacrificial layer 404. Nevertheless, in operation 206, access to the sacrificial material 404 can be provided for the selective removal of the sacrificial layer 404. Figure 4F As shown, this pathway can be provided by thinning the substrate 402 from the back side. In an embodiment, all or part of the substrate 402 may be removed from the back side to provide access to the sacrificial material 404.

[0088] However, as is known in the art, sacrificial materials such as SiGe are highly selective. Therefore, in an embodiment, operation 206 may include providing one or more access holes through substrate 402 to selectively etch sacrificial material 404, rather than completely removing substrate 402. Additionally or alternatively, side access holes may be provided or enlarged, either alone or in combination with one or more access holes, such as from side 444. Regardless of the method used, it should be understood that sacrificial material 404 is selected to have etching specificity that allows sacrificial material 404 to be selectively etched relative to insulating layers 420 and 428 and junction material 406, channel material 408, and junction material 410. Thus, insulating layer 420 remains disposed between adjacent void spaces 446 formed by removing sacrificial material 404. Nevertheless, although examples have been provided, it should be understood that at operation 206, sacrificial material 404 may be removed using any method known in the art, and as Figure 4F As shown, the sacrificial material 404 has been removed, providing a void space 446 defined by the insulating material 420 and the junction material 406.

[0089] See Figure 4G In the illustrated embodiment, during operation 207, the void space 446 may allow access to the first source / drain region (e.g., the junction material 406 in the illustrated embodiment). The first source / drain region 406 may undergo a metallization process, such as silicide, to form a metallization interface 450 between the void space 446 and the first source / drain region 406. For example, a metal layer may be coated over the first source / drain 406, which is then exposed to the silicide process. In this embodiment, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species of the foregoing, alloys of the foregoing, or combinations thereof. Thus, the resulting interface may be a metallization layer of any one or more of the foregoing metals and a channel material such as silicon. Only in this example may the interface layer be titanium silicide, molybdenum silicide, hafnium silicide, or a combination thereof.

[0090] Nevertheless, in this embodiment, the void space 446 can then be filled with a metal bit line 448 material. In this embodiment, the metal can be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species of the above, alloys of the above, or combinations thereof. The bit line metal is selected to be the same as or different from the gate metal 426. As shown in the illustrated embodiment, the bit line metal 448 can be filled in the void space 446 in a highly aligned (e.g., self-aligned) manner. Therefore, in this embodiment, the metal bit line 448 can be directly disposed above the corresponding channel 408 without any mask or photoresist operation.

[0091] However, this technology also surprisingly finds that the processes and methods discussed herein also allow for the inclusion of bit line spacers or air gaps. For example, in an embodiment, bit line metal 448 may fill the air gap space 446 such that bit line metal 448 at least partially intersects the source / drain region 406. For example, in an embodiment, bit line metal 448 may be offset, or have a smaller width than the corresponding overlay channel 408, such that the bit line offset (or has a smaller width) is approximately 10% to approximately 90% of the corresponding channel width, such as greater than or about 15%, such as greater than or about 20%, such as greater than or about 30%, such as greater than or about 40%, such as greater than or about 50%, such as greater than or about 60%, such as greater than or about 70%, such as greater than or about 80%, such as greater than or about 85%, or such as less than or about 80%, less than or about 70%, less than or about 60%, less than or about 50%, less than or about 40%, less than or about 30%, less than or about 20%, less than or about 15%, or any range or value between these values. The aforementioned spacers can be removed downstream to form an air gap as needed.

[0092] In one embodiment, the insulating material 420 may be filled or etched after the trench 414 is filled, such that only a portion of the trench 414 is filled with the insulating material 420. Therefore, the metal bit line 448 may be filled such that the bit line 448 is slightly offset from the center of the corresponding channel, but is still supported by the insulating layer 420. In this embodiment, the metal bit line 448 can be considered as a folding unit. Nevertheless, it should be understood that, regardless of whether the offset (or width reduction) is used alone or in combination with the partially filled trench 414, according to the aforementioned ratio, at least a portion of the bit line metal 448 intersects with the corresponding channel. Furthermore, in this embodiment, the partially filled trench 414 leads to the sacrificial material 404. Therefore, in this embodiment, the removal of the sacrificial material 404 and the filling of the bit line metal 448 can be considered as a front-end process, and the remaining portion of the trench 414 can be filled with the insulating material after the metal bit line 448 is formed.

[0093] Nevertheless, after filling, bit line 448 can be further metallized as needed. In any case, structure 400 can re-enter the regular processing flow for further processing, such as for vertical cell DRAM arrays (such as 4F...). 2 Polishing, addition, or interconnection of DRAM arrays, etc. For example, semiconductor structure 400 may undergo contact redistribution, pad formation, and / or copper contact formation. Despite the additional processing, the semiconductor structure can still exhibit significantly improved bit line resistivity and alignment with little or no damage typically associated with conventional technologies.

[0094] Next, see Figure 5A Examples of forming one or more self-aligned storage nodes can be provided. Figure 5AThe structure 500 shown can undergo a process similar to that described above. Figures 4A to 4C The operations discussed here may branch out into one or more operations or process steps. Although it should be understood that different processing operations may occur... Figure 5A This happened before, but in the implementation method, Figure 5A Can be used with Figures 4A to 4C One or more operations occurring in a similar manner are formed via operation 204, and therefore will not be repeated for clarity. Although it should be understood that a variety of challenging structures can be advantageously formed using the precursor semiconductor structure 300, Figures 5A to 5D Exemplary structures and methods for forming such structures are shown, with the precursor semiconductor structure 300 being illustrative only. However, it should be understood that this example is non-limiting, and further structures and methods for forming such structures from the aforementioned precursors are contemplated.

[0095] See Figure 5A In an implementation, one or more word line grooves 522 may be formed in operation 205. Because... Figures 5A to 5D One or more metallized memory node contacts can be formed, thus allowing the word line trench 522 to advantageously extend vertically through the sacrificial material 504. In an embodiment, the word line trenches extending through the sacrificial material 504 to the substrate 502 can be formed using one or two etching steps, thereby separating adjacent portions of the sacrificial layer 504 in a spaced-apart and isolated manner below the respective junction 506 and channel 508. As shown, the sacrificial material 504 can be neatly aligned with the respective channel, allowing for precise formation of the subsequently formed memory node contacts in a self-aligned manner. In any case, in the illustrated embodiment, by utilizing a material with etch selectivity for the junction material 406, channel material 408, and junction material 410, the sacrificial material 404 can be retained during the first etching of the word line trench 522 formation. This allows for height-controlled depth of the trench 522 to be achieved without further processing.

[0096] After the trench 522 is formed, in the embodiment, it can be formed with 4F 2 One or more additional components associated with a dynamic random access memory (DRAM) component, such as Figure 5B As shown. For example, the gate dielectric 524 may be formed generally around the periphery of the trench 522. Additionally or alternatively, if silicon is used as the channel material 508, the trench 522 may be subjected to in-situ vapor generation to provide silicon oxide as the gate dielectric 524 around the periphery of the trench 522. However, in embodiments, the gate dielectric 524 may be a dielectric material such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, combinations thereof, or other dielectric materials known in the art, formed using any of the filling methods discussed above and known in the art.

[0097] In addition, such as Figure 5B As shown, in one embodiment, gate metal 526 may be formed within trench 522 along gate dielectric 524. Gate metal 526 may be a conductive material with low resistivity, such as tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species thereof, alloys thereof, or combinations thereof, deposited by any one or more methods known in the art or as described above. Nevertheless, as shown, gate metal 526 may be under-punched to remove it from the bottom surface of trench 522, thereby separating adjacent gates 526.

[0098] In one embodiment, after stamping, insulating material 528 may be filled in the trench 522 between adjacent gates 526. However, in another embodiment, insulating material 528 may be a dielectric oxide, such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon carbonitride, or a combination thereof, or other dielectric materials known in the art, formed using any filling method discussed above and known in the art.

[0099] Furthermore, as shown, an insulating plug 530 may be formed between the gate 526 and the top surface 532 of the channel 508. The insulating plug 530 may be formed of any insulating material known in the art, such as one or more dielectric materials, including silicon nitride, silicon oxynitride, silicon dioxide, or other similar materials. Although the description herein will formally discuss silicon dioxide or silicon nitride as dielectric and / or spacer materials, it should be understood that any number of dielectric materials may be used in embodiments of the present technology, and the present technology should not be limited to any particular dielectric material in which features may be formed.

[0100] In one embodiment, junction 510 may undergo a metallization process, such as silicide, to form a metallized interface over junction 510. For example, a metal layer may be coated on junction 510, which is then exposed to a silicide process to form metallized contacts 536. In one embodiment, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species of the foregoing, alloys of the foregoing, or combinations thereof. Thus, the resulting interface may be a metallization layer of any one or more of the foregoing metals and a channel material such as silicon. Only in this example may the interface layer be titanium silicide, molybdenum silicide, hafnium silicide, or combinations thereof.

[0101] Nevertheless, in embodiments, one or more bit lines 534 may be formed on the metallized contact 536. In embodiments, the metal may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species of the foregoing, alloys of the foregoing, or combinations thereof. The bit line metal may be selected to be the same as or different from the gate metal 526 described above.

[0102] After the bit lines are formed, the front-side DRAM capacitors can be completed. However, in an embodiment, as described above, structure 400 may undergo one or more further operations, which can also be considered as front-side operations.

[0103] Nevertheless, in operation 206, structure 500 can be rotated 180 degrees (referred to herein as "flipping"), such that the previous top surface of structure 500 is now oriented as the bottom surface. However, as mentioned above, in this embodiment, this step may not be necessary for access to the sacrificial layer 504. Nevertheless, in operation 206, access to the sacrificial material 504 can be provided for selective removal of the sacrificial layer 504. Figure 5C As shown, this pathway can be provided by thinning the substrate 502 from the back side. In an embodiment, all or part of the substrate 502 may be removed from the back side to provide access to the sacrificial material 504.

[0104] However, as is known in the art, sacrificial materials such as SiGe are highly selective. Therefore, in an embodiment, operation 206 may include providing one or more access holes through substrate 502 to selectively etch sacrificial material 504, rather than completely removing substrate 502. Additionally or alternatively, side access holes may be provided or enlarged, either alone or in combination with one or more access holes, such as from side 544. Regardless of the method used, it should be understood that sacrificial material 504 is selectively etched with etching specificity that allows sacrificial material 504 to be selectively etched relative to insulating layers 520 and 528 and junction material 506, channel material 508, and junction material 510. Thus, insulating layer 520 remains disposed between adjacent void spaces 546 formed due to the removal of sacrificial material 404. Nevertheless, although examples have been provided, it should be understood that at operation 206, sacrificial material 504 can be removed using any method known in the art, and as... Figure 5C As shown, the sacrificial material 504 has been removed, providing one or more void spaces 546 defined by the insulating material 520 and the junction material 506.

[0105] See Figure 5DIn this embodiment, during operation 207, the void space 546 may allow access to a first source / drain region (e.g., junction material 506 in the illustrated embodiment). The first source / drain region 506 may undergo a metallization process, such as silicide, to form a metallization interface 536 between the void space 546 and the first source / drain region 506. For example, a metal layer may be coated on the first source / drain 506, which is then exposed to the silicide process. In this embodiment, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species of the foregoing, alloys of the foregoing, or combinations thereof. Thus, the resulting interface may be a metallization layer of any one or more of the foregoing metals and a channel material such as silicon. In this example only, the interface layer may be titanium silicide, molybdenum silicide, hafnium silicide, or a combination thereof.

[0106] Nevertheless, the void space 546 can then be filled with the metal storage node contact 548 material. In embodiments, the metal can be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, metal species of the foregoing, alloys of the foregoing, or combinations thereof. The storage node contact metal can be selected to be the same as or different from the gate metal 526 described above. As shown in the illustrated embodiment, the storage node contact metal 548 can be filled in the void space 546 in a highly aligned (e.g., self-aligned) manner. Therefore, in embodiments, the storage node contacts 548 can be directly disposed above the corresponding channels 508 without any mask or photoresist operation.

[0107] In this implementation, after filling, the memory node contacts 548 may be further metallized as needed. Regardless, the structure 500 can re-enter a regular processing flow for further processing, such as for vertical cell DRAM arrays (e.g., 4F...). 2 Polishing, addition, or interconnection of DRAM arrays, etc. For example, semiconductor structure 500 may undergo contact redistribution, bonding pad formation, and / or copper contact formation, including landing pad 550 formation. Despite the additional processing, the semiconductor structure can exhibit significantly improved bit line and memory node contact resistivity and alignment with little or no damage generally associated with conventional technologies.

[0108] It should be understood that the specific steps illustrated in the figures provide a method for forming a 4F according to various implementations. 2A specific method for DRAM arrays. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments may perform the above steps in a different order. Furthermore, each step shown in the figures may include multiple sub-steps, which may be performed in different orders depending on the specific application. Additionally, extra steps may be added or removed depending on the application. Many variations, modifications, and alternatives also fall within the scope of this disclosure.

[0109] The terms “about,” “approximately,” or “substantially” as used herein are to be interpreted as within the range that a person skilled in the art would expect from the specification.

[0110] In the foregoing description, numerous specific details have been listed for ease of explanation, in order to provide a thorough understanding of the various implementations. However, it will be apparent that some implementations can be carried out without some of these specific details. In other cases, well-known structures and apparatuses are represented in block diagram form.

[0111] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments will provide an advantageous disclosure for implementing at least one embodiment. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the spirit and scope of some of the embodiments set forth in the appended claims.

[0112] Specific details have been provided in the foregoing description to offer a thorough understanding of the implementation. However, it is understood that implementations can be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form to avoid obscuring the implementation with unnecessary details. In other cases, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary details to avoid obscuring the implementation.

[0113] Furthermore, it should be noted that each implementation can be described as a process, which may be represented by a flowchart, data flow diagram, structure diagram, or block diagram. While a flowchart may describe operations as a sequential process, many operations can be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates upon completion of its operations, but there may be additional steps not included in the diagram. A process can correspond to a method, a function, a procedure, a subroutine, a subroutine, etc. When a process corresponds to a function, its termination can correspond to the function returning to the calling function or the main function.

[0114] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and other media capable of storing, containing, or carrying instructions and / or data. Code segments or machine-executable instructions can represent any combination of procedures, functions, subroutines, programs, routines, subroutines, modules, software packages, classes, or instructions, data structures, or program statements. A code segment can be coupled to another code segment or hardware circuitry by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., can be passed, forwarded, or transmitted in any suitable manner, including memory sharing, message passing, token passing, network transmission, etc.

[0115] Furthermore, the implementation can be carried out using hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented using software, firmware, middleware, or microcode, the program code or code segments that perform the necessary tasks can be stored in a machine-readable medium. The processor can then perform the necessary tasks.

[0116] In the foregoing description, features have been described with reference to specific embodiments thereof, but it should be understood that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used individually or in combination. Furthermore, embodiments may be used in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of this specification. Therefore, this specification and accompanying drawings should be considered illustrative rather than restrictive.

[0117] Furthermore, for illustrative purposes, the methods are described in a specific order. It should be understood that in alternative embodiments, the methods may be performed in a different order. It should also be understood that the methods described above can be executed by hardware components or implemented as a sequence of machine-executable instructions that can be used to cause a machine (such as a general-purpose or special-purpose processor or logic circuit programmed with instructions) to execute these methods. These machine-executable instructions may be stored on one or more machine-readable media, such as optical discs or other types of optical discs, floppy disks, ROM, RAM, EPROM, EEPROM, magnetic cards or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions. Alternatively, these methods may also be executed by a combination of hardware and software.

Claims

1. A vertical cell dynamic random access memory (DRAM) precursor structure, comprising: a substrate; one or more sacrificial layers formed over the substrate; one or more first epitaxially grown junction materials formed over the sacrificial layers; an epitaxially grown channel material formed over the first junction materials; one or more second epitaxially grown junction material layers formed over the channel material.

2. The vertical cell dynamic random access memory (DRAM) precursor structure of claim 1, wherein the one or more sacrificial layers are epitaxially grown silicon germanium (SiGe).

3. The vertical cell dynamic random access memory (DRAM) precursor structure of claim 2, wherein germanium is present in the one or more sacrificial layers in an amount greater than or about 5% by weight.

4. The vertical cell dynamic random access memory (DRAM) precursor structure of claim 1, wherein the one or more sacrificial layers have a thickness greater than or about 5 nm.

5. The vertical cell dynamic random access memory (DRAM) precursor structure of claim 1, wherein the one or more first epitaxially grown junction material layers, the one or more second epitaxially grown junction material layers, or both the one or more first epitaxially grown junction material layers and the one or more second epitaxially grown junction material layers have a doping concentration at any point along or within the junction material layers that is greater than or about 50% of an average doping concentration of the respective layer of junction material.

6. The vertical cell dynamic random access memory (DRAM) precursor structure of claim 1, wherein the one or more first epitaxially grown junction material layers comprise n-doped silicon, the channel material comprises silicon, and the one or more second epitaxially grown junction material layers comprise n-doped silicon.

7. A method for forming a vertical cell dynamic random access memory (DRAM) precursor structure, comprising: growing one or more sacrificial layers over a semiconductor substrate; epitaxially growing a channel material over the one or more sacrificial layers while providing one or more n-type dopants, forming one or more first junction layers; epitaxially growing the channel material over the one or more first junction layers, forming one or more channel layers; epitaxially growing the channel material over the one or more channel layers while providing one or more n-type dopants, forming one or more second junction layers.

8. The method of claim 7, wherein the one or more sacrificial layers are grown to a height greater than or about 10 nm.

9. The method of claim 8, wherein the one or more sacrificial layers contain germanium in an amount greater than or about 5% by weight, based on the weight of the one or more sacrificial layers.

10. The method of claim 7, wherein the one or more first junction layers, the one or more second junction layers, or both the one or more first junction layers and the one or more second junction layers have a target doping concentration, wherein a doping concentration along or at any point in the one or more of the first junction layers, the second junction layers, or both the first junction layers and the second junction layers is greater than or about 50% of the target doping concentration of the respective layer.

11. The method of claim 7, wherein the one or more channel layers are grown to a height greater than or about 10 nm.

12. A vertical cell dynamic random access memory (DRAM) array, comprising: a plurality of metalized bit lines arranged in a first horizontal direction; a plurality of word lines arranged in a second horizontal direction; a plurality of channels extending in a vertical direction substantially orthogonal to the first and second horizontal directions such that the plurality of metalized bit lines intersect source / drain regions of the plurality of channels and the plurality of word lines intersect gate regions of the plurality of channels; and a dielectric material spacer disposed between adjacent bit lines of the plurality of bit lines.

13. The vertical cell dynamic random access memory (DRAM) array of claim 12, wherein the dielectric material spacer comprises a dielectric oxide.

14. The vertical cell dynamic random access memory (DRAM) array of claim 12, wherein at least a portion of the metalized bit lines is offset from a respective channel of the plurality of channels by about 10% to less than or about 90% of a width of the respective channel.

15. The vertical cell dynamic random access memory (DRAM) array of claim 14, wherein at least a portion of the dielectric material spacer at least partially intersects a source / drain region of the plurality of channels.

16. The vertical cell dynamic random access memory (DRAM) array of claim 12, wherein the bit lines are self-aligned bit lines disposed beneath single crystalline channels.

17. The vertical cell dynamic random access memory (DRAM) array of claim 12, further comprising one or more metalized storage node contacts disposed on top ends of the plurality of channels.

18. A method of forming a vertical cell dynamic random access memory (DRAM) array, comprising: providing a substrate, comprising: a sacrificial material over a substrate material, and one or more channel materials disposed over the sacrificial layer, etching the substrate to form one or more shallow trench isolations and a plurality of vertically extending channels having at least first source / drain regions; forming a dielectric material in the one or more shallow trench isolations; removing at least a portion of the sacrificial material forming a void space at least partially intersecting a portion of the first source / drain regions of the vertically extending channels; and forming a metalized bit line in the void space.

19. The method of claim 18, further comprising forming word lines in the word line trenches, wherein the word lines intersect gate regions of the plurality of vertically extending channels.

20. The method of claim 18, wherein the portion of the sacrificial material is removed through one or more access holes.

21. The method of claim 18, wherein the portion of the sacrificial material is removed through an exposed region at a backside or side surface of the substrate.

22. The method of claim 18, further comprising reducing a thickness of the substrate material prior to removing the at least a portion of the sacrificial material.

23. The method of claim 18, further comprising removing all of the sacrificial material.

24. The method of claim 18, wherein the one or more channel materials comprise a doped channel material and an undoped channel material.

25. The method of claim 18, further comprising forming one or more of the plurality of vertically extending channels by depositing a doped channel material over the sacrificial material, depositing an undoped channel material over the doped channel material, and depositing a second doped channel material over the undoped channel material.

26. The method of claim 18, further comprising flipping the substrate and removing all or a portion of the substrate prior to removing the sacrificial material.

27. The method of claim 18, further comprising silicidizing the first source / drain regions prior to forming the metallized bit lines.

28. The method of claim 18, wherein the metallized bit lines comprise tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, a metal-containing species of each of the foregoing, an alloy of each of the foregoing, or a combination of each of the foregoing.

29. A vertical cell dynamic random access memory (DRAM) array, comprising: a plurality of bit lines arranged in a first horizontal direction; a plurality of word lines arranged in a second horizontal direction; a plurality of channels extending in a vertical direction generally orthogonal to the first horizontal direction and the second horizontal direction, such that the plurality of bit lines intersect source / drain regions of the plurality of channels and the plurality of word lines intersect gate regions of the plurality of channels; and a plurality of metallized storage node contacts.

30. The vertical cell dynamic random access memory (DRAM) array of claim 29, wherein the plurality of metallized storage node contacts are self-aligned under single crystalline channels.

31. The vertical cell dynamic random access memory (DRAM) array of claim 29, wherein the plurality of bit lines comprise metallized bit lines disposed on top ends of the plurality of channels.

32. A method of forming a vertical cell dynamic random access memory (DRAM) array, comprising: providing a substrate, comprising: a sacrificial layer over a substrate material, and one or more channel materials disposed over the sacrificial layer, etching the substrate to form one or more shallow trench isolations and a plurality of vertically extending channels having at least a first source / drain region; ​ forming a dielectric material in one or more of the shallow trench isolations; removing at least a portion of the sacrificial material, forming a void space at least partially intersecting a portion of the first source / drain region of the vertically extending channel; and forming one or more metallized storage node contacts in the void space.

33. The method of claim 32, further comprising forming word lines in the word line trenches, wherein the word lines intersect gate regions of the plurality of channels.

34. The method of claim 32, further comprising forming one or more of the plurality of vertically extending channels by depositing a doped channel material over the sacrificial material, depositing an undoped channel material over the doped channel material, and depositing a second doped channel material over the undoped channel material.

35. The method of claim 32, further comprising flipping the substrate and removing all or a portion of the substrate prior to removing the sacrificial material.

36. The method of claim 32, further comprising silicidizing the first source / drain region prior to forming the one or more metallized storage node contacts.

37. The method of claim 32, wherein the one or more metallized storage node contacts comprise tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, a metal-containing species of each of the foregoing, an alloy of each of the foregoing, or a combination of each of the foregoing.

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