Data technology for system startup procedures

Abstract

The present application is directed to data technology for a system boot procedure. A memory system may receive a set of commands from a host system as part of a boot procedure for the host system. The set of commands may request data stored in a first set of locations of a memory array of the memory system. The memory system may retrieve the data from the first set of locations based on receiving the commands as part of the boot procedure. The memory system may determine an order in which to retrieve the data from each location in the first set of locations. The memory system may transfer the data from the first set of locations to a second set of locations based on the order in which to retrieve the data from each location in the first set of locations.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 16 / 888,212 filed by Liang et al. on May 29, 2020, entitled “DATA TECHNIQUES FOR SYSTEM BOOT PROCEDURES,” which is assigned to the present assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to data technology for system startup procedures. Background Art

[0004] The following generally relates to one or more systems for memory, and more specifically, to data techniques for system boot procedures.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to a logical 1 or a logical 0. In some examples, a single memory cell can support more than two possible states, and the memory cell can store either of the two possible states. In order to access information stored by a memory device, a component can read or sense the state of one or more memory cells within the memory device. In order to store information, a component can write or program one or more memory cells within the memory device to a corresponding state.

[0006] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), three-dimensional cross-point memory (3D XPoint), NOR and NAND memory devices, etc. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless they are periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long time even in the absence of external power. Summary of the invention

[0007] An apparatus is described. The apparatus may include: a memory array; and a control component coupled to the memory array and configured to cause the apparatus to: receive a set of commands from a host system as part of a boot procedure for a host system, the set of commands requesting data stored in a first set of locations of the memory array; retrieve the data from the first set of locations of the memory array based at least in part on the received set of commands as part of the boot procedure; determine an order in which to retrieve the data from each location in the first set of locations as part of the boot procedure; and transfer the data from the first set of locations to a second set of locations based at least in part on the order in which to retrieve the data from each location in the first set of locations.

[0008] A non-transitory computer-readable medium is described. The non-transitory computer-readable medium may store code including instructions that, when executed by a processor of an electronic device, may cause the electronic device to: receive a set of commands from a host system as part of a boot procedure for a host system, the set of commands requesting data stored in a first set of locations in a memory array; retrieve the data from the first set of locations in the memory array based at least in part on receiving the set of commands as part of the boot procedure; determine an order in which to retrieve the data from each location in the first set of locations as part of the boot procedure; and transfer the data from the first set of locations to a second set of locations based at least in part on the order in which to retrieve the data from each location in the first set of locations.

[0009] A method is described. The method may be performed by a memory system. The method may include: receiving a set of commands from a host system as part of a boot procedure for the host system, the set of commands requesting data stored in a first set of locations in a memory array; retrieving the data from the first set of locations in the memory array based at least in part on receiving the set of commands as part of the boot procedure; determining as part of the boot procedure an order in which to retrieve the data from each location in the first set of locations; and transferring the data from the first set of locations to a second set of locations based at least in part on the order in which to retrieve the data from each location in the first set of locations. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system supporting data technology for a system boot procedure according to examples disclosed herein is described.

[0011] Figure 2 An example of a data scheme supporting data techniques for a system boot program according to examples disclosed herein is described.

[0012] Figure 3 A block diagram showing a memory system supporting data techniques for a system boot procedure according to examples disclosed herein.

[0013] Figure 4 and 5 A flow chart illustrating one or more methods of supporting data techniques for a system boot procedure according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0014] Some systems (e.g., electronic devices, smart phones, etc.) may take a certain amount of time to boot up. For example, a host system may request data from a memory system of the system during a boot procedure (e.g., while power is being provided to the device). In some cases, the boot procedure may take a relatively long time to execute, for example, because the host system requests a relatively large amount of data during the boot procedure (e.g., it may take a relatively large period of time to read the requested data). This relatively long time for the boot procedure may cause the memory system to experience performance loss, increased signaling or processing overhead, or increased power consumption. Therefore, it may be desirable to improve the user's experience by reducing the boot time of the overall system, which may result in increased efficiency of the memory system, among other benefits.

[0015] Systems, devices, and techniques are described for a memory system to organize at least some data (e.g., information) for a system boot procedure for a host system. For example, a host system may send one or more commands to the memory system requesting data as part of a system boot procedure. The memory system may determine an order of the commands (e.g., a sequential order of locations at which the memory system reads the data). The memory system may reorganize the requested data based on the order. For example, the memory system may transfer data from a random pattern to a sequential layout of physical addresses according to the order of the one or more commands, as described herein. Such techniques may result in reduced boot time (e.g., due to more efficient retrieval of reorganized data for the boot procedure), improved read speeds, reduced power consumption, reduced processing complexity, and improved processing time, among other benefits.

[0016] First, in the reference Figure 1 The features of the present disclosure are described in the context of the described system. Figure 2 The features of the present disclosure are described in the context of the described data scheme. Figures 3 to 5 The described device diagrams and flow charts involving data techniques for a system boot procedure illustrate and describe these and other features of the present disclosure.

[0017] Figure 1An example of a system 100 supporting data techniques for a system boot procedure according to examples disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110.

[0018] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other possibilities.

[0019] System 100 may be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, drone, train, automobile, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0020] The system 100 may include a host system 105 that may be coupled to a memory system 110. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to the memory system 110 and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but it should be understood that the host system 105 may be coupled to any number of memory systems 110 .

[0021] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 may be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105). Examples of the physical host interface may include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a Peripheral Component Interconnect Express (PCIe) interface, a USB interface, a Fibre Channel, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a DIMM interface (e.g., a DIMM socket interface supporting DDR), an Open NAND Flash Interface (ONFI), DDR, a Low Power Double Data Rate (LPDDR). In some cases, the host system 105 may be coupled to the memory system 110 via a corresponding physical host interface for each memory device 130 or memory device 140 included in the memory system 110, or for each type of memory device 130 or memory device 140 included in the memory system 110.

[0022] Memory system 110 may include memory system controller 115, memory device 130, and memory device 140. Memory device 130 may include one or more memory arrays of a first type of memory cells (e.g., a type of non-volatile memory cells), and memory device 140 may include one or more memory arrays of a second type of memory cells (e.g., a type of volatile memory cells). Figure 1 Although one memory device 130 and one memory device 140 are shown in the example of , it should be understood that the memory system 110 may include any number of memory devices 130 and memory devices 140, and in some cases, the memory system 110 may lack memory devices 130 or memory devices 140.

[0023] The memory system controller 115 may be coupled and communicate with the host system 105 (e.g., via a physical host interface). The memory system controller 115 may also be coupled and communicate with the memory device 130 or the memory device 140 to perform operations such as reading data, writing data, erasing data, or refreshing data at the memory device 130 or the memory device 140, as well as other such operations that may be generally referred to as access operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 or the memory devices 140 to perform such commands (e.g., at a memory array within the one or more memory devices 130 or the memory devices 140). For example, the memory system controller 115 may receive commands or operations from the host system 105, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130 or the memory device 140. And in some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 or 140 (e.g., in response to or otherwise in conjunction with a command from the host system 105). For example, the memory system controller 115 may convert a response (e.g., a data packet or other signal) associated with the memory device 130 or 140 into a corresponding signal for the host system 105.

[0024] The memory system controller 115 may be configured for other operations associated with the memory device 130 or the memory device 140. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error checking operations such as error detection operations or error correction operations or error correction code (ECC) operations, encryption operations, cache operations, media management operations, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130 or the memory device 140.

[0025] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0026] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operating codes (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or operations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, when reading from or writing to the memory device 130 or the memory device 140, the data may be stored to the local memory 120 and may be available within the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130 or the memory device 140).

[0027] although Figure 1 The example of the memory system 110 in has been illustrated as including the memory system controller 115, but in some cases the memory system 110 may not include the memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 or local controllers 145 that may be internal to the memory device 130 or memory device 140, respectively, to perform the functions attributed herein to the memory system controller 115. In general, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135 or the local controller 145, or any combination thereof, in some cases. In some cases, the memory system 110 may include a non-transitory computer-readable medium (CRM) (e.g., the local memory 120, the memory device 130, and / or the memory device 140) storing instructions (e.g., firmware) for performing the methods described herein (e.g., methods 400 and 500). For example, the instructions, when executed by the controller 115 (or more specifically, the processor of the controller 115), cause the controller to perform the methods described herein.

[0028] Memory device 140 may include one or more arrays of volatile memory cells. For example, memory device 140 may include random access memory (RAM) memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells. In some examples, memory device 140 may support random access operations (e.g., by host system 105) with reduced latency relative to memory device 130, or may provide one or more other performance differences relative to memory device 130.

[0029] The memory device 130 may include one or more arrays of non-volatile memory cells. For example, the memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM).

[0030] In some examples, memory device 130 or memory device 140 may include (e.g., on the same die or within the same package) a local controller 135 or local controller 145, respectively, which may perform operations on one or more memory cells of memory device 130 or memory device 140. Local controller 135 or local controller 145 may operate in conjunction with memory system controller 115, or may perform one or more functions attributed herein to memory system controller 115. In some cases, memory device 130 or memory device 140 including local controller 135 or local controller 145 may be referred to as a managed memory device, and may include a memory array and related circuitry (e.g., in combination with a local (e.g., on-die or within a package) controller (e.g., local controller 135 or local controller 145). An example of a managed memory device is a managed NAND (MNAND) device.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be a package including one or more dies 160. In some examples, die 160 may be a piece of electronic grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, wherein each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as a single-level cell (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as a multi-level cell (MLC) if configured to store two bits of information each, a triple-level cell (TLC) if configured to store three bits of information each, a quad-level cell (QLC) if configured to store four bits of information each, or more generally, a multi-level memory cell. A multi-level memory cell may provide greater storage density relative to an SLC memory cell, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0033] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share (e.g., be coupled to) a common word line, and memory cells in the same string may share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently programmed or read (programmed or read simultaneously as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, a used page 175 may not be updated without erasing the entire block 170 that includes page 175.

[0036] In some cases, in order to update some data within a block 170 while retaining other data within the block 170, the memory device 130 may copy the data to be retained to a new block 170 and write the updated data to one or more remaining pages of the new block 170. The memory device 130 (e.g., the local controller 135) or the memory system controller 115 may mark or otherwise indicate the data remaining in the old block 170 as invalid or obsolete, and update the L2P mapping table so that the logical address (e.g., LBA) of the data is associated with the new valid block 170, rather than the old invalid block 170. In some cases, such copying and remapping may be better than erasing and rewriting the entire old block 170, for example due to latency or wear considerations. In some cases, one or more copies of the L2P mapping table may be stored within a memory unit of the memory device 130 (e.g., within one or more blocks 170 or planes 165) for use (e.g., reference and update) by the local controller 135 or the memory system controller 115.

[0037] In some cases, an L2P mapping table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that is outdated because the latest or updated version of the data is stored in a different page 175 of the memory device 130. Invalid data has been previously programmed to an invalid page 175, but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the latest version of this data stored on the memory device 130. A page 175 that does not contain data may be a page 175 that has not been written to or has been erased.

[0038] In some cases, the memory system controller 115, the local controller 135, or the local controller 145 may perform operations of the memory device 130 or the memory device 140 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, scrubbing, block scanning, health monitoring, or other operations, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for some or all of the pages 175 in the block 170 to have invalid data in order to be erased and to reuse the block 170, an algorithm known as "garbage collection" may be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example, selecting blocks 170 containing valid and invalid data, selecting pages 175 in the blocks containing valid data, copying valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170), marking data in previously selected pages 175 as invalid, and erasing the selected blocks 170. Thus, the number of erased blocks 170 may be increased so that more blocks 170 may be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0039] In some examples, the memory system 110 may include an error control unit (ECU) 150. For example, the ECU 150 may be in electronic communication with the memory device 130, the memory device 140, one or more controllers (e.g., the memory system controller 115 and / or the local controller 135), or any combination thereof. The ECU 150 may perform operations such as error detection operations, error correction operations, error correction code operations, or a combination thereof. In some cases, a portion of the NAND of the memory device 130 may store a replay script (e.g., a boot sequence). The replay script may include commands and addresses of a boot procedure to track the location of requested boot data during the boot procedure.

[0040] In some examples, the memory system 110 may implement one or more operations for organizing at least some data for a system boot procedure for the host system 105. For example, the host system 105 may send one or more commands to the memory system 110 requesting data as part of the system boot procedure. The memory system 110 may determine the order of the commands (e.g., the sequential order of the locations where the memory system 110 reads the data). The memory system 110 may reorganize the requested data based on the order. For example, the memory system 110 may transfer the data from a random pattern to a sequential layout according to the order of the one or more commands, as described herein. Such techniques may result in reduced boot time (e.g., due to more efficient retrieval of reorganized data for the boot procedure), improved read speeds, reduced power consumption, reduced processing complexity, and improved processing time, among other benefits.

[0041] Figure 2 An example of a data scheme 200 supporting data techniques for a system boot program according to examples disclosed herein is described. The data scheme 200 may be executed by processing logic, which may include hardware (e.g., a processing device, a circuit, specialized logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some examples, the data scheme 200 may be executed by a memory system or as described in reference Figure 1 and 3 The system implementation in the described memory system. In some examples, the memory system can execute a set of codes to control the functional elements of the memory system to perform the functions described below. In addition or alternatively, the memory system can use dedicated hardware to perform aspects of the operations described below.

[0042] In some examples, a memory system may implement data layout 205 for executing a system startup procedure (e.g., a boot procedure). Data layout 205-a may show an illustrative example of a random data pattern for startup data locations 215, and data layout 205-b may show an illustrative example of a sequential data pattern for startup data locations 215. For example, data layout 205 may include data locations 210, which may be an example of a physical address of a memory array of a memory system storing data (e.g., data stored on page 175, block 170, etc.). Additionally or alternatively, data layout 205 may include startup data locations 215, which may be an example of a physical address of a memory array storing data requested by a host system as part of a system startup procedure (e.g., a boot procedure).

[0043] The memory system may identify the occurrence of such a boot procedure. For example, the memory system may identify one or more commands from the host system that indicate a boot procedure (e.g., a command for a boot procedure, one or more read commands associated with a boot procedure, and other instances of a command that indicates a boot procedure). The boot procedure may occur when the host system is powered on (e.g., turned on) or when an application associated with the host system is started. For example, the boot procedure may occur when an operating system implemented by the host system is started.

[0044] As part of a boot procedure, the memory system may access the boot data location 215 (e.g., a physical address of a memory device). For example, the host system may send one or more read commands requesting data stored at the boot data location 215 from the memory system (e.g., data used by the host system to boot). The memory system may perform a read operation for the boot data location 215 based on the read command set and provide the requested data to the host system. In some examples, the memory system may access the boot data location 215 in a sequential order based on the sequential order of the received read command set. For example, the boot data location 215 of the data layout 205-a may include an index number that illustrates the order in which the boot data location 215 is accessed as part of the system boot procedure (e.g., the memory system may access the boot data location 215 marked as "1" based on the first read command of the read command set, the memory system may access the boot data location 215 marked as "2" based on the second read command in the read command set after accessing the boot data location 215 marked as "1", and so on). The memory system may signal data read from the activation data location 215 in response to one or more commands.

[0045] In some examples, a memory system may perform a boot procedure using data layout 205-a. The boot data locations 215 (e.g., a first set of locations) of data layout 205-a may be located in a memory array of the memory system according to a "random" pattern, meaning that there is no correlation between the order in which the data is retrieved and the physical address at which the data is stored. As an illustrative example, the data requested for the boot procedure (e.g., the boot data locations 215 storing data for the boot procedure) may be scattered throughout the data layout 205-a (e.g., the physical and / or logical addresses of the boot data may be scattered). In some examples, the memory system may perform a garbage collection procedure that may produce the random pattern illustrated by data layout 205-a (e.g., pages may be moved across blocks during a garbage collection procedure, which may scatter the boot data locations 215). Additionally or alternatively, the pattern of data layout 205-a may be the result of a read disturbance (e.g., a read disturbance of a page may cause the data to be moved to a new block) and / or a host system updating a boot image (e.g., updating the boot data may cause one or more of the boot data locations 215 to be scattered). However, in some examples, this data layout 205 - a may be relatively inefficient. For example, executing a boot process using a random pattern of boot data locations 215 may be relatively inefficient, which may result in a relatively long time to execute the boot process.

[0046] The memory system may be enabled to reorganize the startup data locations 215 into a sequential pattern (e.g., a sequential layout) of physical addresses, such as illustrated by data layout 205-b. For example, the memory system may determine an order of commands received for a startup procedure (e.g., a sequential order of read commands for startup data locations 215). As an illustrative example, the memory system may determine the order in which the startup data locations 215 are accessed during a first startup procedure using data layout 205-a (e.g., the memory system may track or record that the startup data locations 215 marked as "1" are accessed first, the startup data locations 215 marked as "2" are accessed second, and so on, until the order in which data is retrieved from each of the startup data locations 215 is determined). That is, the memory system may record the sequential access pattern of the first startup procedure to determine the order. In some examples, the order is stored as a list of physical block addresses (PBAs). In some examples, the list is stored in SRAM of the memory system until defragmentation occurs (eg, until data is transferred using the list during an idle cycle of the memory system).

[0047] The memory system may transfer the startup data locations 215 based on the determined order. For example, the memory system may transfer the startup data locations 215 described by the data layout 205-a (e.g., a first set of physical addresses for startup data) to the startup data locations 215 described by the data layout 205-b (e.g., a second set of physical addresses for startup data). The memory system may transfer the data so that the startup data locations 215 are arranged in a different pattern (e.g., the startup data locations 215 may be transferred to physical addresses that are packed closer together). The memory system may transfer the startup data according to the determined order. For example, the memory system may organize the start data locations 215 in the data layout 205-b so that the start data locations 215 can be accessed in a sequential mode (e.g., the start data locations may be physically arranged in the order in which the start data locations 215 are read in a startup procedure), as shown in the data layout 205-b for clarity of illustration, but it should be understood that other data layouts 205 may be used (e.g., the index values ​​of the data layout 205-b may increase from right to left, from the top of the data layout 205-b to the bottom of the data layout 205-b, and other examples).

[0048] In some examples, the memory system may transfer data to the startup data locations 215 of the data layout 205-b during an idle period of the memory system (e.g., during a time period when the memory system operates in an idle mode). For example, the memory system may determine the access order of the startup data locations 215 of the data layout 205-a during a first startup procedure (e.g., during a first time period). After the startup procedure, the memory system may enter an idle mode (e.g., during a time period when the memory system may be relatively inactive). During the idle mode, the memory system may transfer the startup data from the startup data locations 215 of the data layout 205-a (e.g., a first set of physical addresses) to the startup data locations 215 of the data layout 205-b (e.g., a second set of physical addresses). The memory system may perform a second startup procedure using the data layout 205-b. For example, the memory system may retrieve the startup data requested by the host system from the startup data locations 215 in a sequential mode (e.g., in a time order and a physical location order, as illustrated by the example of the data layout 205-b).

[0049] In some examples, the memory system may update a mapping table based on the transferred data. The mapping table may include a correspondence between one or more logical addresses (e.g., LBAs) of the memory array and one or more physical addresses (e.g., data locations 210) of the memory array. In some cases, the mapping table may be an example of a logical-to-physical (L2P) mapping table. The memory system may update the mapping table based on the transferred data. For example, the memory system may update a first mapping associated with data layout 205-a (e.g., one or more entries of an L2P table indicating a correspondence between an LBA and a physical block address (PBA) of the boot data) to a second mapping associated with data layout 205-b immediately after the data is transferred. In some examples, the memory system may adjust the granularity of one or more entries of the mapping table based on the transfer. The granularity may indicate the number of physical addresses corresponding to the logical address. For example, a first mapping of the startup data may use a first granularity (e.g., for a 4 kilobyte (kB) granularity, 1 megabyte (MB) of SRAM may be mapped to 1 gigabyte (GB) of physical NAND locations, among other examples of granularity), and a second mapping of the startup data may be adjusted to use a second granularity (e.g., 64 kB granularity, 128 kB granularity, etc.). The second granularity may be relatively larger than the first granularity, for example, because the startup data may be aggregated in relatively large chunks of data due to transferring data, as described herein. Such adjustments may enable more efficient memory operations. For example, a memory system may use less SRAM to map the startup data using a larger granularity, which may enable the device to use free SRAM space for read buffering, among other advantages.

[0050] In some examples, the memory system may transfer data and / or determine a startup data location 215 (e.g., a second set of physical addresses) of the data layout 205-b based on one or more media management operations. For example, the memory system may identify a relatively less worn memory block (e.g., a portion of a memory array that has been accessed relatively infrequently) based on the media management operation. The memory system may move the startup data to the identified memory block. In some examples, the data stored at the startup data location 215 may be identified by a flag for the media management operation, which may enable the media management operation to process the startup data location 215 differently from the data location 210 (e.g., one or more rules may be different for tagged startup data for one or more media management operations (e.g., refresh algorithms, read disturb operations, etc.)).

[0051] In some examples, the techniques described herein may yield one or more advantages. For example, reorganizing the boot data from a random access mode (e.g., as illustrated by the example of data layout 205-a) to a sequential mode (e.g., as illustrated by the example of data layout 205-b) may enable a memory system to achieve reduced boot time. Additionally or alternatively, implementing data layout 205-b may result in relatively lower latency for a host system to receive the boot data, more efficient NAND sensing resulting from packing the read data on the same access line (e.g., word lines in data layout 205-b may include a higher density of target boot data locations 215 compared to data layout 205-a), efficiency gains in the memory system (e.g., if the pages storing the boot data are contiguous and / or in the same block, there may be efficiency gains for multi-plane read operations, single-pass read operations, cache read operations, etc.), and other benefits.

[0052] Figure 3 A block diagram 300 is shown of a memory system 305 supporting data technology for a system boot procedure according to examples disclosed herein. The memory system 305 may be a memory system 305 as described in reference to Figure 1 and 2 Memory system 305 may include command component 310, data retrieval component 315, order component 320, data transfer component 325, location component 330, idle mode component 335, mapping component 340, and media management component 345. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0053] The command component 310 may receive a set of commands from a host system as part of a boot program for the host system, the set of commands requesting data stored in a first set of locations in a memory array. In some examples, the command component 310 may receive a second set of commands from a second boot program from the host system, the second set of commands requesting the data.

[0054] The data retrieval component 315 may retrieve data from a first set of locations of the memory array based on receiving the set of commands as part of a boot procedure. In some examples, the data retrieval component 315 may retrieve data from a second set of locations of the memory array as part of a second boot procedure based on receiving a second set of commands and transferring the data from the first set of locations to the second set of locations. In some examples, the data retrieval component 315 may access a word line that includes a sequential set of physical addresses at which data is stored, the second set of locations including the sequential set of physical addresses.

[0055] The order component 320 can determine, as part of a startup procedure, an order in which to retrieve data from each location in the first set of locations.

[0056] The data transfer component 325 can transfer data from the first set of locations to the second set of locations based on the order in which the data is retrieved from each location in the first set of locations. In some examples, the data transfer component 325 can transfer data from a first set of physical addresses to a second set of physical addresses, where the first set of physical addresses corresponds to a first pattern and the second set of physical addresses corresponds to a second pattern different from the first pattern. In some cases, the first pattern includes a random pattern and the second pattern includes a sequential pattern.

[0057] The location component 330 can determine a second set of locations in the memory array for storing the data based on the order in which the data is retrieved, the second set of locations comprising a sequential set of physical addresses in the memory array, wherein transferring the data is based on determining the second set of locations. In some examples, the location component 330 can determine the second set of locations in the memory array for storing the data based on one or more media management operations.

[0058] The idle mode component 335 can operate in the idle mode after determining an order to retrieve data from each location in the first set of locations, wherein transferring the data from the first set of locations to the second set of locations is based on operating in the idle mode.

[0059] The mapping component 340 may update a mapping table based on transferring the data from the first set of locations to the second set of locations, the mapping table including a correspondence between one or more logical addresses and one or more physical addresses of a memory device. In some examples, the mapping component 340 may update a first mapping associated with the data to a second mapping associated with the data, the first mapping indicating a correspondence between one or more logical addresses of the data and a first set of physical addresses of the data, the second mapping indicating a correspondence between one or more logical addresses of the data and a second set of physical addresses of the data. In some examples, the mapping component 340 may adjust the granularity of entries of the mapping table, the granularity indicating a number of physical addresses of the data corresponding to a logical address of the data.

[0060] The media management component 345 can perform one or more media management operations for the memory array.In some examples, the media management component 345 can identify that the data is associated with a boot program, wherein determining the second set of locations is based on the data being associated with the boot program.

[0061] Figure 4 A flowchart is shown illustrating one or more methods 400 of supporting data techniques for system boot procedures according to examples as disclosed herein. The operations of the method 400 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 400 may be implemented by a memory system or components thereof as described herein. Figure 3The method 400 may be implemented as instructions stored in a memory (e.g., firmware stored in a local memory). For example, the instructions, when executed by a controller, may cause the controller to perform the operations of the method 400.

[0062] At 405, the memory system may receive a set of commands from a host system as part of a boot procedure for the host system, the set of commands requesting data stored in a first set of locations in a memory array. The operations of 405 may be performed according to the methods described herein. In some examples, aspects of the operations of 405 may be described by reference to Figure 3 The command component described executes.

[0063] At 410, the memory system may retrieve data from a first set of locations in the memory array based on receiving the set of commands as part of a boot procedure. The operations of 410 may be performed according to the methods described herein. In some examples, aspects of the operations of 410 may be described by reference to Figure 3 The described data retrieval component performs

[0064] At 415, the memory system may determine, as part of a boot procedure, an order in which to retrieve data from each location in the first set of locations. The operations of 415 may be performed according to the methods described herein. In some examples, aspects of the operations of 415 may be described by reference to Figure 3 Components are executed in the order described.

[0065] At 420, the memory system may transfer data from the first set of locations to the second set of locations based on the order in which the data was retrieved from each location in the first set of locations. The operations of 420 may be performed according to the methods described herein. In some examples, aspects of the operations of 420 may be described by reference to Figure 3 The described data transfer component performs.

[0066] In some examples, an apparatus as described herein may perform one or more methods, such as method 400. The apparatus may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a set of commands from a host system as part of a boot procedure for the host system, the set of commands requesting data stored in a first set of locations of a memory array; retrieving the data from the first set of locations of the memory array based on receiving the set of commands as part of the boot procedure; determining as part of the boot procedure an order in which to retrieve the data from each location in the first set of locations; and transferring the data from the first set of locations to a second set of locations based on the order in which to retrieve the data from each location in the first set of locations.

[0067] Some instances of the method 400 and apparatus described herein may further include operations, features, components, or instructions for determining a second set of locations in a memory array for storing data based on an order in which the data may be retrieved, the second set of locations comprising a set of sequential physical addresses in the memory array, wherein transferring the data may be based on determining the second set of locations.

[0068] In some instances of the method 400 and apparatus described herein, transferring data from a first set of locations to a second set of locations may include operations, features, components, or instructions for transferring data from a first set of physical addresses to a second set of physical addresses, wherein the first set of physical addresses corresponds to a first pattern and the second set of physical addresses corresponds to a second pattern different from the first pattern.

[0069] In some examples of the methods 400 and apparatus described herein, the first pattern includes a random pattern and the second pattern includes a sequential pattern.

[0070] Some instances of the method 400 and apparatus described herein may further include operations, features, components, or instructions for operating in an idle mode after determining an order in which data may be retrieved from each location in a first set of locations, wherein transferring data from the first set of locations to a second set of locations may be based on operating in the idle mode.

[0071] Some instances of the method 400 and apparatus described herein may further include operations, features, components, or instructions for receiving a second set of commands for a second boot procedure from a host system, the second set of commands requesting the data; and retrieving data from a second set of locations of the memory array based on receiving the second set of commands and transferring the data from the first set of locations to the second set of locations as part of the second boot procedure.

[0072] In some examples of the method 400 and apparatus described herein, retrieving data from a second set of locations may include operations, features, means, or instructions for accessing a word line including a sequential set of physical addresses storing data.

[0073] Some instances of the method 400 and apparatus described herein may further include operations, features, components, or instructions for updating a mapping table based on transferring data from a first set of locations to a second set of locations, wherein the mapping table includes a correspondence between one or more logical addresses and one or more physical addresses of a memory device.

[0074] In some instances of the method 400 and apparatus described herein, updating a mapping table may include operations, features, components, or instructions for updating a first mapping associated with the data to a second mapping associated with the data, wherein the first mapping indicates a correspondence between one or more logical addresses of the data and a first set of physical addresses of the data, and the second mapping indicates a correspondence between one or more logical addresses of the data and a second set of physical addresses of the data.

[0075] In some examples of the method 400 and apparatus described herein, updating a mapping table may include operations, features, means, or instructions for adjusting the granularity of entries of the mapping table, the granularity indicating the number of physical addresses of data corresponding to the logical addresses of the data.

[0076] Some examples of method 400 and apparatus described herein may further include operations, features, means, or instructions for performing one or more media management operations for the memory array and determining a second set of locations in the memory array for storing data based on the one or more media management operations.

[0077] In some examples of the method 400 and apparatus described herein, performing the one or more media management operations may include operations, features, means, or instructions for identifying that the data may be associated with a launcher, wherein determining that the second set of locations may be associated with the launcher based on the data.

[0078] Figure 5 A flowchart is shown illustrating one or more methods 500 of supporting data techniques for system boot procedures according to examples as disclosed herein. The operations of the method 500 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 500 may be implemented by a memory system or components thereof as described herein. Figure 3The method 500 may be implemented as instructions stored in a memory (e.g., firmware stored in a local memory). For example, the instructions, when executed by a controller, may cause the controller to perform the operations of the method 500.

[0079] At 505, the memory system may receive a set of commands from a host system as part of a boot procedure for the host system, the set of commands requesting data stored in a first set of locations in a memory array. The operations of 505 may be performed according to the methods described herein. In some examples, aspects of the operations of 505 may be described by reference to Figure 3 The command component described executes.

[0080] At 510, the memory system may retrieve data from a first set of locations of a memory array based on receiving the set of commands as part of a boot procedure. The operations of 510 may be performed according to the methods described herein. In some examples, aspects of the operations of 510 may be described by reference to Figure 3 The data retrieval component described here performs.

[0081] At 515, the memory system may determine, as part of a boot procedure, an order in which to retrieve data from each location in the first set of locations. The operations of 515 may be performed according to the methods described herein. In some examples, aspects of the operations of 515 may be described by reference to Figure 3 Components are executed in the order described.

[0082] At 520, the memory system may determine a second set of locations in the memory array for storing the data based on the order in which the data was retrieved, the second set of locations comprising a set of sequential physical addresses in the memory array, wherein transferring the data is based on determining the second set of locations. The operations of 520 may be performed according to the methods described herein. In some examples, aspects of the operations of 520 may be described as in reference to Figure 3 The location component described performs.

[0083] At 525, the memory system may transfer data from the first set of locations to the second set of locations based on the order in which the data was retrieved from each location in the first set of locations. The operations of 525 may be performed according to the methods described herein. In some examples, aspects of the operations of 525 may be described by reference to Figure 3 The described data transfer component performs.

[0084] It should be noted that the methods described above describe possible implementations, and that the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0085] An apparatus for a method performed by a memory system is described. The apparatus may include a processor, a memory in electronic communication with the processor, and instructions stored in the memory. The instructions are executable by the processor to cause the apparatus to: receive a set of commands from a host system as part of a boot procedure for a host system, the set of commands requesting data stored in a first set of locations in a memory array; retrieve the data from the first set of locations in the memory array based on receiving the set of commands as part of the boot procedure; determine an order in which to retrieve the data from each location in the first set of locations as part of the boot procedure; and transfer the data from the first set of locations to a second set of locations based on the order in which the data is retrieved from each location in the first set of locations.

[0086] Some examples may further include determining a second set of locations in the memory array for storing the data based on an order in which the data may be retrieved, the second set of locations comprising a sequential set of physical addresses in the memory array, wherein transferring the data may be based on determining the second set of locations.

[0087] Some examples may further include transferring data from a first set of physical addresses to a second set of physical addresses, wherein the first set of physical addresses corresponds to a first pattern and the second set of physical addresses corresponds to a second pattern different from the first pattern.

[0088] In some examples, the first pattern includes a random pattern and the second pattern includes a sequential pattern.

[0089] Some examples may further include operating in an idle mode after determining an order in which data may be retrieved from each location in the first set of locations, wherein transferring the data from the first set of locations to the second set of locations may be based on operating in the idle mode.

[0090] Some instances may further include: receiving a second set of commands of a second boot procedure from the host system, the second set of commands requesting the data; and as part of the second boot procedure, retrieving data from a second set of locations of the memory array based on receiving the second set of commands and transferring the data from the first set of locations to the second set of locations.

[0091] Some examples may further include accessing a word line that includes a sequential set of physical addresses storing data, the second set of locations including the sequential set of physical addresses.

[0092] Some examples may further include updating a mapping table including a correspondence between one or more logical addresses and one or more physical addresses of the memory device based on transferring the data from the first set of locations to the second set of locations.

[0093] Some instances may further include updating a first mapping associated with the data to a second mapping associated with the data, wherein the first mapping indicates a correspondence between one or more logical addresses of the data and a first set of physical addresses of the data, and the second mapping indicates a correspondence between one or more logical addresses of the data and a second set of physical addresses of the data.

[0094] Some examples may further include adjusting a granularity of entries of the mapping table, the granularity indicating a number of physical addresses of the data corresponding to a logical address of the data.

[0095] Some examples may further include performing one or more media management operations for the memory array, and determining a second set of locations in the memory array for storing data based on the one or more media management operations.

[0096] Some examples may further include identifying that the data may be associated with an initiator, wherein determining the second set of locations may be based on associating the data with the initiator.

[0097] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, one of ordinary skill in the art will understand that the signal may represent a signal bus, where the bus may have a variety of bit widths.

[0098] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of electrons between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between the components that are electronically connected (or in conductive contact or connected or coupled) to each other may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include an intermediate component such as a switch, transistor, or other component. In some instances, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as a switch or transistor.

[0099] The term "coupled" refers to the condition of moving from an open circuit relationship between components, in which signals are currently unable to communicate between components through conductive paths, to a closed circuit relationship between components, in which signals are able to communicate between components through conductive paths. When a component, such as a controller, couples other components together, the component initiates a change that allows signals to flow between other components via conductive paths that previously did not permit signal flow.

[0100] The term "isolation" refers to a relationship between components where a signal cannot currently flow between the components. Components are isolated from one another if an open circuit exists between the components. For example, components separated by a switch positioned between two components are isolated from one another when the switch is open. When a controller isolates two components, the controller implements a change that blocks a signal from flowing between the components using a conductive path that previously permitted the signal to flow.

[0101] The devices discussed herein, including memory arrays, may be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed during the initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0102] The switch component or transistor discussed herein may represent a field effect transistor (FET) and include a three-terminal device including a source, a drain and a gate. The terminals may be connected to other electronic components by a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped, such as degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., most of the carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., most of the carriers are holes), then the FET may be referred to as a p-type FET. The channel may be terminated by an insulating gate oxide. Channel conductivity may be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "started". When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "unstarted".

[0103] The description set forth herein in conjunction with the accompanying drawings describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and is not "preferred to" or "superior to" other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0104] In the drawings, similar components or features may have the same reference label. Additionally, various components of the same type may be distinguished by following the reference label with a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0105] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0106] The various illustrative blocks and modules described in connection with the present disclosure herein may be implemented or performed using a general purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device designed to perform the functions described herein, discrete gate or transistor logic, discrete hardware components, or any combination thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0107] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on a computer-readable medium or transmitted via a computer-readable medium. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. The features of the implementation functions may also be physically located at various locations, including being distributed so that parts of the functions are implemented at different physical locations. Also, as used herein, included in the claims, the "or" used in the list of items (e.g., a list of items starting with a phrase such as "at least one of" or "one or more of") indicates an inclusive list, such that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). In addition, as used herein, the phrase "based on" should not be understood as referring to a closed set of conditions. For example, without departing from the scope of the present disclosure, the exemplary steps described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be equally interpreted as the phrase "based at least in part on."

[0108] Computer-readable media include both non-transitory computer storage media and communication media including any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media may be any available media that can be accessed by a general or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disk (CD) ROM or other optical disk storage device, magnetic disk storage device or other magnetic storage device, or any other non-transitory media that can be used to carry or store the desired program code device in the form of an instruction or data structure and can be accessed by a general or special-purpose computer or a general or special-purpose processor. Moreover, any connection may be appropriately referred to as a computer-readable medium. For example, if a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are used to transmit software from a website, server or other remote source, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technologies such as infrared, radio and microwaves are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0109] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to one skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: Memory array; as well as a control component coupled to the memory array and configured to cause the apparatus to: receiving a set of commands from a host system as part of a boot procedure for the host system, the set of commands requesting data stored in a first set of locations in the memory array; retrieving the data from the first set of locations of the memory array based at least in part on receiving the set of commands as part of the boot procedure; determining as part of the startup procedure an order in which to retrieve the data from each location in the first set of locations; identifying a low-wear memory block based at least in part on the first media management operation; entering an idle mode of operation after determining the order in which to retrieve the data from each location in the first set of locations; transferring the data from the first set of locations to a second set of locations within the low wear memory block while operating in the idle operating mode based at least in part on identifying the low wear memory block and the order in which the data is retrieved from each location in the first set of locations; as well as A granularity of entries of a mapping table including a correspondence between one or more logical addresses and one or more physical addresses of the memory array is adjusted, the granularity indicating a number of physical addresses of the data corresponding to the logical addresses of the data.

2. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to: The second set of locations in the memory array for storing the data is determined based at least in part on the order in which the data is retrieved, the second set of locations comprising a sequential set of physical addresses in the memory array, wherein transferring the data is based at least in part on determining the second set of locations.

3. The apparatus of claim 1 , wherein the control component is further configured to cause the apparatus to: The data is transferred from a first set of physical addresses to a second set of physical addresses, wherein the first set of physical addresses corresponds to a first pattern and the second set of physical addresses corresponds to a second pattern different from the first pattern. 4 . The apparatus of claim 3 , wherein the first pattern comprises a random pattern and the second pattern comprises a sequential pattern.

5. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to: receiving a second command set of a second boot program from the host system, the second command set requesting the data; and The data is retrieved from the second set of locations of the memory array as part of the second boot procedure based at least in part on receiving the second set of commands and transferring the data from the first set of locations to the second set of locations.

6. The apparatus of claim 5, the control component being further configured to cause the apparatus to: A word line is accessed that includes a sequential set of physical addresses storing the data, the second set of locations including the sequential set of physical addresses.

7. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to: The mapping table is updated based at least in part on transferring the data from the first set of locations to the second set of locations.

8. The apparatus of claim 7, the control component being further configured to cause the apparatus to: A first mapping associated with the data is updated to a second mapping associated with the data, wherein the first mapping indicates a first correspondence between the one or more logical addresses of the data and a first set of physical addresses of the data, and the second mapping indicates a second correspondence between the one or more logical addresses of the data and a second set of physical addresses of the data.

9. The apparatus of claim 1, wherein the data transferred to the second set of locations within the low-wear memory block is identified based at least in part on a flag associated with identifying initiation data for a corresponding media management operation.

10. The apparatus of claim 1, wherein the control component is further configured to cause the apparatus to: performing one or more media management operations for the memory array; and The second set of locations in the memory array for storing the data is determined based at least in part on the one or more media management operations.

11. The apparatus of claim 10, the control component being further configured to cause the apparatus to: The data is identified as being associated with the launcher, wherein determining the second set of locations is based at least in part on associating the data with the launcher.

12. A non-transitory computer-readable medium storing code including instructions that, when executed by a processor of an electronic device, cause the electronic device to: receiving a set of commands from a host system as part of a boot procedure for the host system, the set of commands requesting data stored in a first set of locations in a memory array; retrieving the data from the first set of locations of the memory array based at least in part on receiving the set of commands as part of the boot procedure; determining as part of the startup procedure an order in which to retrieve the data from each location in the first set of locations; identifying a low-wear memory block based at least in part on the first media management operation; entering an idle mode of operation after determining the order in which to retrieve the data from each location in the first set of locations; transferring the data from the first set of locations to a second set of locations within the low wear memory block while operating in the idle operating mode based at least in part on identifying the low wear memory block and the order in which the data is retrieved from each location in the first set of locations; as well as A granularity of entries of a mapping table including a correspondence between one or more logical addresses and one or more physical addresses of the memory array is adjusted, the granularity indicating a number of physical addresses of the data corresponding to the logical addresses of the data.

13. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: The second set of locations in the memory array for storing the data is determined based at least in part on the order in which the data is retrieved, the second set of locations comprising a sequential set of physical addresses in the memory array, wherein transferring the data is based at least in part on determining the second set of locations.

14. The non-transitory computer-readable medium of claim 12, wherein the instructions for transferring the data from the first set of locations to the second set of locations are executable by the processor of the electronic device to: The data is transferred from a first set of physical addresses to a second set of physical addresses, wherein the first set of physical addresses corresponds to a first pattern and the second set of physical addresses corresponds to a second pattern different from the first pattern.

15. The non-transitory computer-readable medium of claim 12, wherein the instructions, when executed by the processor of the electronic device, further cause the electronic device to: A mapping table is updated based at least in part on transferring the data from the first set of locations to the second set of locations, the mapping table including a correspondence between one or more logical addresses and one or more physical addresses.

16. The non-transitory computer-readable medium of claim 12, wherein the data transferred to the second set of locations within the low-wear memory block is identified based at least in part on a flag associated with identifying startup data for a respective media management operation.

17. A method performed by a memory system, the method comprising: receiving a set of commands from a host system as part of a boot procedure for the host system, the set of commands requesting data stored in a first set of locations in a memory array; retrieving the data from the first set of locations of the memory array based at least in part on receiving the set of commands as part of the boot procedure; determining as part of the startup procedure an order in which to retrieve the data from each location in the first set of locations; identifying a low-wear memory block based at least in part on the first media management operation; entering an idle mode of operation after determining the order in which to retrieve the data from each location in the first set of locations; transferring the data from the first set of locations to a second set of locations within the low wear memory block while operating in the idle operating mode based at least in part on identifying the low wear memory block and the order in which the data is retrieved from each location in the first set of locations; as well as A granularity of entries of a mapping table including a correspondence between one or more logical addresses and one or more physical addresses of the memory array is adjusted, the granularity indicating a number of physical addresses of the data corresponding to the logical addresses of the data.

18. The method according to claim 17, further comprising: The second set of locations in the memory array for storing the data is determined based at least in part on the order in which the data is retrieved, the second set of locations comprising a sequential set of physical addresses in the memory array, wherein transferring the data is based at least in part on determining the second set of locations.

19. The method of claim 17, wherein transferring the data from the first set of locations to the second set of locations comprises: The data is transferred from a first set of physical addresses to a second set of physical addresses, wherein the first set of physical addresses corresponds to a first pattern and the second set of physical addresses corresponds to a second pattern different from the first pattern.

20. The method of claim 19, wherein the first pattern comprises a random pattern and the second pattern comprises a sequential pattern.

21. The method of claim 17, further comprising: receiving a second command set of a second boot program from the host system, the second command set requesting the data; as well as The data is retrieved from the second set of locations of the memory array as part of the second boot procedure based at least in part on receiving the second set of commands and transferring the data from the first set of locations to the second set of locations.

22. The method of claim 21 , wherein retrieving the data from the second set of locations comprises: A word line is accessed that includes a sequential set of physical addresses storing the data, the second set of locations including the sequential set of physical addresses.

23. The method of claim 17, further comprising: A mapping table is updated based at least in part on transferring the data from the first set of locations to the second set of locations, the mapping table including a correspondence between one or more logical addresses and one or more physical addresses of the memory system.

24. The method of claim 17, wherein the data transferred to the second set of locations within the low-wear memory block is identified based at least in part on a flag associated with identifying initiation data for a corresponding media management operation.

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