Display device

Abstract

A display device is provided. The display device includes a display panel, a mode selector, and a switch. The display panel includes pixels, voltage lines supplying a power supply voltage to the pixels, and a reference voltage line supplying one of a reference voltage and a power supply voltage to the pixels. The mode selector is configured to output one of a first selection signal and a second selection signal according to an operating mode of the display panel. The switch is configured to provide the reference voltage or the power supply voltage to the reference voltage line in response to one of the first selection signal and the second selection signal.

Description

Technical Field

[0001] This disclosure relates to display devices, and more specifically, to display devices having improved overall display quality. Background Technology

[0002] Display devices may include various electronic components, such as display panels for displaying images, input detection components for detecting external input, and electronic modules. These electronic components can be electrically interconnected via signal lines arranged in different configurations. The display panel includes multiple pixels. Each of the multiple pixels includes a light-emitting element that generates light and circuitry that controls the amount of current flowing through the light-emitting element.

[0003] Leakage current generated in the circuitry of a pixel can alter the amount of current flowing through the light-emitting element and degrade the display quality of the display device. Summary of the Invention

[0004] This disclosure provides a display device capable of improving display quality based on the operating mode of the display panel.

[0005] According to an embodiment of the present invention, a display device includes a display panel, a mode selector, and a switch. The display panel includes pixels, a voltage line supplying a power supply voltage to the pixels, and a reference voltage line supplying one of a reference voltage and a power supply voltage to the pixels. The mode selector is configured to output one of a first selection signal and a second selection signal according to an operating mode of the display panel. The switch is configured to provide a reference voltage or a power supply voltage to the reference voltage line in response to one of the first selection signal and the second selection signal.

[0006] The switch may include: a first switching element configured to supply a reference voltage to a reference voltage line in response to a first selection signal, and a second switching element configured to supply a power supply voltage to the reference voltage line in response to a second selection signal.

[0007] When the display panel is operated in a first mode for displaying still images, the mode selector can activate a first selection signal, and when the display panel is operated in a second mode for displaying video, the mode selector can activate a second selection signal.

[0008] The display panel may include a display area with a plurality of pixels arranged therein and a peripheral area adjacent to the display area, and a first switching element and a second switching element may be arranged in the peripheral area of ​​the display panel.

[0009] The second switching element can receive the power supply voltage through the voltage line.

[0010] A pixel may include: a light-emitting element comprising a cathode and an anode, a first transistor connected between the anode of the light-emitting element and a voltage line, a second transistor connected between a data line providing a data signal and the first transistor, a first capacitor connected between a first node and a voltage line, and a second capacitor connected between the first transistor and the second transistor.

[0011] The first transistor may include: a first electrode connected to a voltage line, a second electrode connected to a second capacitor at a second node, and a third electrode connected to the anode of a light-emitting element. The second transistor may include: a first electrode connected to a data line, a second electrode configured to receive a write scan signal, and a third electrode connected to the first node.

[0012] The pixel may also include a third transistor, which includes a first electrode connected to a reference voltage line, a second electrode configured to receive a compensation scan signal, and a third electrode connected to the first node.

[0013] The activation period of the compensation scan signal may have a first duration that is longer than the second duration of the activation period of the write scan signal.

[0014] The compensation scan signal can be activated before the write scan signal is activated.

[0015] The pixel may also include a fourth transistor and a fifth transistor. The fourth transistor includes a first electrode connected to the second electrode of the first transistor, a second electrode configured to receive a compensation scan signal, and a third electrode connected to the third electrode of the first transistor. The fifth transistor includes a first electrode connected to the third electrode of the first transistor, a second electrode configured to receive a light emission control signal, and a third electrode connected to the anode of the light-emitting element.

[0016] During the deactivation period of the optical emission control signal, the compensation scan signal can be activated before the write scan signal is activated.

[0017] The pixel may also include a sixth transistor and a seventh transistor. The sixth transistor includes a first electrode connected to an initialization voltage line, a second electrode configured to receive an initialization scan signal, and a third electrode connected to the second electrode of the first transistor. The seventh transistor includes a first electrode connected to an initialization voltage line, a second electrode configured to receive a black scan signal, and a third electrode connected to the anode of the light-emitting element.

[0018] The compensation scan signal can be activated before the write scan signal is activated, and the initialization scan signal can be activated before the compensation scan signal is activated.

[0019] The first activation period of the compensation scan signal and the second activation period of the initialization scan signal can be longer than the third activation period of the write scan signal.

[0020] The write scan signal can be activated before the black scan signal is activated.

[0021] In an embodiment of the present invention, the display device includes a display panel, a mode selector, and a switch. The display panel includes pixels, a voltage line supplying a power supply voltage to the pixels, and a reference voltage line supplying one of a reference voltage and a power supply voltage to the pixels. The mode selector is configured to output one of a first selection signal and a second selection signal according to the operation mode of the display panel. The switch is configured to provide a reference voltage or a power supply voltage to the reference voltage line in response to one of the first selection signal and the second selection signal.

[0022] The pixel includes: a light-emitting element including a cathode and an anode, a first transistor connected between the anode of the light-emitting element and a voltage line, a second transistor connected between a data line providing a data signal and the first transistor, a first capacitor connected between a first node and the voltage line, a second capacitor connected between the first transistor and the second transistor, and a third transistor connected between a reference voltage line and the second transistor, wherein the third transistor is turned on during a compensation period for compensating the potential of the first node, and the compensation period precedes a data writing period in which a data signal is applied.

[0023] The first transistor may include: a first electrode connected to a voltage line, a second electrode connected to a second capacitor at a second node, and a third electrode connected to the anode of a light-emitting element. The second transistor may include: a first electrode connected to a data line, a second electrode configured to receive a write scan signal, and a third electrode connected to a first node. The third transistor may include: a first electrode connected to a reference voltage line, a second electrode configured to receive a compensation scan signal, and a third electrode connected to a first node.

[0024] The switch may include: a first switching element configured to supply a reference voltage to a reference voltage line in response to a first selection signal, and a second switching element configured to supply a power supply voltage to the reference voltage line in response to a second selection signal.

[0025] The second switching element can receive the power supply voltage through the voltage line.

[0026] In an embodiment of the present invention, the display device includes a display panel, the display panel including pixels, a voltage line supplying a first power supply voltage to the pixels, and a reference voltage line supplying a second power supply voltage to the pixels.

[0027] The pixel includes a first transistor connected between the anode of the light-emitting element and the voltage line, a second transistor connected between the data line and the first transistor, a third transistor connected between the reference voltage line and the second transistor, and a capacitor connected between the first transistor and the third transistor.

[0028] The display panel operates in a first mode and a second mode, and the first power supply voltage has a first voltage level in both modes. The second power supply voltage has a second voltage level in the first mode and a first voltage level in the second mode, wherein the first voltage level is different from the second voltage level. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated into and constitute a part of this disclosure. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0030] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention;

[0031] Figure 2 This is a plan view showing a display panel according to an embodiment of the concept of the present invention;

[0032] Figure 3 yes Figure 2 An enlarged plan view of part AA shown in the diagram;

[0033] Figure 4 This is a plan view illustrating a display device according to an embodiment of the concept of the present invention;

[0034] Figure 5 This is a circuit diagram of a pixel according to an embodiment of the concept of the present invention;

[0035] Figure 6A This is a circuit diagram illustrating the operation of pixels during the initialization period;

[0036] Figure 6B It is shown in Figure 6A A graph of the signal waveform during the initialization period;

[0037] Figure 7A This is a circuit diagram showing the operation of the pixels during the compensation period;

[0038] Figure 7B It is shown in Figure 7A A graph of the signal waveform during the compensation period;

[0039] Figure 8A This is a circuit diagram illustrating the operation of pixels during the data writing period;

[0040] Figure 8B It is shown in Figure 8A The waveform of the signal during the data writing period;

[0041] Figure 9A This is a circuit diagram showing the operation of pixels during the black period;

[0042] Figure 9B It is shown in Figure 9A A waveform diagram of the signal during the black period;

[0043] Figure 10 This is a circuit diagram of a pixel according to an embodiment of the concept of the present invention;

[0044] Figure 11 This is a circuit diagram of a pixel according to an embodiment of the concept of the present invention; and

[0045] Figure 12 It shows that it is applied to Figure 11 The waveform diagram shows the signal waveform of the pixel shown. Detailed Implementation

[0046] In this disclosure, the term "on," "connected to," or "bonded to" another component means that the component may be directly on, directly connected to, or directly bonded to another component, or that there may be a third component between them.

[0047] The same reference numerals indicate the same elements. Additionally, in the accompanying drawings, the thickness, scale, and dimensions of parts may be exaggerated for effective description.

[0048] "And / or" includes all of one or more combinations defined by the relevant components.

[0049] It should be understood that the terms "first" and "second" are used herein to describe various components, but these components should not be limited by these terms. The terms above are used only to distinguish one component from another. For example, without departing from the scope of the invention, a first component may be referred to as a second component, and vice versa. Unless otherwise expressly stated, singular terms may include plural forms.

[0050] Additionally, terms such as "below," "lower side," "upper," and "upper side" are used to describe the relationships of the configurations shown in the accompanying drawings. It should be understood that these terms describe relative relationships based on the directions shown in the accompanying drawings.

[0051] Unless otherwise defined, the terms used herein (including technical and scientific terms) may have the same meaning as those commonly understood by one of ordinary skill in the art to which this disclosure pertains. In general, terms defined in dictionaries should be regarded as having the same meaning as the contextual meaning in the relevant field, and should not be interpreted anomalously or as having an overly rigid meaning unless clearly defined herein.

[0052] In various embodiments of the present invention, the terms "include", "comprise", "including" or "comprising" specify attributes, areas, fixed numbers, steps, processes, elements and / or components, but do not exclude other attributes, areas, fixed numbers, steps, processes, elements and / or components.

[0053] In the following description, various embodiments of the concept of the present invention will be described with reference to the accompanying drawings.

[0054] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0055] Reference Figure 1 The display device DD includes a display panel DP, a signal controller 100, a scan driver 200, a data driver 300, a mode selector 400, and a switch 500. The display device DD can be activated in response to an electrical signal. The display device DD can include various implementations. For example, the display device DD can include a computer, a personal computer (PC), a tablet PC, a laptop computer, a television, and a smartphone.

[0056] The signal controller 100 can receive an input image signal (not shown), convert the data format of the input image signal, and generate an image data signal RGB suitable for interfacing with the data driver 300. The signal controller 100 can generate a scan control signal SCS for controlling the drive of the scan driver 200 and a data control signal DCS for controlling the drive of the data driver 300.

[0057] The scan driver 200 may receive a scan control signal SCS from the signal controller 100. The scan control signal SCS may include a start signal and a clock signal indicating the start of operation of the scan driver 200. The scan driver 200 may generate multiple scan signals and sequentially output the multiple scan signals to scan lines as described in further detail later. In addition, the scan driver 200 may generate multiple optical emission control signals in response to the scan control signal SCS and output them to multiple optical emission control lines EML1 to EMLn (n is an integer greater than 1).

[0058] In an exemplary embodiment of the present invention, the scan driver 200 may include an initialization scan driver, a compensation scan driver, a write scan driver, and a black scan driver. The initialization scan driver outputs an initialization scan signal to the initialization scan lines GIL1 to GILn of the display panel DP, and the compensation scan driver outputs a compensation scan signal to the compensation scan lines GCL1 to GCLn of the display panel DP. The initialization scan driver and the compensation scan driver may be implemented in separate circuits or integrated into a single circuit. When the initialization scan driver and the compensation scan driver are integrated into a single circuit, the initialization scan signal may be referred to as the previous scan signal, and the compensation scan signal may be referred to as the current scan signal.

[0059] The write scan driver outputs the write scan signal to the write scan lines GWL1 to GWLn of the display panel DP, and the black scan driver outputs the black scan signal to the black scan lines GBL1 to GBLn of the display panel DP. The write scan driver and the black scan driver can be implemented in separate circuits or integrated into a single circuit. When the write scan driver and the black scan driver are integrated into a single circuit, the write scan signal can be referred to as the current scan signal, and the black scan signal can be referred to as the subsequent scan signal.

[0060] although Figure 1 The illustration shows multiple scan signals and multiple optical emission control signals output from scan driver 200, but the concept of the invention is not limited thereto. In another embodiment of the concept of the invention, scan driver 200 may include one or more scan drivers that output multiple scan signals, and an optical emission driver that outputs multiple optical emission control signals separately from the one or more scan drivers.

[0061] The data driver 300 can receive a data control signal DCS and an image data signal RGB from the signal controller 100. The data driver 300 can convert the image data signal RGB into a data signal and output the data signal to multiple data lines DL1 to DLm (m is an integer greater than 1). The data signal can be an analog voltage corresponding to the grayscale value of the image data signal RGB.

[0062] The display device DD also includes a voltage generator (not shown) for generating voltages for the operation of the display device DD. In this embodiment, the voltage generator can generate a first power supply voltage ELVDD, a second power supply voltage ELVSS, a reference voltage Vref, and an initialization voltage Vint.

[0063] The display panel DP generates an image. The display panel DP includes scan lines, data lines DL1 to DLm, and pixels PX11 to PXnm. The scan lines may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2. The data lines DL1 to DLm may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. As an example of the concept of the present invention, the scan lines include initialization scan lines GIL1 to GILn, compensation scan lines GCL1 to GCLn, write scan lines GWL1 to GWLn, and black scan lines GBL1 to GBLn.

[0064] Each of pixels PX11 to PXnm is connected to a corresponding data line and a corresponding scan line. For example, the first pixel PX11 among pixels PX11 to PXnm is connected to the first data line DL1, the first initialization scan line GIL1, the first compensation scan line GCL1, the first write scan line GWL1, and the first black scan line GBL1. The last pixel PXnm among pixels PX11 to PXnm is connected to the m-th data line DLm, the n-th initialization scan line GILn, the n-th compensation scan line GCLn, the n-th write scan line GWLn, and the n-th black scan line GBLn. As an example of the concept of the present invention, each of pixels PX11 to PXnm may be electrically connected to four different scan lines.

[0065] The display panel DP can receive a first power supply voltage ELVDD, a second power supply voltage ELVSS, and an initialization voltage Vint. The display panel DP may include a first voltage line VL1 for transmitting the first power supply voltage ELVDD, a second voltage line VL2 for transmitting the second power supply voltage ELVSS, and an initialization voltage line VIL for transmitting the initialization voltage Vint. Each of pixels PX11 to PXnm can be electrically connected to the first voltage line VL1, the second voltage line VL2, and the initialization voltage line VIL, and receives the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage Vint. Each of pixels PX11 to PXnm can be electrically connected to a reference voltage line VRL for transmitting a reference voltage Vref or the first power supply voltage ELVDD.

[0066] Switch 500 can select one of a reference voltage Vref and a first power supply voltage ELVDD and apply it to the reference voltage line VRL. Mode selector 400 can output one of a first selection signal SS1 and a second selection signal SS2 according to the operating mode of the display panel DP. For example, when the display panel DP operates in the first mode, mode selector 400 can output the first selection signal SS1, and when the display panel DP operates in the second mode, mode selector 400 can output the second selection signal SS2. The operating mode of the display panel DP can be selected by the user. As an example of the inventive concept, the first mode can be a document working mode, and the second mode can be a video viewing mode. When the user selects one of the first mode and the second mode, mode selector 400 can provide a selection signal corresponding to the selected mode to switch 500.

[0067] Switch 500 can select one of a reference voltage Vref and a first power supply voltage ELVDD in response to a selection signal received from mode selector 400. For example, when a first selection signal SS1 is received, switch 500 outputs the reference voltage Vref to the reference voltage line VRL in response to the first selection signal SS1, and when a second selection signal SS2 is received, switch 500 outputs the first power supply voltage ELVDD to the reference voltage line VRL in response to the second selection signal SS2.

[0068] Figure 2 This is a plan view of a display panel DP according to an exemplary embodiment of the concept of the present invention, and Figure 3 yes Figure 2 The enlarged plan view of part AA shown.

[0069] Reference Figure 2 The display panel DP can be divided into a display area DA and a non-display area NDA. Multiple pixels PX11 to PXnm can be arranged in an n x m matrix in the display area DA. Data lines DL1 to DLm and scan lines can be arranged in the display area DA. A scan driver 200 connected to the scan lines can be arranged in the non-display area NDA of the display panel DP. For example, the scan driver 200 can be disposed in the non-display area NDA using a thin-film process that forms multiple pixels PX11 to PXnm in the display area DA. Multiple pixels PX11 to PXnm and the scan driver 200 can be formed simultaneously using the same thin-film process.

[0070] The pad area PA can be set in the non-display area NDA of the display panel DP. Data pads D_PD1 to D_PDm connected to data lines DL1 to DLm can be arranged in the pad area PA. This is used to transmit the scan control signal SCS (in...) Figure 1 (As shown in the figure) The scan pad S_PD supplied to the scan driver 200 can be arranged in the pad area PA.

[0071] The display panel DP can receive signals from external devices via pads arranged in the pad area PA. Although not shown in the figures, a flexible circuit film can be attached to the pad area PA of the display panel DP.

[0072] In the pad area PA of the display panel DP, a first power pad VPD1 connected to the first voltage line VL1 and a second power pad VPD2 connected to the reference voltage line VRL can also be arranged. Although in Figure 2 Not shown in the diagram, but in the pad area PA of the display panel DP, a connection to the second voltage line VL2 can also be arranged (in... Figure 1 The third power pad (shown in the diagram) and connected to the initialization voltage line VIL (in... Figure 1 The fourth power pad (shown in the image).

[0073] Switch 500 can be arranged in the non-display area NDA of the display panel DP. Switch 500 can be arranged between the second power pad VPD2 and the reference voltage line VRL. Switch 500 can be set in the non-display area NDA by a thin-film process that forms pixels PX11 to PXnm in the display area DA. Multiple pixels PX11 to PXnm and switch 500 can be formed simultaneously by the same thin-film process.

[0074] like Figure 3 As shown, switch 500 may include a first switching element ST1 and a second switching element ST2. The first switching element ST1 may be selected from mode selector 400 (in Figure 1 (as shown in the diagram) receives a first selection signal SS1, and a second switching element ST2 can receive a second selection signal SS2 from the mode selector 400.

[0075] The first switching element ST1 includes a first electrode electrically connected to the second power pad VPD2, a second electrode electrically connected to the first select signal pad SPD1, and a third electrode electrically connected to the reference voltage line VRL. The second switching element ST2 includes a first electrode electrically connected to the first power pad VPD1, a second electrode electrically connected to the second select signal pad SPD2, and a third electrode electrically connected to the reference voltage line VRL.

[0076] The first selection signal pad SPD1, which provides the first selection signal SS1 to the second electrode of the first switching element ST1, and the second selection signal pad SPD2, which provides the second selection signal SS2 to the second electrode of the second switching element ST2, can be arranged in the pad area PA of the display panel DP. The first switching element ST1 receives the first selection signal SS1 through the first selection signal pad SPD1, and the second switching element ST2 receives the second selection signal SS2 through the second selection signal pad SPD2.

[0077] In the first mode, when the first selection signal SS1 from the mode selector 400 is supplied to the switch 500, the first switching element ST1 is turned on, and the second switching element ST2 is turned off. The reference voltage Vref can be supplied to the reference voltage line VRL through the turned-on first switching element ST1. Simultaneously, the supply of the first power supply voltage ELVDD to the reference voltage line VRL can be blocked by the turned-off second switching element ST2. Therefore, in the first mode, the pixels PX11 to PXnm of the display panel DP (in...) Figure 2 (As shown in the figure) the reference voltage Vref can be received through the reference voltage line VRL.

[0078] On the other hand, in the second mode, when the second selection signal SS2 from the mode selector 400 is supplied to the switch 500, the second switching element ST2 is turned on, and the first switching element ST1 is turned off. The first power supply voltage ELVDD can be supplied to the reference voltage line VRL through the turned-on second switching element ST2. At the same time, the supply of the reference voltage Vref to the reference voltage line VRL can be blocked by the turned-off first switching element ST1. Therefore, in the second mode, pixels PX11 to PXnm of the display panel DP can receive the first power supply voltage ELVDD through the reference voltage line VRL.

[0079] The second switching element ST2 can receive the first power supply voltage ELVDD via the first voltage line VL1 located in the display panel DP. Multiple pixels PX11 to PXnm and the second switching element ST2 can be connected together to the first voltage line VL1.

[0080] Display device DD (in) Figure 1 (As shown in the diagram) Switch 500 can be used to selectively supply the reference voltage Vref or the first power supply voltage ELVDD to the reference voltage line VRL, depending on the operating mode of the display panel DP.

[0081] Figure 4 This is a plan view illustrating a display device DD according to an embodiment of the concept of the present invention. The same reference numerals are used interchangeably with those used in the present invention. Figure 2 and Figure 3 The components shown are the same as those shown, and redundant detailed descriptions of them will be omitted.

[0082] Reference Figure 4 The display device DD includes a display panel DP, multiple flexible circuit films CF1 to CF3, and a printed circuit board PCB. The flexible circuit films CF1 to CF3 can provide various electrical signals to the display panel DP to drive it. These electrical signals can be generated from the flexible circuit films CF1 to CF3 or received from the printed circuit board PCB. The printed circuit board PCB may include various drive circuits for generating the electrical signals used to drive the display panel DP.

[0083] Flexible circuit films CF1 to CF3 can be connected to the pad area PA of the display panel DP. Data pads D_PD1 to D_PDm are connected to data lines DL1 to DLm (in...). Figure 2 (As shown in the diagram) can be arranged in the pad area PA. Used to transmit the scan control signal SCS (in...) Figure 1 (As shown in the image) The scan pad S_PD (in the image) is supplied to the scan driver 200. Figure 2 (As shown in the diagram) can be arranged in the pad area PA.

[0084] The display panel DP can receive electrical signals from the flexible circuit films CF1 to CF3 through the pads arranged in the pad area PA.

[0085] Data drive 300 (in) Figure 1 (As shown in the diagram) can be implemented using chips, and can be mounted on flexible circuit films CF1 to CF3. As an example of the inventive concept, the data driver 300 may include a plurality of driver chips DIC1 to DIC3. The plurality of driver chips DIC1 to DIC3 can be mounted on flexible circuit films CF1 to CF3. As another example, the plurality of driver chips DIC1 to DIC3 can be mounted on a display panel DP.

[0086] Flexible circuit films CF1 to CF3 can be bonded to a printed circuit board (PCB) for electrical connection to a display panel (DP). As an example of the inventive concept, a switch 500 can be disposed on the PCB. In this case, the switch 500 can be electrically connected to the reference voltage line VRL of the display panel (DP) via one of the flexible circuit films CF1 to CF3. The switch 500 may include signals for receiving a first selection signal SS1 and a second selection signal SS2 (in... Figure 3 The first switching element ST1 and the second switching element ST2 (shown in) Figure 3 (As shown in the diagram). In response to one of the first selection signal SS1 and the second selection signal SS2, switch 500 can select one of the reference voltage Vref and the first power supply voltage ELVDD, and supply the selected one to the reference voltage line VRL.

[0087] Figure 2 An embodiment in which the switch 500 is disposed on the display panel DP is shown, and Figure 4 An embodiment in which switch 500 is disposed on a printed circuit board (PCB) is shown, but the concept of the invention is not limited thereto. As another example, switch 500 may be disposed on at least one of driver chips DIC1 to DIC3.

[0088] Figure 5 This is a circuit diagram of a pixel according to an embodiment of the concept of the present invention. Figure 2Each of the pixels PX11 to PXnm shown can have the same configuration. As a representative example, Figure 5 The configuration of the first pixel PX11 is shown, and the description of the configuration of the remaining pixels PX12 to PXnm will be omitted.

[0089] Reference Figure 5 The first pixel PX11 may include multiple transistors T1 to T7, two capacitors C1 and C2, and a light-emitting element ED. The multiple transistors T1 to T7 and the two capacitors C1 and C2 can control the amount of current flowing through the light-emitting element ED in response to data signals and scan signals.

[0090] Each of the plurality of transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). For convenience, the input electrode, control electrode, and output electrode may be referred to as the first electrode, the second electrode, and the third electrode, respectively. Furthermore, the plurality of transistors T1 to T7 are referred to as the first transistor T1 to the seventh transistor T7, and the two capacitors C1 and C2 are referred to as the first capacitor C1 and the second capacitor C2.

[0091] A first transistor T1 may be connected between a first voltage line VL1 and a light-emitting element ED. The first transistor T1 may include a first electrode electrically connected to the first voltage line VL1, a second electrode connected to a second node N2, and a third electrode electrically connected to the light-emitting element ED. The first transistor T1 may receive a first power supply voltage ELVDD via the first voltage line VL1. The third electrode of the first transistor T1 may be electrically connected to the anode of the light-emitting element ED via a fifth transistor T5. The first transistor T1 may control the amount of current flowing through the light-emitting element ED in response to the voltage applied to its second electrode.

[0092] A second transistor T2 may be connected between the first data line DL1 and the first node N1. The second transistor T2 may include a first electrode connected to the first data line DL1, a second electrode connected to the first write scan line GWL1, and a third electrode connected to the first node N1. During the data write period, the second transistor T2 may be turned on in response to a first write scan signal GW1 provided to the first write scan line GWL1, and the first data line DL1 and the first node N1 may be electrically connected through the turned-on second transistor T2. That is, during the data write period, the data voltage Vdata applied to the first data line DL1 may be transmitted to the first node N1 through the turned-on second transistor T2.

[0093] A first capacitor C1 may be electrically connected between a first voltage line VL1 and a first node N1, and a second capacitor C2 may be electrically connected between the first node N1 and a second electrode of the first transistor T1. The first capacitor C1 may include a first electrode electrically connected to the first voltage line VL1 and a second electrode electrically connected to the first node N1, and the second capacitor C2 includes a first electrode electrically connected to the first node N1 and a second electrode electrically connected to the second node N2.

[0094] A third transistor T3 may be electrically connected between the first node N1 and the reference voltage line VRL. The third transistor T3 may include a first electrode connected to the reference voltage line VRL, a second electrode electrically connected to the first compensation scan line GCL1, and a third electrode electrically connected to the first node N1. The reference voltage line VRL may provide a reference voltage Vref or a first power supply voltage ELVDD depending on the operating mode of the display panel DP. During the compensation period, the third transistor T3 may be turned on in response to a first compensation scan signal GC1 provided to the first compensation scan line GCL1, and the reference voltage line VRL and the first node N1 may be electrically connected through the turned-on third transistor T3. That is, during the compensation period, the reference voltage Vref or the first power supply voltage ELVDD may be applied to the first node N1.

[0095] A fourth transistor T4 may be electrically connected between the second electrode (or second node N2) of the first transistor T1 and the third electrode of the first transistor T1. The fourth transistor T4 may include a first electrode electrically connected to the second node N2, a second electrode electrically connected to the first compensation scan line GCL1, and a third electrode electrically connected to the third electrode of the first transistor T1. During the compensation period, the fourth transistor T4 may be turned on in response to a first compensation scan signal GC1 provided to the first compensation scan line GCL1. That is, during the compensation period, the first transistor T1 may be connected in diode form by the turned-on fourth transistor T4. As an example of the inventive concept, the second electrodes of the third transistor T3 and the fourth transistor T4 are commonly connected to the first compensation scan line GCL1, but the inventive concept is not limited thereto. For example, the second electrodes of the third transistor T3 and the fourth transistor T4 may be connected to different compensation scan lines and receive different compensation scan signals.

[0096] A fifth transistor T5 may be electrically connected between the third electrode of the first transistor T1 and the anode of the light-emitting element ED. The fifth transistor T5 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode electrically connected to the first light emission control line EML1, and a third electrode electrically connected to the anode of the light-emitting element ED. During the light emission period, the fifth transistor T5 may be turned on by a first light emission control signal EM1 provided to the first light emission control line EML1.

[0097] A sixth transistor T6 may be electrically connected between the second node N2 and the initialization voltage line VIL. The sixth transistor T6 may include a first electrode electrically connected to the initialization voltage line VIL, a second electrode electrically connected to the first initialization scan line GIL1, and a third electrode electrically connected to the second node N2. An initialization voltage Vint may be applied to the initialization voltage line VIL. During the initialization period, the sixth transistor T6 may be turned on in response to a first initialization scan signal GI1 provided to the first initialization scan line GIL1. That is, during the initialization period, the second node N2 may be initialized to the initialization voltage Vint through the turned-on sixth transistor T6.

[0098] A seventh transistor T7 may be electrically connected between the initialization voltage line VIL and the anode of the light-emitting element LD. The seventh transistor T7 may include a first electrode connected to the initialization voltage line VIL, a second electrode electrically connected to the first black scan line GBL1, and a third electrode connected to the anode of the light-emitting element ED. During the black period, the seventh transistor T7 may be turned on in response to a first black scan signal GB1 provided to the first black scan line GBL1. That is, during the black period, the anode of the light-emitting element ED can be initialized to the initialization voltage Vint through the turned-on seventh transistor T7.

[0099] exist Figure 5 In this invention, the first transistor T1 to the seventh transistor T7 may be p-type metal-oxide-semiconductor (PMOS) transistors, but this disclosure is not limited thereto. In another embodiment of the concept of the invention, some or all of the first transistor T1 to the seventh transistor T7 may be configured as n-type metal-oxide-semiconductor (NMOS) transistors.

[0100] A light-emitting element (ED) can be electrically connected between a fifth transistor T5 and a second voltage line VL2. The anode of the ED can be connected to the third electrode of the fifth transistor T5, and the cathode of the ED can be connected to the second voltage line VL2. A second power supply voltage ELVSS can be applied to the second voltage line VL2. The second power supply voltage ELVSS can have a lower level than the first power supply voltage ELVDD. Therefore, the ED can emit light according to the voltage difference between the voltage transmitted through the fifth transistor T5 and the second power supply voltage ELVSS.

[0101] Figure 6A This is a circuit diagram illustrating the operation of pixels during the initialization period, and Figure 6B It is shown in Figure 6A A diagram of the waveform of the signal during the initialization period.

[0102] Display device DD (in) Figure 1 (As shown in the image) Displays a unit image for each frame period. Figure 1 Each of the pixels PX11 to PXnm shown can receive a corresponding data signal for each frame period.

[0103] Figure 6B This shows one of several frame periods, frame period F1. (Refer to...) Figure 6B For illustrative purposes, the operation of the first pixel PX11 in frame period F1 will be described. However, it should be noted that the other pixels PX12 to PXnm can operate in a similar manner to the first pixel PX11 in frame period F1, and that pixels PX11 to PXnm can also operate in a similar manner in other frame periods.

[0104] Based on the first optical transmission control signal EM1, the frame period F1 can be divided into a non-optical transmission period Te and an optical transmission period Tn. During the non-optical transmission period Te, the first optical transmission control signal EM1 may have a high level, and during the optical transmission period Tn, the first optical transmission control signal EM1 may have a low level. However, this is when the fifth transistor T5 receiving the first optical transmission control signal EM1 is a PMOS transistor. When the fifth transistor T5 is an NMOS transistor, the first optical transmission control signal EM1 may have a low level during the non-optical transmission period Te, and a high level during the optical transmission period Tn.

[0105] The first initialization scan signal GI1 can be activated during the non-light emission period Te. In this embodiment, Figure 6B The signals shown are described as being activated when they are low, but the concept of the invention is not limited thereto. Here, the first initialization scan signal GI1 may be low during the activation period and high during the deactivation period. Figure 6B The low level of the signal shown can be the turn-on voltage of the transistor to which the signal is applied in this example where the transistor is a PMOS transistor. However, as another example where the transistor is an NMOS transistor, Figure 6B The high level of the signal shown can be the turn-on voltage of the transistor to which the signal is applied.

[0106] The activation period of the first initialization scan signal GI1 can be referred to as the initialization period Ti. The first initialization scan signal GI1 can be applied to the sixth transistor T6 through the first initialization scan line GIL1, and the sixth transistor T6 is turned on during the initialization period Ti when the first initialization scan signal GI1 is activated. During the initialization period Ti, the potential of the second node N2 can be initialized to the initialization voltage Vint through the turned-on sixth transistor T6.

[0107] The first compensation scan signal GC1, the first write scan signal GW1, and the first black scan signal GB1 can also be subsequently activated during the non-light emission period Te after the initialization period Ti. That is, during the initialization period Ti, each of the first compensation scan signal GC1, the first write scan signal GW1, and the first black scan signal GB1 can be deactivated, and only the first initialization scan signal GI1 can be activated. Here, the activation period of the first compensation scan signal GC1 can be called the compensation period Tc, the activation period of the first write scan signal GW1 can be called the data write period Td, and the activation period of the first black scan signal GB1 can be called the black period Tb.

[0108] like Figure 6B As shown, the initialization period Ti, compensation period Tc, data writing period Td, and black period Tb can be included in the non-light emission period Te without overlapping with each other. Furthermore, each of the initialization period Ti, compensation period Tc, data writing period Td, and black period Tb can have the same duration or different durations. As an example of the inventive concept, the duration of the initialization period Ti can be longer than the duration of the data writing period Td. For example, the duration of the data writing period Td can be approximately one horizontal period 1H, and the initialization period Ti can have a duration of approximately three horizontal periods 3H, which is three times the duration of the data writing period Td. Horizontal period H represents driving the display panel DP (see...). Figure 1 The duration of a pixel in a row on the first direction DR1 is defined as follows: Additionally, the duration of the compensation period Tc may be longer than the duration of the data write period Td, and may be the same as the duration of the initialization period Ti. The duration of the black period Tb may be the same as the duration of the data write period Td. However, it should be noted that this is merely an example, and the duration of each period is not limited to this example, and various modifications may be made without departing from the scope of this disclosure.

[0109] The first initialization scan signal GI1 can be generated during the non-light emission period Te. That is, the initialization period Ti can be generated before the compensation period Tc, the data writing period Td, and the black period Tb. When the first initialization scan signal GI1 is deactivated, the initialization period Ti ends, and the first compensation scan signal GC1 can be activated.

[0110] Figure 7A This is a circuit diagram illustrating the operation of pixels during the compensation period, and Figure 7B It is shown Figure 7A A diagram of the signal waveform during the compensation period.

[0111] Reference Figure 7A and Figure 7BThe first compensation scan signal GC1 can be activated during the compensation period Tc within the non-optical emission period Te. Here, the first compensation scan signal GC1 can have a low level during the compensation period Tc and a high level during the deactivation period.

[0112] The first compensation scan signal GC1 can be applied to the fourth transistor T4 through the first compensation scan line GCL1, and the fourth transistor T4 is turned on during the compensation period Tc when the first compensation scan signal GC1 is activated. During the compensation period Tc, the first transistor T1 is connected as a diode, and the turned-on fourth transistor T4 is forward biased. Then, the compensation voltage "ELVDD-Vth" corresponding to the first power supply voltage ELVDD after subtracting the threshold voltage Vth of the first transistor T1 can be applied to the second node N2. That is, during the compensation period Tc, the potential of the second node N2 can be compensated by the compensation voltage "ELVDD-Vth".

[0113] Furthermore, since the first compensation scan signal GC1 is supplied to the third transistor T3 through the first compensation scan line GCL1 during the compensation period Tc, the third transistor T3 is turned on. The reference voltage Vref or the first power supply voltage ELVDD can be applied to the first node N1 through the turned-on third transistor T3. That is, the potential of the first node N1 can be the reference voltage Vref or the first power supply voltage ELVDD.

[0114] During the non-light emission period Te, the compensation period Tc precedes the data write period Td and the black period Tb. After the first compensation scan signal GC1 is deactivated, the compensation period Tc ends, and the first write scan signal GW1 can be activated.

[0115] Figure 8A This is a circuit diagram illustrating the operation of pixels during the data writing period, and Figure 8B It is shown in Figure 8A The data is written to a waveform diagram of the signal during the specified time period.

[0116] Reference Figure 8A and Figure 8B The first write scan signal GW1 can be activated during the data write period Td within the non-optical emission period Te. Here, the first write scan signal GW1 can be low during the data write period Td and high during the deactivation period.

[0117] The first write scan signal GW1 can be applied to the second transistor T2 through the first write scan line GWL1, and the second transistor T2 is turned on during the data write period Td when the first write scan signal GW1 is activated. During the data write period Td, the data voltage Vdata supplied to the first data line DL1 can be applied to the first node N1 through the turned-on second transistor T2. This changes the potential of the first node N1 from the reference voltage Vref or the first power supply voltage ELVDD to the data voltage Vdata. When the reference voltage Vref is supplied to the reference voltage line VRL during the compensation period Tc in the first mode, the potential change of the first node N1 corresponds to "Vdata-Vref". However, when the first power supply voltage ELVDD is supplied to the reference voltage line VRL during the compensation period Tc in the second mode, the potential change of the first node N1 corresponds to "Vdata-ELVDD".

[0118] During the data writing period Td, when the potential of the first node N1 changes from the reference voltage Vref or the first power supply voltage ELVDD to the data voltage Vdata, the potential of the second node N2 changes from the compensation voltage "ELVDD-Vth" to the first gate voltage Vg1 or the second gate voltage Vg2 through the coupling of the second capacitor C2. That is, in the first mode where the reference voltage Vref is supplied to the reference voltage line VRL during the compensation period Tc, the potential of the second node N2 changes to the first gate voltage Vg1 corresponding to "Vg1 = ELVDD-Vth + Vdata-Vref". On the other hand, in the second mode where the first power supply voltage ELVDD is supplied to the reference voltage line VRL during the compensation period Tc, the potential of the second node N2 changes to the second gate voltage Vg2 corresponding to "Vg2 = ELVDD-Vth + Vdata-ELVDD".

[0119] In the first mode, the first voltage difference Vgs1 ("Vgs1 = Vs - Vg1") between the source voltage Vs ("Vs = ELVDD") of the first electrode of the first transistor T1 and the first gate voltage Vg1 ("Vg1 = ELVDD - Vth + Vdata - Vref") of the second electrode of the first transistor T1 at the second node N2 is obtained by "Vgs1 = ELVDD - ELVDD + Vth - Vdata + Vref". In the second mode, the second voltage difference Vgs2 ("Vgs2 = Vs - Vg2") between the source voltage Vs ("Vs = ELVDD") of the first electrode of the first transistor T1 and the second gate voltage Vg2 ("Vg2 = ELVDD - Vth + Vdata - ELVDD") of the second electrode of the first transistor T1 at the second node N2 is obtained by "Vgs2 = ELVDD - ELVDD + Vth - Vdata + ELVDD".

[0120] The black period Tb can be set between the data writing period Td and the light emission period Tn. After the first write scan signal GW1 is deactivated, the data writing period Td ends, and the first black scan signal GB1 can be activated.

[0121] Figure 9A This is a circuit diagram illustrating the operation of pixels during the black period, and Figure 9B It is shown Figure 9A A graph showing the waveform of the signal during the black period.

[0122] Reference Figure 9A and Figure 9B The first black scan signal GB1 can be activated during the black period Tb within the non-light emission period Te. Here, the first black scan signal GB1 can have a low level during the black period Tb and a high level during the deactivation period.

[0123] The first black scan signal GB1 can be applied to the seventh transistor T7 through the first black scan line GBL1, and the seventh transistor T7 is turned on during the black period Tb when the first black scan signal GB1 is activated. During the black period Tb, the initialization voltage Vint supplied to the initialization voltage line VIL can be transmitted to the anode of the light-emitting element ED through the turned-on seventh transistor T7. Then, the anode of the light-emitting element ED can be initialized to the initialization voltage Vint. When the anode of the light-emitting element ED is initialized to the initialization voltage Vint during the black period Tb, the black characteristics of the first pixel PX11 can be improved. That is, by initializing the anode of the light-emitting element ED, current leakage through the first transistor T1 can be prevented, and the first pixel PX11 can display the correct black grayscale.

[0124] Subsequently, when the first light emission control signal EM1 is activated during the light emission period Tn, the fifth transistor T5 can be turned on, and a current path can be formed between the first transistor T1 and the light-emitting element ED. Therefore, in the first mode, the first drive current of the first transistor T1 is applied to the light-emitting element ED, and in the second mode, the second drive current of the first transistor T1 is applied to the light-emitting element ED. In the first mode, the first drive current is proportional to the first drive voltage "Vref-Vdata" between the first voltage difference Vgs1 and the threshold voltage Vth of the first transistor T1, and in the second mode, the second drive current is proportional to the second drive voltage "ELVDD-Vdata" between the second voltage difference Vgs2 and the threshold voltage Vth of the first transistor T1. Since the voltage applied to the reference voltage line VRL can be determined according to the display panel DP (in Figure 2 The operating mode (as shown in the figure) varies, so the driving current of the light-emitting element ED can vary accordingly.

[0125] Reference Figure 1 , Figure 2 , Figure 5 and Figure 9A Because the driving current of the light-emitting element ED varies depending on the operating mode of the display panel DP, the light-emitting element ED of the display device DD can emit light of different intensities.

[0126] Comparing a first mode where a reference voltage Vref is applied to the reference voltage line VRL with a second mode where a first power supply voltage ELVDD is applied to the reference voltage line VRL, the potential deviation of the first node N1 between pixels PX11 and PXnm can differ. That is, in the first mode where the reference voltage Vref is applied to the reference voltage line VRL, the potential deviation of the first node N1 between pixels PX11 and PXnm may be small, but in the second mode where the first power supply voltage ELVDD is applied to the reference voltage line VRL, the potential deviation of the first node N1 between pixels PX11 and PXnm may be large. This may be because the reference voltage line VRL is supplied with the first power supply voltage ELVDD through the first voltage line VL1, and the voltage drop of the first power supply voltage ELVDD based on location can be greater than the voltage drop of the reference voltage Vref.

[0127] In a first mode, for example, for displaying a still image such as a document, when a reference voltage Vref, having a small voltage drop depending on the position, is applied to the reference voltage line VRL, the light-emitting element ED of each of pixels PX11 to PXnm can emit light according to a first driving current proportional to the first driving voltage "Vref-Vdata". That is, since the factor of the first power supply voltage ELVDD can be removed from the first driving current of the light-emitting element ED, the amount of voltage drop of the first power supply voltage ELVDD is not reflected in the brightness of each of pixels PX11 to PXnm. Therefore, the brightness deviation between pixels PX11 to PXnm can be reduced in the first mode.

[0128] On the other hand, in a second mode, for example, for displaying video, when a first power supply voltage ELVDD with a large voltage drop based on location is applied to the reference voltage line VRL, the light-emitting element ED of each of pixels PX11 to PXnm can emit light according to a second driving current proportional to the second driving voltage "ELVDD-Vdata". Because the amount of voltage drop of the first power supply voltage ELVDD is reflected in the brightness of each of pixels PX11 to PXnm, in the case where a screen includes areas displaying white grayscale and areas displaying black grayscale, the white grayscale areas can be displayed more sharply.

[0129] As described above, by changing the voltage supplied to the reference voltage line VRL according to the operating mode of the display panel DP, in addition to reducing the overall brightness deviation of the display device DD, the image quality of the white area can also be improved in the high-frequency drive mode.

[0130] Figure 10 This is a circuit diagram of a pixel according to an embodiment of the concept of the present invention. The same reference numerals are used interchangeably with those of the pixel. Figure 5 The components shown are the same as those shown, and redundant detailed descriptions of them will be omitted.

[0131] Reference Figure 10 The first pixel PX11 may include multiple transistors T1 to T9, two capacitors C1 and C2, and a light-emitting element ED. The multiple transistors T1 to T9 and the two capacitors C1 and C2 can control the amount of current flowing through the light-emitting element ED in response to data signals and scan signals.

[0132] For ease of description, the multiple transistors T1 to T9 are referred to as the first transistor T1 to the ninth transistor T9, and the two capacitors C1 and C2 are referred to as the first capacitor C1 and the second capacitor C2.

[0133] The first transistor T1 to the seventh transistor T7, the first capacitor C1, and the second capacitor C2 have the same characteristics as... Figure 5The first transistor T1 to the seventh transistor T7, as well as the first capacitor C1 and the second capacitor C2, are shown with the same connections. Therefore, the description of the first transistor T1 to the seventh transistor T7, as well as the first capacitor C1 and the second capacitor C2, is omitted.

[0134] The first pixel PX11 may further include an eighth transistor T8 and a ninth transistor T9. The eighth transistor T8 may be disposed between the first transistor T1 and the bias voltage line VBL. The eighth transistor T8 may include a first electrode connected to the bias voltage line VBL, a second electrode connected to the first bias scan line GBL1_2, and a third electrode connected to the first electrode of the first transistor T1. The bias voltage line VBL may supply a bias voltage Vbias, and the first bias scan line GBL1_2 may supply a first bias scan signal GB1_2. As an example of the inventive concept, the first bias scan signal GB1_2 may be activated simultaneously with the first black scan signal GB1_1 supplied to the seventh transistor T7.

[0135] The potential of the first electrode of the first transistor T1 can be determined during the black period Tb (in Figure 9B During the period shown in the diagram, the bias voltage Vbias is reset by the eighth transistor T8, and a constant bias voltage can be formed between the first electrode and the second electrode of the first transistor T1. Therefore, it is possible to prevent the degradation of display quality that may be caused by the potential difference between the second electrode and the first electrode of the first transistor T1 increasing above a certain level due to hysteresis.

[0136] A ninth transistor T9 may be disposed between the first voltage line VL1 and the first transistor T1. The ninth transistor T9 may include a first electrode connected to the first voltage line VL1, a second electrode connected to the second light emission control line EML1_2, and a third electrode connected to the first electrode of the first transistor T1. The second light emission control line EML1_2 may supply a second light emission control signal EM1_2. As an example of the inventive concept, the second electrode of the fifth transistor T5 may be connected to the first light emission control line EML1_1, which supplies the first light emission control signal EM1_1. The first light emission control signal EM1_1 and the second light emission control signal EM1_2 may be activated simultaneously. In this case, depending on the operation of the fifth transistor T5 and the ninth transistor T9, a current path may be formed or blocked between the first voltage line VL1 and the light-emitting element ED.

[0137] In this example, using a first pixel PX11 with nine transistors and two capacitors, the voltage applied to the reference voltage line VRL can be determined according to the display panel DP (in... Figure 2The operation mode varies depending on the display panel DP. That is, when the display panel DP operates in the first mode, the reference voltage Vref can be applied to the reference voltage line VRL, and when the display panel DP operates in the second mode, the first power supply voltage ELVDD can be applied to the reference voltage line VRL.

[0138] In a first mode, for example, for displaying a still image such as a document, when a reference voltage Vref, having a small voltage drop depending on the position, is applied to the reference voltage line VRL, the light-emitting element ED of each of pixels PX11 to PXnm can emit light according to a first driving current proportional to the first driving voltage "Vref-Vdata". That is, since the factor of the first power supply voltage ELVDD can be removed from the first driving current of the light-emitting element ED, the amount of voltage drop of the first power supply voltage ELVDD is not reflected in the brightness of each of pixels PX11 to PXnm. Therefore, the brightness deviation between pixels PX11 to PXnm can be reduced in the first mode.

[0139] On the other hand, in a second mode, for example, for displaying video, when a first power supply voltage ELVDD with a large voltage drop based on location is applied to the reference voltage line VRL, the light-emitting element ED of each of pixels PX11 to PXnm can emit light according to a second driving current proportional to the second driving voltage "ELVDD-Vdata". Because the amount of voltage drop of the first power supply voltage ELVDD is reflected in the brightness of each of pixels PX11 to PXnm, the sharpness of the white grayscale area can be improved in the case where a screen includes areas displaying white grayscale and areas displaying black grayscale.

[0140] As described above, by changing the voltage supplied to the reference voltage line VRL according to the operating mode of the display panel DP, in addition to reducing the overall brightness deviation of the display device DD, the image quality of the white area can also be improved in the high-frequency drive mode.

[0141] Figure 11 This is a circuit diagram of a pixel according to an embodiment of the concept of the present invention, and Figure 12 It shows that it is applied to Figure 11 The image shows a waveform diagram of the signal waveform of the pixel. The same reference numerals are used with respect to... Figure 5 and / or Figure 10 The components shown are the same as those shown, and redundant detailed descriptions of them will be omitted.

[0142] Reference Figure 11 and Figure 12The first pixel PX11 may include multiple transistors T1, T2a, T3a, T4, T5, T7, T8, and T9, two capacitors C1 and C3, and a light-emitting element ED. For ease of description, the multiple transistors T1, T2a, T3a, T4, T5, T7, T8, and T9 are referred to as the first transistor T1, the second transistor T2a, the third transistor T3a, the fourth transistor T4, the fifth transistor T5, and the seventh transistors T7 through the ninth transistor T9, and the two capacitors C1 and C3 are referred to as the first capacitor C1 and the third capacitor C3.

[0143] A first transistor T1 may be connected between a first voltage line VL1 and a light-emitting element ED. The first transistor T1 may include a first electrode electrically connected to the first voltage line VL1, a second electrode connected to a first node N1, and a third electrode electrically connected to the light-emitting element ED. The first transistor T1 may receive a first power supply voltage ELVDD via the first voltage line VL1. The third electrode of the first transistor T1 may be electrically connected to the anode of the light-emitting element ED via a fifth transistor T5.

[0144] A second transistor T2a may be connected between the first data line DL1 and the third node N3. The second transistor T2a may include a first electrode connected to the first data line DL1, a second electrode connected to the first write scan line GWL1, and a third electrode connected to the third node N3. During the data write period Td, the second transistor T2a may be turned on in response to a first write scan signal GW1 provided to the first write scan line GWL1, and the first data line DL1 and the third node N3 may be electrically connected through the turned-on second transistor T2a. That is, during the data write period Td, the data voltage Vdata applied to the first data line DL1 may be transmitted to the third node N3 through the turned-on second transistor T2a.

[0145] The first capacitor C1 may be electrically connected between the first voltage line VL1 and the first node N1, and the third capacitor C3 may be electrically connected between the third node N3 and the fourth node N4. The third capacitor C3 may include a first electrode electrically connected to the fourth node N4 and a second electrode electrically connected to the third node N3.

[0146] The third transistor T3a may be electrically connected between the third node N3 and the reference voltage line VRL. The third transistor T3a may include a first electrode connected to the reference voltage line VRL, a second electrode electrically connected to the first black scan line GBL1_1, and a third electrode electrically connected to the third node N3. The reference voltage line VRL may provide a reference voltage Vref or a first power supply voltage ELVDD depending on the operating mode of the display panel DP.

[0147] A fourth transistor T4 may be electrically connected between the second electrode (or first node N1) of the first transistor T1 and the third electrode of the first transistor T1. The fourth transistor T4 may include a first electrode electrically connected to the second electrode of the first transistor T1, a second electrode electrically connected to the first compensation scan line GCL1, and a third electrode electrically connected to the fourth node N4. During the compensation period Tc, the fourth transistor T4 may be turned on in response to a first compensation scan signal GC1 provided to the first compensation scan line GCL1. That is, during the compensation period Tc, the first transistor T1 may be connected in diode form by the turned-on fourth transistor T4.

[0148] A fifth transistor T5 may be electrically connected between the third electrode of the first transistor T1 and the anode of the light-emitting element ED. The fifth transistor T5 may include a first electrode connected to the third electrode of the first transistor T1, a second electrode electrically connected to the first light emission control line EML1_1, and a third electrode electrically connected to the anode of the light-emitting element ED. During the light emission period Tn, the fifth transistor T5 may be turned on by a first light emission control signal EM1_1 provided to the first light emission control line EML1_1.

[0149] A seventh transistor T7 may be electrically connected between the initialization voltage line VIL and the anode of the light-emitting element ED. The seventh transistor T7 may include a first electrode connected to the initialization voltage line VIL, a second electrode electrically connected to the first black scan line GBL1_1, and a third electrode connected to the anode of the light-emitting element ED. During the black period Tb1, the seventh transistor T7 may be turned on in response to a first black scan signal GB1_1 provided to the first black scan line GBL1_1.

[0150] Reference Figure 12 According to the first optical emission control signal EM1_1 and the second optical emission control signal EM1_2, the frame period F1 can be divided into a non-optical emission period Te and an optical emission period Tn. During the non-optical emission period Te, at least one of the first optical emission control signal EM1_1 and the second optical emission control signal EM1_2 may have a high level, and during the optical emission period Tn, both the first optical emission control signal EM1_1 and the second optical emission control signal EM1_2 may have a low level. Within the frame period F1, the first compensation scan signal GC1 may include multiple activation periods Ac1, Ac2, and Ac3. Although Figure 12The diagram illustrates the structure of the first compensated scan signal GC1 within frame time period F1, comprising three active periods Ac1, Ac2, and Ac3; however, the concept of the invention is not limited thereto. That is, the number of active periods included in the first compensated scan signal GC1 is not particularly limited. Here, for ease of explanation, the multiple active periods Ac1, Ac2, and Ac3 of the first compensated scan signal GC1 are referred to as the first compensated active period Ac1, the second compensated active period Ac2, and the third compensated active period Ac3. Within frame time period F1, the first black scan signal GB1_1 may also include multiple active periods. Although... Figure 12 The diagram illustrates a structure in which the first black scan signal GB1_1 within frame time period F1 includes two active time periods Bc1 and Bc2, but the concept of the invention is not limited thereto. That is, the number of active time periods included in the first black scan signal GB1_1 is not particularly limited. Here, for ease of description, the multiple active time periods Bc1 and Bc2 of the first black scan signal GB1_1 are referred to as the first black active time period Bc1 and the second black active time period Bc2.

[0151] The first black activation period Bc1 may overlap with the first compensation activation period Ac1 and the second compensation activation period Ac2. Additionally, the activation period of the first optical emission control signal EM1_1 may overlap with both the first compensation activation period Ac1 and the first black activation period Bc1.

[0152] The fifth transistor T5 is turned on during the activation period of the first optical emission control signal EM1_1, and the third transistor T3a and the seventh transistor T7 are turned on during the first black activation period Bc1. Therefore, the initialization voltage Vint can be applied to the fourth node N4 through the turned-on seventh transistor T7 and fifth transistor T5. Subsequently, when the fourth transistor T4 is turned on during the first compensation activation period Ac1, the potential of the first node N1 changes to the initialization voltage Vint. Here, the first compensation activation period Ac1 of the first compensation scan signal GC1 can be referred to as the initialization period Ti.

[0153] During the first black active period Bc1, the reference voltage Vref or the first power supply voltage ELVDD can be applied to the third node N3 through the turned-on third transistor T3a. That is, the potential of the third node N3 can have the reference voltage Vref or the first power supply voltage ELVDD.

[0154] Subsequently, when the first optical emission control signal EM1_1 is deactivated and the second optical emission control signal EM1_2 is activated, the fifth transistor T5 can be turned off, and the ninth transistor T9 can be turned on. When the fifth transistor T5 is turned off and the ninth transistor T9 is turned on, the fourth transistor T4 is turned on during the second compensation activation period Ac2. Then, the potential of the first node N1 can be compensated by the compensation voltage “ELVDD-Vth” corresponding to the first power supply voltage ELVDD after subtracting the threshold voltage Vth of the first transistor T1. Therefore, the second compensation activation period Ac2 of the first compensation scan signal GC1 can be called the compensation period Tc.

[0155] After the compensation period Tc ends, the first write scan signal GW1 can be activated. The activation period of the first write scan signal GW1 can be referred to as the data write period Td. As an example of the concept of the present invention, the initialization period Ti and the compensation period Tc can have a duration longer than the duration of the data write period Td.

[0156] During the data write period Td, the second transistor T2 can be turned on in response to the first write scan signal GW1 provided to the first write scan line GWL1, and the data voltage Vdata supplied to the first data line DL1 can be transmitted to the third node N3 through the turned-on second transistor T2. The third compensation activation period Ac3 of the first compensation scan signal GC1 can overlap with the data write period Td. That is, the fourth transistor T4 can be turned on during the data write period Td.

[0157] During the data write period Td, the potential of the third node N3 changes from the reference voltage Vref or the first power supply voltage ELVDD to the data voltage Vdata. In the first mode, when the reference voltage Vref is supplied to the reference voltage line VRL during the first black activation period Bc1, the potential change of the third node N3 corresponds to "Vdata - Vref". However, in the second mode, when the first power supply voltage ELVDD is supplied to the reference voltage line VRL during the first black activation period Bc1, the potential change of the third node N3 corresponds to "Vdata - ELVDD".

[0158] During the data writing period Td, when the potential of the third node N3 changes from the reference voltage Vref or the first power supply voltage ELVDD to the data voltage Vdata, the potential of the first node N1 changes from the compensation voltage "ELVDD-Vth" to the first gate voltage Vg1 or the second gate voltage Vg2 through the coupling of the third capacitor C3. That is, in the first mode where the reference voltage Vref is supplied to the reference voltage line VRL during the first black activation period Bc1, the potential of the first node N1 changes to the first gate voltage Vg1 corresponding to "Vg1 = ELVDD-Vth + Vdata-Vref". On the other hand, in the second mode where the first power supply voltage ELVDD is supplied to the reference voltage line VRL during the first black activation period Bc1, the potential of the first node N1 changes to the second gate voltage Vg2 corresponding to "Vg2 = ELVDD-Vth + Vdata-ELVDD".

[0159] In the first mode, the first voltage difference Vgs1 ("Vgs1 = Vs - Vg1") between the source voltage Vs ("Vs = ELVDD") of the first electrode of the first transistor T1 and the first gate voltage Vg1 ("Vg1 = ELVDD - Vth + Vdata - Vref") of the second electrode of the first transistor T1 at the first node N1 is obtained by "Vgs1 = ELVDD - ELVDD + Vth - Vdata + Vref". In the second mode, the second voltage difference Vgs2 ("Vgs2 = Vs - Vg2") between the source voltage Vs ("Vs = ELVDD") of the first electrode of the first transistor T1 and the second gate voltage Vg2 ("Vg2 = ELVDD - Vth + Vdata - ELVDD") of the second electrode of the first transistor T1 at the first node N1 is obtained by "Vgs2 = ELVDD - ELVDD + Vth - Vdata + ELVDD".

[0160] The black period Tb1 can be set between the data writing period Td and the light emission period Tn. After the first write scan signal GW1 is deactivated, the data writing period Td ends, and the second black activation period Bc2 of the first black scan signal GB1_1 can be activated.

[0161] During the second black activation period Bc2, the seventh transistor T7 is turned on, and the initialization voltage Vint supplied to the initialization voltage line VIL can be transmitted to the anode of the light-emitting element ED through the turned-on seventh transistor T7. Then, the anode of the light-emitting element ED can be initialized to the initialization voltage Vint. When the anode of the light-emitting element ED is initialized to the initialization voltage Vint during the second black activation period Bc2, the black characteristics of the first pixel PX11 are improved. That is, by initializing the anode of the light-emitting element ED, current leakage through the first transistor T1 is prevented, and the first pixel PX11 can display the correct black grayscale. Here, the second black activation period Bc2 can be referred to as the black period Tb1.

[0162] Subsequently, when the first light emission control signal EM1_1 and the second light emission control signal EM1_2 are activated during the light emission period Tn, the fifth transistor T5 and the ninth transistor T9 can be turned on, and a current path can be formed between the first transistor T1 and the light-emitting element ED. Therefore, in the first mode, the first drive current of the first transistor T1 is applied to the light-emitting element ED, and in the second mode, the second drive current of the first transistor T1 is applied to the light-emitting element ED. In the first mode, the first drive current is proportional to the first drive voltage "Vref-Vdata" between the first voltage difference Vgs1 and the threshold voltage Vth of the first transistor T1, and in the second mode, the second drive current is proportional to the second drive voltage "ELVDD-Vdata" between the second voltage difference Vgs2 and the threshold voltage Vth of the first transistor T1. Since the voltage applied to the reference voltage line VRL can be determined according to the display panel DP (in Figure 2 The operating mode (as shown in the figure) varies, so the driving current of the light-emitting element ED can vary accordingly.

[0163] As an example of the concept of this invention, the second electrode of the third transistor T3a and the second electrode of the seventh transistor T7 can be jointly connected to the first black scan line GBL1_1, but the concept of this invention is not limited thereto. That is, the second electrode of the third transistor T3a and the second electrode of the seventh transistor T7 can be connected to different scan lines and receive different scan signals.

[0164] Furthermore, the eighth transistor T8 can be turned on by the first bias scan signal GB1_2 during the bias period Tb2, and the potential of the first electrode of the first transistor T1 can be reset to the bias voltage Vbias. Therefore, a constant bias voltage can be formed between the first and second electrodes of the first transistor T1 during the bias period Tb2. As an example of the concept of the present invention, within the frame period F1, the initialization period Ti, the compensation period Tc, and the data writing period Td can precede the bias period Tb2. In the frame period F1, the bias period Tb2 can overlap with the black period Tb1.

[0165] In this example, using eight transistors and two capacitors for the first pixel PX11, the voltage applied to the reference voltage line VRL can be determined according to the display panel DP (in... Figure 2 The operation mode varies depending on the display panel DP. That is, when the display panel DP operates in the first mode, the reference voltage Vref can be applied to the reference voltage line VRL, and when the display panel DP operates in the second mode, the first power supply voltage ELVDD can be applied to the reference voltage line VRL.

[0166] In a first mode, for example, for displaying a still image such as a document, when a reference voltage Vref, having a small voltage drop depending on the position, is applied to the reference voltage line VRL, the light-emitting element ED of each of pixels PX11 to PXnm can emit light according to a first driving current proportional to the first driving voltage "Vref-Vdata". That is, since the factor of the first power supply voltage ELVDD can be removed from the first driving current of the light-emitting element ED, the amount of voltage drop of the first power supply voltage ELVDD is not reflected in the brightness of each of pixels PX11 to PXnm. Therefore, the brightness deviation between pixels PX11 to PXnm can be reduced in the first mode.

[0167] On the other hand, in a second mode, for example, for displaying video, when a first power supply voltage ELVDD with a large voltage drop based on location is applied to the reference voltage line VRL, the light-emitting element ED of each of pixels PX11 to PXnm can emit light according to a second driving current proportional to the second driving voltage "ELVDD-Vdata". Because the amount of voltage drop of the first power supply voltage ELVDD is reflected in the brightness of each of pixels PX11 to PXnm, the sharpness of the white grayscale area can be improved in the case where a screen includes areas displaying white grayscale and areas displaying black grayscale.

[0168] As described above, by changing the voltage supplied to the reference voltage line VRL according to the operating mode of the display panel DP, in addition to reducing the overall brightness deviation of the display device DD, the image quality of the white area can also be improved in the high-frequency drive mode.

[0169] Although exemplary embodiments of the inventive concept have been described, it should be understood that the inventive concept is not limited to these exemplary embodiments, but rather various changes and modifications can be made by those skilled in the art within the spirit and scope of the inventive concept claimed below.

Claims

1. A display device comprising: a display panel including a pixel, a voltage line supplying a power supply voltage to the pixel, and a reference voltage line supplying one of a reference voltage and the power supply voltage to the pixel; a mode selector configured to output one of a first selection signal and a second selection signal in accordance with an operation mode of the display panel; and a switch configured to supply the reference voltage or the power supply voltage to the reference voltage line in response to one of the first selection signal and the second selection signal, the pixel including: a light emitting element including a cathode and an anode; a first transistor connected between the anode of the light emitting element and the voltage line; a second transistor connected between a data line supplying a data signal and the first transistor; and a third transistor connected between the reference voltage line and the second transistor. the switch including:

2. The display device according to claim 1, wherein a first switching element configured to supply the reference voltage to the reference voltage line in response to the first selection signal; and a second switching element configured to supply the power supply voltage to the reference voltage line in response to the second selection signal. the mode selector activates the first selection signal when the display panel operates in a first mode for displaying a still image, and 3. The display device according to claim 2, wherein wherein the mode selector activates the second selection signal when the display panel operates in a second mode for displaying a video. the display panel includes a display region in which a plurality of pixels are arranged, and a peripheral region adjacent to the display region, and 4. The display device according to claim 2, wherein wherein the first switching element and the second switching element are disposed in the peripheral region of the display panel. the second switching element receives the power supply voltage through the voltage line.

5. The display device according to claim 2, wherein the pixel further includes:

6. The display device according to claim 1, wherein a first capacitor connected between a first node and the voltage line; and a second capacitor connected between the first transistor and the second transistor. the first transistor includes:

7. The display device of claim 6, wherein, a first electrode connected to the voltage line; a second electrode connected to the second capacitor at a second node; and a third electrode connected to the anode of the light emitting element, and wherein the second transistor includes: a first electrode connected to the data line; a second electrode configured to receive a write scan signal; and a third electrode connected to the first node. the third transistor includes a first electrode connected to the reference voltage line, a second electrode configured to receive a compensation scan signal, and a third electrode connected to the first node.

8. The display device of claim 7, wherein, an activation period of the compensation scan signal has a first duration that is longer than a second duration of an activation period of the write scan signal.

9. The display device of claim 8, wherein, the compensation scan signal is activated before the write scan signal is activated.

10. The display device of claim 9, wherein, the pixel further includes:

11. The display device of claim 8, wherein, ​ a fourth transistor including a first electrode connected to the second electrode of the first transistor, a second electrode configured to receive the compensation scan signal, and a third electrode connected to the third electrode of the first transistor; and a fifth transistor including a first electrode connected to the third electrode of the first transistor, a second electrode configured to receive a light emission control signal, and a third electrode connected to the anode of the light emitting element.

12. The display device of claim 11, wherein, the compensation scan signal is activated before the write scan signal is activated during a deactivation period of the light emission control signal.

13. The display device of claim 8, wherein, The pixel further includes: a sixth transistor including a first electrode connected to an initialization voltage line, a second electrode configured to receive an initialization scan signal, and a third electrode connected to the second electrode of the first transistor; and a seventh transistor including a first electrode connected to the initialization voltage line, a second electrode configured to receive a black scan signal, and a third electrode connected to the anode of the light emitting element.

14. The display device of claim 13, wherein, the compensation scan signal is activated before the write scan signal is activated, and wherein the initialization scan signal is activated before the compensation scan signal is activated.

15. The display device of claim 14, wherein, a first activation period of the compensation scan signal and a second activation period of the initialization scan signal are greater than a third activation period of the write scan signal.

16. A display device comprising: a display panel including a pixel, a voltage line supplying a first power supply voltage to the pixel, and a reference voltage line supplying a second power supply voltage to the pixel, wherein the pixel includes: a first transistor connected between an anode of a light emitting element and the voltage line; a second transistor connected between a data line and the first transistor; a third transistor connected between the reference voltage line and the second transistor; and a capacitor connected between the first transistor and the third transistor, wherein the display panel operates in a first mode and a second mode, and the first power supply voltage has a first voltage level in the first mode and the second mode, wherein the second power supply voltage has a second voltage level in the first mode, and has the first voltage level in the second mode, wherein the first voltage level is different from the second voltage level.

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