Memory device and operation method thereof

Abstract

The present technology relates to a memory device and an operation method thereof. The memory device includes: a memory block including a plurality of strings; a peripheral circuit configured to perform an erase operation including a first erase operation, an erase verification operation, and a second erase operation on the memory block; and a control logic configured to control the peripheral circuit to perform the erase operation. During the second erase operation, the control logic controls the peripheral circuit to apply a first erase voltage to a source line of the memory block and a second erase voltage lower than the first erase voltage to a bit line connected to a string determined to be erased among the plurality of strings.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a memory device and an operating method thereof. Background Art

[0002] Among semiconductor devices, memory devices are generally classified into two types: volatile memory devices and nonvolatile memory devices.

[0003] The writing speed and reading speed of non-volatile memory devices are relatively slow; however, even if the power supply is turned off, the non-volatile memory device continues to store data. Therefore, non-volatile memory devices are used to store data to be maintained regardless of the power supply. Examples of non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc. The flash memory can be of NOR type or NAND type.

[0004] Flash memory has the advantages of RAM that can freely program and erase data and ROM that can retain stored data even if power is cut off. Flash memory is widely used as a storage medium for portable electronic devices such as digital cameras, personal digital assistants (PDAs), and MP3 players. Summary of the invention

[0005] Embodiments of the present disclosure provide a memory device capable of improving threshold voltage distribution of memory cells during an erase operation of the memory device and an operating method thereof.

[0006] A memory device according to an embodiment of the present disclosure includes: a memory block including a plurality of strings; a peripheral circuit configured to perform an erase operation including a first erase operation, an erase verification operation, and a second erase operation on the memory block; and a control logic configured to control the peripheral circuit to perform the erase operation. During the second erase operation, the control logic controls the peripheral circuit to apply a first erase voltage to a source line of the memory block and a second erase voltage lower than the first erase voltage to a bit line connected to a string determined to be erased among the plurality of strings.

[0007] A memory device according to an embodiment of the present disclosure includes: a memory block including a plurality of strings; a peripheral circuit configured to perform an erase operation including a first erase operation, an erase verification operation, and a second erase operation on the memory block; and a control logic configured to control the peripheral circuit to perform the erase operation. During the second erase operation, the control logic controls the peripheral circuit to apply an erase voltage to a source line of the memory block and float a bit line connected to a string determined to be erased among the plurality of strings.

[0008] A method for operating a memory device according to an embodiment of the present disclosure includes the following steps: performing a first erase operation of applying a first erase voltage to a source line and a bit line of a selected memory block; determining whether each of a plurality of strings included in the selected memory block is erased by performing an erase verification operation; and when at least one of the plurality of strings is determined to have failed erase as a result of the erase verification operation, performing a second erase operation of applying the first erase voltage to the source line and applying a second erase voltage to the bit line of the string determined to have passed erase.

[0009] A method for operating a memory device according to an embodiment of the present disclosure includes the following steps: performing a first erase operation of applying an erase voltage to a source line and a bit line of a selected memory block; determining whether each of a plurality of strings included in the selected memory block is erased by performing an erase verification operation; and when at least one of the plurality of strings is determined to have failed to erase as a result of the erase verification operation, performing a second erase operation of applying an erase voltage to the source line, floating the bit line of the string determined to have passed the erase, and applying an erase voltage to the bit line of the string determined to have failed to erase.

[0010] A memory device according to an embodiment of the present disclosure includes: a memory block including a first string and a second string of memory cells; a control circuit configured to perform a current erase operation on the memory block when the first string is verified as successful and the second string is verified as failed as a result of a previous erase operation, wherein, during the current erase operation, the control circuit applies a first erase voltage to a bit line of the second string and a source line of the memory block and applies a second erase voltage to the bit line of the first string, and wherein the second erase voltage is lower than the first erase voltage.

[0011] A memory device according to an embodiment of the present disclosure includes: a memory block including a first string and a second string of memory cells; a control circuit configured to perform a current erase operation on the memory block when the first string is determined to have succeeded and the second string is determined to have failed as a result of a previous erase operation, wherein during the current erase operation, the control circuit applies an erase voltage to a bit line of the second string and a source line of the memory block and floats the bit line of the first string. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0013] Figure 2 It shows that Figure 1 Diagram of a memory device.

[0014] Figure 3 It shows that Figure 2 A diagram of a storage block.

[0015] Figure 4 is a diagram showing an embodiment of a three-dimensional storage block.

[0016] Figure 5 is a diagram showing another embodiment of a three-dimensional storage block.

[0017] Figure 6 It shows that Figure 2 Diagram of the page buffer shown.

[0018] Figure 7 is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0019] Figure 8 is a diagram illustrating application of a first erase voltage and a second erase voltage to a source line and a bit line during an erase operation according to an embodiment of the present disclosure.

[0020] Fig. 9 It is shown that including Figure 2 A diagram of another embodiment of a memory system of a memory device is shown.

[0021] Fig.10 It is shown that including Figure 2 A diagram of another embodiment of a memory system of a memory device is shown.

[0022] Fig.11 It is shown that including Figure 2 A diagram of another embodiment of a memory system of a memory device is shown.

[0023] Fig.12 It is shown that including Figure 2 A diagram of another embodiment of a memory system of a memory device is shown. DETAILED DESCRIPTION

[0024] The specific structural and functional descriptions provided herein relate to embodiments of the present disclosure. However, the present invention can be implemented in various ways and realized in various forms. Therefore, the present invention is not limited to any embodiment, nor to any specific details described herein. On the contrary, the present invention is defined by the claims.

[0025] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure belongs can practice and easily implement the present invention. Throughout this specification, references to "an embodiment", "another embodiment", etc. do not necessarily refer to only one embodiment, and different references to any such phrases do not necessarily refer to the same embodiment. When used herein, the term "embodiment" does not necessarily refer to all embodiments.

[0026] Figure 1 is a diagram illustrating a memory system according to an embodiment of the present disclosure.

[0027] Reference Figure 1 , the memory system 1000 includes a memory device 1100 storing data and a memory controller 1200 controlling the memory device 1100 under the control of a host 2000 .

[0028] The host 2000 may communicate with the memory system 1000 using an interface protocol such as Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached Small Computer System Interface (SCSI) (SAS). Other interface protocols that may be used for communication between the host 2000 and the memory system 1000 include Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Minidisk Interface (ESDI), and Integrated Drive Electronics (IDE). More generally, any suitable interface protocol may be used.

[0029] The memory device 1100 may perform a program operation, a read operation, or an erase operation under the control of the memory controller 1200. The memory device 1100 may include a plurality of memory blocks, and may perform a program operation, a read operation, and an erase operation on a selected memory block among the plurality of memory blocks.

[0030] According to an embodiment of the present disclosure, the memory device 1100 performs a first erase operation according to a gate-induced drain leakage (GIDL) method by applying a first erase voltage to a bit line and a source line connected to a selected storage block. Thereafter, a second erase operation is performed after performing an erase verification operation. During the second erase operation, according to the result of the erase verification operation, a second erase voltage lower than the first erase voltage is applied to a bit line corresponding to a memory cell determined to have passed the erase among the bit lines, and according to the result of the erase verification operation, the first erase voltage is applied to a bit line corresponding to a memory cell determined to have failed the erase. Therefore, the phenomenon that a memory cell determined to have passed the erase operation is over-erased can be prevented or reduced.

[0031] The storage controller 1200 is connected between the host 2000 and the memory device 1100. The storage controller 1200 is configured to access the memory device 1100 in response to a request from the host 2000. For example, the storage controller 1200 is configured to control a program operation, a read operation, an erase operation, and a background operation of the memory device 1100 in response to a request received from the host 2000. The storage controller 1200 is configured to provide an interface between the memory device 1100 and the host 2000. The storage controller 1200 is configured to drive firmware for controlling the memory device 1100.

[0032] The storage controller 1200 and the memory device 1100 may be integrated into one semiconductor device to form a semiconductor drive (solid state drive (SSD)). The semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of the host 2000 connected to the memory system 1000 is greatly improved.

[0033] In another example, the memory system 1000 is provided as one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3D TV, a digital audio recorder, a digital audio player, a digital image recorder, a digital image player, a digital video recorder, and a digital video player, a device capable of sending and receiving information in a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, an RFID device, or one of various components configuring a computing system.

[0034] In an embodiment, the memory device 1100 or the memory system 1000 may be installed as any of various types of packages. For example, the memory device 1100 or the memory system 1000 may be packaged and installed in a method such as a stacked package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic chip carrier with leads (PLCC), a plastic dual in-line package (PDIP), a waffle die package, a wafer form die, a chip on board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline package (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system in package (SIP), a multi-chip package (MCP), a wafer-level manufacturing package (WFP), or a wafer-level processing stacked package (WSP).

[0035] Figure 2 It is shown Figure 1 Diagram of a memory device.

[0036] Reference Figure 2 , the memory device 1100 may include a memory cell array 100 storing data. The memory device 1100 may include a peripheral circuit 200 configured to perform a program operation to store data in the memory cell array 100, a read operation to output the stored data, and an erase operation to erase the stored data. The memory device 1100 may include a control logic 300, the control logic 300 according to Figure 1 The peripheral circuit 200 is controlled by the control of the memory controller 1200. During the erase operation, the memory device 1100 according to the embodiment of the present disclosure may perform a first erase operation of applying a first erase voltage to the bit lines and source lines of the selected memory block and a second erase operation of applying a second erase voltage to the bit lines corresponding to the memory cells that passed the erase and applying the first erase voltage to the bit lines corresponding to the memory cells that failed the erase after the first erase operation. The first erase voltage may be applied to the source line of the selected memory block during the second erase operation.

[0037] The memory cell array 100 may include a plurality of memory blocks 110, also referred to as MB1 to MBk (k is a positive integer). Local lines LL and bit lines BL1 to BLn (n is a positive integer) may be connected to each of the memory blocks MB1 to MBk. For example, the local line LL may include a first selection line, a second selection line, and a plurality of word lines arranged between the first selection line and the second selection line. In addition, the local line LL may include a dummy line arranged between the first selection line and the word line and between the second selection line and the word line. Here, the first selection line may be a source selection line, and the second selection line may be a drain selection line. For example, the local line LL may include a word line, a drain selection line, a source selection line, and a source line. For example, the local line LL may also include a dummy line. For example, the local line LL may also include a pipeline. The local line LL may be connected to the memory blocks MB1 to MBk, respectively, and the bit lines BL1 to BLn may be connected to the memory blocks MB1 to MBk in common. The memory blocks MB1 to MBk may be implemented in a two-dimensional or three-dimensional structure. For example, the memory cells may be arranged in a two-dimensional structure in a direction parallel to the substrate in the memory block 110. In another embodiment, memory cells may be stacked in a direction perpendicular to the substrate in the memory block 110 to form a three-dimensional structure.

[0038] The peripheral circuit 200 may be configured to perform a program operation, a read operation, and an erase operation of the selected memory block 110 under the control of the control logic 300. For example, the peripheral circuit 200 may include a voltage generation circuit 210, a row decoder 220, a page buffer group 230, a column decoder 240, an input / output circuit 250, a pass / fail determiner (pass / fail check circuit) 260, and a source line driver 270.

[0039] The voltage generating circuit 210 may generate various operating voltages Vop for programming, reading, and erasing operations in response to the operating signal OP_CMD. In addition, the voltage generating circuit 210 may selectively discharge the local line LL in response to the operating signal OP_CMD. For example, the voltage generating circuit 210 may generate a programming voltage, a reading voltage, a verification voltage, a pass voltage, and a selection transistor operating voltage under the control of the control logic 300.

[0040] The row decoder 220 may transmit the operation voltage Vop to the local line LL connected to the selected memory block 110 in response to the row decoder control signal AD_signals. For example, the row decoder 220 may selectively apply the operation voltage (e.g., program voltage, read voltage, verification voltage, pass voltage, etc.) generated by the voltage generation circuit 210 to the local line LL in response to the row decoder control signal AD_signals, and some local lines LL (e.g., word lines and source selection lines) may be floated.

[0041] The page buffer group 230 may include a plurality of page buffers 231 (also referred to as PB1 to PBn) connected to the bit lines BL1 to BLn. The page buffers PB1 to PBn may operate in response to the page buffer control signal PBSIGNALS. For example, the page buffers PB1 to PBn may control the bit lines BL1 to BLn in a floating state during the application of the erase voltage in the erase operation, and may sense the current or potential level of the bit lines BL1 to BLn during the erase verification operation.

[0042] During the erase operation, the page buffer group 230 may apply the first erase voltage or the second erase voltage to the bit lines BL1 to BLn. For example, the page buffer group 230 may apply the first erase voltage to the bit lines BL1 to BLn during the first erase operation, and may selectively apply the first erase voltage or the second erase voltage to the bit lines BL1 to BLn according to the result of the erase verification operation performed after the first erase operation. For example, the page buffer group 230 may apply the second erase voltage to the bit lines connected to the memory cells determined to be erased as a result of the erase verification operation, and apply the first erase voltage to the bit lines connected to the memory cells determined to be erased failed as a result of the erase verification operation. In another embodiment, the page buffer group 230 may control the bit lines connected to the memory cells determined to be erased as a result of the erase verification operation to be in a floating state. The page buffer group 230 may generate and output the sensing voltage VPB according to the result of the erase verification operation.

[0043] The column decoder 240 may transfer data between the input / output circuit 250 and the page buffer group 230 in response to the column address CADD. For example, the column decoder 240 may exchange data with the page buffer 231 through the data line DL, or may exchange data with the input / output circuit 250 through the column line CL.

[0044] The input / output circuit 250 can be Figure 1 The memory controller 1200 transmits the received command CMD and address ADD to the control logic 300 , or may exchange data DATA with the column decoder 240 .

[0045] During a read operation or a verification operation, the pass / fail determiner 260 may generate a reference current in response to the enable bit VRY_BIT<#>, compare the sensing voltage VPB received from the page buffer group 230 with a reference voltage generated by the reference current, and output a pass signal PASS or a fail signal FAIL.

[0046] The source line driver 270 may be connected to the memory cells included in the memory cell array 100 through the source lines SL and may control the voltage applied to the source lines SL. For example, during an erase operation, the source line driver 270 may generate a first erase voltage and apply the first erase voltage to the source lines of the memory cell array 100.

[0047] The source line driver 270 may receive a source line control signal CTRL_SL from the control logic 300 and control a source line voltage applied to the source line SL based on the source line control signal CTRL_SL.

[0048] The control logic 300 may output an operation signal OP_CMD, a decoder control signal AD_signals, a page buffer control signal PBSIGNALS, and an enable bit VRY_BIT<#> in response to a command CMD and an address ADD to control the peripheral circuit 200. In addition, the control logic 300 may determine whether a verification operation passes or fails in response to a pass signal PASS or a fail signal FAIL.

[0049] Figure 3 It is shown Figure 2 Figure 2 shows a representative storage block of .

[0050] Reference Figure 3 , the memory block 110 may be connected to a plurality of word lines arranged in parallel with each other between a first selection line and a second selection line. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL. More specifically, the memory block 110 may include a plurality of strings ST connected between the bit lines BL1 to BLn and the source line SL. The bit lines BL1 to BLn may be connected to the strings ST, respectively, and the source line SL may be connected to the strings ST in common. Since the respective strings ST may be configured identically, the string ST connected to the first bit line BL1 is specifically described as an example.

[0051] The string ST may include a source selection transistor SST, a plurality of memory cells F1 to F16, and a drain selection transistor DST connected in series between a source line SL and a first bit line BL1. One string ST may include one or more of the source selection transistor SST and the drain selection transistor DST, and may include more than the 16 memory cells F1 to F16 shown in the figure.

[0052] The source of the source select transistor SST may be connected to the source line SL, and the drain of the drain select transistor DST may be connected to the first bit line BL1. The memory cells F1 to F16 may be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors SST included in different strings ST may be connected to the source select line SSL, the gates of the drain select transistors DST may be connected to the drain select line DSL, and the gates of the memory cells F1 to F16 may be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST may be referred to as a page PPG. Therefore, the memory block 11 may include the same number of page PPGs as the word lines WL1 to WL16.

[0053] One memory cell can store 1 bit of data. This is generally referred to as a single-level cell (SLC). In this case, one physical page PPG can store one logical page (LPG) of data. One logical page (LPG) of data can include the same number of data bits as the cells included in one physical page PPG. In addition, one memory cell can store two or more bits of data. This is generally referred to as a multi-level cell (MLC). In this case, one physical page PPG can store two or more logical pages (LPG) of data.

[0054] Figure 4 is a diagram showing an embodiment of a three-dimensionally arranged memory block.

[0055] Reference Figure 4 , the memory cell array 10 may include a plurality of memory blocks 110 (MB1 to MBk). Each memory block 110 may include a plurality of strings ST11 to ST1n and ST21 to ST2n. In an embodiment, each of the plurality of strings ST11 to ST1n and ST21 to ST2n may be formed in a "U" shape. In the first memory block MB1, n strings may be arranged in a row direction (X direction). Figure 4 In FIG. 1 , two strings are arranged in the column direction (Y direction), but this is for clarity; three or more strings may be arranged in the column direction (Y direction).

[0056] Each of the plurality of strings ST11 to ST1n and ST21 to ST2n may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0057] The source selection transistor SST, the drain selection transistor DST, and the memory cells MC1 to MCn may have similar structures. For example, each of the source selection transistor SST, the drain selection transistor DST, and the memory cells MC1 to MCn may include a channel film, a tunnel insulating film, a charge capture film, and a blocking insulating film. For example, a column for providing a channel film may be provided in each string. For example, a column for providing at least one of a channel film, a tunnel insulating film, a charge capture film, and a blocking insulating film may be provided in each string.

[0058] A source selection transistor SST of each string may be connected between a source line SL and the memory cells MC1 to MCp.

[0059] In an embodiment, source selection transistors of strings arranged in the same row may be connected to a source selection line extending in a row direction, and source selection transistors of strings arranged in different rows may be connected to different source selection lines. Figure 4 , source selection transistors of strings ST11 to ST1n of a first row may be connected to a first source selection line SSL1. Source selection transistors of strings ST21 to ST2n of a second row may be connected to a second source selection line SSL2.

[0060] In another embodiment, the source selection transistors of the strings ST11 to ST1n and ST21 to ST2n may be commonly connected to one source selection line.

[0061] The first to nth memory cells MC1 to MCn of each string may be connected between a source select transistor SST and a drain select transistor DST.

[0062] The first to nth memory cells MC1 to MCn may be divided into the first to pth memory cells MC1 and the (p+1)th memory cells MCp+1 to the nth memory cells MCn. The first to pth memory cells MC1 to MCp may be sequentially arranged in the vertical direction (Z direction) and may be connected in series between the source selection transistor SST and the tube transistor PT. The (p+1)th memory cells MCp+1 to the nth memory cells MCn may be sequentially arranged in the vertical direction (Z direction) and may be connected in series between the tube transistor PT and the drain selection transistor DST. The first to pth memory cells MC1 and the (p+1)th memory cells MCp+1 to the nth memory cells MCn may be connected to each other through the tube transistor PT. The gates of the first to nth memory cells MC1 to MCn of each string may be connected to the first to nth word lines WL1 to WLn, respectively.

[0063] In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, a voltage or current of a corresponding string may be stably controlled. The gate of the tube transistor PT of each string may be connected to the pipeline PL.

[0064] The drain selection transistors DST of each string may be connected between the bit line and the memory cells MCp+1 to MCn. The strings arranged in the row direction may be connected to the drain selection lines extending in the row direction. The drain selection transistors of the strings ST11 to ST1n of the first row may be connected to the first drain selection line DSL1. The drain selection transistors of the strings ST21 to ST2n of the second row may be connected to the second drain selection line DSL2.

[0065] The strings arranged in the column direction may be connected to the bit lines extending in the column direction. Figure 4 , the strings ST11 and ST21 of the first column may be connected to the first bit line BL1. The strings ST1n and ST2n of the nth column may be connected to the nth bit line BLn.

[0066] Among the strings arranged in the row direction, memory cells connected to the same word line may configure one page. For example, memory cells connected to the first word line WL1 among the strings ST11 to ST1n of the first row may configure one page.

[0067] Memory cells connected to the first word line WL1 among the strings ST21 to ST2n of the second row may configure another page. Strings arranged in a row direction are selected by selecting any one of the drain selection lines DSL1 and DSL2. One page of the selected string is selected by selecting any one of the word lines WL1 to WLn.

[0068] Figure 5 FIG. 1 is a diagram showing another embodiment of a three-dimensionally arranged memory block.

[0069] Reference Figure 5 , the memory cell array 100 may include a plurality of memory blocks 110 (MB1 to MBk). A representative memory block 110 may include a plurality of strings ST11' to ST1n' and ST21' to ST2n'. Each of the plurality of strings ST11' to ST1n' and ST21' to ST2n' may extend along a vertical direction (Z direction). In the memory block 110, n strings may be arranged in a row direction (X direction). Figure 5 In FIG. 1 , two strings are arranged in the column direction (Y direction), but this is for clarity; three or more strings may be arranged in the column direction (Y direction).

[0070] Each of the plurality of strings ST11 ′ to ST1n ′ and ST21 ′ to ST2n ′ may include at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

[0071] The source select transistors SST of each string may be connected between the source line SL and the memory cells MC1 to MCn. The source select transistors of the strings arranged in the same row may be connected to the same source select line. The source select transistors of the strings ST11' to ST1n' arranged in the first row may be connected to the first source select line SSL1. The source select transistors of the strings ST21' to ST2n' arranged in the second row may be connected to the second source select line SSL2. In another embodiment, the source select transistors of the strings ST11' to ST1n' and ST21' to ST2n' may be connected together to one source select line.

[0072] First to nth memory cells MC1 to MCn of each string may be connected in series to each other between source select transistors SST and drain select transistors DST. Gates of first to nth memory cells MC1 to MCn may be connected to first to nth word lines WL1 to WLn, respectively.

[0073] In an embodiment, at least one of the first to nth memory cells MC1 to MCn may be used as a dummy memory cell. When a dummy memory cell is provided, a voltage or current of a corresponding string may be stably controlled. Therefore, the reliability of data stored in the memory block 110 may be improved.

[0074] The drain selection transistors DST of each string may be connected between the bit line and the memory cells MC1 to MCn. The drain selection transistors DST of the strings arranged in the row direction may be connected to the drain selection lines extending in the row direction. The drain selection transistors DST of the strings ST11' to ST1n' of the first row may be connected to the first drain selection line DSL1. The drain selection transistors DST of the strings ST21' to ST2n' of the second row may be connected to the second drain selection line DSL2.

[0075] That is, in addition to excluding the tube transistor PT from each string, Figure 5 The memory block 110 may have Figure 4 An equivalent circuit similar to the storage block 110 is shown in FIG.

[0076] Reference Figure 4 and Figure 5 The described plurality of memory blocks MB1 to MBk may share a source line SL.

[0077] Figure 6 It is shown Figure 2 Diagram of the page buffer.

[0078] Figure 2 Each of the page buffers PB1 to PBn may be configured identically. Therefore, the page buffer PB1 is described as an example.

[0079] Reference Figure 6 , the page buffer PB1 may include an erase voltage controller 231A and a bit line sensor 232B.

[0080] The erase voltage controller 231A may be connected to the bit line BL1 and may apply a first erase voltage to the bit line BL1 during a first erase operation in an erase operation. In addition, during a second erase operation performed after the first erase operation, the erase voltage controller 231A may apply a first erase voltage or a second erase voltage to the bit line BL1 in response to a verification signal (verify_signal) output from the bit line sensor 232B. For example, during the second erase operation, the erase voltage controller 231A may apply a second erase voltage to the bit line BL1 in response to a verification signal of a first logic level indicating an erase pass as a result of the erase verification operation, or apply a first erase voltage to the bit line BL1 in response to a verification signal of a second logic level indicating an erase fail as a result of the erase verification operation. In another embodiment, during the second erase operation, the erase voltage controller 231A may control the bit line BL1 to a floating state in response to a verification signal of a first logic level indicating an erase pass as a result of the erase verification operation.

[0081] The bit line sensor 232B may be initialized before the first erase operation, and generate and output a verification signal of a second logic level during the first erase operation. The bit line sensor 232B may perform an erase verification operation by sensing a voltage or current amount of the bit line BL1 after the first erase operation and the second erase operation. In addition, the bit line sensor 232B may generate and output a verification signal based on a result of the erase verification operation. For example, the bit line sensor 232B may verify whether a memory cell included in a string corresponding to the bit line BL1 is erased at a threshold voltage equal to or less than a target level by sensing a voltage or current amount of the bit line BL1 during the erase verification operation. When all memory cells included in the string corresponding to the bit line BL1 are erased at a threshold voltage equal to or less than a target level, the bit line sensor 232B may determine that an erase operation (erase pass) of the memory cell has passed and generate and output a verification signal of a first logic level. Additionally, when one or more memory cells included in the string corresponding to the bit line BL1 have a threshold voltage greater than a target level, the bit line sensor 232B may determine that an erase operation of the memory cells has failed (erase fail) and generate and output a verification signal of a second logic level.

[0082] Figure 7is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0083] Figure 8 is a diagram illustrating a first erase voltage and a second erase voltage applied to a source line and a bit line during an erase operation according to an embodiment of the present disclosure.

[0084] Reference Figures 1 to 8 An operating method of a memory device according to an embodiment of the present disclosure is described as follows.

[0085] In operation S710, the memory controller 1200 generates an erase command CMD in response to an erase request from the host 2000, and transmits the generated erase command CMD to the memory device 1100. The memory controller 1200 transmits an address ADD corresponding to a memory block (e.g., MB1) for performing an erase operation to the memory device 1100 together with the erase command CMD.

[0086] In operation S720 , the memory device 1100 performs a first erase operation of the selected memory block MB1 in response to an erase command CMD and an address ADD, and applies a first erase voltage Vera1 to a source line SL and bit lines BL1 to BLn of the selected memory block MB1 during the first erase operation.

[0087] For example, during the first erase operation, the source line driver 270 applies the first erase voltage Vera 1 to the source line SL connected to the selected memory block MB1 based on the source line control signal CTRL_SL generated by the control logic 300. During the first erase operation, the page buffer group 230 applies the first erase voltage Vera 1 to the bit lines BL1 to BLn connected to the selected memory block MB1. For example, during the first erase operation, the bit line sensor 232B of each of the page buffers PB1 to PBn is initialized and generates and outputs a verification signal of a second logic level. During the first erase operation, the erase voltage controller 231A of each of the page buffers PB1 to PBn applies the first erase voltage Vera 1 to the corresponding bit lines BL1 to BLn in response to the verification signal of the second logic level. During the first erase operation, the row decoder 220 applies a cutoff voltage (e.g., 0V) to the drain selection lines DSL1 and DSL2 and the source selection lines SSL1 and SSL2 of the selected memory block MB1. Therefore, a GIDL current is generated in the lower channel of the drain select transistor DST and the source select transistor SST included in the selected memory block MB1. The row decoder 220 applies an erase operation voltage (e.g., 0V) to the word lines WL1 to WLn of the selected memory block MB1. Therefore, the GIDL current generated in the lower channel of the drain select transistor DST and the source select transistor SST flows into the channel of the selected memory block MB1, and the electrons stored in the charge storage layer of the memory cells MC1 to MCn are released by the potential difference between the channel and the gate of the memory cells MC1 to MCn. Therefore, the threshold voltage of the memory cells MC1 to MCn drops.

[0088] In operation S730 , the memory device 1100 performs an erase verification operation on the selected memory block MB1 .

[0089] During the erase verification operation, the voltage generation circuit 210 generates and outputs the verification voltage, and the row decoder 220 applies the verification voltage to the word lines WL1 to WLn of the selected memory block MB1. The page buffers PB1 to PBn of the page buffer group 230 sense the voltage or current of the bit lines BL1 to BLn. For example, the bit line sensor 232B of each of the page buffers PB1 to PBn senses the voltage or current of the corresponding bit line to determine the erase pass or erase fail for the string ST corresponding to the bit line. For example, when the threshold voltage of at least one of the multiple memory cells MC1 to MCn included in the string ST is greater than the target threshold voltage, the erase fail is determined, and when the threshold voltage of all the multiple memory cells MC1 to MCn included in the string ST is equal to or less than the target threshold voltage, the erase pass is determined. That is, during the erase verification operation, each of the page buffers PB1 to PBn can determine the erase pass or erase fail of the corresponding string ST.

[0090] In operation S740, the control logic 300 determines the result of the erase verification operation. For example, the page buffer group 230 may generate and output a sensing voltage VPB according to the result of the erase verification operation, and the pass / fail determiner 260 may compare the sensing voltage VPB received from the page buffer group 230 with a reference voltage generated by a reference current to output a pass signal PASS or a fail signal FAIL. For example, during the erase verification operation, when all strings ST in the selected memory block MB1 are determined to be erase passed, the control logic 300 may determine the selected memory block MB1 as erase passed, and when at least one string among the strings ST in the selected memory block MB1 is determined to be erase failed, the control logic 300 may determine the selected memory block MB1 as erase failed.

[0091] As a result of the erase verification operation of S740 , when the selected memory block MB1 is determined to be erase passed (PASS), the erase operation ends.

[0092] As a result of the erase verification operation of S740, when at least one string among the strings ST included in the selected memory block MB1 is determined to fail to erase, and the selected memory block MB1 is thus determined to fail to erase (fail), the memory device 1100 performs a second erase operation of the memory block MB1. During the second erase operation, the memory device 1100 applies a first erase voltage Vera 1 to the source line SL of the selected memory block MB1, applies a second erase voltage Vera 2 lower than the first erase voltage Vera 1 to a bit line corresponding to the erased string ST among the bit lines BL1 to BLn, and applies the first erase voltage Vera 1 to a bit line corresponding to the erased string ST among the bit lines BL1 to BLn. The second erase voltage Vera 2 may be equal to or less than 5V.

[0093] For example, during the second erase operation, the source line driver 270 applies the first erase voltage Vera 1 to the source line SL connected to the selected memory block MB1 based on the source line control signal CTRL_SL generated by the control logic 300. During the second erase operation, the page buffer group 230 applies the first erase voltage Vera 1 or the second erase voltage Vera 2 to the bit lines BL1 to BLn connected to the selected memory block MB1. For example, the bit line sensor 232B of each of the page buffers PB1 to PBn generates and outputs a verification signal of a first logic level or a second logic level according to a result of an erase verification operation immediately before the second erase operation, and the erase voltage controller 231A of each of the page buffers PB1 to PBn applies the first erase voltage Vera 1 or the second erase voltage Vera 2 to the corresponding bit lines BL1 to BLn in response to the verification signal. For example, when the corresponding string ST is determined to be erased as a result of the erase verification operation, during the second erase operation, the bit line sensor 232B generates and outputs a verification signal of a first logic level, and the erase voltage controller 231A applies the second erase voltage Vera 2 to the corresponding bit line in response to the verification signal of the first logic level. When the corresponding string ST is determined to be erased failed as a result of the erase verification operation, during the second erase operation, the bit line sensor 232B generates and outputs a verification signal of a second logic level, and the erase voltage controller 231A applies the first erase voltage Vera 1 to the corresponding bit line in response to the verification signal of the second logic level.

[0094] During the second erase operation, the row decoder 220 applies a cutoff voltage (e.g., 0V) to the drain select lines DSL1 and DSL2 and the source select lines SSL1 and SSL2 of the selected memory block MB1. Therefore, a GIDL current is generated in the lower channel of the drain select transistor DST and the source select transistor SST included in the selected memory block MB1. The first erase voltage Vera 1 is applied to the bit line of the string ST that failed to erase to generate a GIDL current amount similar to the first erase operation, and the second erase voltage Vera 2 is applied to the bit line of the string ST that passed the erase, so the generated GIDL current amount is relatively small compared to the string ST to which the first erase voltage Vera 1 is applied. The row decoder 220 applies an erase operation voltage (e.g., 0V) to the word lines WL1 to WLn of the selected memory block MB1. Therefore, the GIDL current generated in the lower channel of the drain selection transistor DST and the source selection transistor SST flows into the channel of the selected memory block MB1, and the electrons stored in the charge storage layer of the memory cells MC1 to MCn are released by the potential difference between the channel and the gate of the memory cells MC1 to MCn. Therefore, the threshold voltage of the memory cells MC1 to MCn decreases. Compared with the string ST where the erase fails, a relatively small GIDL current flows into the channel of the string ST where the erase is passed, so the threshold voltage of the memory cells MC1 to MCn included in the string ST where the erase is passed decreases less than the threshold voltage of the memory cells MC1 to MCn included in the string ST where the erase fails. Therefore, the phenomenon of over-erasing the memory cells of the string ST determined as the erase pass as a result of the first erase operation during the second erase operation can be suppressed.

[0095] After performing the above-mentioned second erasing operation, the above-mentioned erasing verification operation (S730) and subsequent operations are performed again.

[0096] In the above-described embodiment of the present disclosure, during the second erase operation, the second erase voltage is applied to the bit line of the string determined to be erased, but in another embodiment, during the second erase operation, the bit line of the string determined to be erased may be controlled to float.

[0097] Fig. 9 It is shown that Figure 2 A diagram of another embodiment of a memory system of a memory device is shown.

[0098] Reference Fig. 9, the memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device. The memory system 30000 may include a memory device 1100 and a memory controller 1200 capable of controlling the operation of the memory device 1100. The memory controller 1200 may control a data access operation (e.g., a program operation, an erase operation, or a read operation) of the memory device 1100 under the control of the processor 3100.

[0099] Data programmed in the memory device 1100 may be output through the display 3200 under the control of the memory controller 1200 .

[0100] The radio transceiver 3300 can send and receive radio signals through the antenna ANT. For example, the radio transceiver 3300 can convert the radio signal received through the antenna ANT into a signal that can be processed by the processor 3100. Therefore, the processor 3100 can process the signal output from the radio transceiver 3300 and send the processed signal to the storage controller 1200 or the display 3200. The storage controller 1200 can program the signal processed by the processor 3100 to the memory device 1100. In addition, the radio transceiver 3300 can convert the signal output from the processor 3100 into a radio signal and output the radio signal to an external device through the antenna ANT. The input device 3400 can be a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be implemented as a pointing device, a keypad or a keyboard such as a touch pad or a computer mouse. The processor 3100 may control the operation of the display 3200 so that data output from the memory controller 1200 , data output from the radio transceiver 3300 , or data output from the input device 3400 is output through the display 3200 .

[0101] According to an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 3100 , or may also be implemented as a chip separate from the processor 3100 .

[0102] Fig.10 It is shown that Figure 2 A diagram of another embodiment of a memory system of a memory device is shown.

[0103] Reference Fig.10 , the memory system 40000 may be implemented as a personal computer (PC), a tablet PC, a netbook, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

[0104] The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation of the memory device 1100 .

[0105] The processor 4100 may output data stored in the memory device 1100 through the display 4300 according to data input through the input device 4200. For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

[0106] The processor 4100 may control the overall operation of the memory system 40000 and control the operation of the memory controller 1200. According to an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100 or may be implemented as a chip separate from the processor 4100.

[0107] Fig.11 It is shown that Figure 2 A diagram of another embodiment of a memory system of a memory device is shown.

[0108] Reference Fig.11 , the memory system 50000 may be implemented as an image processing device, such as a digital camera, a portable phone provided with a digital camera, a smart phone provided with a digital camera, or a tablet PC provided with a digital camera.

[0109] The memory system 50000 includes a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation (eg, a program operation, an erase operation, or a read operation) of the memory device 1100 .

[0110] The image sensor 5200 of the memory system 50000 may convert an optical image into a digital signal. The digital signal may be transmitted to the processor 5100 or the memory controller 1200. Under the control of the processor 5100, the digital signal may be output through the display 5300 or stored in the memory device 1100 through the memory controller 1200. In addition, the data stored in the memory device 1100 may be output through the display 5300 under the control of the processor 5100 or the memory controller 1200.

[0111] According to an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 5100 , or may be implemented as a chip separate from the processor 5100 .

[0112] Fig.12 It is shown that Figure 2 A diagram of another embodiment of a memory system of a memory device is shown.

[0113] Reference Fig.12 The memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a memory controller 1200 , and a card interface 7100 .

[0114] The memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100. According to an embodiment, the card interface 7100 may be a secure digital (SD) card interface or a multimedia card (MMC) interface, but is not limited thereto.

[0115] The card interface 7100 may interface data exchange between the host 60000 and the storage controller 1200 according to a protocol of the host 60000. According to an embodiment, the card interface 7100 may support a universal serial bus (USB) protocol and an inter-chip (IC)-USB protocol. Here, the card interface may refer to hardware capable of supporting a protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

[0116] When the memory system 70000 is connected to the host interface 6200 of the host 60000 (e.g., a PC, a tablet PC, a digital camera, a digital audio player, a mobile phone, a console video game hardware, or a digital set-top box), the host interface 6200 can perform data communication with the memory device 1100 through the card interface 7100 and the storage controller 1200 under the control of the microprocessor 6100.

[0117] Although specific embodiments are shown and described, various modifications may be made without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present invention is not limited to the above-described embodiments. On the contrary, the present invention covers all modifications and changes that fall within the scope of the claims.

[0118] CROSS-REFERENCE TO RELATED APPLICATIONS

[0119] This application claims priority to Korean Patent Application No. 10-2020-0064487, filed on May 28, 2020, which is hereby incorporated by reference in its entirety.

Claims

1. A memory device, the memory device comprising: A storage block, the storage block comprising a plurality of strings; a peripheral circuit configured to perform an erase operation including a first erase operation, an erase verification operation, and a second erase operation on the memory block; as well as a control logic configured to control the peripheral circuit to perform the erase operation, wherein, during the second erasing operation, the control logic controls the peripheral circuit to apply a first erasing voltage to a source line of the memory block and float a bit line connected to a string determined to be erased among the plurality of strings, and During each of the first erase operation and the second erase operation, a cutoff voltage is applied to a drain select line and a source select line of the memory block.

2. The memory device according to claim 1, wherein: The control logic controls the peripheral circuit to perform the erase verification operation after the first erase operation and to perform the second erase operation when it is determined that the erase verification operation fails.

3. The memory device according to claim 1, wherein: The control logic controls the peripheral circuit to apply the first erase voltage to the source line of the memory block and the bit line of the memory block during the first erase operation.

4. The memory device according to claim 1, wherein: The peripheral circuit comprises: a source line driver configured to apply the first erase voltage to the source line under the control of the control logic; and A page buffer is configured to apply the first erase voltage to the bit lines connected to the plurality of strings or float the bit lines connected to the plurality of strings under the control of the control logic.

5. The memory device according to claim 4, in, Each of the page buffers is connected to a corresponding bit line among the plurality of bit lines, and Wherein, each of the page buffers comprises: an erase voltage controller configured to apply the first erase voltage to the corresponding bit line or float the corresponding bit line in response to a verification signal; and A bit line sensor is configured to sense a potential or a current amount of the corresponding bit line through the corresponding bit line during the erase verification operation and generate the verification signal according to a sensing result.

6. The memory device according to claim 5, wherein: The bit line sensor generates the verification signal of a first logic level when the corresponding string is determined to be erase pass as the sensing result, and generates the verification signal of a second logic level when the corresponding string is determined to be erase fail.

7. The memory device according to claim 6, wherein: During the first erase operation, the bit line sensor generates the verification signal of the second logic level.

8. The memory device according to claim 6, wherein: During the second erase operation, the erase voltage controller floats the corresponding bit line in response to the verification signal of the first logic level, or applies the first erase voltage to the corresponding bit line in response to the verification signal of the second logic level.

9. The memory device according to claim 1, wherein: The control logic controls the peripheral circuit to end the erase operation of the memory block when all of the plurality of strings are determined to be erase passed during the erase verification operation, and to perform the second erase operation when at least one of the plurality of strings is determined to be erase failed.

10. A method of operating a memory device, the method comprising the steps of: performing a first erase operation of applying a first erase voltage to a bit line and a source line of a selected memory block; determining whether each of a plurality of strings included in the selected memory block is erased by performing an erase verification operation; as well as When at least one string among the plurality of strings is determined to have failed erasure as a result of the erase verification operation, performing a second erase operation of applying the first erase voltage to the source line and floating a bit line of the string determined to have passed erasure, During each of the first erase operation and the second erase operation, a cutoff voltage is applied to a drain select line and a source select line of the selected memory block.

11. The method according to claim 10, wherein: During the second erase operation, the first erase voltage is applied to a bit line of a string determined to have failed erase among the plurality of strings.

12. A method of operating a memory device, the method comprising the steps of: performing a first erase operation of applying an erase voltage to a bit line and a source line of a selected memory block; determining whether each of a plurality of strings included in the selected memory block is erased by performing an erase verification operation; as well as When at least one string among the plurality of strings is determined to have failed erasure as a result of the erase verification operation, performing a second erase operation of applying the erase voltage to the source line, floating a bit line of the string determined to have passed erasure, and applying the erase voltage to a bit line of the string determined to have failed erasure, During each of the first erase operation and the second erase operation, a cutoff voltage is applied to a drain select line and a source select line of the selected memory block.

13. A memory device, the memory device comprising: a memory block comprising a first string and a second string of memory cells; a control circuit configured to perform a current erase operation on the memory block when the first string is verified as successful and the second string is verified as failed as a result of a previous erase operation, wherein, during the current erase operation, the control circuit applies a first erase voltage to the bit line of the second string and the source line of the memory block and floats the bit line of the first string, and Wherein, during each of the current erase operation and the previous erase operation, a cutoff voltage is applied to a drain select line and a source select line of the memory block.

14. A memory device, the memory device comprising: a memory block comprising a first string and a second string of memory cells; a control circuit configured to perform a current erase operation on the memory block when the first string is determined to have succeeded and the second string is determined to have failed as a result of a previous erase operation, wherein, during the current erase operation, the control circuit applies an erase voltage to the bit line of the second string and the source line of the memory block and floats the bit line of the first string, and Wherein, during each of the current erase operation and the previous erase operation, a cutoff voltage is applied to a drain select line and a source select line of the memory block.

Images