Method for producing an integrated thermoelectric converter and the integrated thermoelectric converter obtained thereby

Abstract

Embodiments of the present disclosure relate to methods for making integrated thermoelectric converters and the integrated thermoelectric converters obtained thereby. One method includes: providing a silicon-based material layer having a first surface and a second surface opposite the first surface and separated from the first surface by a thickness of the silicon-based material layer; forming a plurality of first thermoelectric active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectric active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, the first and second thermoelectric active elements being formed to extend from the first surface through the thickness of the silicon-based material layer to the second surface; forming conductive interconnects corresponding to the first and second surfaces of the silicon-based material layer, and forming input electrical terminals and output electrical terminals electrically connected to the conductive interconnects, the first and second thermoelectric semiconductor materials comprising a silicon-based material selected from porous silicon, polycrystalline SiGe, or polycrystalline silicon.

Description

Technical Field

[0001] The present disclosure relates generally to the field of solid-state technology, particularly semiconductor technology and devices, and more particularly to a solid-state integrated thermoelectric converter and method of making the same, such as a thermoelectric generator (also known as a "TEG"). Background Art

[0002] The direct conversion of thermal energy into electrical energy (and vice versa) via the Seebeck effect is a promising method for harvesting energy from thermal sources, particularly when reduced temperature gradients are involved and when these are not otherwise utilized (such as waste heat from industrial plants, residual heat from automobile engines, low-temperature heat sources).

[0003] Thermoelectric generators are low-enthalpy waste heat utilization devices used, for example, in battery-free radiator valve actuators or flashlights (in the latter case, utilizing the temperature difference between human body temperature and ambient temperature).

[0004] Thermoelectric generators utilize thermoelectric materials that are able to generate electricity directly from heat by converting temperature differences into voltage.

[0005] A good thermoelectric material should have both high electrical conductivity (σ) and low thermal conductivity (κ). Having low thermal conductivity ensures that when one side of the material gets hot, the other side remains cold, which helps generate significant voltage even under very low temperature gradients.

[0006] Tellurium-based thermoelectric generators utilize tellurium-based materials as thermoelectric materials.

[0007] Tellurium compounds, such as bismuth telluride (Bi2Te3), exhibit a good Seebeck coefficient (the Seebeck coefficient of a material (also known as thermal power, thermoelectric power, or thermoelectric sensitivity, which is a measure of the magnitude of the thermoelectric voltage induced in response to a temperature difference across the material caused by the Seebeck effect), high electrical conductivity, and low thermal conductivity (by way of example only, the thermal conductivity of bismuth telluride is 2 W / mK). These properties make bismuth telluride suitable for use in forming "thermoelectric active elements" of thermoelectric generators (by "thermoelectric active element" or "active element" is meant a thermoelectric element in a thermoelectric material that is capable of converting a temperature drop or temperature gradient across it into an electrical potential by the Seebeck effect).

[0008] Tellurium-based thermoelectric generators include multiple interconnected n-doped bismuth telluride active elements and p-doped bismuth telluride active elements (these active elements are also called "legs") between a pair of opposing ceramic substrates provided with metal (Cu or Au) contact areas and conductive wires. These active elements interconnect the multiple n-doped and p-doped bismuth telluride active elements. The n-doped bismuth telluride active elements are typically formed as discrete components using a process that involves forming an ingot from powdered material, then slicing the ingot to form a pellet, which is then placed (in a manual or semi-automated assembly stage) between two ceramic substrates to form a Seebeck leg.

[0009] Therefore, existing tellurium-based thermoelectric generators are discrete components. Bismuth telluride is not suitable for use as a material in standard integrated circuit (IC) manufacturing processes, which are based on silicon.

[0010] Furthermore, tellurium-based thermoelectric generators typically exhibit relatively good efficiency only within a limited temperature range (typically, around 100K at room temperature), and their thermoelectric properties deteriorate rapidly as the temperature rises, which limits their application areas.

[0011] Additionally, tellurium is a relatively rare element, which inherently limits its widespread use.

[0012] Furthermore, the large-scale use of tellurium compounds, such as bismuth telluride, may raise environmental concerns, particularly with regard to the disposal of end-of-life equipment.

[0013] In silicon-based thermoelectric generators, silicon-based materials (n-doped and p-doped to exhibit different Seebeck coefficients) are used as thermoelectric materials to form the active elements.

[0014] Silicon-based thermoelectric generators (TEGs) fabricated using compatible silicon technology can be categorized into two families: in the first family of devices, the heat flow is parallel to the substrate, while in the other family, the heat flow is orthogonal to the substrate ("out-of-plane" heat flux). The architecture of these integrated TEGs typically consists of multiple units with np-doped legs, arranged in such a way that the units are thermally connected in parallel and electrically connected in series. Typically, TEGs with heat flow parallel to the substrate can have the conductive legs of the thermoelectrically active material deposited on a very high thermal resistance material or membrane (suspended a few hundred microns above the substrate), or the active material legs themselves are freestanding (no membrane).

[0015] Out-of-plane heat flux thermoelectric generators minimize heat losses, simplify system-level thermal coupling, enhance overall performance, and are suitable for miniaturization and integration in microelectronics and optoelectronic devices, among other applications.

[0016] In their paper, "10μW / cm2-Class High Power Density Planar Si-Nanowire Thermoelectric Energy Harvester Compatible with CMOS-VLSI Technology," presented at the 38th IEEE Symposium on VLSI Technology 2018, held in Honolulu, USA, from June 18 to 22, 2018, M. Tomita et al. criticized planar silicon-based thermoelectric generators (TEGs) that use silicon nanowires (SiNWs) about 10 to 100 μm long as active elements. These SiNWs are suspended from a cavity to cut off thermal current bypass and maintain a temperature difference across the SiNWs. The authors proposed a design concept for a planar short SiNW TEG without a cavity structure, but instead exploit the steep temperature gradient formed near the main thermal current source.

[0017] WO 2018 / 078515 discloses an integrated thermoelectric generator in an out-of-plane heat flux configuration. The generator further includes a top capping layer deposited on a free surface of the planar non-conductive cover layer oriented in an opposite direction relative to the void space so as to cover the through-holes of the non-conductive cover layer. Summary of the Invention

[0018] The Applicant has recognized that the silicon-based thermoelectric generators proposed in the art exhibit disadvantages.

[0019] Silicon has a high electrical conductivity and a good Seebeck coefficient, but as a thermoelectric material, it has the disadvantage of having a higher thermal conductivity (148 W / mK) than bismuth telluride (2 W / mK). In addition, silicon-based thermoelectric generators with cavities have very low mechanical stability due to the presence of the cavity. Other disadvantages of known silicon-based thermoelectric generators include: difficulty in industrialization; low power (~100 μW / cm 2 ); and high semiconductor area consumption.

[0020] The Applicant has addressed the problem of designing a novel thermoelectric converter which overcomes the drawbacks affecting known thermoelectric generators.

[0021] The applicant has discovered that the active elements of thermoelectric converters can be realized in alternative materials (other than bismuth telluride and silicon known in the art) that are good thermoelectric materials and amenable to standard IC fabrication techniques, thereby enabling the fabrication of integrated thermoelectric converters.

[0022] The applicant has found that an alternative good thermoelectric material suitable for realizing the active elements of an integrated thermoelectric converter is porous silicon, for example n-doped or p-doped.

[0023] N-doped and p-doped porous silicon thermoelectric active elements can be made by converting n + and p + Porous silicon advantageously has a low thermal conductivity (0.15 to 1.5 W / mK at a porosity of approximately 75%).

[0024] The present applicant has also found that another suitable alternative good thermoelectric material for realizing the active element of the integrated thermoelectric converter is polycrystalline silicon germanium (polycrystalline SiGe), for example, n-doped or p-doped. Polycrystalline SiGe has a thermal conductivity of 3 to 5 W / mK, and the applicant uses it as the material for realizing the active element of the thermoelectric converter.

[0025] Another thermoelectric material for realizing active elements of integrated thermoelectric converters is polysilicon, for example n-doped and p-doped.

[0026] According to one aspect of the present disclosure, a method for fabricating an out-of-plane (e.g., having a heat flux normal to a substrate) thermoelectric converter includes:

[0027] Providing a silicon-based material layer having a first surface and a second surface opposite to the first surface and separated from the first surface by a thickness of the silicon-based material layer;

[0028] forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first thermoelectrically active elements and the second thermoelectrically active elements are formed to extend through the thickness of the silicon-based material layer from the first surface to the second surface;

[0029] forming conductive interconnects corresponding to the first and second surfaces of the silicon-based material layer to electrically interconnect the plurality of first thermoelectrically active elements and the plurality of second thermoelectrically active elements, and

[0030] Input electrical terminals and output electrical terminals are formed that are electrically connected to the conductive interconnects.

[0031] The first thermoelectric semiconductor material and the second thermoelectric semiconductor material include a silicon-based material selected from porous silicon or polycrystalline SiGe or polycrystalline silicon.

[0032] In an embodiment, the silicon-based material layer is poly SiGe (specifically poly Si 0.7 Ge 0.3 ) or epitaxial polysilicon.

[0033] In an embodiment, a plurality of first thermoelectric active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient include doped porous silicon or polycrystalline SiGe or polycrystalline silicon doped with acceptor dopants or donor dopants, and a plurality of second thermoelectric active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient include doped porous silicon or polycrystalline SiGe or polycrystalline silicon, each doped with a donor dopant or an acceptor dopant.

[0034] In an embodiment, providing the silicon-based material layer includes epitaxially growing a polysilicon layer on an oxidized surface of the substrate.

[0035] In an embodiment, forming a plurality of first thermoelectric active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient comprises:

[0036] forming a first trench in the silicon-based material layer; and

[0037] The first trench is filled with polysilicon or poly-SiGe doped with an acceptor or donor dopant.

[0038] In an embodiment, forming a plurality of second thermoelectric active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient comprises:

[0039] forming a second trench in the silicon-based material layer; and

[0040] The second trench is filled with polysilicon or poly-SiGe doped with a donor or acceptor dopant.

[0041] In an embodiment, the method may further include converting the doped polysilicon filling the first trench and the second trench into doped porous silicon.

[0042] In an embodiment, providing a silicon-based material layer comprises:

[0043] Iterate the following steps at least twice:

[0044] forming a polycrystalline SiGe layer on the oxidized surface of the substrate, wherein the polycrystalline SiGe layer has a thickness that is a fraction of the thickness of the silicon-based material layer;

[0045] selectively doping the first region of the polycrystalline SiGe layer with an acceptor or donor dopant; and

[0046] selectively doping a second region of the polycrystalline SiGe layer with a donor or acceptor dopant,

[0047] Such that after said iterations, the stack of polycrystalline SiGe layers has an overall thickness corresponding to the thickness of said silicon-based material layer; and

[0048] Trenches are formed in the stack of respective polycrystalline SiGe layers to obtain separate portions of the doped first region and the doped second region.

[0049] According to another aspect of the present disclosure, an out-of-plane integrated thermoelectric converter is provided. The device comprises:

[0050] a silicon-based material layer having a first surface and a second surface opposite to the first surface and separated from the first surface by a thickness of the silicon-based material layer;

[0051] a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient and a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first thermoelectrically active elements and the second thermoelectrically active elements extend through the thickness of the silicon-based material layer from the first surface to the second surface;

[0052] conductive interconnects corresponding to the first surface and the second surface of the silicon-based material layer to electrically interconnect the plurality of first thermoelectrically active elements and the plurality of second thermoelectrically active elements, and

[0053] An input electrical terminal and an output electrical terminal are electrically connected to the conductive interconnect.

[0054] The first thermoelectric semiconductor material and the second thermoelectric semiconductor material include a silicon-based material selected from porous silicon, polycrystalline silicon, or polycrystalline SiGe.

[0055] In an embodiment, the silicon-based material layer is poly SiGe (specifically poly Si 0.7 Ge 0.3 ) or materials selected from epitaxial polysilicon.

[0056] In an embodiment, the first thermoelectric semiconductor material having a first Seebeck coefficient is porous silicon or polycrystalline silicon or polycrystalline SiGe doped with an acceptor dopant or a donor dopant, and the second thermoelectric semiconductor material having a second Seebeck coefficient is porous silicon or polycrystalline silicon or polycrystalline SiGe each doped with a donor dopant or an acceptor dopant.

[0057] In the examples:

[0058] Each of the plurality of first and second thermoelectrically active elements and each of the second thermoelectrically active elements has a first end at the first surface of the silicon-based material layer and a second end at the second surface, the conductive interconnect electrically connecting:

[0059] a first end of the first thermoelectrically active element to a first end of the second thermoelectrically active element in common; and

[0060] The second end of the common first thermoelectrically active element is connected to the second end of another second thermoelectrically active element, so that the plurality of first thermoelectrically active elements and the plurality of second thermoelectrically active elements are connected in series and alternate with each other.

[0061] According to still another aspect of the present disclosure, an electronic system including the thermoelectric converter according to the previous aspect is proposed.

[0062] The advantages of using this alternative material to form the active element of a thermoelectric converter are:

[0063] ease of industrialization;

[0064] The power level is about 1 mA (while the characteristic power level of conventional thermoelectric generator structures is about 100 μW / cm for a typical ΔT=10K) 2 );

[0065] Ability to operate at low or high ΔT;

[0066] No mechanical stability issues; and

[0067] Low area consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] These and other features and advantages of the present disclosure will become apparent from the following description of example embodiments provided by way of non-limiting examples only.

[0069] For better readability, the following description should be read with reference to the accompanying drawings, in which:

[0070] Figures 1A to 1G Some steps of a method for manufacturing a thermoelectric converter according to an exemplary embodiment of the present disclosure are shown;

[0071] Figures 2A to 2L Some steps of a method for manufacturing a thermoelectric converter according to an exemplary embodiment of the present disclosure are shown;

[0072] Figures 3A to 3I Some steps of a method for manufacturing a thermoelectric converter according to another exemplary embodiment of the present disclosure are shown;

[0073] Figures 4A to 4E In an exemplary embodiment of the present disclosure, Figures 2A to 2L or Figures 3A to 3I Some steps of the production method after the step (the same or similar process steps can also be Figures 1A to 1G after the steps);

[0074] Figure 4F Example steps for forming contact pads are shown;

[0075] Figure 5In a top plan view is shown a layout of a thermoelectric converter obtained by a method according to an example embodiment of the present disclosure, the method of the example embodiment comprising Figures 1A to 1G The steps shown are similar to Figures 4A to 4E Steps;

[0076] Figure 6 In a top plan view is shown a layout of a thermoelectric converter obtained by a method according to an embodiment of the present disclosure, the method of the example embodiment comprising Figures 2A to 2L or Figures 3A to 3I and Figures 4A to 4E The steps shown;

[0077] Figure 7 shows a simplified block diagram of an electronic system including a thermoelectric converter according to an embodiment of the present disclosure;

[0078] Figure 8 Shown is the use of after bonding the thermoelectric wafer and solar cell wafer Figure 4F Thermoelectric converters for solar energy recovery along with Figure 9A and 9B A cross section taken along section line VIII-VIII;

[0079] Figure 9A yes Figure 8 A top plan view of the thermoelectric wafer before bonding;

[0080] Figure 9B yes Figure 8 A bottom plan view of a solar cell wafer before bonding;

[0081] Figure 10 In another manufacturing step Figure 8 Cross-section of a solar energy recycling device;

[0082] Figure 11 In another manufacturing step Figure 10 Along with the solar recycling equipment Figure 12A and 12B A cross section taken along section line XI-XI;

[0083] Figure 12A yes Figure 11 A top plan view of a thermoelectric wafer;

[0084] Figure 12B yes Figure 11 A bottom plan view of a solar cell wafer;

[0085] Figure 13 It depicts Figure 11 Possible connection schemes of solar energy recovery equipment;

[0086] Figure 14 and 15 shows a cross section of another solar energy recovery device during different manufacturing steps;

[0087] Figure 16 is a cross section of different solar energy recycling equipment;

[0088] Figure 17 is a schematic representation of the system disclosed herein; and

[0089] Figure 18 is a cross-section of an example of a solar cell wafer that may be used in a solar energy recycling device according to the present disclosure.

[0090] It is noted that the drawings in the accompanying drawings are not necessarily drawn to scale. DETAILED DESCRIPTION

[0091] In the following, reference will be made to the accompanying drawings, which illustrate some steps of a method for manufacturing a thermoelectric converter according to an exemplary embodiment of the present disclosure. In the accompanying drawings, identical and / or corresponding elements are denoted by identical reference numerals.

[0092] First refer to Figures 1A to 1G , which shows some steps of a manufacturing method according to an example embodiment of the present disclosure.

[0093] Starting with a silicon substrate (first silicon wafer) 105, the surface of the silicon substrate 105 is oxidized (e.g., by thermal oxidation) to form an oxide layer 110, such as silicon dioxide (SiO2). Then, a polycrystalline SiGe layer 115 is formed on top of the oxide layer 110. The resulting structure is Figure 1A Schematically depicted in .

[0094] The polycrystalline SiGe layer 115 is, for example, polycrystalline Si 0.7 Ge 0.3 layer. The polycrystalline SiGe layer 115 can be formed, for example, by deposition, such as, but not limited to, chemical deposition, such as chemical vapor deposition (CVD); among a variety of different CVD techniques, low-pressure CVD (LPCVD) can be utilized. Deposition is performed from silane (SiH4) and germanium (GeH4). Alternatively, the SiGe polysilicon layer 115 can be formed by epitaxial growth in an epitaxial reactor. Both techniques produce a conformal polycrystalline SiGe layer 115.

[0095] The polycrystalline SiGe layer 115 may, for example, have a thickness of a few micrometers, for example approximately 1 μm.

[0096] Then, if Figure 1B and Figure 1CAs depicted, alternating n+ doped regions 120a and p+ doped regions 120b of n+ doped and p+ doped polycrystalline SiGe are each formed in the polycrystalline SiGe layer 115. Dopants (donor dopants for the n+ doped regions 120a and donor dopants for the p+ doped regions 120b) can be selectively introduced into the polycrystalline SiGe layer 115 by ion implantation. For example, suitable donor dopants can be phosphorus or arsenic, and suitable acceptor dopants can be boron. The n+ doped regions 120a and the p+ doped regions 120b can, for example, have the shape of substantially parallel strips formed in the polycrystalline SiGe layer 115 (where "parallel" is intended to be parallel to the strips extending along the same plane as ... Figure 1B and Figure 1C In a direction perpendicular to the drawing plane), the n+ doped regions 120a and the p+ doped regions 120b are alternated and, for example (but not limited to), continuous with each other (in a direction from left to right in the drawing).

[0097] The steps of forming a polycrystalline SiGe layer and forming an n+ doped region and a p+ doped region in the polycrystalline SiGe layer are repeated two or more times. Figure 1D As depicted, each new layer of poly-SiGe is formed on a previous layer of poly-SiGe (e.g., by the same technique as the first poly-SiGe layer 115), and in each newly formed poly-SiGe layer is aligned with the previously formed n+ doped regions 120a and p+ doped regions 120b formed in the previous poly-SiGe layer(s) (e.g., in the order of Figure 1D In this way, the stack 125a of n+ doped regions and the stack 125b of p+ doped regions are obtained, from which the thermoelectric elements of the thermoelectric converter will be formed. In this way, the stack 125a of n+ doped regions and the stack 125b of p+ doped regions take the form of substantially parallel strips formed by a stack of polycrystalline SiGe layers (wherein, again, "parallel" is intended to mean along the same direction as the stack of polycrystalline SiGe layers). Figure 1D In a direction orthogonal to the plane of the drawing), the stacks of n+ doped regions 125a and the stacks of p+ doped regions 125b alternate and are, for example (but not limited to), continuous with each other (in the direction from left to right along the drawing), as can be seen, for example, in 1E.

[0098] The number of times the steps of forming a polycrystalline SiGe layer and forming n+ and p+ doped regions in the polycrystalline SiGe layer are repeated depends on the thickness of each polycrystalline SiGe layer in the polycrystalline SiGe layer (the stacked polycrystalline SiGe layers can have all the same thickness or different thicknesses from each other) and on the desired overall thickness of the stack of polycrystalline SiGe layers. Even for relatively low temperature gradients, the overall thickness of the stack of polycrystalline SiGe layers should be such as to ensure a sufficient thermal difference between the bottom and top of the stack 125a of n+ doped regions and the stack 125b of p+ doped regions. For example, the overall thickness of the stack of polycrystalline SiGe layers can be tens of microns, in particular about 10 μm to about 30 μm (thus, for an example thickness of a common polycrystalline SiGe layer of about 1 μm, the steps of forming a polycrystalline SiGe layer and forming n+ doped regions and p+ doped regions in the polycrystalline SiGe layer are repeated dozens of times).

[0099] Then, trenches 130 are formed in the stack 125a of n+ doped regions and the stack 125b of p+ doped regions. The trenches 130 are formed, for example, as cylindrical shells. The trenches 130 extend downward to the oxide layer 110. A plurality of trenches 130 are formed along each stack 125a and 125b in a strip-like shape, such as Figure 1E As shown. Each trench 130 defines a corresponding (e.g., cylindrical) portion 133a of the corresponding stack 125a of n+ doped regions or a corresponding (e.g., cylindrical) portion 133b of the corresponding stack 125b of p+ doped regions, which portions 133a and 133b are kept separate from the rest of the corresponding stack 125a of n+ doped regions and the stack 125b of p+ doped regions. The (e.g., cylindrical) portions 133a and 133b of the stack 125a of n+ doped regions and the stack 125b of p+ doped regions will form thermoelectrically active elements (e.g., "legs") of the thermoelectric converter.

[0100] By means of an oxidation process, the trench 130 is filled with oxide, and the top surface of the structure (e.g., the surface opposite to the silicon substrate 105) is covered by an oxide layer 135. The oxide may be, for example, SiO2. Specifically, the oxidation process may involve a thermal oxidation process to coat the sidewalls of the trench 130 with oxide, followed by the deposition of a thick oxide layer using TEOS (tetraethyl orthosilicate) to fill the trench and cover the surface of the structure with the oxide layer 135. The resulting structure is as shown in FIG. Figure 1FAs shown. In this way, the (e.g., cylindrical) portions of the stack 125a of n+ doped regions and the stack 125b of p+ doped regions defined by the trench 130 are kept insulated from the remaining portions of the corresponding stack 125a of n+ doped regions and the stack 125b of p+ doped regions. As mentioned, the (e.g., cylindrical) portions of the stack 125a of n+ doped regions and the stack 125b of p+ doped regions defined by the trench 130 will form thermoelectric elements (e.g., "legs") 133a (n-doped, e.g., having a first Seebeck coefficient, in particular, having a first sign, e.g., positive) and 133b (p-doped, e.g., having a second, different Seebeck coefficient, in particular, having an opposite sign, e.g., negative) of the thermoelectric converter.

[0101] As in Figure 1G As can be seen in FIG, contact openings are formed in oxide layer 135 corresponding to n+ doped thermoelectric elements 133a and p+ doped thermoelectric elements 133b defined by trench 130, and a conductive layer 140, such as a metal, is formed on oxide layer 135 and then patterned to define conductive lines 143 interconnecting n+ doped thermoelectric elements 133a and p+ doped thermoelectric elements 133b. The surface of the structure is then covered with an oxide (e.g., SiO2) layer 145.

[0102] Now refer to 2A to Figure 2L , which shows some steps of a method according to another example embodiment of the present disclosure.

[0103] Starting with a silicon substrate (first silicon wafer) 205 , the surface of the silicon substrate 205 is oxidized to form an oxide layer 210 , such as silicon dioxide (SiO 2 ).

[0104] Then, a (relatively thick) layer 215 of polycrystalline silicon ("epitaxial poly") is formed over the oxide layer 210. For example, the polycrystalline silicon layer 215 is formed by means of epitaxial growth in an epitaxial reactor.

[0105] The resulting structure is Figure 2A Depicted in.

[0106] The thickness d of the polysilicon layer 215 should be such as to ensure a sufficient thermal difference between the bottom and top of the thermoelectric element to be formed therein (as described below) even for relatively low ambient temperature gradients. For example, the thickness of the layer 215 can be several tens of micrometers, in particular from about 10 μm to about 30 μm.

[0107] The surface of the polysilicon layer 215 is then oxidized to form an oxide layer 220, such as a silicon dioxide (SiO2) layer. Figure 2B shown.

[0108] like Figure 2C As shown, trench 225 is then formed in polysilicon layer 215. Trench 225 extends down to oxide layer 210 covering the surface of silicon substrate 205. Trench 225 may be cylindrical, for example. Trench 225 may have a width w of approximately 3 μm, for example.

[0109] Then as Figure 2D As depicted, the walls of the trench 225 are covered with an oxide layer 230 , such as a silicon dioxide (SiO 2 ) layer, for example by means of thermal oxidation. In this way, a cylindrical shell of oxide 230 is created within the trench 225 .

[0110] The n+ doped polycrystalline SiGe layer 235 is formed on a surface of the structure (eg, a surface opposite to the silicon substrate 205). The n+ doped polycrystalline SiGe layer 235 is, for example, an n+ doped polycrystalline SiGe layer. 0.7 Ge 0.3 Polycrystalline silicon layer. The n+ doped polycrystalline SiGe layer 235 can be formed, for example, by means of deposition, in particular chemical deposition, even more particularly chemical vapor deposition (CVD); among various CVD techniques, low pressure CVD (LPCVD) can be utilized. The deposition is carried out from silane (SiH4) and germanium (GeH4). The n+ doped polycrystalline SiGe is conformal. During the deposition process, the n+ doped polycrystalline SiGe fills the trench 225 (the walls of which are covered by the oxide 230). The resulting structure is as shown in FIG. Figure 2E shown.

[0111] By means of a chemical mechanical polishing (“CMP”) step, the n+ doped poly-SiGe layer 235 is removed from above the surface of the oxide layer 220, leaving only a (e.g. cylindrical) portion 237 of n+ doped poly-SiGe within the trench 225 (whose walls are covered by the oxide 230), as shown in FIG. Figure 2F Depicted.

[0112] Then, further trenches 240 are formed in layer 215. Similar to trenches 225, further trenches 240 extend down to oxide layer 210 covering the surface of silicon substrate 205. Further trenches 240 may, for example, be cylindrical. Similar to trenches 225, trenches 240 may, for example, have a width of approximately 3 μm. Further trenches 240 are formed to obtain Figure 2G The structure shown, wherein other grooves 240 alternate with the grooves 225.

[0113] Then as Figure 2H As depicted, the walls of the other trenches 240 are covered with an oxide layer 245 , such as a silicon dioxide (SiO 2 ) layer, for example by means of a thermal oxidation process. In this way, a cylindrical shell of oxide 245 is created within the trenches 240 .

[0114] A p+ doped polycrystalline SiGe layer 247 is formed on the surface of the structure. The p+ doped polycrystalline SiGe layer 247 is, for example, a p+ doped polycrystalline Si 0.7 Ge 0.3 layer. The p+ doped polycrystalline SiGe layer 247 can be formed, for example, by means of deposition, in particular chemical deposition, even more particularly chemical vapor deposition (CVD); among various CVD techniques, low pressure CVD (LPCVD) can be utilized. The deposition is carried out from silane (SiH4) and germanium (GeH4). The p+ doped polycrystalline SiGe is conformal. During the deposition process, the p+ doped polycrystalline SiGe fills the further trenches 240 (the walls of which are covered with oxide 245). The resulting structure is as shown in FIG. Figure 2I shown.

[0115] By means of a chemical mechanical polishing (“CMP”) step, the p+ doped poly-SiGe layer 247 is removed from above the surface of the oxide layer 220, leaving only a (e.g. cylindrical) portion 249 of p+ doped poly-SiGe (whose walls are covered by the oxide 245) within the further trench 240, as shown in FIG. Figure 2J Depicted.

[0116] In this way, the (e.g. cylindrical) portion 237 of n+ doped poly-SiGe and the (e.g. cylindrical) portion 249 of p+ doped poly-SiGe defined by trenches 225 and 245 (whose walls are covered by oxides 230 and 245) are insulated from the surrounding polysilicon layer 215. These (e.g. cylindrical) portions 237 of n+ doped poly-SiGe and portions 249 of p+ doped poly-SiGe will form thermoelectric elements (e.g. “legs”) of the thermoelectric converter.

[0117] It should be pointed out that in Figure 2J Each portion of the n+ doped poly-SiGe portion 237 and each portion of the p+ doped poly-SiGe portion 249 visible in FIG. 1 can be identified along with Figure 2J The direction perpendicular to the drawing plane (as can be described later) Figure 5 The present invention also provides a plurality of layers of n+ doped poly-SiGe extending therefrom (as clearly understood herein), and a plurality of layers of n+ doped poly-SiGe extending therefrom, each formed in a respective trench 225, the walls of which are covered by oxide 230, and a plurality of layers of n+ doped poly-SiGe extending therefrom, each formed in a respective trench 225, the walls of which are covered by oxide 230, and a plurality of layers of n+ doped poly-SiGe extending therefrom, each formed in a respective further trench 240, the walls of which are covered by oxide 245.

[0118] The surface of the structure (opposite to the silicon substrate 205) is then oxidized to form an oxide layer 250, such as a silicon dioxide (SiO2) layer, covering the entire surface of the structure. Figure 2K shown.

[0119] As in Figure 2L As can be seen in FIG, contact openings are formed on oxide layer 250 corresponding to each portion of n+ doped polycrystalline SiGe portion 237 and each portion of p+ doped polycrystalline SiGe portion 249, and a conductive layer 255, such as a metal, is formed on oxide layer 250 and then patterned to define first conductive lines 257 interconnecting thermoelectric elements 235 and 245. The surface of the structure is then covered with another oxide layer 260, such as SiO2. Oxide layers 250 and 260 together form a surface oxide layer 270 that embeds first conductive lines 257.

[0120] In an alternative embodiment, instead of being made of n+ doped polycrystalline SiGe and p+ doped polycrystalline SiGe, the thermoelectric elements 235 and 245 can be made of n-doped porous silicon and p-doped porous silicon, respectively. As mentioned above, porous silicon advantageously has a very low thermal conductivity (0.15 to 1.5 W / mK when the porosity is about 75%). The n-doped porous silicon and p-doped porous silicon thermoelectric elements 235 and 245 can be made of n-doped porous silicon and p-doped porous silicon, respectively, by converting n + and p + It is obtained by doping polysilicon.

[0121] Figures 3A to 3I Some steps of the process of forming thermoelectric elements 235 and 245 made of porous silicon are depicted.

[0122] from Figure 2B Starting with the structure shown, Figure 3A As depicted, a mask layer 305 (eg, a silicon nitride layer or a thick oxide layer) is formed over oxide layer 220 .

[0123] like Figure 3B As shown, trench 310 is then formed by selective etching, starting from the surface of mask layer 305 (which protects the structure from etching when the trench is not formed) and extending down to oxide layer 210 covering silicon substrate 205. Trench 310 can be similar to trench 225 of the previously described embodiment (e.g., a cylindrical trench having a width of approximately 3 μm).

[0124] like Figure 3C As depicted, the walls of trench 310 are then coated with an oxide layer 315 , for example by means of a thermal oxidation process.

[0125] like Figure 3D As shown, a mask layer 320 of, for example, silicon nitride is then deposited over the entire structure. The material of the mask layer 320 penetrates into the trenches 310 and coats the walls and bottom of the trenches 310.

[0126] Move to Figure 3E, the structure is etched, and during the etching process, a portion of the mask layer 320 is etched away; when the material of the mask layer 320 and the portion of the bottom of the trench 310 of the oxide layer 210 are removed, the etching stops, thereby exposing the silicon substrate 205 at the bottom of the trench 310.

[0127] Similar to Figures 2E to 2J The process steps of φ 10 and φ 20 are then performed to fill the trenches 310 with n+ doped polysilicon and p+ doped polysilicon.

[0128] After the chemical mechanical polishing step, Figure 3F The structure depicted in FIG is obtained (in this figure and the following figures, the silicon nitride layer remaining on the top surface and sidewalls of the trench 310 after the etching of step 3E is not shown for better readability). The trench 310 is filled with an n+ doped polysilicon pillar 325a and a p+ doped polysilicon (e.g., cylindrical) pillar 325b, respectively.

[0129] Then the n+ doped polysilicon columns 325a and the p+ doped polysilicon columns 325b are converted into n+ doped porous silicon columns and p+ doped porous silicon columns. To this end, the structure is immersed in a tank or anodizing cell, for example, made of polytetrafluoroethylene, which is filled with a solution of hydrogen fluoride (HF) acid and is provided with an anode and a cathode. The structure to be processed is connected to the anode (the cathode can be, for example, a mesh electrode made of platinum). HF acid affects the n+ doped polysilicon columns 325a and the p+ doped polysilicon columns 325b, thereby converting them into n+ doped porous silicon columns and p+ doped porous silicon columns. Preferably, the process is stopped before the bottom (base) of the n+ doped polysilicon columns 325a and the p+ doped polysilicon columns 325b is converted into porous silicon. This ensures that the integrity of the porous silicon is preserved during the subsequent stages of the manufacturing process. The resulting structure is Figure 3G , where reference numerals 330a and 330b denote pillars of n+ doped porous silicon and pillars of p+ doped porous silicon, respectively, and reference numeral 335 denotes the bottoms of the pillars 330a and 330b that have not undergone conversion to porous silicon.

[0130] It should be noted that in an embodiment, the step of converting the n+ doped polysilicon pillars 325a and the p+ doped polysilicon pillars 325b into n+ doped porous silicon pillars and p+ doped porous silicon pillars can be avoided: the applicant has found that even though the performance is not as good as that of n+ doped porous silicon and p+ doped porous silicon, n+ doped polysilicon and p+ doped polysilicon are viable choices as thermoelectric materials.

[0131] In an embodiment, the process may envision forming (e.g., by deposition) a polysilicon layer 340 over the surface of the structure. Donor dopant ions and acceptor dopant ions are then selectively implanted into the polysilicon 340 to form n+ doped polysilicon regions 345a and p+ doped polysilicon regions 345b over the pillars of n+ doped porous silicon 330a and p+ doped porous silicon 330b, respectively. The resulting structure is as shown in FIG. Figure 3H The remaining portion of the polysilicon layer 340 (except for the n+ doped polysilicon region 345a and the p+ doped polysilicon region 345b) is then etched away to obtain Figure 3I In this way, the n+ doped polysilicon region 345a and the p+ doped polysilicon region 345b above the pillars of n+ doped porous silicon 330a and p+ doped porous silicon 330b provide an expanded contact area to the pillars of n+ doped porous silicon 330a and p+ doped porous silicon 330b, which can facilitate forming electrical contacts to the pillars. Similar considerations can be applied to the first two embodiments described above.

[0132] Figures 4A to 4E Some steps of a method for continuing to manufacture a thermoelectric converter according to any of the previously described embodiments are shown according to an exemplary embodiment of the present disclosure. Although the steps of the manufacturing method to be described below are also applicable to any of the embodiments described so far, for simplicity reasons, they will be referred to in the following. Figures 2A to 2L The second embodiment described in is described and illustrated.

[0133] like Figure 4A As shown, from Figure 2L Starting with the structure of , a second silicon wafer 405 is bonded to the surface of the structure opposite to the silicon substrate (first silicon wafer) 205.

[0134] Then as Figure 4B As shown (in this figure and the following figures Figure 4C and Figure 4D In this structure, Figure 4A The silicon substrate (first silicon wafer) 205 is removed (as depicted upside down). After the silicon substrate (first silicon wafer) 205 is removed, the oxide layer 210 remains uncovered.

[0135] Contact openings are formed in the oxide layer 210 corresponding to the thermoelectric elements 237 and 249, and a conductive layer 410, such as a metal, is formed on the oxide layer 210 and then patterned to define a second conductive line 413 interconnecting the thermoelectric elements 237 and 249. The resulting structure is as shown in FIG. Figure 4C shown.

[0136] The surface of the structure is then covered with a further oxide (eg SiO2) layer 415, thereby obtaining Figure 4D structure.

[0137] The second silicon wafer 405 is then selectively etched to form trenches, leaving material of the second silicon wafer only above the thermoelectric elements 237, 249, and with the second silicon wafer 405 removed, the oxide layer 260 covering the first wire 257 is etched and removed to expose portions 257', 257" of the first wire 257; the exposed portions 257', 257" of the first wire 257 will form contact pads for the thermoelectric converter to which the bonding wire 265 ( Figure 1G A similar portion of the conductive line 143 in the structure will form a contact pad). The resulting structure is as shown in FIG. Figure 4E As shown (similar to Figures 2A to 2L Directional).

[0138] In use, the side of the structure on which (a portion of) the second silicon wafer 405 is present (the left side and not removed) will, for example, be the "hot" side of the thermoelectric converter (e.g., the side where the temperature of the environment in which the thermoelectric converter is inserted is higher), while the opposite side of the structure will, in use, be, for example, the "cold" side of the thermoelectric converter (e.g., the side where the temperature of the environment in which the thermoelectric converter is inserted is lower). Naturally, in use, the roles of the "hot" and "cold" sides of the thermoelectric converter can be reversed: typically, the two sides of the thermoelectric converter will experience a temperature gradient in use. The portion(s) of the second silicon wafer 405 that is left and not removed can form structural support for the device.

[0139] Figure 4F Shows 4D and Figure 4E 4. Alternatively, the step of forming the contact pad for the bonding wire 265 can be described. In this case, the contact pad can be part of the second wire 413 interconnecting the thermoelectric elements 237 and 249. To open the contact area of ​​the contact pad, the oxide layer 415 is selectively etched. It is not necessary to selectively etch the second silicon wafer 405, which can be left to serve as a mechanical support for the structure.

[0140] Figure 5 Shown by Figures 1A to 1G The production process and Figures 4A to 4EThe layout of the structure obtained in the subsequent steps is shown. The device includes a plurality of first thermoelectric elements 133a (n-doped, for example, having a first Seebeck coefficient, in particular having a first sign, such as positive) and a plurality of second thermoelectric elements 133b (p-doped, for example, having a second, different Seebeck coefficient, in particular having an opposite sign, such as negative). Each first thermoelectric element and each second thermoelectric element has a first end on the "hot" side of the device and a second end on the "cold" side of the device. The first thermoelectric elements 133a and the second thermoelectric elements 133b are arranged in an alternating array extending parallel to each other and are contacted in a "zigzag" manner (at opposite ends of the thermoelectric elements, the "hot" side and the "cold" side) by wires 143 (here forming first wires 257) and second wires 413. The first wire 257 has an input contact pad 257' and an output contact pad 257".

[0141] The first thermoelectric element 133 a and the second thermoelectric element 133 b are thermally connected in parallel and electrically connected in series.

[0142] Figure 6 Shown by Figures 2A to 2L (or Figures 3A to 3I )and Figures 4A to 4D and Figure 4F The layout of the structure obtained during the fabrication process.

[0143] therefore, Figure 6 The device comprises a plurality of first thermoelectric elements 237 (n-doped, e.g., having a first Seebeck coefficient, in particular, having a first sign, e.g., positive) and a plurality of second thermoelectric elements 249 (p-doped, e.g., having a second, different Seebeck coefficient, in particular, having an opposite sign, e.g., negative). Each first thermoelectric element 237 and each second thermoelectric element 249 has a first end on a "hot" side of the device and a second end on a "cold" side of the device. The first thermoelectric elements 237 and the second thermoelectric elements 249 are arranged in alternating rows or arrays extending parallel to each other and are contacted in a "zigzag" manner (at opposite ends of the thermoelectric elements, the "hot" side and the "cold" side) by first wires 257 and second wires 413. The second wire 413 has an input contact pad 413′ and an output contact pad 413″.

[0144] The first thermoelectric element 237 and the second thermoelectric element 249 are connected thermally in parallel and electrically in series.

[0145] Figure 7 An electronic system 700 including a thermoelectric converter according to an embodiment of the present disclosure is schematically illustrated in a simplified block diagram.

[0146] System 700 includes a thermoelectric converter 705, such as a thermoelectric generator, adapted to convert heat, represented by arrow 710, in the environment of system 700 into electrical energy, which is used to charge a battery 715 of system 700. Battery 715 supplies electrical energy to an application 720, such as an electronic subsystem such as a smartwatch, a wearable device, a flashlight, or the like.

[0147] The proposed solution exhibits several advantages. It is easy to industrialize, offers power levels in the mA range, consumes little semiconductor area, and operates with low or high temperature gradients. Furthermore, the proposed solution allows for the reduction of the size of standard thermoelectric devices from the macro to the micro scale, utilizing technological steps typical of semiconductor (silicon) manufacturing technology.

[0148] Thermoelectric converters according to the present disclosure can be utilized in several practical applications, such as wearable and fitness devices, pedometers and heart rate meters, smart watches and wristbands, wireless sensor nodes for smart homes and cities, and other energy harvesting systems, as described below with reference to Figure 17 discussed.

[0149] Furthermore, as disclosed herein, thermoelectric converters according to the present disclosure may be used in solar energy recovery devices.

[0150] Figures 8 to 13 Some steps of a method for manufacturing a solar energy recycling device using a thermoelectric converter of any one of the previously described embodiments according to an exemplary embodiment of the present disclosure are shown. Although the steps of the manufacturing method to be described below are also applicable to any of the embodiments described so far, for simplicity, they will be referred to Figures 4A to 4D and Figure 4F The continuation of the described process steps is described and shown. Figure 8 、 Figure 10 In the cross section (along Figure 9A 、 Figure 9B The cross-sectional plane VIII-VIII is intercepted) and Figure 11 In the cross section (along Figure 12A 、 Figure 12B ), only the first conductor 257 is completely visible; the second conductor 413 is only partially visible.

[0151] like Figure 8 As shown, the third silicon wafer 501 is bonded to Figure 4FSurface 500A of the structure, denoted herein by 500 and also referred to as thermoelectric generator structure 500, is disposed opposite second silicon wafer 405. Third silicon wafer 501, which may be a silicon wafer, particularly single-crystal silicon, doped with acceptor dopants and thus of P-type, has a first surface 501A and a second surface 501B. Third silicon wafer 501 is bonded to thermoelectric generator structure 500 at its first surface 501A.

[0152] To this end, a bonding multilayer 502 is used; for example, the bonding multilayer 502 may include a first bonding layer 504 extending on the surface 500A of the thermoelectric generator structure 500; a second bonding layer 505 extending on the first surface 501A of the third silicon wafer 501; and an intermediate bonding layer 506. The materials of the first bonding layer 504 and the second bonding layer 505 may be copper (Cu); and the material of the intermediate bonding layer 506 may be tin (Sn).

[0153] The first bonding layer 504, the second bonding layer 505, and the intermediate bonding layer 506 may be applied on the surface 500A of the thermoelectric generator structure 500 or on the first surface 501A of the third silicon wafer 501. In an alternative embodiment, the first bonding layer 504 may be applied to the surface 500A of the thermoelectric generator structure 500, the second bonding layer 505 may be applied to the first surface 501A of the third silicon wafer 501, and the intermediate bonding layer 506 may be applied to one of the first bonding layer 504 or the second bonding layer 505.

[0154] In some embodiments, the bonding layers 502 are defined to form an annular portion 502A that surrounds an area housing the thermoelectric elements 237, 249 in the thermoelectric generator structure 500 (see also FIG. Figure 9A and 9B The bonding multilayer 502 also forms intermediate fingers 502B which can be arranged in various ways to allow good bonding and to allow the connection to extend over the surface 500A of the thermoelectric generator structure 500 or over the first surface 501A of the third silicon wafer 501 .

[0155] For example, Figure 8 The thermoelectric elements 237, 249 form a plurality of thermoelectric modules 510 coupled in parallel with each other (see Figure 9A ).exist Figure 8 、 Figure 10 and Figure 11 In the embodiment of the present invention, each thermoelectric module 510 may include Figure 6 A row of thermoelectric elements 237 and a row of thermoelectric elements 249 are shown coupled (see, e.g., Figure 6 ); In an alternative embodiment, each thermoelectric module 510 may include, for example Figure 6The entire structure is shown.

[0156] In some embodiments, the thermoelectric modules 510 are coupled by connectors 511, which may be formed partially in the oxide layer 270 and partially on the oxide layer 415. Figure 8 ). Interrupted by annular portion 502A joining multiple layers 502, connector 511 is coupled to input pads 512 and output pads 513 arranged at the periphery of thermoelectric generator structure 500. Input pads 512 and output pads 513 can be coupled to input contact pads 413′ and output contact pads 413″ by vias in a manner known per se. In addition, annular portion 502A forms an anode pad 514, as explained below.

[0157] exist Figure 10 In, N + The implantation of N-type dopant species is performed in the third wafer 501 through its second surface 501B. For example, a suitable N + The type dopant species can be phosphorus or arsenic.

[0158] The implant is then annealed and activated by an intense laser beam pulse. The pulse length can be approximately one hundred nanoseconds (<200 ns). Thus, cathode region 520 is formed. The heat generated by the pulse is sufficient to perform local annealing, thereby eliminating local implant damage and activating the dopant. Specifically, using very short pulses, no temperature changes are generated in the metal region; therefore, the bonding of multilayer 502, first wire 257 and second wire 413, and connection 511 is unaffected.

[0159] The cathode region 520 forms a diode together with the base of the third wafer 501 (hereinafter also referred to as P-type substrate 521 ), which can convert solar energy into electric current in a manner known per se.

[0160] exist Figure 11 In the embodiment, the third wafer 501 is etched to remove a portion thereof covering the pads 512 to 514 (see also Figure 12A 、 12B , which shows that the thermoelectric generator structure 500 and the third wafer 501 have not yet been bonded together. Etching can be performed by laser or blade cutting. As a result, a recess 525 is formed, which exposes the pads 512 to 514.

[0161] Wires 530 are bonded to input pad 512 and output pad 513, and external connections 531A, 531B are each bonded to anode pad 514 and cathode region 520. External connections 531A, 531B may be wires or cables.

[0162] Thus, a solar photovoltaic thermoelectric module 550 is obtained.

[0163] Figure 13 An example connection of three solar photovoltaic thermoelectric modules 550 to form a hybrid solar energy recovery device 570 is shown. Generally, multiple solar photovoltaic thermoelectric modules 550 can be coupled in series or in parallel with one another, with the input pads 512 of all solar photovoltaic thermoelectric modules 550 coupled together and the output pads 513 of all solar photovoltaic thermoelectric modules 550 coupled together via corresponding external connections 531A, 531B. Hybrid solar photovoltaic thermoelectric device 570 is capable of efficiently recovering electrical energy.

[0164] Conventional solar cells can only absorb photon energy of solar radiation at a frequency close to the band gap of the solar cell, and the remaining energy is converted into heat energy and wasted. In addition, the conversion efficiency decreases with temperature.

[0165] In contrast, using Figure 8 12 , waste heat generated at the solar photovoltaic cell wafer 501 can be recovered by the thermoelectric generator structure 500 , and the total power is the sum of the power supplied by the thermoelectric generator 500 and the power supplied by the solar photovoltaic cell wafer 501 , thereby providing synergy.

[0166] Manufacturing can be carried out using common techniques in the semiconductor industry. For example, the solar photovoltaic cell wafers 501 are bonded before the front end. In this way, possible cracks (e.g., in the metal areas) that may occur due to the pressure exerted by the piston on the two wafers during bonding are avoided.

[0167] Figure 14 and Figure 15 Another embodiment of a thermoelectric generator obtained by aerosol jet printing of semiconductor materials is shown. Specifically, maskless mesoscale material deposition (M3D) can be used to deposit the semiconductor materials. According to one aspect of the present disclosure, regions of bismuth telluride (Bi2Te3) of opposite conductivity types are printed.

[0168] For example, Figure 14 A first wafer 600 and a second wafer 601 are shown. The first wafer 600 and the second wafer 601 can be silicon wafers, such as single crystal silicon wafers. One of the wafers 600 and 601 (here, the second wafer 601) is of P-type.

[0169] The first wafer 600 has a surface 600A on which a P-type bismuth telluride region 604 and a first adhesion region 605 have been deposited, optionally using M3D.

[0170] The second wafer 601 has a surface 601A on which an N-type bismuth telluride region 606 and a second adhesion region 607 have been deposited, optionally using M3D.

[0171] P-type bismuth telluride region 604 and first adhesion region 605 are deposited on first metal region 610 extending on surface 600A of first wafer 600. N-type bismuth telluride region 606 and second adhesion region 607 are deposited on second metal region 611. First metal region 610 and second metal region 611 may be, for example, gold (Au).

[0172] For example, a bismuth telluride region 604 or 606 and an adhesion region 605 or 607 are formed on each metal region 610 , and the distance between the P-type bismuth telluride region 604 and the adjacent first adhesion region 605 is the same as the distance between the N-type bismuth telluride region 606 and the adjacent second adhesion region 607 .

[0173] In addition, despite Figures 14 and 15 It is fully visible that the metal areas 610, 611 generally have Figure 5 or Figure 6 The patterns for the conductive lines 143 or 257 and 413 are shown for connecting the bismuth telluride regions 604 and 606 in series. The adhesion regions 605 and 607 can be a tin-silver (Sn-Ag) alloy and have a lower thickness than the bismuth telluride regions 604 and 606. Here, the bismuth telluride regions 604 and 606 have the same thickness, for example, in the range of 20 to 30 μm; the adhesion regions 605 and 607 have the same thickness, for example, in the range of 1 to 2 μm.

[0174] By turning one wafer (here, the second wafer 601) upside down and bonding the P-type bismuth telluride region 604 to the second adhesion region 607 and the N-type bismuth telluride region 606 to the first adhesion region 605 ( Figure 15 ), the first wafer 600 and the second wafer 601 are bonded to each other.

[0175] The bonding may be accomplished by applying pressure (eg, 1 to 20 MPa) at a low temperature (eg, approximately 400° C.).

[0176] After bonding, the bismuth telluride regions 604 , 606 form a thermoelectric element.

[0177] Then, N + An implantation of a type dopant species is performed in one of the wafers 600, 601 (here the second wafer 601) through its exposed surface. For example, phosphorus or arsenic ions are implanted.

[0178] The implant is then annealed and activated by an intense laser beam pulse, thereby forming the cathode region 620. The remaining portion of the second wafer 601 forms the anode region 621.

[0179] Figure 15 The structure can withstand the above reference Figure 11 、 Figure 12A and Figure 12B Discussion of the fabrication steps.

[0180] Thus, a solar photovoltaic thermoelectric module 650 is obtained.

[0181] like Figure 13 As shown, multiple solar photovoltaic thermoelectric modules 650 can be coupled to form a hybrid solar energy recovery device.

[0182] Figure 16 Shows something like Figure 15 The solar photovoltaic thermoelectric module 650 is a solar photovoltaic thermoelectric module 750, but for the arrangement of bismuth telluride regions 604, 606 formed here on the same wafer (here the first wafer 600) and an adhesive region denoted here by reference numeral 705 formed on another wafer (here the second wafer 601). The other elements have been Figures 14 and 15 The same reference numerals as those in FIG.

[0183] In some implementations, Figure 16 In an embodiment, the P-type bismuth telluride region 604 and the N-type bismuth telluride region 606 are printed on the first wafer 600 (after forming the first metal region 610) by M3D printing technology, and the adhesion region 705 is entirely printed on the second wafer 601 (after forming the second metal region 611).

[0184] After bonding the first wafer 600 and the second wafer 601 , a solar photovoltaic thermoelectric module 750 is obtained.

[0185] like Figure 17 As shown by Figure 15 Solar photovoltaic thermoelectric modules 650 or Figure 16 The energy recovered by the solar photovoltaic thermoelectric module 750 can be increased by using a passive cooling system.

[0186] Figure 17 A solar energy recovery system 800 is shown comprising solar collector panels 801 and a loop for recirculating a cooling fluid 802. In the embodiment considered, the cooling fluid is water and the following description is made with water in mind; however, other cooling fluids may be used.

[0187] A tank 803 with a cold water input tap 804 and a warm water output tap 805 is arranged along the water recirculation loop 802 .

[0188] Solar collector panels 801 house Figure 13 A plurality of solar photovoltaic thermoelectric modules 550, 650, or 750 are shown coupled together. The solar photovoltaic thermoelectric modules 550, 650, or 750 can be attached to a support wall 810 that defines a water chamber 811 arranged along a loop 802. The water chamber 811 has an input (cold) side 811A and an output (warm) side 811B; the tank 803 is arranged near the output (warm) side 811B of the water chamber 811.

[0189] Due to the temperature gradient between the input (cold) side 811A and the output (warm) side 811B, and due to the principle of communicating containers, the water in loop 802 does not require a pump to circulate.

[0190] For example, in an embodiment, loop 802 may include a circuit below the ground plane (at Figure 17 The underground section 820 extends from the cooling water (indicated in FIG by 830). In particular, by arranging the underground section 820 at a depth of 8 to 10 m below ground level 830, a particularly efficient heat extraction from the cooling water is obtained, and no chiller or pump is required.

[0191] By recirculating cooling water, the loop 802 provides cooling of the solar collector panel 801 and thereby reduces the temperature of the solar photovoltaic cell wafers 501 , 601 and increases the photovoltaic effect.

[0192] Figure 18 A possible embodiment of a solar photovoltaic cell wafer 900 is shown.

[0193] The solar photovoltaic cell wafer 900 is based on the use of amorphous silicon, in the case of being hydrogen passivated (a-Si:H), and comprises a stack formed by a first doped layer 901 having N-type conductivity; an intermediate intrinsic layer 902 covering the first doped layer 901; and a second doped layer 903 having P-type conductivity, which covers the intermediate intrinsic layer 902.

[0194] For example, Figure 18 The structure of the present invention can be obtained by depositing an aluminum layer 905, a first doped layer 901, an intermediate intrinsic layer 902, a second doped layer 903, a transparent conductive oxide (TCO) layer 906 and a glass layer 907 on the third wafer 501. Figure 8 The structure begins to be obtained.

[0195] In an embodiment, the first doped layer 901 may have a thickness of approximately 10 nm; the intermediate intrinsic layer 902 may have a thickness of approximately 400 nm; and the second doped layer 901 may have a thickness of approximately 10 nm.

[0196] The TCO layer 906 may be, for example, indium tin oxide.

[0197] Due to the fact that electron-hole recombination is particularly high in doped silicon, the intermediate intrinsic layer 902 provides efficient absorption of optical radiation, while the first doped layer 901 and the second doped layer 903 provide efficient generation of electron current. Therefore, the solar photovoltaic cell wafer 900 is very efficient and can be advantageously combined with the thermoelectric generator structures described herein, such as the thermoelectric generator structure 500.

[0198] A method of making an integrated thermoelectric converter can be summarized as comprising: providing a silicon-based material layer (115; 215), the silicon-based material layer having a first surface and a second surface opposite the first surface and separated from the first surface by a thickness of the silicon-based material layer; forming a plurality of first thermoelectric active elements (133a; 237; 330a) of a first thermoelectric semiconductor material having a first Seebeck coefficient, and forming a plurality of second thermoelectric active elements (133b; 249; 330b) of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first thermoelectric active elements and the second thermoelectric active elements Formed to extend from a first surface through the thickness of a silicon-based material layer (115; 215) to a second surface; forming conductive interconnects (143, 413; 257, 413) corresponding to the first and second surfaces of the silicon-based material layer (115; 215) to electrically interconnect a plurality of first thermoelectric active elements and a plurality of second thermoelectric active elements, and forming input electrical terminals (257') and output electrical terminals (257") electrically connected to the conductive interconnects, wherein the first thermoelectric semiconductor material and the second thermoelectric semiconductor material include a silicon-based material selected from porous silicon or polycrystalline SiGe or polycrystalline silicon.

[0199] The silicon-based material layer (115; 215) may be a poly-SiGe (specifically poly-Si 0.7 Ge 0.3 ) or materials selected from epitaxial polysilicon.

[0200] The plurality of first thermoelectric active elements (133a; 237; 330a) of the first thermoelectric semiconductor material having a first Seebeck coefficient may include doped porous silicon or polycrystalline SiGe or polycrystalline silicon doped with acceptor dopants or donor dopants, and the plurality of second thermoelectric active elements (133b; 249; 330b) of the second thermoelectric semiconductor material having a second Seebeck coefficient may include doped porous silicon or polycrystalline SiGe or polycrystalline silicon, each doped with a donor dopant or an acceptor dopant.

[0201] Providing the silicon-based material layer (115; 215) may include epitaxially growing a polysilicon layer (115; 215) on an oxidized surface of the substrate.

[0202] The forming of a plurality of first thermoelectric active elements (237) of a first thermoelectric semiconductor material having a first Seebeck coefficient may include forming a first trench (225, 230) in a silicon-based material layer (215), and filling the first trench with polysilicon or polycrystalline SiGe doped with an acceptor or donor dopant, and the forming of a plurality of second thermoelectric active elements (249) of a second thermoelectric semiconductor material having a second Seebeck coefficient may include forming a second trench (240, 245) in a silicon-based material layer (215), and filling the second trench with polysilicon or polycrystalline SiGe doped with a donor or acceptor dopant.

[0203] The method may further include converting the doped polysilicon filling the first trench and the second trench into doped porous silicon.

[0204] The providing of the silicon-based material layer may include iterating the following steps at least twice: forming a polycrystalline SiGe layer (115) on an oxidized surface of a substrate (205), wherein the polycrystalline SiGe layer (115) has a thickness of a fraction compared to the thickness of the silicon-based material layer; selectively doping a first region (120a) of the polycrystalline SiGe layer with an acceptor or donor dopant, and selectively doping a second region (120b) of the polycrystalline SiGe layer with a donor or acceptor dopant, so that after the iteration, the stack of the respective polycrystalline SiGe layers (115) has an overall thickness corresponding to the thickness of the silicon-based material layer, and forming trenches (130) in the stack of the respective polycrystalline SiGe layers to obtain separated portions (133a, 133b) of the doped first region and the doped second region.

[0205] An integrated thermoelectric converter can be summarized as comprising: a silicon-based material layer (115; 215) having a first surface and a second surface opposite to the first surface and separated from the first surface by a thickness of the silicon-based material layer; a plurality of first thermoelectric active elements (133a; 237; 330a) of a first thermoelectric semiconductor material having a first Seebeck coefficient and a plurality of second thermoelectric active elements (133b; 249; 330b) of a second thermoelectric semiconductor material having a second Seebeck coefficient, wherein the first thermoelectric active elements and the second thermoelectric active elements are An electrically active element extends from a first surface through the thickness of the silicon-based material layer to a second surface; conductive interconnects (143, 413; 257, 413) corresponding to the first surface and the second surface of the silicon-based material layer to electrically interconnect a plurality of first thermoelectric active elements and a plurality of second thermoelectric active elements; and input electrical terminals (257') and output electrical terminals (257") electrically connected to the conductive interconnects, wherein the first thermoelectric semiconductor material and the second thermoelectric semiconductor material include a silicon-based material selected between porous silicon or polycrystalline silicon or polycrystalline SiGe.

[0206] The silicon-based material layer may be poly-SiGe (specifically poly-Si 0.7 Ge 0.3 ) or epitaxial polysilicon.

[0207] The first thermoelectric semiconductor material having a first Seebeck coefficient may be porous silicon or polycrystalline silicon or polycrystalline SiGe doped with an acceptor dopant or a donor dopant, and the second thermoelectric semiconductor material having a second Seebeck coefficient may be porous silicon or polycrystalline silicon or polycrystalline SiGe each doped with a donor dopant or an acceptor dopant.

[0208] Each of the plurality of first and second thermoelectric active elements and each second thermoelectric active element of the second thermoelectric active elements may have a first end at the first surface of the silicon-based material layer and a second end at the second surface, and the conductive interconnect may electrically connect the first end of the common first thermoelectric active element to the first end of the second thermoelectric active element and electrically connect the second end of the common first thermoelectric active element to the second end of another second thermoelectric active element, so that the plurality of first thermoelectric active elements and the plurality of second thermoelectric active elements are connected in series and alternate with each other.

[0209] An electronic system (600) may be summarized as including a thermoelectric converter.

[0210] The present disclosure can also be understood based on the following example implementations.

[0211] Example implementation 1: A method for making a thermoelectric converter, comprising: forming a thermoelectric active element of a first thermoelectric semiconductor material having a first Seebeck coefficient and a plurality of second thermoelectric active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient in a silicon-based material layer, the silicon-based material layer having a first surface, a second surface opposite to the first surface, and a first thickness between the first surface and the second surface, the first thermoelectric active element and the second thermoelectric active element each being formed to extend from the first surface through the first thickness to the second surface; and forming a conductive interconnect on at least one of the first surface or the second surface of the silicon-based material layer, the conductive interconnect each electrically interconnecting a first thermoelectric active element of the plurality of first thermoelectric active elements with a corresponding second thermoelectric active element of the plurality of second thermoelectric active elements; and forming an input electrical terminal and an output electrical terminal electrically coupled to the conductive interconnect, wherein the first thermoelectric semiconductor material and the second thermoelectric semiconductor material each include a silicon-based material selected from the group consisting of porous silicon, polycrystalline silicon germanium (SiGe), and polycrystalline silicon.

[0212] Example implementation 2: The method according to example implementation 1, wherein the silicon-based material layer is formed on a substrate having Si 0.7 Ge 0.3 The material is selected from polycrystalline SiGe or epitaxial polysilicon.

[0213] Example implementation 3: The method according to example implementation 1, wherein the plurality of first thermoelectric active elements of the first thermoelectric semiconductor material having a first Seebeck coefficient are doped with acceptor dopants, and the plurality of second thermoelectric active elements of the second thermoelectric semiconductor material having a second Seebeck coefficient are doped with donor dopants.

[0214] Example implementation 4: The method according to example implementation 1, wherein the silicon-based material layer is polysilicon, and the method includes epitaxially growing the polysilicon layer on an oxidized surface of a substrate.

[0215] Example implementation 5: The method according to example implementation 4, wherein forming the plurality of first thermoelectric active elements having the first thermoelectric semiconductor material having the first Seebeck coefficient includes: forming a first trench in the silicon-based material layer, and filling the first trench with polycrystalline silicon or polycrystalline SiGe doped with an acceptor dopant; and wherein forming the plurality of second thermoelectric active elements having the second thermoelectric semiconductor material having the second Seebeck coefficient includes: forming a second trench in the silicon-based material layer, and filling the second trench with polycrystalline silicon or polycrystalline SiGe doped with a donor dopant.

[0216] Example implementation 6: The method according to example implementation 5, wherein each of the first trench and the second trench is filled with polysilicon, and the method further comprises: converting the doped polysilicon filling the first trench and the second trench into doped porous silicon.

[0217] Example implementation 7: The method according to example implementation 1 includes: forming the silicon-based material layer includes: iterating the following steps at least twice: forming a polycrystalline SiGe layer on the oxidized surface of the substrate, wherein the polycrystalline SiGe layer has a thickness that is a portion of the first thickness of the silicon-based material layer; selectively doping a first region of the polycrystalline SiGe layer with an acceptor dopant; and selectively doping a second region of the polycrystalline SiGe layer with a donor dopant, wherein after the iteration, the stack of each polycrystalline SiGe layer has an overall thickness corresponding to the first thickness of the silicon-based material layer; and forming a trench in the stack of each polycrystalline SiGe layer to obtain separated portions of the doped first region and the doped second region.

[0218] Example implementation 8: The method according to example implementation 1, further comprising: bonding the silicon-based material layer to an amorphous silicon solar photovoltaic cell wafer.

[0219] Example Implementation 9: The method according to Example Implementation 8, wherein bonding the silicon-based material layer includes forming a conductive bonding layer in electrical contact with the solar photovoltaic cell wafer, and forming a first electrical contact for the solar photovoltaic cell wafer.

[0220] Example implementation 10: The method according to example implementation 9, wherein the solar photovoltaic cell wafer includes a first region of a first conductivity type, the method including implanting dopant species to form a second region of a second conductivity type opposite to the first conductivity type, and forming a second electrical contact electrically coupled to the second region.

[0221] Example implementation 11: A method for making a thermoelectric converter, comprising: forming conductive interconnects on a first wafer and a second wafer; printing semiconductor regions of a first conductivity type and a second conductivity type on the conductive interconnects of at least one of the first silicon wafer or the second silicon wafer by maskless mesoscale material deposition according to a pattern; forming a bonding area of ​​conductive material on the other silicon wafer of the at least one of the first silicon wafer or the second silicon wafer, the bonding area being arranged to correspond to the pattern; and bringing the semiconductor region into contact with the bonding area; and bonding the semiconductor region to the bonding area by applying pressure to the first silicon wafer and the second silicon wafer.

[0222] Example Implementation 12: The method of Example Implementation 11, wherein the semiconductor region is a bismuth telluride region.

[0223] Example Implementation 13: The method of Example Implementation 11, wherein the bonding region is formed using maskless mesoscale material deposition.

[0224] Example Implementation 14: The method according to Example Implementation 11, comprising: forming an anode region on a surface of the first silicon wafer away from the second silicon wafer.

[0225] Example Implementation 15: The method according to Example Implementation 14 includes forming a cathode region in the first silicon wafer.

[0226] Example implementation 16: An integrated thermoelectric converter comprising: a first pillar structure, the first pillar structure comprising one of porous silicon, polycrystalline silicon germanium or polycrystalline silicon, and being doped with a first conductivity type; a second pillar structure, the second pillar structure comprising one of porous silicon, polycrystalline silicon germanium or polycrystalline silicon, and being doped with a second conductivity type; and a first conductive interconnect structure electrically contacting a first end of the first pillar structure and a first end of the second pillar structure.

[0227] Example Implementation 17: The integrated thermoelectric converter according to Example Implementation 16, comprising: a first insulating structure surrounding the first pillar structure, and a second insulating structure surrounding the second pillar structure.

[0228] Example Implementation 18: The integrated thermoelectric converter of Example Implementation 16, wherein the first pillar structure comprises polycrystalline silicon germanium, and the first pillar structure comprises a plurality of polycrystalline silicon germanium layers stacked on each other.

[0229] Example Implementation 19: The integrated thermoelectric converter of Example Implementation 16, comprising: a substrate, wherein the first pillar structure comprises a first portion of porous silicon and a second portion of polycrystalline silicon, the second portion being between the first portion and the substrate.

[0230] Example Implementation 20: The integrated thermoelectric converter of Example Implementation 19, wherein the second portion of the first pillar structure is in contact with the substrate.

[0231] Example Implementation 21: The integrated thermoelectric converter of Example Implementation 16, wherein each thermoelectrically active element of the first plurality of thermoelectrically active elements and each thermoelectrically active element of the second plurality of thermoelectrically active elements is cylindrical.

[0232] Example implementation 22: The integrated thermoelectric converter according to example implementation 16 includes: a third column structure, the third column structure including one of porous silicon, polycrystalline silicon germanium or polycrystalline silicon, and being doped with the second conductivity type; and a second conductive interconnect structure electrically contacting the second end of the first column structure and the second end of the third column structure.

[0233] Example implementation 23: The integrated thermoelectric converter according to example implementation 16 includes: a fourth column structure, the fourth column structure including one of porous silicon, polycrystalline silicon germanium or polycrystalline silicon, and being doped with the first conductivity type; and a third conductive interconnect structure electrically contacting the second end of the second column structure and the second end of the fourth column structure.

[0234] Example Implementation 24: The integrated thermoelectric converter according to Example Implementation 16, comprising: an insulating layer covering the first conductive interconnect structure; and a silicon wafer on the insulating layer.

[0235] Example implementation 25: An integrated solar photovoltaic thermoelectric module, comprising: a substrate wafer; a first conductive interconnect on the substrate wafer; a thermoelectric converter structure on the substrate layer, the thermoelectric converter structure comprising a plurality of first thermoelectric active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient and a plurality of second thermoelectric active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient, the first thermoelectric active elements and the second thermoelectric active elements being in the shape of pillars and each having a first end and a second end, the first end of each first thermoelectric active element being electrically coupled to the first end of the second thermoelectric active element through a corresponding first conductive interconnect; a second conductive interconnect coupled to the second end of the first thermoelectric active element and the second thermoelectric active element; an amorphous silicon solar cell wafer bonded to the thermoelectric converter structure, the solar cell wafer comprising an anode region and a cathode region; a first input electrical terminal and a first output electrical terminal electrically coupled to the conductive interconnect; and a second input electrical terminal and a second output electrical terminal each electrically coupled to the anode region and the cathode region.

[0236] Example implementation 26: An integrated thermoelectric converter, comprising: a silicon-based material layer having a first surface and a second surface opposite to the first surface, the second surface being separated from the first surface by a first thickness of the silicon-based material; a plurality of first thermoelectric active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient; and a plurality of second thermoelectric active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient; the first thermoelectric active elements and the second thermoelectric active elements each extending from the first surface through the silicon-based material layer; a conductive interconnect on at least one of the first surface or the second surface of the silicon-based material layer, each electrically contacting a first thermoelectric active element of the plurality of first thermoelectric active elements and a corresponding one of the plurality of second thermoelectric active elements; and an input electrical terminal and an output electrical terminal electrically coupled to the conductive interconnect, wherein the first thermoelectric semiconductor material and the second thermoelectric semiconductor material each comprise a silicon-based material selected from the group consisting of porous silicon, polycrystalline silicon germanium (SiGe), and polycrystalline silicon.

[0237] Example Implementation 27: The thermoelectric converter according to Example Implementation 26, wherein the silicon-based material layer is formed on a substrate having Si 0.7 Ge 0.3 The material is selected between polycrystalline SiGe or epitaxial polysilicon.

[0238] Example Implementation 28: The thermoelectric converter of Example Implementation 26, wherein the first thermoelectric semiconductor material having a first Seebeck coefficient is doped with an acceptor dopant, and the second thermoelectric semiconductor material having a second Seebeck coefficient is doped with a donor dopant.

[0239] Example implementation 29: A thermoelectric converter according to example implementation 26, wherein: each of the plurality of first thermoelectric active elements and the plurality of second thermoelectric active elements has a first end at the first surface of the silicon-based material layer and a second end at the second surface of the silicon-based material layer; and the conductive interconnect electrically connects: the first end of the first thermoelectric active element to the second end of the second thermoelectric active element; and the second end of the first thermoelectric active element to the second end of another second thermoelectric active element, so that the plurality of first thermoelectric active elements and the plurality of second thermoelectric active elements are coupled in series and alternate with each other.

[0240] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified to provide other embodiments.

[0241] In light of the above detailed description, these and other changes can be made to the embodiments. Generally, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which such claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A method for manufacturing a thermoelectric converter, comprising: forming a plurality of first thermoelectrically active elements of a first thermoelectric semiconductor material having a first Seebeck coefficient and a plurality of second thermoelectrically active elements of a second thermoelectric semiconductor material having a second Seebeck coefficient in a silicon-based material layer, the silicon-based material layer having a first surface, a second surface opposite the first surface, and a first thickness between the first surface and the second surface, the first thermoelectrically active elements and the second thermoelectrically active elements each being formed to extend from the first surface through the first thickness to the second surface; as well as forming conductive interconnects over at least one of the first surface or the second surface of the silicon-based material layer, the conductive interconnects each electrically interconnecting a first thermoelectrically active element of the plurality of first thermoelectrically active elements with a corresponding second thermoelectrically active element of the plurality of second thermoelectrically active elements; and forming input electrical terminals and output electrical terminals electrically coupled to the conductive interconnects, wherein the first thermoelectric semiconductor material and the second thermoelectric semiconductor material each comprise a silicon-based material selected from the group consisting of porous silicon, polycrystalline silicon germanium SiGe, and polycrystalline silicon; wherein forming the plurality of first thermoelectrically active elements and the plurality of second thermoelectrically active elements comprises: forming an annular groove surrounding each of the plurality of first thermoelectrically active elements and the plurality of second thermoelectrically active elements; The first thermoelectric active element includes a first portion of porous silicon and a second portion of polycrystalline silicon, wherein the second portion is between the first portion and the substrate.

2. The method according to claim 1, wherein the silicon-based material layer is formed on a substrate having Si 0.7 Ge 0.3 The material is selected from polycrystalline SiGe composed of a material or epitaxial polysilicon.

3. The method of claim 1 , wherein the plurality of first thermoelectric active elements of the first thermoelectric semiconductor material having a first Seebeck coefficient are doped with an acceptor dopant, and the plurality of second thermoelectric active elements of the second thermoelectric semiconductor material having a second Seebeck coefficient are doped with a donor dopant.

4. The method according to claim 1 , wherein the silicon-based material layer is polysilicon, and the method comprises: The polysilicon of the silicon-based material layer is epitaxially grown on the oxidized surface of the substrate.

5. The method of claim 4, wherein forming the plurality of first thermoelectric active elements of the first thermoelectric semiconductor material having the first Seebeck coefficient comprises: forming a first trench in the silicon-based material layer, and Filling the first trench with polysilicon or polycrystalline SiGe doped with an acceptor dopant; as well as wherein forming the plurality of second thermoelectric active elements of the second thermoelectric semiconductor material having the second Seebeck coefficient comprises: forming a second trench in the silicon-based material layer, and The second trench is filled with polysilicon or polycrystalline SiGe doped with a donor dopant.

6. The method according to claim 5, wherein each of the first trench and the second trench is filled with polysilicon, and the method further comprises: The doped polysilicon filling the first trench and the second trench is converted into doped porous silicon.

7. The method according to claim 1, comprising: Forming the silicon-based material layer includes: Iterate the following steps at least twice: forming a polycrystalline SiGe layer on the oxidized surface of the substrate, wherein the polycrystalline SiGe layer has a thickness that is a fraction of the first thickness of the silicon-based material layer; selectively doping the first region of the polycrystalline SiGe layer with an acceptor dopant; and selectively doping a second region of the polycrystalline SiGe layer with a donor dopant, wherein after said iteration, the stack of each of said polycrystalline SiGe layers has an overall thickness corresponding to said first thickness of said silicon-based material layer; and Trenches are formed in the stack of each of the poly-SiGe layers to obtain separate portions of the doped first region and the doped second region.

8. The method according to claim 1, further comprising: The silicon-based material layer is bonded to an amorphous silicon solar photovoltaic cell wafer.

9. The method of claim 8, wherein bonding the silicon-based material layer comprises: A conductive bonding layer is formed in electrical contact with the solar photovoltaic cell wafer, and a first electrical contact of the solar photovoltaic cell wafer is formed.

10. The method of claim 9, wherein the solar photovoltaic cell wafer comprises a first region of a first conductivity type, the method comprising: Dopant species are implanted to form a second region of a second conductivity type opposite to the first conductivity type, and a second electrical contact is formed electrically coupled to the second region.

11. An integrated thermoelectric converter, comprising: a first pillar structure comprising one of porous silicon, polycrystalline silicon germanium, or polycrystalline silicon, and being doped with a first conductivity type; a second pillar structure comprising one of porous silicon, polycrystalline silicon germanium, or polycrystalline silicon, and being doped with a second conductivity type; a first conductive interconnect structure in electrical contact with the first end of the first pillar structure and the first end of the second pillar structure; a plurality of annular grooves, respectively surrounding each of the first column structure and the second column structure; as well as A substrate, wherein the first pillar structure includes a first portion of porous silicon and a second portion of polycrystalline silicon, the second portion being between the first portion and the substrate.

12. The integrated thermoelectric converter according to claim 11, comprising: A first insulating structure surrounds the first pillar structure, and a second insulating structure surrounds the second pillar structure. 13 . The integrated thermoelectric converter of claim 11 , wherein the first pillar structure comprises polycrystalline silicon germanium, and the first pillar structure comprises a plurality of polycrystalline silicon germanium layers stacked on each other. The integrated thermoelectric converter of claim 11 , wherein the second portion of the first pillar structure is in contact with the substrate.

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