Overcurrent detection circuits, integrated devices, and battery management systems

Abstract

The present disclosure provides an overcurrent detection circuit for detecting overcurrent conditions in a battery / battery pack during charging and discharging. The circuit controls the charging and discharging of the battery / battery pack via a charge control transistor and a discharge control transistor connected in series with the battery / battery pack. The drain of the charge control transistor is connected to the drain of the discharge control transistor. The overcurrent detection circuit includes: a first detection transistor and a second detection transistor; a first voltage acquisition circuit and a second voltage acquisition circuit; a constant current source; and a comparison unit. The present disclosure also provides an integrated device and a battery management system.

Description

Technical Field

[0001] The present disclosure provides an overcurrent detection circuit, an integrated device, and a battery management system. Background Art

[0002] With the development of rechargeable battery technology, rechargeable batteries are now widely used in various fields such as power tools, portable devices, and electric vehicles. Rechargeable batteries are charged and supplied to power-consuming devices. However, during the charging and discharging process of rechargeable batteries, the charging and discharging currents need to be detected to avoid overcharging and over-discharging, thereby preventing safety accidents and shortening the battery life.

[0003] Therefore, in the event of overcurrent charging or overcurrent discharging, a warning should be issued or the rechargeable battery should be stopped. Currently, during overcurrent detection, the detected current is affected by factors such as the transistor manufacturing process and ambient temperature, so the detection is not accurate. Summary of the Invention

[0004] To address one of the aforementioned technical issues, the present disclosure provides an overcurrent detection circuit, integrated device, and battery management system. Compared to existing technologies, the technical solution of the present disclosure can more accurately detect overcurrent conditions during charge and discharge, without being affected by factors such as ambient temperature and transistor manufacturing processes.

[0005] According to one aspect of the present disclosure, an overcurrent detection circuit is provided. The overcurrent detection circuit is used to detect overcurrent conditions in the charge and discharge of a battery / battery pack. The charging and discharging of the battery / battery pack is controlled by a charge control transistor and a discharge control transistor connected in series with the battery / battery pack. The drain of the charge control transistor is connected to the drain of the discharge control transistor. The overcurrent detection circuit includes:

[0006] a first detection transistor and a second detection transistor, the first detection transistor and the second detection transistor being configured to detect the discharge current and / or the charge current, the drain of the first detection transistor being connected to the drains of the discharge control transistor and the charge control transistor, and the drain of the second detection transistor being connected to the drains of the discharge control transistor and the charge control transistor;

[0007] a first voltage acquisition circuit and a second voltage acquisition circuit, wherein an input end of the first voltage acquisition circuit is connected to the source of the first detection transistor, and an input end of the second voltage acquisition circuit is connected to the source of the second detection transistor;

[0008] a constant current source, configured to provide a constant current, wherein an output terminal of the constant current source is connected to a source of the first detection transistor; and

[0009] A comparison unit, wherein two input terminals of the comparison unit are respectively connected to the output terminal of the first voltage acquisition circuit and the output terminal of the second voltage acquisition circuit.

[0010] Optionally, a channel aspect ratio / number of cells of the first detection transistor and / or the second detection transistor is proportional to a channel aspect ratio / number of cells of the discharge control transistor and / or the charge control transistor;

[0011] Optionally, the on-resistance of the first detection transistor and / or the second detection transistor is proportional to the on-resistance of the discharge control transistor and / or the charge control transistor;

[0012] Optionally, an on-resistance of the first detection transistor and / or the second detection transistor is greater than an on-resistance of the discharge control transistor and / or the charge control transistor;

[0013] Optionally, the on-resistances of the first detection transistor and the second detection transistor, and / or the on-resistances of the discharge control transistor and / or the charge control transistor are the same;

[0014] Optionally, the first detection transistor, the second detection transistor, the discharge control transistor and the charge control transistor are integrated into one device;

[0015] Optionally, when detecting the discharge current and / or the charge current, the first detection transistor is turned on and the second detection transistor is turned off;

[0016] Optionally, the first transistor, the second transistor, the discharge control transistor and the charge control transistor are NMOS transistors or PMOS transistors of the same type.

[0017] Optionally, the comparison unit determines whether a discharge overcurrent occurs based on the current value of the constant current and the ratio of the on-resistance of the first detection transistor to the discharge control transistor or the charge control transistor; or the comparison unit determines whether a charge overcurrent occurs based on the current value of the constant current and the ratio of the on-resistance of the first detection transistor to the discharge control transistor or the charge control transistor.

[0018] Optionally, the first voltage acquisition unit includes a first switch and a first acquisition capacitor, and the second voltage acquisition circuit includes a second switch and a second acquisition capacitor. The first switch and the second switch are turned on or off at the same time, and through the conduction of the first switch and the second switch, the voltage of the source of the first detection transistor is transferred to the first acquisition capacitor and the voltage of the source of the second detection transistor is transferred to the second acquisition capacitor.

[0019] Optionally, optionally, the comparison unit is used to detect a discharge overcurrent condition, including: a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, a first control capacitor, a second control capacitor, a third control capacitor and a comparator, wherein the first end of the first control switch is connected to the voltage of the source of the first detection transistor, the second end of the first control switch is connected to the first end of the first control capacitor, the second end of the first control capacitor is connected to the positive input terminal of the comparator, the first end of the second control switch is connected to the second end of the first control capacitor, the second end of the second control switch is connected to the ground terminal, the first end of the third control switch is connected to the second end of the first control switch, the second end of the third control switch is connected to the common mode voltage, the first end of the second control capacitor is connected to the first control a first end of the fourth control switch connected to the voltage of the source of the second detection transistor, a second end of the fourth control switch connected to the first end of the third control capacitor, a second end of the third control capacitor connected to the negative input of the comparator, a first end of the fifth control switch connected to the second end of the third control capacitor, a second end of the fifth control switch connected to the ground, a first end of the sixth control switch connected to the second end of the fourth control switch, a second end of the sixth control switch connected to the common-mode voltage, the first control switch and the second control switch are turned on, the fourth control switch and the fifth control switch are controlled by the first switch control signal, the third control switch and the sixth control switch are controlled by the second switch control signal, and the first switch control signal and the second switch control signal are non-overlapping clock signals;

[0020] Optionally, the comparison unit is used to detect a charging overcurrent condition, which includes: a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, a first control capacitor, a second control capacitor, a third control capacitor and a comparator, wherein the first end of the first control switch is connected to the voltage of the source of the first detection transistor, the second end of the first control switch is connected to the first end of the first control capacitor, the second end of the first control capacitor is connected to the negative input terminal of the comparator, the first end of the second control switch is connected to the second end of the first control capacitor, the second end of the second control switch is connected to the ground terminal, the first end of the third control switch is connected to the second end of the first control switch, the second end of the third control switch is connected to the common mode voltage, the first end of the second control capacitor is connected to the first control capacitor The second end of the second control capacitor is connected to the ground end, the first end of the fourth control switch is connected to the voltage of the source of the second detection transistor, the second end of the fourth control switch is connected to the first end of the third control capacitor, the second end of the third control capacitor is connected to the positive input terminal of the comparator, the first end of the fifth control switch is connected to the second end of the third control capacitor, the second end of the fifth control switch is connected to the ground end, the first end of the sixth control switch is connected to the second end of the fourth control switch, and the second end of the sixth control switch is connected to the common mode voltage. The first control switch and the second control switch are turned on, the fourth control switch and the fifth control switch are controlled by the first switch control signal, the third control switch and the sixth control switch are controlled by the second switch control signal, and the first switch control signal and the second switch control signal are non-overlapping clock signals.

[0021] Optionally, a first end of the first switch of the first voltage acquisition unit is connected to the source of the first detection transistor, a second end of the first switch is connected to an input end of the comparison unit, a first end of the first acquisition capacitor is connected to the second end of the first switch, and a second end of the first acquisition capacitor is connected to the source of the second detection transistor via a third switch;

[0022] A first end of the second switch of the second voltage acquisition unit is connected to the source of the second detection transistor, a second end of the second switch is connected to the other input end of the comparison unit, a first end of the second acquisition capacitor is connected to the second end of the second switch, and a second end of the second acquisition capacitor is connected to the negative terminal of the battery / battery pack via a fourth switch.

[0023] Optionally, the comparison unit is used to detect discharge overcurrent, including a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch, a first control capacitor, a second control capacitor, a third control capacitor, and a comparator; the first end of the first control switch is connected to the voltage of the source of the first detection transistor, the second end of the first control switch is connected to the first end of the first control capacitor, the second end of the first control capacitor is connected to the positive input of the comparator, the first end of the second control switch is connected to the second end of the first control capacitor, the second end of the second control switch is connected to the ground, the first end of the third control switch is connected to the second end of the first control switch, the second end of the third control switch is connected to the ground, the first end of the second control capacitor is connected to the second end of the first control capacitor, and the second end of the second control capacitor is connected to the ground through the fourth control switch. The first end of the second control capacitor is connected to the ground through the fifth control switch, the second end of the second control capacitor is connected to the ground through the sixth control switch, the first end of the seventh control switch is connected to the voltage of the source of the second detection transistor, the second end of the seventh control switch is connected to the first end of the third control capacitor, and the second end of the third control capacitor is connected to the negative input of the comparator. a first end of the eighth control switch connected to the second end of the third control capacitor, a second end of the eighth control switch connected to the ground, a first end of the ninth control switch connected to the second end of the fourth control switch, and a second end of the ninth control switch connected to the ground;

[0024] Optionally, the comparison unit is used to detect charging overcurrent, and the comparison unit includes a comparator, a negative input terminal of the comparator is connected to the voltage of the source of the second detection transistor, and a positive input terminal of the comparator is connected to the negative terminal of the battery / battery pack.

[0025] Optionally, the number of the first detection transistor and the second detection transistor is one or more. When the number of the first detection transistor and the second detection transistor is two or more, the two or more first detection transistors are connected in parallel between the drain of the discharge control transistor and the input end of the first voltage acquisition unit, and one first detection transistor is selected by a gating switch. The two or more second detection transistors are connected in parallel between the drain of the charge control transistor and the input end of the first voltage acquisition unit, and one second detection transistor is selected by the gating switch.

[0026] Optionally, the on-resistances of the two or more first detection transistors are proportional, and / or the on-resistances of the two or more second detection transistors are proportional;

[0027] Optionally, the channel aspect ratios of two or more first detection transistors are proportional to the number of cells, and / or the channel aspect ratios of two or more second detection transistors are proportional to the number of cells, and / or the channel aspect ratios of the second detection transistor and the charging control transistor are proportional to the number of cells, and / or the channel aspect ratios of the first detection transistor and the second detection transistor are the same as the channel aspect ratios of the second detection transistor and the number of cells and are proportional to the channel aspect ratios of the discharge control transistor and the charging control transistor.

[0028] Optionally, the constant current is a constant current that is independent of temperature;

[0029] A calibration resistor is also included, which is connected between the output terminal of the current source and the ground terminal to calibrate the on-resistance of the constant current, the discharge control transistor, the charge control transistor, the first transistor, and / or the second transistor so as to be independent of temperature.

[0030] According to another aspect of the present disclosure, an integrated device is provided, wherein the integrated device integrates at least a discharge control transistor, a charge control transistor, a first detection transistor, and a second detection transistor in the overcurrent detection circuit as described in any one of the above items.

[0031] According to another aspect of the present disclosure, a battery management system includes:

[0032] The overcurrent detection circuit as described in any one of the above items or the integrated device as described in claim 1; and

[0033] a logic control circuit for providing gate control signals to the discharge control transistor, the charge control transistor, the first detection transistor, and the second detection transistor so as to control the on and off of the discharge control transistor, the charge control transistor, the first detection transistor, and the second detection transistor;

[0034] Optionally, the logic control circuit generates the gate control signal according to an overcurrent condition. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure. These drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification.

[0036] Figure 1 A schematic diagram of an overcurrent detection circuit according to one embodiment of the present disclosure is shown.

[0037] Figure 2 A schematic diagram of a comparison unit according to one embodiment of the present disclosure is shown.

[0038] Figure 3 A schematic diagram of a switch control signal according to one embodiment of the present disclosure is shown.

[0039] Figure 4 A schematic diagram of a comparison unit according to one embodiment of the present disclosure is shown.

[0040] Figure 5 A schematic diagram of an overcurrent detection circuit according to one embodiment of the present disclosure is shown.

[0041] Figure 6 A schematic diagram of a comparison unit according to one embodiment of the present disclosure is shown.

[0042] Figure 7 A schematic diagram of a comparison unit according to one embodiment of the present disclosure is shown.

[0043] Figure 8 A schematic diagram of a comparator according to one embodiment of the present disclosure is shown.

[0044] Figure 9 A schematic diagram of a battery management system according to one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0045] The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only intended to explain the relevant content and are not intended to limit the present disclosure. It should also be noted that, for ease of description, only the portions relevant to the present disclosure are shown in the accompanying drawings.

[0046] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure can be combined with each other. The technical solution of the present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0047] Unless otherwise stated, the exemplary embodiments / examples shown are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure can be implemented in practice. Therefore, unless otherwise stated, the features of the various embodiments / examples may be further combined, separated, interchanged, and / or rearranged without departing from the technical concepts of the present disclosure.

[0048] The use of cross hatching and / or shading in the accompanying drawings is generally used to make the boundaries between adjacent components clear. As such, unless otherwise indicated, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific materials, material properties, dimensions, proportions, commonalities between the components shown, and / or any other characteristics, attributes, properties, etc. of the components. In addition, in the accompanying drawings, the sizes and relative sizes of the components may be exaggerated for clarity and / or descriptive purposes. When the exemplary embodiments can be implemented differently, the specific process sequence can be performed in a different order than described. For example, two successively described processes can be performed substantially simultaneously or in an order opposite to the order described. In addition, the same figure numbers represent the same components.

[0049] When a component is referred to as being “on,” “over,” “connected to,” or “coupled to” another component, the component may be directly on, directly connected to, or directly coupled to the other component, or intervening components may be present. However, when a component is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another component, there are no intervening components present. For this purpose, the term “connected” may refer to a physical connection, an electrical connection, etc., with or without intervening components.

[0050] For descriptive purposes, the present disclosure may use spatially relative terms such as "below," "beneath," "under," "down," "above," "upper," "above," "higher," and "side (e.g., as in "sidewall")," to describe the relationship of one component to another (other) component as shown in the accompanying drawings. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientation depicted in the accompanying drawings. For example, if the device in the drawings is turned over, a component described as "below" or "beneath" another component or feature would then be positioned "above" the other component or feature. Thus, the exemplary term "below" can encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and as such, the spatially relative descriptors used herein should be interpreted accordingly.

[0051] The terms used herein are for the purpose of describing specific embodiments and are not intended to be restrictive. As used herein, unless the context clearly indicates otherwise, the singular forms "one (kind, person)" and "said (the)" are also intended to include plural forms. In addition, when the terms "comprise" and / or "include" and their variations are used in this specification, the features, integral bodies, steps, operations, parts, assemblies and / or their groups stated are explained, but the presence or addition of one or more other features, integral bodies, steps, operations, parts, assemblies and / or their groups is not excluded. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and not as degree terms, so that they are used to explain the inherent deviations of the measured values, calculated values and / or the values provided that will be recognized by those of ordinary skill in the art.

[0052] According to one embodiment of the present disclosure, a charge and discharge current overcurrent detection circuit is provided. The charge and discharge current overcurrent detection circuit can be used to detect overcurrent conditions of the charging current and the discharging current of a battery pack.

[0053] Figure 1 A charge / discharge current overcurrent detection circuit according to one embodiment of the present disclosure is shown. This charge / discharge current overcurrent detection circuit can be used to detect overcurrent conditions in a battery or battery pack. Furthermore, the charge / discharge current overcurrent detection circuit of the present disclosure can achieve more accurate detection of charge / discharge current overcurrent conditions.

[0054] The charge and discharge current overcurrent detection circuit may include a discharge control transistor MD and a charge control transistor MC, wherein the discharge control transistor MD and the charge control transistor MC may be NMOS transistors or PMOS transistors. Figure 1 Although the discharge control transistor MD and the charge control transistor MC are shown as being located at the low-voltage side of the negative terminal of the battery, those skilled in the art will appreciate that they can also be located at the high-voltage side of the positive terminal of the battery. The following description will use the low-voltage side as an example. The principles for the high-voltage side are the same and will not be further elaborated here.

[0055] Figure 1 shows the discharge current overcurrent detection situation, as shown in Figure 1As shown, the source S1 of the discharge control transistor MD can be connected to the negative terminal B- of the battery pack BAT, and the drain D of the discharge control transistor MD can be connected to the drain D of the charge control transistor MC, and the drain S2 of the charge control transistor MC can be connected to the negative terminal P- of the load LOAD. Alternatively, the source S2 of the charge control transistor MC can be connected to the negative terminal of the battery pack BAT, and the drain D of the charge control transistor MC can be connected to the drain D of the discharge control transistor MD, and the drain S1 of the discharge control transistor MD can be connected to the load LOAD.

[0056] In addition, a reverse-connected parasitic diode D1 may exist between the source S1 and the drain D of the discharge control transistor MD, and a reverse-connected parasitic diode D2 may exist between the source S2 and the drain D of the charge control transistor MC.

[0057] A discharge control signal DSG is supplied to the gate of the discharge control transistor MD to control the on / off state of the discharge control transistor MD, thereby controlling the discharge of the battery pack BAT. A charge control signal CHG is supplied to the gate of the charge control transistor MC to control the on / off state of the charge control transistor MC, thereby controlling the charging of the battery pack BAT.

[0058] The charge and discharge current overcurrent detection circuit may further include a first detection transistor MS1 and a second detection transistor MS2 . The drain D of the first detection transistor MS1 may be connected to the drain D of the discharge control transistor MD, and the drain D of the second detection transistor MS2 may be connected to the drain of the charge control transistor MC.

[0059] In addition, a reverse-connected parasitic diode D3 may exist between the source S3 and the drain D of the first detection transistor MS1 , and a reverse-connected parasitic diode D4 may exist between the source S4 and the drain D of the second detection transistor MS2 .

[0060] By providing a discharge current detection control signal DSG1 to the gate of the first detection transistor MS1, the first detection transistor MS1 is controlled to be turned on and off, thereby controlling the detection of the discharge current. By providing a charge current detection control signal CHG1 to the gate of the second detection transistor MS2, the second detection transistor MS2 is controlled to be turned on and off, thereby controlling the detection of the charge current. It should be noted that although Figure 2 The following figures show that the discharge control signal DSG and the discharge current detection control signal DSG1 are the same signal, but they can also be different control signals. Figure 2The following figures show that the charging control signal CHG and the charging current detection control signal CHG1 are the same signal, but they can also be different control signals. It should be noted that in the present disclosure, the first detection transistor can detect the charging current and the discharging current, and it can also remain in the on state, and the second detection transistor can remain in the off state, and the corresponding current can flow through the parasitic diode.

[0061] The charge and discharge current overcurrent detection circuit may further include a constant current source, and the constant current source may generate a constant current IREF according to the voltage AVDD, wherein the constant current IREF does not change with temperature.

[0062] The charge and discharge current overcurrent detection circuit may further include a first voltage acquisition unit and a second voltage acquisition unit. The first voltage acquisition unit is used to acquire the voltage of the source S3 of the first detection transistor MS1, and the second voltage acquisition unit is used to acquire the voltage of the source S4 of the second detection transistor MS2 (that is, the voltage of the drain D during the discharge current detection process).

[0063] As an example of the present disclosure, the first voltage acquisition unit may include a first switch and a first capacitor. The first end of the first switch is connected to the source terminal of the first detection transistor MS1, the second end of the first switch is connected to the first end of the first capacitor, and the second end of the first capacitor is grounded. The source S4 of the second detection transistor MS2 is also connected to the second voltage acquisition circuit, which may include a second switch and a second capacitor. The first end of the second switch is connected to the source S4 of the second detection transistor MS2, the second end of the second switch is connected to the first end of the second capacitor, and the second end of the second capacitor is grounded. In the present disclosure (including the following description), the ground terminal can be the negative terminal B- of the battery / battery pack, or the negative terminal P- of the load / charger. For example, the ground terminal can preferably be the negative terminal B- of the battery / battery pack.

[0064] The first voltage acquisition unit outputs the voltage VS3 of the source S3 of the first detection transistor MS1 , and the second voltage acquisition unit outputs the voltage VS4 of the source S4 of the second detection transistor MS2 (ie, the voltage of the drain D).

[0065] In addition, although not shown in the accompanying drawings, a first end of the first capacitor can be connected via a first analog-to-digital converter to detect the voltage of the first capacitor, and a first end of the second capacitor can be connected via a second analog-to-digital converter to detect the voltage of the second capacitor. The first analog-to-digital converter and the second analog-to-digital converter can be the same analog-to-digital converter or different analog-to-digital converters. In addition, a reference voltage generation circuit can be used to provide a reference voltage to the analog-to-digital converter so as to serve as a reference voltage for the analog-to-digital converter to perform digital signal conversion. In addition, the reference voltage generation circuit is used to provide a reference voltage that is independent of temperature.

[0066] In the present disclosure, more than two first detection transistors MS1 may be included, and each first detection transistor MS1 is connected in the same manner. In addition, more than two second detection transistors MS2 may be included, and each second detection transistor MS2 is connected in the same manner.

[0067] In the case of certain types of transistors, the channel length-to-width ratio of the first detection transistor can be proportional to the channel length-to-width ratio of the discharge control transistor MD, and the ratio can be 100, 1000, 10,000, etc. The channel length-to-width ratio of the second detection transistor can be proportional to the channel length-to-width ratio of the charge control transistor MC, and the ratio can be 100, 1000, 10,000, etc. In this way, the on-resistance of the first detection transistor can be proportional to the on-resistance of the discharge control transistor MD, and the on-resistance of the second detection transistor can be proportional to the on-resistance of the charge control transistor MC.

[0068] In the case of certain types of transistors, the number of cells of the first detection transistor can be proportional to the number of cells of the discharge control transistor MD, and the ratio can be 100, 1000, or 10,000, etc. The number of cells of the second detection transistor can be proportional to the number of cells of the charge control transistor MC, and the ratio can be 100, 1000, or 10,000, etc. This can make the on-resistance of the first detection transistor and the on-resistance of the discharge control transistor MD also have the same ratio, and the on-resistance of the second detection transistor and the on-resistance of the charge control transistor MC also have the same ratio. In addition, the channel aspect ratio / number of cells of the first detection transistor and the channel aspect ratio / number of cells of the second detection transistor can be set to be the same and proportional to the channel aspect ratio / number of cells of the discharge control transistor MD and the channel aspect ratio / number of cells of the charge control transistor MC.

[0069] In the present disclosure, the discharge control transistor MD, the first detection transistor, the second detection transistor and the charge control transistor MC are integrated into one device, so that when the temperature or process conditions change, the on-resistance of the discharge control transistor MD, the first detection transistor, the second detection transistor and the charge control transistor MC can be ensured to change accordingly at the same time.

[0070] When the battery pack BAT is under discharge control, the discharge control signal DSG and the discharge current detection control signal DSG1 are at a high level, while the charge control signal CHG and the charge current detection control signal CHG1 are at a low level, so that the discharge control transistor MD is turned on, the first detection transistor MS1 is turned on, the charge control transistor MC is turned off, and the second detection transistor MS2 is turned off.

[0071] In this case, the discharge current ILOAD flows from the positive terminal of the battery pack BAT through the load LOAD and to the negative terminal of the battery pack BAT, and the constant current IREF may flow to the discharge control transistor MD via the first detection transistor MS1.

[0072] During battery pack discharge, due to the direction of discharge current ILOAD, the voltage VD at the drain terminal D is positive relative to the negative terminal of the battery pack. The voltage VS3 at the source terminal S3 of the first sensing transistor MS1 is calculated as follows: VS3 = IREF × Ron(MS1) + VD, where IREF is the constant current and Ron(MS1) is the on-resistance of the first sensing transistor MS1. During discharge, VS4 equals VD because the second sensing transistor MS2 is off.

[0073] At the same time, VD=ILOAD×Ron(MD), where ILOAD is the current value of the discharge current, and Ron(MD) is the on-resistance value of the discharge control transistor MD.

[0074] Set VK=V3S×K, where K is the proportional coefficient. In the case of VD>VK, VD>VS3×K=K×(IREF×Ron(MS1)+VD), that is,

[0075] Since VD=ILOAD×Ron(MD),

[0076] Wherein, M is the ratio of the on-resistance of the first detection transistor to the on-resistance of the discharge control transistor.

[0077] The comparison unit is used to receive VS3 and VS4 (VD), and when the output of the comparison unit is 1, it is considered that the discharge current is in an overcurrent state.

[0078] The specific form of the comparison unit will be described in detail below. Figure 2 A comparison unit according to one embodiment of the present disclosure is shown, in which offset voltage and the like can be effectively suppressed, thereby making detection more accurate. Figure 3 Shown Figure 2 Switch control signal for the switch shown.

[0079] like Figure 2 As shown, the comparison unit may include a first control switch S1, a second control switch S2, a third control switch S3, a fourth control switch S4, a fifth control switch S5, a sixth control switch S6, a first control capacitor C1a, a second control capacitor C1b and a third control capacitor C2.

[0080] A first end of the first control switch is connected to the voltage VS3 at the source of the first detection transistor, and a second end of the first control switch is connected to the first end of the first control capacitor. The second end of the first control capacitor is connected to the positive input of the comparator. A first end of the second control switch is connected to the second end of the first control capacitor, and the second end of the second control switch is connected to ground. A first end of the third control switch is connected to the second end of the first control switch, and the second end of the third control switch is connected to a first voltage VCM (common mode voltage). A first end of the second control capacitor is connected to the second end of the first control capacitor, and the second end of the second control capacitor is connected to ground.

[0081] A first terminal of the fourth control switch is connected to the voltage VS4 at the source of the second detection transistor, and a second terminal of the fourth control switch is connected to the first terminal of the third control capacitor. The second terminal of the third control capacitor is connected to the negative input terminal of the comparator. A first terminal of the fifth control switch is connected to the second terminal of the third control capacitor, and a second terminal of the fifth control switch is connected to ground. A first terminal of the sixth control switch is connected to the second terminal of the fourth control switch, and a second terminal of the sixth control switch is connected to the first voltage VCM (common mode voltage).

[0082] The switch control signals φ1 and φ2 are used as switch control signals to control the respective switches. Figure 3 As shown, the two switch control signals are non-overlapping clock signals.

[0083] When switch control signal φ1 is high and φ2 is low, the first and second control switches are turned on, the third control switch is turned off, the fourth and fifth control switches are turned on, and the sixth control switch is turned off. In this way, the first control capacitor C1a samples the voltage of VS3, and the third control capacitor C2 samples the voltage of VS4.

[0084] When the switch control signal φ2 is at a high level and φ1 is at a low level, the first control switch and the second control switch are turned off, the third control switch is turned on, the fourth control switch and the fifth control switch are turned off, and the sixth control switch is turned on.

[0085] The voltage V1 at the positive input of the comparator is as follows.

[0086] Wherein VCM is the voltage value of the first voltage, C1a is the capacitance value of the first control capacitor, C1b is the capacitance value of the second control capacitor, is the proportionality coefficient K mentioned above.

[0087] The voltage V2 at the negative input terminal of the comparator is V2 = VCM - VS4 = VCM - VD.

[0088] If VD>K×VS3, then VCM-VD<VCM-K×VS3, that is, V1>V2.

[0089] According to the calculation formula of VS3 and VD above, it can be concluded that ILOAD is too large, and discharge overcurrent will occur.

[0090] As shown above, since the on-resistance of the first detection transistor MS1 is significantly greater than the on-resistance of the discharge control transistor MD, the voltage value generated by the current value IREF of the constant current in the discharge control transistor MD will be significantly smaller than the voltage value generated by the current value IREF of the constant current in the first detection transistor MS1. Therefore, the voltage value generated by the current value IREF of the constant current in the discharge control transistor MD can be omitted in the above formula.

[0091] During the process of detecting the voltage at the source S3 end of the first detection transistor MS1, the first switch of the first voltage acquisition unit can be turned on, so that the charge will be transferred to the first capacitor, and the voltage across the first capacitor will be equal to the voltage at the source S3 end of the first detection transistor MS1, and the voltage VS3 will be detected by the first analog-to-digital converter.

[0092] In addition, the voltage VS4 at the source S4 of the second detection transistor MS2 is simultaneously detected by the second voltage acquisition circuit. During the detection process, the second switch of the second voltage acquisition circuit can be turned on, so that the charge will be transferred to the second capacitor, and the second capacitor will be equal to VS4. The voltage VS4 is detected by the second analog-to-digital converter. It should be noted that in the present disclosure, it is necessary to detect voltages VS3 and VS4 simultaneously. If the detection is not performed simultaneously, whether during the charging process or the discharging process, the charging current and the discharging current will change with time, which will cause errors, for example, due to the influence of temperature.

[0093] In the above formula, the coefficient M is the ratio of the on-resistance of the first detection transistor MS1 to the on-resistance of the discharge control transistor MD. Since the two are integrated into a single device, their on-resistances will vary accordingly with changes in ambient temperature and manufacturing process. Therefore, the coefficient M will not be affected by changes in ambient temperature and manufacturing process. The proportional coefficient K is limited by the capacitance, and the temperature coefficient of the capacitance itself is low. Since different capacitors are at the same temperature, the proportional coefficient K will not change due to the influence of ambient temperature. Therefore, according to the method disclosed in the present invention, a discharge current detection value that is completely unaffected by changes in ambient temperature and manufacturing process can be obtained.

[0094] In addition, the charge and discharge current overcurrent detection circuit may further include an external resistor REXT, which can be used for calibration. When a constant current flows through the external resistor REXT and the first detection transistor MS1, the voltage generated by the external resistor REXT and the voltage generated by the on-resistance of the first detection transistor MS1 can be compared to calibrate the on-resistance of the first detection transistor MS1, thereby also correspondingly calibrating the discharge control transistor MD. In the present disclosure, it is preferred that the constant current IREF be calibrated by the external resistor REXT so that the constant current IREF is completely independent of temperature. For example, the external resistor REXT can be selected as a low temperature coefficient resistor or a zero temperature coefficient resistor, for example, the temperature coefficient can be 10ppm / ℃. In the process of calibrating the constant current IREF, the voltage of the external resistor can be measured. For example, at 27℃, if the actual measured voltage of the external resistor is inconsistent with the reference voltage (pre-stored), it indicates that the constant current IREF is affected by temperature and changes. In order to eliminate this influence, the constant current IREF value can be adjusted according to the inconsistency. In addition, the inconsistency can also be considered in the processing of analog-to-digital converters or logic control units, for example, by setting corresponding coefficients according to the inconsistency, so that the inconsistency is eliminated.

[0095] According to the embodiments of the present disclosure, those skilled in the art should understand that the embodiments can perfectly realize accurate detection of the discharge current without being affected by changes in ambient temperature and manufacturing process.

[0096] In an optional embodiment of the present disclosure, the number of first detection transistors and / or second detection transistors can be more than two, and the on-resistance of each first detection transistor can be set proportionally and the on-resistance of each second detection transistor can also be set proportionally, for example, 100, 1000, etc., and are set in parallel. In this case, a suitable first detection transistor and / or second detection transistor can be selected according to the size of the discharge current value. The on-resistance value of the first detection transistor is significantly greater than the on-resistance value of the discharge control transistor MD. In the case of a relatively small discharge current, if a first detection transistor with a large on-resistance is selected, the voltage generated by the first detection transistor will overwhelm the voltage generated by the discharge control transistor MD, thereby making the overcurrent detection of the discharge current inaccurate. By switching the first detection transistors of different proportions, the overcurrent detection of the discharge current can be made more accurate.

[0097] Figure 4 FIG4 shows the setting of the comparison unit in the case of overcurrent detection of the charging current ICHG. Figure 2 The difference between the arrangement of the comparison unit shown is that V1 is connected to the negative input terminal of the comparator and V2 is connected to the positive input terminal of the comparator. Figure 2 The principle of charging current overcurrent detection is the same as that of discharging current overcurrent detection, and will not be described in detail here.

[0098] In addition, although the effect is not ideal, as a simple example, one input terminal of the comparator can be connected to VS3 or VS4, and the other terminal can be grounded, so as to perform discharge current overcurrent detection and charging current overcurrent detection respectively.

[0099] According to a further embodiment of the present disclosure, a charge-discharge current overcurrent detection circuit is provided. The charge-discharge current overcurrent detection circuit of this embodiment can achieve more accurate detection of charge-discharge current overcurrent.

[0100] The charge and discharge current overcurrent detection circuit may include a discharge control transistor MD and a charge control transistor MC, wherein the discharge control transistor MD and the charge control transistor MC may be NMOS transistors or PMOS transistors. Figure 5 Although the discharge control transistor MD and the charge control transistor MC are shown as being located at the low-voltage side of the negative terminal of the battery, those skilled in the art will appreciate that they can also be located at the high-voltage side of the positive terminal of the battery. The following description will use the low-voltage side as an example. The principles for the high-voltage side are the same and will not be further elaborated here.

[0101] Figure 5 shows the discharge current overcurrent detection situation, as shown in Figure 5As shown, the source S1 of the discharge control transistor MD can be connected to the negative terminal of the battery pack BAT, and the drain D of the discharge control transistor MD can be connected to the drain D of the charge control transistor MC, and the drain S2 of the charge control transistor MC can be connected to the load LOAD. Alternatively, the source S2 of the charge control transistor MC can be connected to the negative terminal of the battery pack BAT, and the drain D of the charge control transistor MC can be connected to the drain D of the discharge control transistor MD, and the drain S1 of the discharge control transistor MD can be connected to the load LOAD.

[0102] In addition, a reverse-connected parasitic diode D1 may exist between the source S1 and the drain D of the discharge control transistor MD, and a reverse-connected parasitic diode D2 may exist between the source S2 and the drain D of the charge control transistor MC.

[0103] A discharge control signal DSG is supplied to the gate of the discharge control transistor MD to control the on / off state of the discharge control transistor MD, thereby controlling the discharge of the battery pack BAT. A charge control signal CHG is supplied to the gate of the charge control transistor MC to control the on / off state of the charge control transistor MC, thereby controlling the charging of the battery pack BAT.

[0104] The charge and discharge current overcurrent detection circuit may further include a first detection transistor MS1 and a second detection transistor MS2 . The drain D of the first detection transistor MS1 may be connected to the drain D of the discharge control transistor MD, and the drain D of the second detection transistor MS2 may be connected to the drain of the charge control transistor MC.

[0105] In addition, a reverse-connected parasitic diode D3 may exist between the source S3 and the drain D of the first detection transistor MS1 , and a reverse-connected parasitic diode D4 may exist between the source S4 and the drain D of the second detection transistor MS2 .

[0106] By providing a discharge current detection control signal DSG1 to the gate of the first detection transistor MS1, the first detection transistor MS1 is controlled to be turned on and off, thereby controlling the detection of the discharge current. By providing a charge current detection control signal CHG to the gate of the second detection transistor MS2, the second detection transistor MS2 is controlled to be turned on and off, thereby controlling the detection of the charge current. It should be noted that although Figure 5 The following figures show that the discharge control signal DSG and the discharge current detection control signal DSG1 are the same signal, but they can also be different control signals. Figure 5 The following figures show that the charging control signal CHG and the charging current detection control signal CHG1 are the same signal, but they can also be different control signals.

[0107] The charge and discharge current overcurrent detection circuit may further include a constant current source, and the constant current source may generate a constant current IREF according to the voltage AVDD, wherein the constant current IREF does not change with temperature.

[0108] The charge and discharge current overcurrent detection circuit may further include a first voltage acquisition unit and a second voltage acquisition unit. The first voltage acquisition unit is used to acquire the voltage of the source S3 of the first detection transistor MS1, and the second voltage acquisition unit is used to acquire the voltage of the source S4 of the second detection transistor MS2 (that is, the voltage of the drain D during the discharge current detection process).

[0109] As an example of the present disclosure, the first voltage acquisition unit may include a first switch SW1 and a first capacitor CS1. A first end of the first switch SW1 is connected to the source of the first detection transistor MS1, a second end of the first switch SW1 is connected to the first end of the first capacitor CS1, and a second end of the first capacitor CS1 is grounded. A source S4 of the second detection transistor MS2 is also connected to a second voltage acquisition circuit, which may include a second switch SW2 and a second capacitor CS2. A first end of the second switch SW2 is connected to the source S4 of the second detection transistor MS2, a second end of the second switch SW2 is connected to the first end of the second capacitor, and a second end of the second capacitor CS2 is grounded.

[0110] The first voltage acquisition unit outputs the voltage VS3 of the source S3 of the first detection transistor MS1 , and the second voltage acquisition unit outputs the voltage VS4 of the source S4 of the second detection transistor MS2 (ie, the voltage of the drain D).

[0111] In addition, although not shown in the accompanying drawings, a first end of the first capacitor can be connected via a first analog-to-digital converter to detect the voltage of the first capacitor, and a first end of the second capacitor can be connected via a second analog-to-digital converter to detect the voltage of the second capacitor. The first analog-to-digital converter and the second analog-to-digital converter can be the same analog-to-digital converter or different analog-to-digital converters. In addition, a reference voltage generation circuit can be used to provide a reference voltage to the analog-to-digital converter so as to serve as a reference voltage for the analog-to-digital converter to perform digital signal conversion. In addition, the reference voltage generation circuit is used to provide a reference voltage that is independent of temperature.

[0112] In the present disclosure, more than two first detection transistors MS1 may be included, and each first detection transistor MS1 is connected in the same manner. In addition, more than two second detection transistors MS2 may be included, and each second detection transistor MS2 is connected in the same manner.

[0113] In the case of certain types of transistors, the channel length-to-width ratio of the first detection transistor can be proportional to the channel length-to-width ratio of the discharge control transistor MD, and the ratio can be 100, 1000, 10,000, etc. The channel length-to-width ratio of the second detection transistor can be proportional to the channel length-to-width ratio of the charge control transistor MC, and the ratio can be 100, 1000, 10,000, etc. In this way, the on-resistance of the first detection transistor can be proportional to the on-resistance of the discharge control transistor MD, and the on-resistance of the second detection transistor can be proportional to the on-resistance of the charge control transistor MC.

[0114] In the case of certain types of transistors, the number of cells of the first detection transistor can be proportional to the number of cells of the charge and / or discharge control transistor MD, and the ratio can be 100, 1000, or 10,000, etc. The number of cells of the second detection transistor can be proportional to the number of cells of the charge and / or discharge control transistor MC, and the ratio can be 100, 1000, or 10,000, etc. This can make the on-resistance of the first detection transistor and the on-resistance of the discharge control transistor MD also have the same ratio, and the on-resistance of the second detection transistor and the on-resistance of the charge control transistor MC also have the same ratio. In addition, the channel aspect ratio / number of cells of the first detection transistor and the channel aspect ratio / number of cells of the second detection transistor can be set to be the same and proportional to the channel aspect ratio / number of cells of the discharge control transistor MD and the channel aspect ratio / number of cells of the charge control transistor MC.

[0115] In the present disclosure, the discharge control transistor MD, the first detection transistor, the second detection transistor and the charge control transistor MC are integrated into one device, so that when the temperature or process conditions change, the on-resistance of the discharge control transistor MD, the first detection transistor, the second detection transistor and the charge control transistor MC can be ensured to change accordingly at the same time.

[0116] When the battery pack BAT is under discharge control, the discharge control signal DSG and the discharge current detection control signal DSG1 are at a high level, while the charge control signal CHG and the charge current detection control signal CHG1 are at a low level, so that the discharge control transistor MD is turned on, the first detection transistor MS1 is turned on, the charge control transistor MC is turned off, and the second detection transistor MS2 is turned off.

[0117] In this case, the discharge current ILOAD flows from the positive terminal of the battery pack BAT through the load LOAD and to the negative terminal of the battery pack BAT, and the constant current IREF may flow to the discharge control transistor MD via the first detection transistor MS1.

[0118] During battery pack discharge, due to the direction of discharge current ILOAD, the voltage VD at the drain terminal D is positive relative to the negative terminal of the battery pack. The voltage VS3 at the source terminal S3 of the first sensing transistor MS1 is calculated as follows: VS3 = IREF × Ron(MS1) + VD, where IREF is the constant current and Ron(MS1) is the on-resistance of the first sensing transistor MS1. During discharge, VS4 equals VD because the second sensing transistor MS2 is off.

[0119] At the same time, VD=ILOAD×Ron(MD), where ILOAD is the current value of the discharge current, and Ron(MD) is the on-resistance value of the discharge control transistor MD.

[0120] Set VK=V3S×K, where K is the proportional coefficient. In the case of VD>VK, VD>VS3×K=K×(IREF×Ron(MS1)+VD), that is,

[0121] Since VD=ILOAD×Ron(MD),

[0122] Wherein, M is the ratio of the on-resistance of the first detection transistor to the on-resistance of the discharge control transistor.

[0123] The comparison unit is used to receive VS3 and VS4 (VD), and when the output of the comparison unit is 1, it is considered that the discharge current is in an overcurrent state.

[0124] The specific form of the comparison unit will be described in detail below. Figure 6 FIG1 shows a comparison unit according to an embodiment of the present disclosure. In the comparison unit, the offset voltage and the like can be effectively suppressed, thereby making the detection more accurate. Figure 6 The control signals of each switch can be Figure 3 The signal format is shown.

[0125] like Figure 6 As shown, the comparison unit may include a first control switch S11, a second control switch S12, a third control switch S13, a fourth control switch S14, a fifth control switch S15, a sixth control switch S16, a seventh control switch S17, an eighth control switch S18, a ninth control switch S19, a first control capacitor C11a, a second control capacitor C11b and a third control capacitor C12.

[0126] The first end of the first control switch is connected to the voltage VS3 at the source of the first detection transistor, and the second end of the first control switch is connected to the first end of the first control capacitor. The second end of the first control capacitor is connected to the positive input of the comparator. The first end of the second control switch is connected to the second end of the first control capacitor, and the second end of the second control switch is connected to the ground. The first end of the third control switch is connected to the second end of the first control switch, and the second end of the third control switch is connected to the ground. The first end of the second control capacitor is connected to the second end of the first control capacitor, and the second end of the second control capacitor is connected to the ground via the fourth control switch. The first end of the second control capacitor is connected to the ground via the fifth control switch, and the second end of the second control capacitor is connected to the ground via the sixth control switch.

[0127] A first end of the seventh control switch is connected to the voltage VS4 at the source of the second detection transistor, and a second end of the seventh control switch is connected to the first end of the third control capacitor. The second end of the third control capacitor is connected to the negative input terminal of the comparator. A first end of the eighth control switch is connected to the second end of the third control capacitor, and the second end of the eighth control switch is connected to the ground terminal. A first end of the ninth control switch is connected to the second end of the fourth control switch, and the second end of the ninth control switch is connected to the ground terminal.

[0128] The switch control signals φ1 and φ2 are used as switch control signals to control the respective switches. Figure 3 As shown, the two switch control signals are non-overlapping clock signals.

[0129] When the switch control signal φ1 is at a high level and φ2 is at a low level, the first control switch, the second control switch, the fourth control switch, the fifth control switch, the seventh control switch, and the eighth control switch are turned on, and the third control switch, the sixth control switch, and the ninth control switch are turned off. In this way, the first control capacitor C1a collects the voltage of VS3, and the third control capacitor C2 collects the voltage of VS4.

[0130] When the switch control signal φ2 is at a high level and φ1 is at a low level, the first control switch and the second control switch are turned off, the third control switch is turned on, the fourth control switch and the fifth control switch are turned off, and the sixth control switch is turned on.

[0131] The voltage at the positive input of the comparator is The voltage at the negative input terminal of the comparator is V2 = -VS4 = -VD.

[0132]

[0133] final,

[0134] when When ILOAD×RonMD>IREF×RonM1S, then ILOAD>M×IREF, where M is the ratio of RonMS1 to RonMD. At this time, the comparator output is 1, indicating discharge overcurrent.

[0135] As shown above, since the on-resistance of the first detection transistor MS1 is significantly greater than the on-resistance of the discharge control transistor MD, the voltage value generated by the current value IREF of the constant current in the discharge control transistor MD will be significantly smaller than the voltage value generated by the current value IREF of the constant current in the first detection transistor MS1. Therefore, the voltage value generated by the current value IREF of the constant current in the discharge control transistor MD can be omitted in the above formula.

[0136] During the process of detecting the voltage at the source S3 end of the first detection transistor MS1, the first switch of the first voltage acquisition unit can be turned on, so that the charge will be transferred to the first capacitor, and the voltage across the first capacitor will be equal to the voltage at the source S3 end of the first detection transistor MS1, and the voltage VS3 will be detected by the first analog-to-digital converter.

[0137] In addition, the voltage VS4 at the source S4 of the second detection transistor MS2 is simultaneously detected by the second voltage acquisition circuit. During the detection process, the second switch of the second voltage acquisition circuit can be turned on, so that the charge will be transferred to the second capacitor, and the second capacitor will be equal to VS4. The voltage VS4 is detected by the second analog-to-digital converter. It should be noted that in the present disclosure, it is necessary to detect voltages VS3 and VS4 simultaneously. If the detection is not performed simultaneously, whether during the charging process or the discharging process, the charging current and the discharging current will change with time, which will cause errors, for example, due to the influence of temperature.

[0138] In the above formula, coefficient M is the ratio of the on-resistance of the first detection transistor MS1 to the on-resistance of the discharge control transistor MD. Since both are integrated into a single device, their on-resistances will vary with changes in ambient temperature and the manufacturing process. Therefore, coefficient M is unaffected by these changes. IREF is the constant current provided by the constant current source, which is also unaffected by these changes. Therefore, according to the disclosed method, a discharge current detection value can be obtained that is completely unaffected by changes in ambient temperature and the manufacturing process.

[0139] In addition, the charge and discharge current overcurrent detection circuit may further include an external resistor REXT, which can be used for calibration. When a constant current flows through the external resistor REXT and the first detection transistor MS1, the on-resistance of the first detection transistor MS1 can be calibrated by comparing the voltage generated by the external resistor REXT with the voltage generated by the on-resistance of the first detection transistor MS1, thereby correspondingly calibrating the discharge control transistor MD. In particular, the above description can be used to make the effects of the constant current independent of temperature.

[0140] According to the embodiments of the present disclosure, those skilled in the art should understand that the embodiments can perfectly realize accurate detection of the discharge current without being affected by changes in ambient temperature and manufacturing process.

[0141] In an optional embodiment of the present disclosure, the number of first detection transistors and / or second detection transistors can be more than two, and the on-resistance of each first detection transistor can be set proportionally and the on-resistance of each second detection transistor can also be set proportionally, for example, 100, 1000, etc., and are set in parallel. In this case, a suitable first detection transistor and / or second detection transistor can be selected according to the size of the discharge current value. The on-resistance value of the first detection transistor is significantly greater than the on-resistance value of the discharge control transistor MD. In the case of a relatively small discharge current, if a first detection transistor with a large on-resistance is selected, the voltage generated by the first detection transistor will overwhelm the voltage generated by the discharge control transistor MD, thereby making the overcurrent detection of the discharge current inaccurate. By switching the first detection transistors of different proportions, the overcurrent detection of the discharge current can be made more accurate.

[0142] Figure 7 FIG. 2 shows the setting of the comparison unit in the case of overcurrent detection of the charging current ICHG. Figure 7 As shown, the negative input terminal of the comparator can be directly connected to the voltage VS4, and the positive input terminal of the comparator can be connected to the negative terminal B- (ground terminal) of the battery pack.

[0143] When VS4 is less than 0, the charging current is overcurrent.

[0144] VS4 = IREF × Ron(MS1) - ICHG × Ron(MD) (because the charging current is opposite to the discharging current, the VD voltage is lower than the B- voltage and is a negative voltage).

[0145] VS4<0→IREF×Ron(MS1)<ICHG×Ron(MD)→ICHG>M×IREF, where M is the ratio of Ron(MD) to Ron(MS1). This can detect charging overcurrent.

[0146] According to one embodiment of the present disclosure, a circuit structure for the comparator of the above embodiment is provided.

[0147] Figure 8 FIG1 shows a schematic diagram of a comparator with a dynamic latch according to an embodiment of the present disclosure. The comparator includes PMOS transistors P1 to P12 and NMOS transistors N1 to N11. In the comparator, Q and as its output.

[0148] According to a further embodiment of the present disclosure, an integrated device (electronic chip) is also provided. The integrated device includes at least a discharge control transistor, a charge control transistor, a first detection transistor, and a second detection transistor. This allows the transistors to be manufactured using the same process, avoiding differences between different manufacturers and between different batches of the same manufacturer. Furthermore, the aforementioned constant current source, various switches, reference voltage generation circuits, and analog-to-digital converters may also be integrated. The functions of the various components in the integrated device are the same as those described above and will not be repeated here.

[0149] The present disclosure also provides a battery management system, which can be used to manage battery packs, such as controlling charging and discharging, and detecting the temperature of the battery packs. The battery packs can be charged by a charger and supply power to loads such as electrical equipment, which can be power tools, portable terminals, electric vehicles, etc.

[0150] Figure 9 A battery management system according to an embodiment of the present disclosure is shown, wherein the battery management system may include the integrated device and related elements as described above (of course, it can also be replaced by the current acquisition circuit described above, and the integrated device is used as an example for explanation below), and may also include a logic control unit, which can receive overcurrent conditions and, depending on the situation, provide control signals to various transistors in the integrated device and / or provide switching signals to various switches. In addition, a temperature detection unit may be included to detect the temperature of the battery pack. Of course, other parts may also be included in the battery management system as needed, such as a battery voltage detection unit, which can be used to detect the voltage of each battery cell.

[0151] In the description of this specification, the description with reference to the terms "one embodiment / method", "some embodiments / methods", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment / method or example are included in at least one embodiment / method or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment / method or example. Moreover, the specific features, structures, materials or characteristics described may be combined in an appropriate manner in any one or more embodiments / methods or examples. In addition, those skilled in the art may combine and combine different embodiments / methods or examples described in this specification and the features of different embodiments / methods or examples, unless they are contradictory.

[0152] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. Throughout the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0153] Those skilled in the art will appreciate that the above embodiments are merely intended to clearly illustrate the present disclosure and are not intended to limit the scope of the present disclosure. Other changes or modifications may be made based on the above disclosure, and such changes or modifications are still within the scope of the present disclosure.

Claims

1. An overcurrent detection circuit, configured to detect overcurrent conditions in a battery / battery pack, and controlling the charging and discharging of the battery / battery pack by means of a charge control transistor and a discharge control transistor connected in series with the battery / battery pack, wherein the drain of the charge control transistor is connected to the drain of the discharge control transistor, characterized in that: The overcurrent detection circuit comprises: a first detection transistor and a second detection transistor, wherein the first detection transistor and the second detection transistor are used to detect a discharge current and / or a charge current, wherein a drain of the first detection transistor is connected to a drain of the discharge control transistor and the charge control transistor, and a drain of the second detection transistor is connected to a drain of the discharge control transistor and the charge control transistor; a first voltage acquisition circuit and a second voltage acquisition circuit, wherein an input end of the first voltage acquisition circuit is connected to the source of the first detection transistor, and an input end of the second voltage acquisition circuit is connected to the source of the second detection transistor, and the first voltage acquisition circuit and the second voltage acquisition circuit simultaneously detect the source voltage of the first detection transistor and the source voltage of the second detection transistor; a constant current source, configured to provide a constant current, wherein an output terminal of the constant current source is connected to a source of the first detection transistor; and a comparison unit, wherein two input terminals of the comparison unit are respectively connected to the output terminal of the first voltage acquisition circuit and the output terminal of the second voltage acquisition circuit, and the comparison unit determines whether a discharge overcurrent occurs based on a current value of the constant current source and a ratio of an on-resistance of the first detection transistor to an on-resistance of the discharge control transistor or the charge control transistor.

2. The overcurrent detection circuit according to claim 1, wherein: The channel aspect ratio / number of cells of the first detection transistor and / or the second detection transistor is proportional to the channel aspect ratio / number of cells of the discharge control transistor and / or the charge control transistor.

3. The overcurrent detection circuit according to claim 1, wherein: The on-resistance of the first detection transistor and / or the second detection transistor is proportional to the on-resistance of the discharge control transistor and / or the charge control transistor.

4. The overcurrent detection circuit according to claim 1, wherein: An on-resistance of the first detection transistor and / or the second detection transistor is greater than an on-resistance of the discharge control transistor and / or the charge control transistor.

5. The overcurrent detection circuit according to claim 1, wherein: The on-resistances of the first detection transistor and the second detection transistor, and / or the on-resistances of the discharge control transistor and / or the charge control transistor are the same.

6. The overcurrent detection circuit according to claim 1, wherein: The first detection transistor, the second detection transistor, the discharge control transistor, and the charge control transistor are integrated into one device.

7. The overcurrent detection circuit according to claim 1, wherein: When the discharge current and / or the charge current is detected, the first detection transistor is turned on and the second detection transistor is turned off.

8. The overcurrent detection circuit according to claim 1, wherein: The first detection transistor, the second detection transistor, the discharge control transistor, and the charge control transistor are the same type of NMOS transistors or PMOS transistors.

9. The overcurrent detection circuit according to claim 1, wherein: The comparison unit determines whether a charge overcurrent occurs based on a current value of the constant current source and a ratio of an on-resistance of the second detection transistor to an on-resistance of the discharge control transistor or the charge control transistor.

10. The overcurrent detection circuit according to claim 1, wherein: The first voltage acquisition circuit includes a first switch and a first acquisition capacitor, and the second voltage acquisition circuit includes a second switch and a second acquisition capacitor. The first switch and the second switch are turned on or off at the same time, and when the first switch and the second switch are turned on, the voltage at the source of the first detection transistor is transferred to the first acquisition capacitor, and the voltage at the source of the second detection transistor is transferred to the second acquisition capacitor.

11. The overcurrent detection circuit according to claim 10, wherein: The comparison unit is used to detect the discharge overcurrent condition, and includes: a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, a first control capacitor, a second control capacitor, a third control capacitor and a comparator, wherein the first end of the first control switch is connected to the voltage of the source of the first detection transistor, the second end of the first control switch is connected to the first end of the first control capacitor, the second end of the first control capacitor is connected to the positive input end of the comparator, the first end of the second control switch is connected to the second end of the first control capacitor, the second end of the second control switch is connected to the ground end, the first end of the third control switch is connected to the second end of the first control switch, the second end of the third control switch is connected to the common mode voltage, and the first end of the second control capacitor is connected to the positive input end of the first control capacitor. The second end of the second control capacitor is connected to the ground end, the first end of the fourth control switch is connected to the voltage of the source of the second detection transistor, the second end of the fourth control switch is connected to the first end of the third control capacitor, the second end of the third control capacitor is connected to the negative input terminal of the comparator, the first end of the fifth control switch is connected to the second end of the third control capacitor, the second end of the fifth control switch is connected to the ground end, the first end of the sixth control switch is connected to the second end of the fourth control switch, and the second end of the sixth control switch is connected to the common mode voltage. The first control switch and the second control switch are turned on, the fourth control switch and the fifth control switch are controlled by the first switch control signal, the third control switch and the sixth control switch are controlled by the second switch control signal, and the first switch control signal and the second switch control signal are non-overlapping clock signals.

12. The overcurrent detection circuit according to claim 10, wherein: The comparison unit is used to detect charging overcurrent, and includes: a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, a first control capacitor, a second control capacitor, a third control capacitor and a comparator, wherein the first end of the first control switch is connected to the voltage of the source of the first detection transistor, the second end of the first control switch is connected to the first end of the first control capacitor, the second end of the first control capacitor is connected to the negative input end of the comparator, the first end of the second control switch is connected to the second end of the first control capacitor, the second end of the second control switch is connected to the ground end, the first end of the third control switch is connected to the second end of the first control switch, the second end of the third control switch is connected to the common mode voltage, and the first end of the second control capacitor is connected to the negative input end of the first control capacitor. The second end of the second control capacitor is connected to the ground end, the first end of the fourth control switch is connected to the voltage of the source of the second detection transistor, the second end of the fourth control switch is connected to the first end of the third control capacitor, the second end of the third control capacitor is connected to the positive input terminal of the comparator, the first end of the fifth control switch is connected to the second end of the third control capacitor, the second end of the fifth control switch is connected to the ground end, the first end of the sixth control switch is connected to the second end of the fourth control switch, and the second end of the sixth control switch is connected to the common mode voltage. The first control switch and the second control switch are turned on, the fourth control switch and the fifth control switch are controlled by the first switch control signal, the third control switch and the sixth control switch are controlled by the second switch control signal, and the first switch control signal and the second switch control signal are non-overlapping clock signals.

13. The overcurrent detection circuit according to claim 10, wherein: A first end of the first switch of the first voltage acquisition circuit is connected to the source of the first detection transistor, a second end of the first switch is connected to an input end of the comparison unit, a first end of the first acquisition capacitor is connected to the second end of the first switch, and a second end of the first acquisition capacitor is connected to the source of the second detection transistor via a third switch; A first end of a second switch of the second voltage acquisition circuit is connected to the source of the second detection transistor, a second end of the second switch is connected to the other input end of the comparison unit, a first end of the second acquisition capacitor is connected to the second end of the second switch, and a second end of the second acquisition capacitor is connected to the negative terminal of the battery / battery pack via a fourth switch.

14. The overcurrent detection circuit according to claim 1, wherein: The comparison unit is used to detect discharge overcurrent, and includes a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, a sixth control switch, a seventh control switch, an eighth control switch, a ninth control switch, a first control capacitor, a second control capacitor, a third control capacitor and a comparator; the first end of the first control switch is connected to the voltage of the source of the first detection transistor, the second end of the first control switch is connected to the first end of the first control capacitor, the second end of the first control capacitor is connected to the positive input end of the comparator, the first end of the second control switch is connected to the second end of the first control capacitor, the second end of the second control switch is connected to the ground end, the first end of the third control switch is connected to the second end of the first control switch, and the second end of the third control switch is connected to the positive input end of the comparator. The first end of the second control capacitor is connected to the ground terminal, the second end of the second control capacitor is connected to the ground terminal through the fourth control switch; the first end of the second control capacitor is connected to the ground terminal through the fifth control switch, the second end of the second control capacitor is connected to the ground terminal through the sixth control switch, the first end of the seventh control switch is connected to the voltage of the source of the second detection transistor, the second end of the seventh control switch is connected to the first end of the third control capacitor, the second end of the third control capacitor is connected to the negative input terminal of the comparator, the first end of the eighth control switch is connected to the second end of the third control capacitor, the second end of the eighth control switch is connected to the ground terminal, the first end of the ninth control switch is connected to the second end of the fourth control switch, and the second end of the ninth control switch is connected to the ground terminal.

15. The overcurrent detection circuit according to claim 1, wherein: The comparison unit is used to detect charging overcurrent. The comparison unit includes a comparator, a negative input terminal of the comparator is connected to the voltage of the source of the second detection transistor, and a positive input terminal of the comparator is connected to the negative terminal of the battery / battery pack.

16. The overcurrent detection circuit according to claim 1, wherein: The number of the first detection transistor and the second detection transistor is one or more. When the number of the first detection transistor and the second detection transistor is two or more, the two or more first detection transistors are connected in parallel between the drain of the discharge control transistor and the input end of the first voltage acquisition circuit, and one first detection transistor is selected by a gating switch. The two or more second detection transistors are connected in parallel between the drain of the charge control transistor and the input end of the second voltage acquisition circuit, and one second detection transistor is selected by a gating switch.

17. The overcurrent detection circuit according to claim 16, wherein: The on-resistances of the two or more first detection transistors are proportional to each other, and / or the on-resistances of the two or more second detection transistors are proportional to each other.

18. The overcurrent detection circuit according to claim 16, wherein: The channel aspect ratios of the two or more first detection transistors are proportional to the number of cells, and / or the channel aspect ratios of the two or more second detection transistors are proportional to the number of cells, and / or the channel aspect ratios of the second detection transistor and the charge control transistor are proportional to the number of cells, and / or the channel aspect ratios of the first detection transistor and the second detection transistor are the same as the channel aspect ratios of the second detection transistor and the number of cells and are proportional to the channel aspect ratios of the discharge control transistor and the charge control transistor.

19. The overcurrent detection circuit according to claim 1, wherein: The constant current is a constant current that is independent of temperature.

20. The overcurrent detection circuit according to claim 1, wherein: It also includes a calibration resistor, which is connected between the output terminal of the constant current source and the ground terminal to calibrate the on-resistance of the constant current, the discharge control transistor, the charge control transistor, the first detection transistor, and / or the second detection transistor so that it is independent of temperature.

21. A battery management system, characterized in that: include: The overcurrent detection circuit according to any one of claims 1 to 20; as well as The logic control circuit is used to provide gate control signals to the discharge control transistor, the charge control transistor, the first detection transistor, and the second detection transistor to control the conduction and disconnection of the discharge control transistor, the charge control transistor, the first detection transistor, and the second detection transistor.

22. The battery management system according to claim 21, wherein: The logic control circuit provides the gate control signal according to an overcurrent condition.

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