Method for manufacturing alignment mark and semiconductor structure

Abstract

The present disclosure describes a method for making an alignment mark and a semiconductor structure. The method for making an alignment mark on a wafer includes etching a groove in a first surface area of ​​the wafer. Forming a device structure in a second surface area of ​​the wafer. Depositing a dielectric layer on the first surface of the wafer and filling the groove. Performing a first planarization process to planarize the dielectric layer. After the first planarization process, performing a second planarization process on the device structure on the second surface area of ​​the wafer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to a method for manufacturing an alignment mark and a semiconductor structure. Background Art

[0002] Semiconductor integrated circuit (IC) technology has experienced rapid development, including the continuous minimization of feature size and maximization of packaging density. Minimization of feature size relies on improvements in lithography and its ability to print smaller features or critical dimensions (CDs). This is further related to wafer alignment. Wafer alignment is performed in a lithography scanner. The scanner will expose the wafer based on the alignment results. In order to reduce overlay errors, it is urgent to improve alignment accuracy and overlay measurement accuracy results.

[0003] Alignment marks and the process of aligning them are critical aspects of making wafers and integrated circuit (IC) chips in semiconductor device manufacturing. Alignment marks and the process of aligning them are critical because the chips themselves and the devices used to make the chip components are made by aligning many complex layers of conductors and insulators layer by layer on a substrate (usually silicon). Moreover, in the resulting structure called a wafer, it is critical that each layer is accurately aligned with the previous layer so that the circuits formed therein are functional and reliable.

[0004] Typically, the alignment of one layer relative to another is accomplished with the aid of a tool called a wafer stepper. The wafer stepper is used to optically project the circuit pattern from a reticle mounted in the wafer stepper onto the layer formed on the semiconductor wafer. However, before the pattern on the reticle can be transferred, the wafer must first be accurately positioned or aligned relative to the reticle. Therefore, the wafer that has been prepared for patterning is loaded onto the wafer stepper. Subsequently, the wafer is aligned relative to the reticle using the alignment marks already on the wafer. Once the alignment is complete, the remaining steps of projecting the pattern onto the semiconductor can be performed.

[0005] In lithography alignment, alignment marks are used to align the wafer with the reticle. For example, an off-axis alignment system is used to measure the alignment marks on the target wafer and the reference marks on the reference plate on the wafer base station so that the wafer is aligned with the wafer base station. The reference marks on the wafer base station are also aligned with the alignment marks on the reticle so that alignment between the wafer and the reticle can be achieved.

[0006] Chemical-mechanical polishing (CMP) is a common process used in semiconductor wafer manufacturing. CMP involves chemically etching a surface while also mechanically grinding or lapping it. Because wafers are manufactured by forming multiple layers of different materials one on top of the other, it is important that each layer is extremely flat and smooth or planarized before receiving another layer. CMP has been found to be extremely useful for planarizing all or part of a wafer, and CMP has become one of the most important techniques for planarizing layers in a wafer. Summary of the invention

[0007] A method for making an alignment mark comprises: forming a groove in a first area of ​​a first surface of a wafer, the first area being designated for the alignment mark; forming a device structure in a second area of ​​the first surface of the wafer; depositing a first layer on the first surface of the wafer, the first layer completely filling the groove; performing a first planarization process to remove the first layer to a first level; after the first planarization process, treating the first layer with oxygen plasma; and after treating the first layer with oxygen plasma, performing a second planarization process to remove the device structure to a second level.

[0008] A semiconductor structure comprises: a substrate having a first surface; a first device structure located on a first area of ​​the first surface; an alignment mark located on a second area of ​​the first surface, the alignment mark comprising a groove and a filling material in the groove; and a dielectric layer located directly above the alignment mark, the material composition of the filling material of the alignment mark being different from the material composition of the dielectric layer.

[0009] A method for making an alignment mark includes: forming a groove in a first area of ​​a first surface of a wafer, the first area being designated for the alignment mark; depositing a first layer that completely fills the groove; and forming the alignment mark by treating the first layer with oxygen plasma. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. In the drawings, the same reference numerals identify similar components or actions unless the context indicates otherwise. The sizes and relative positions of the components in the drawings are not necessarily drawn to scale. In practice, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0011] Figure 1 is a diagram illustrating an example wafer with alignment marks;

[0012] FIG. 2A to FIG. 2F It is a diagram showing the process of making alignment marks on a wafer;

[0013] Figure 3 is a drawing showing an exemplary CMP apparatus;

[0014] Figure 4 is a top view illustrating a pad conditioner coupled to a CMP pad;

[0015] Figure 5 is a side view of a pad conditioner coupled to a CMP pad.

[0016]

Explanation of symbols

[0017] 100: Wafer

[0018] 102: Alignment mark

[0019] 104: Groove

[0020] 106: Filler

[0021] 107: Layer

[0022] 108: Edge

[0023] 109: Layer

[0024] 110: Layer

[0025] 112: Layer

[0026] 114:Substrate

[0027] 120:Front

[0028] 122: Structure

[0029] 124: Rear

[0030] 126: Width

[0031] 128: Height

[0032] 200: Wafer, substrate

[0033] 202: first surface, front surface, surface

[0034] 204: Groove

[0035] 208: Edge surface, edge

[0036] 210: bottom surface

[0037] 212: Layer

[0038] 214: Layer

[0039] 215: Ditch features, ditch layers

[0040] 217:Thickness

[0041] 220: Device structure, device features

[0042] 222: Excess

[0043] 230: Isolation layer, layer

[0044] 232: Opening

[0045] 240: Layer

[0046] 242: Groove part

[0047] 244: Bottom level

[0048] 252: Surface

[0049] 260: Layer

[0050] 300:CMP equipment

[0051] 302: Base

[0052] 310: Polishing pad, chemical mechanical polishing pad, pad

[0053] 310a: polishing pad

[0054] 310b: polishing pad

[0055] 310c: polishing pad

[0056] 311: Pad adjuster

[0057] 311a: Pad adjuster

[0058] 311b: Pad adjuster

[0059] 311c: Pad Regulator

[0060] 312a: Slurry supply arm

[0061] 312b: Slurry supply arm

[0062] 312c: Slurry supply arm

[0063] 360: Head wash loading / unloading station

[0064] 362: Loading Cup

[0065] 400: Head rotation unit

[0066] 401: Framework

[0067] 402: Rotary bearing

[0068] 410: Grinding head

[0069] 410a: Grinding head

[0070] 410b: Grinding head

[0071] 410c: Grinding head

[0072] 410d: Grinding head

[0073] 420a: Rotation axis

[0074] 420b: Rotation axis

[0075] 420c: Rotation axis

[0076] 420d: Rotation axis

[0077] 450: Controller

[0078] 500: Rotating platform, platform

[0079] 502: Surface

[0080] 510: Arm

[0081] 512: Adjustment disk

[0082] 520: Pad thickness sensor

[0083] 522: Cutting Edge

[0084] 530: Distance DETAILED DESCRIPTION

[0085] The following disclosure provides many different embodiments or examples to implement different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the disclosure. These are of course only examples and are not intended to be limiting. For example, in the description, a process for forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference symbols and / or letters in multiple examples. This repetition is for the purpose of simplicity and clarity and does not inherently define the relationship between the multiple embodiments and / or configurations discussed.

[0086] Additionally, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and the like, may be used herein to concisely describe the relationship of one element or feature to another element or features as depicted in the accompanying drawings. These spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0087] In the following description, certain specific details are set forth in order to provide a thorough understanding of the various embodiments of the present disclosure. However, those skilled in the art will appreciate that the present disclosure may be implemented without these specific details. In other cases, known structures associated with electronic components and manufacturing techniques are not described in detail to avoid unnecessarily obscuring the description of the embodiments of the present disclosure.

[0088] Unless the context requires otherwise, throughout the specification and the appended claims, the word "comprise" and variations such as "comprises" and "comprising" should be interpreted in an open, inclusive sense, that is, as "including, but not limited to."

[0089] The use of ordinal numbers (such as first, second, and third) does not necessarily imply a sequential ordering meaning but may simply distinguish multiple instances of an action or structure.

[0090] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout this specification do not necessarily all refer to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0091] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural references unless the content clearly dictates otherwise. It should also be noted that the term "or" is generally employed in its sense including "and / or" unless the content clearly dictates otherwise.

[0092] While CMP is extremely useful in a particular process of planarizing a wafer, CMP can complicate problems in other process sets, such as maintaining the integrity of alignment marks that have been formed on a layer. For example, alignment marks are formed on layers of a wafer for the purpose of aligning one layer relative to another in lithography or aligning a layer to a mask. Given the abrasive nature of chemical mechanical polishing, the CMP process may damage the structure or dimensions of the alignment marks. The nature of the above problems can be seen by noting that CMP is typically accomplished by grinding the surface of the wafer on a polishing pad that is wetted with a slurry containing three components: an acidic or alkaline solvent, an abrasive, and a suspension. The combined action of the surface chemical reaction and mechanical polishing allows for the controlled, layer-by-layer removal of desired material from the wafer surface, resulting in preferential removal of protruding surface topography and a planarized wafer surface. Therefore, if features on the surface of the wafer, such as alignment marks, are not properly designed and protected from the effects of CMP, these features may be damaged or destroyed. The disclosed technology herein provides solutions that overcome, among other things, these problems.

[0093] Figure 1 1 is a cross-sectional view of a wafer 100 including an alignment mark 102. According to the top view (not shown for simplicity), the alignment mark 102 may include a simple geometric shape, such as a rectangle, a circle, or a cross. The alignment mark 102 may include any shape in the top view and is not limited by any top view shape. Figure 1 , the alignment mark 102 includes a groove 104 and a filler 106 in the groove 104. In some embodiments, the groove 104 is etched into a corresponding layer 110 (eg, a silicon layer) of the wafer 100 at a relatively shallow depth. Figure 1 1. As shown, the groove 104 extends through the layer 110 and into another layer 112 located below the layer 110 and between the layer 110 and the substrate 114, which is an illustrative example and does not limit the scope of the present disclosure. For example, the groove 104 can extend through the layer 110 and the layer 112 and terminate in the other layer and can extend into the substrate 114. The groove 104 can also terminate in the layer 110 without extending through the layer 110.

[0094] The position of the alignment mark 102 is sensed by a laser beam (not shown) as the laser beam passes through the edge 108 of the alignment mark 102. Therefore, the integrity of the edge 108 and the size of the edge 108 must be maintained throughout the various process steps performed on the wafer 100, or in particular the layer 110, where the alignment mark 102 is located. In some embodiments, the filler 106 includes a conformal material so that the exact shape and depth of the groove 104 are replicated by the filler 106, and the alignment mark 102 can be accurately sensed by, for example, a laser beam. In some embodiments, the filler 106 is silicon oxide, silicon nitride, a low-k dielectric material similar to commonly used low-k dielectric materials, a polymer material, or other suitable material that allows a laser beam or other observation or sensing beam to pass through. In some embodiments, the filler 106 may include multiple layers 107, 109 having different materials.

[0095] In some embodiments, the alignment mark 102 is located on the front side 120 of the wafer 100. For example, some structures 122 of a material different from the material of the layer 110 can be formed in the layer 110 on the front side 120 of the wafer 100. In some embodiments, the alignment mark 102 can also be located on the back side 124 of the wafer 100.

[0096] In some embodiments, the groove 104 of the alignment mark 102 has a width 126 in the range of 1 μm and 2.5 μm and a height 128 in the range of 150 nm and 250 nm. Other dimensions are possible and within the scope of the present disclosure.

[0097] FIG. 2A to FIG. 2F It is a diagram showing the formation of alignment marks (eg Figure 1 Please refer to Figure 2A, a groove 204 is formed in the wafer 200. The groove 204 is formed by etching on the first surface 202 (e.g., the front side surface) of the wafer 200. Specifically, in one example, the groove 204 is formed in the layer 212 and passes through the layer 212 and reaches and terminates in the layer 214 below the layer 212. The layer 212 can be any layer formed in the front-end-of-line (FEOL), back-end-of-line (BEOL), and middle-end-of-line (MEOL) processes. For example, the layer 212 can be a semiconductor layer, such as a silicon layer or other semiconductor materials. The layer 212 can also be a dielectric layer or a metallization layer. Layer 214 may be any layer formed in a front-end-of-line (FEOL), back-end-of-line (BEOL), or middle-end-of-line (MEOL) process. For example, layer 214 may be a semiconductor layer, such as a silicon layer or other semiconductor material. Layer 214 may also be a dielectric layer or a metallization layer. In the description herein, as an illustrative example, layer 212 is a silicon layer and layer 214 is a dielectric layer. In some embodiments, metal features are embedded or formed in dielectric layer 214. In some embodiments, forming recess 204 may include forming a photoresist layer on front side surface 202 of substrate 200. The photoresist layer has an opening formed therein. The opening may be formed using an acceptable lithography technique (e.g., using a lithography mask to expose the photoresist layer to light where the opening is to be formed). After the openings are formed in the photoresist layer, an etching process, such as anisotropic etching, is performed to create a recess 204 recessed below the first surface 202 of the wafer 200 .

[0098] In some embodiments, the groove 204 overlaps with a trench feature 215 in the layer 214. The trench feature 215 can be filled with the same material as the layer 212 (e.g., silicon), or can include a material different from the material of the layer 212. In some embodiments, the material in the trench layer 215 is different from the material of the layer 214. In some embodiments, the groove 204 extends into the trench feature 215. The thickness 217 of the trench feature 215 after the groove 204 has been formed is in a range between about 30 nm and about 90 nm. In some embodiments, the thickness 217 is in a range between about 50 nm and about 75 nm. In some embodiments, the trench feature 215 is an alignment mark in the layer 214.

[0099] like Figure 2BAs shown, a device structure 220 is formed in layer 212. In some embodiments, the device feature 220 includes a material different from the material of layer 212. For example, in some embodiments, layer 212 is silicon and the device feature 220 is silicon germanium, silicon carbide, other silicon-containing semiconductor materials, or other suitable materials. The device structure 220 can be any device structure, such as a doped region, a source / drain structure, a gate structure, an interconnect structure (such as a through silicon via), or other suitable structure or component of a semiconductor device or an integrated circuit formed on wafer 200. In some embodiments, an alignment mark structure is formed in layer 212 so that another feature or layer formed above layer 212 can be correctly aligned based on the alignment mark. For example, an interconnect via structure aligned with the device feature 220 can be formed based on the alignment mark. In some embodiments, the device structure 220 is formed to form an excess portion 222 protruding from the first surface 202. The excess portion 222 will be removed by a planarization process (such as a chemical mechanical polishing (CMP) process). It should be understood that the alignment mark structure can be formed in the formation. Figure 2A The device structure 220 is formed before or after the groove 204 .

[0100] like Figure 2B As shown, in some optional embodiments, one or more isolation layers 230 are formed in the recess 204. The isolation layer 230 may be silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, oxide, polymer material, combinations thereof and / or other suitable materials. The isolation layer 230 may be deposited using an acceptable deposition technique, such as a chemical vapor deposition (CVD) process, or further, by using a low temperature CVD to deposit. In some embodiments, the isolation layer 230 is formed on the exposed first surface 202 and in the recess 204 (including the edge surface 208 and the bottom surface 210 of the recess 204), and is consistent with those surfaces. After the isolation layer is formed, a gap or opening 232 still exists in the recess 204.

[0101] like Figure 2B As shown, for example, excess portion 222 of device structure 220 is exposed from isolation layer 230. The specific example does not limit the scope of the present disclosure. In other embodiments, excess portion 222 can be covered by isolation layer 230. In some embodiments, after isolation layer 230 is formed over layer 212, isolation layer 230 is thinned by, for example, etching. Thinning isolation layer 230 can expose excess portion 222.

[0102] exist Figure 2CIn the embodiment, layer 240 is formed over surface 202 of wafer 200 and fills opening 232 in recess 204. In some embodiments, layer 240 includes silicon oxide, plasma enhanced tetraethyl orthosilicate (P-TEOS), borophosphosilicate glass (BPSG), plasma enhanced oxide (PEOX), oxide made by furnace chemical vapor deposition (FCVD), high density plasma (HDP) oxide, phosphosilicate glass (PSG), spin-on-dielectrics (SOD), thermal oxide, silicon-containing organic polymer, silicon-containing organic / inorganic hybrid material, organosilicate glass (OSG), tetraethyl orthosilicate (TEOS), fluorinated silicate glass (FSG), hemispherical particles (HSQ), carbon-doped oxide (CDO) glass, combinations thereof, or other suitable dielectric materials. In some embodiments, layer 240 has the same material as an interlayer dielectric layer formed on wafer 200 .

[0103] In some embodiments, the thickness of layer 240 is controlled so that opening 232 of recess 204 is completely filled by layer 240. Depending on the properties of the material of layer 240 and / or the properties of the process used to form layer 240, layer 240 may include recess portion 242 that overlaps opening 232 (now filled by layer 240). Bottom level 244 of recess portion 242 does not extend downward beyond first surface 202.

[0104] In some embodiments, Figure 2C As shown, the layer 240 covers the excess portion 222 of the device structure 220. This exemplary embodiment does not limit the scope of the present disclosure. In some embodiments, the excess portion 222 can be exposed from the layer 240.

[0105] exist Figure 2DIn some embodiments, a first planarization process, such as a first CMP process, is performed to planarize the layer 240 to a level, such as to the level of the first surface 202. In some embodiments, the slurry of the first CMP process has a high selectivity between the material of the layer 240 and the material of the excess portion 222, such that the first CMP process does not remove the excess portion 222. In some embodiments, the removal rate ratio between the material of the layer 240 and the excess portion 222 is in the range of 75:1 and 200:1. In some embodiments, when the device structure 220 is silicon germanium (SiGe) and the layer 240 is silicon oxide, the slurry has a removal rate of 1020:12.9 between the layer 240 and the excess portion 222. In addition, in some embodiments, the first CMP process does not include a down force or includes a low down force in the range of 0 psi and 2 psi. The low down force facilitates improved end point detection (EPD) of the excess portion 222 of the device structure 220. If the down force is too large, the first CMP may cause severe dishing on the layer 212 and the layers 230 , 240 in the recess 204 .

[0106] In some embodiments, the first CMP process also removes the isolation layer 230 to the level of the first surface 202, for example, until the first surface 202 is exposed. After the first CMP process is completed, the surface 252 of the layer 240 in the recess 204 is substantially at the same level or coplanar with the first surface 202. During the first CMP process, the layer 240 in the recess 204, or more specifically in the opening 232, remains intact and is not damaged by the first CMP process. For example, in order to maintain the integrity of the layer 240 in the recess 204, for example, to avoid the dishing effect, the first CMP includes a low rotation speed in the range of 30 rpm and 55 rpm. In some embodiments, some remaining portions of the layer 240 may remain on the first surface 202, particularly adjacent to the excess portion 222.

[0107] exist Figure 2E In some embodiments, the layer 240 in the recess 204 is treated with oxygen plasma at a temperature in a range of 350° C. to 450° C. for a duration in a range of 20 seconds to 60 seconds. The oxygen plasma treatment reduces the surface roughness and improves the surface hardness of the surface 252 of the layer 240 in the recess 204. As a result, the surface 252 and the edge 208 of the recess 204 are less susceptible to dishing during a CMP process, such as a CMP process to remove the excess portion 222 of the device structure 220.

[0108] exist Figure 2FIn some embodiments, a second CMP process is performed to remove excess portion 222 of device structure 220. In some embodiments, a slurry used in the second CMP process has a high selectivity between the material of device structure 220 and the material of layer 240 in recess 204. In some embodiments, the ratio of the removal rates of the slurry of the second CMP process on device structure 220 and layer 240 is in a range of 12:1 to 20:1. In some embodiments, the slurry of the second CMP process has very low or no selectivity between device structure 220 and layer 212. In some embodiments, layer 212 is silicon (Si), device structure 220 is silicon germanium (SiGe), and layer 240 in recess 204 is silicon oxide, and the slurry used in the second CMP process has a removal rate of about 57:61:4.2 among silicon, silicon germanium, and silicon oxide. As such, the second CMP process does not damage layer 240 in recess 204. In addition, the slurry of the second CMP is also selected to have an extremely low removal rate for the isolation layer 230 in the groove 204 .

[0109] Because recess 204 is filled with layer 240, edge surface 208 of recess 204 is protected by layer 240 and layer 230 from being damaged by the second CMP process. Thus, the dimensions of recess 204 are not changed by the second CMP process or other CMP processes used to fabricate device features on layer 212. Recess 204 and layer 240 and layer 230 in recess 204 can be used as Figure 1 Because the size of the alignment mark 102 on the layer 212 remains intact, the alignment between the layer 212 and a subsequent layer formed on the wafer 200 or a mask layer used to form a subsequent layer on the wafer 200 is improved.

[0110] After the alignment mark 102 is formed, another layer 260, such as a dielectric layer, is formed directly over the layer 212, the device feature 220, and the alignment mark 102. Because the layer 240 in the recess 204 is treated with oxygen plasma, the material composition and properties of the layer 240 are different from those of the layer 260 even though the layer 260 is the same dielectric material as the layer 240 in the recess 204. For example, in the case where both the layer 240 and the layer 260 are silicon oxide, the silicon oxide of the layer 240 contains fewer surface organic groups, such as residual hydroxyl groups, than the silicon oxide of the layer 260 because the residual hydroxyl groups in the layer 240 have been substantially removed by the oxygen plasma treatment.

[0111] Figure 3 2 is a diagram showing an exemplary CMP apparatus 300. The CMP apparatus 300 includes a base 302; a plurality of polishing pads 310 (polishing pads 310a, 310b, and 310c shown) coupled to corresponding rotating platforms ( Figure 3310 ); a head clean load / unload (HCLU) station 360, comprising a loading cup 362 for loading and unloading wafers (not shown) onto and from the polishing pad 310; and a head rotation unit 400, having a plurality of polishing heads 410 (polishing heads 410a, 410b, 410c and 410d shown) for holding and fixedly rotating the wafers on the polishing pad 310.

[0112] The controller 450 is communicatively coupled to the base 302 and the head rotation unit 400 , and controls the operation of each of the polishing pad 310 and the polishing head 410 .

[0113] The three polishing pads 310a, 310b and 310c facilitate processing multiple wafers simultaneously in a short time. Each of the polishing pads 310 is mounted on a rotatable platform. Pad conditioners 311a, 311b and 311c are disposed on the base 302 and can sweep over the corresponding polishing pad 310 for conditioning the polishing pad. Slurry supply arms 312a, 312b, 312c are further disposed on the base 302 to supply CMP slurry to the surface of the corresponding polishing pad 310.

[0114] The grinding heads 410a, 410b, 410c and 410d of the head rotation unit 400 are mounted on corresponding rotation shafts 420a, 420b, 420c and 420d, which are rotated by a drive mechanism (not shown) inside the frame 401 of the head rotation unit 400. The grinding heads 410 hold corresponding wafers (not shown) and press the wafers against the upper surface of the corresponding grinding pads 310 (grinding pads 310a, 310b and 310c shown). In this way, the material layer is removed from the corresponding wafer. During the CMP process, the head rotation unit 400 is supported on the base 302 by the rotation bearing 402.

[0115] In some embodiments, the polishing pad 310 is constructed of two or more layers, with an elastomeric layer as the outer layer of the pad. The layers are typically made of a polymeric material, such as polyurethane, and may contain fillers for controlling the dimensional stability of the layers. In order to prevent non-planar surfaces from being ground onto the wafer when the wafer is off-center on the polishing pad, the polishing pad 310 is made several times the diameter of the wafer in rotary CMP. During the polishing process, the wafer itself is also rotated, for example by the polishing head 410, to prevent tapered profiles from being ground onto the wafer surface. The rotation axis of the wafer and the rotation axis of the pad are intentionally not co-linear; however, the two axes can be parallel.

[0116] In operation of the CMP apparatus 300 , each wafer is mounted on the polishing head 410 a , 410 b , 410 c or 410 d and is polished in sequence against the polishing pads 310 a , 310 b and 310 c , respectively.

[0117] Figure 4 A top view of a pad conditioner 311 coupled to a CMP pad 310 is shown. Figure 5 FIG. 5 is a side view of a pad conditioner 311 coupled to a CMP pad 310 on a rotating platform 500. Figure 4 and Figure 5 , the adjuster 311 includes an arm 510 and an adjustment disk 512 coupled to the arm 510. A pad thickness sensor 520 is coupled to or integrated on the arm 510. When the adjuster 311 sweeps over the polishing pad 310 to adjust the polishing pad 310, the pad thickness sensor 520 detects the thickness of the pad 310, or in some embodiments, the thickness of the elastic outer layer of the pad 310. When the pad 310 rotates with the platform 500, the pad thickness sensor 520 can detect thickness information on different surface areas of the pad 310. In this way, the pad thickness sensor 520 is able to detect the thickness profile of the pad 310.

[0118] The pad thickness sensor 520 may be a range sensor, a laser sensor, or other suitable type of sensor that can detect a signal indicative of a thickness value of the pad 310. In some embodiments, the pad thickness sensor 520 detects a distance 530 between a tip 522 of the pad thickness sensor 520 and the surface 502 of the platform 500. At pad surface areas of smaller pad thickness, the adjustment disk 512 is lowered to engage with the surface of the pad 310. Thus, the distance 530 becomes smaller. At surface areas of larger pad thickness, the adjustment disk 512 is raised to interface with the surface of the pad 310. Thus, the distance 530 becomes larger. Thus, the detected distance 530 serves as a pad thickness signal indicative of the thickness of the pad 310 in multiple surface areas.

[0119] The pad thickness information or thickness distribution of the pad 310 may be communicated to the controller 450. The controller 450 may control the operation of the base 302 or the head rotation unit 400 based on the pad thickness distribution of the pad 310. For example, the controller 450 may control the wafer to stay longer at a pad 310 having a larger pad thickness than at a pad 310 having a smaller pad thickness. The controller 450 may control the wafer to stay longer at a pad surface area having a larger pad thickness than at a pad surface area having a smaller pad thickness. Other methods of controlling the CMP operation based on the pad thickness information or distribution of the polishing pad 310 are also possible and included in the present disclosure.

[0120] The disclosed technology is further understood with the following embodiments.

[0121] In a first embodiment, a method for making an alignment mark includes: forming a groove in a first area on a first surface of a wafer, the first area being designated for the alignment mark; forming a device structure in a second area on the first surface of the wafer; depositing a first layer on the first surface of the wafer, the first layer completely filling the groove; performing a first planarization process to remove the first layer to a first level; after the first planarization process, treating the first layer with oxygen plasma; and after treating the first layer with oxygen plasma, performing a second planarization process to remove the device structure to a second level.

[0122] According to some embodiments, the second level is substantially the same level as the first level. According to some embodiments, the method further includes hardening the first surface of the first layer adjacent to the groove after the first planarization process. According to some embodiments, the method further includes treating the first surface of the first layer adjacent to the groove with an oxygen plasma after the first planarization process. According to some embodiments, the first layer is silicon oxide. According to some embodiments, the first layer is silicon nitride. According to some embodiments, the first layer is a polymer material. According to some embodiments, the first layer allows laser light to pass through. According to some embodiments, the method further includes forming an isolation layer in the groove, wherein the first layer is formed on the isolation layer. According to some embodiments, the isolation layer is a dielectric material different from the first layer.

[0123] In a second embodiment, a semiconductor structure includes: a substrate having a first surface; a first device structure located in a first area of ​​the first surface; and an alignment mark located in a second area of ​​the first surface, the alignment mark including a groove and a filling material in the groove; and a dielectric layer located directly above the alignment mark, the material composition of the filling material of the alignment mark being different from the material composition of the dielectric layer.

[0124] According to some embodiments, the filling material is silicon oxide. According to some embodiments, the filling material is silicon nitride. According to some embodiments, the filling material is a polymer material. According to some embodiments, the filling material allows the laser to pass through. According to some embodiments, the alignment mark comprises an isolation layer in the groove, and the filling material is located on the isolation layer. According to some embodiments, the isolation layer is a dielectric material different from the filling material.

[0125] In a third embodiment, a wafer includes: a substrate having a first surface; and an alignment mark located on the first surface, the alignment mark including a groove and a layer, the layer completely filling the groove, and a second surface of the layer is substantially at the same level as the first surface.

[0126] In one embodiment, a method for making an alignment mark includes: forming a groove in a first area of ​​a first surface of a wafer, the first area being designated for the alignment mark; depositing a first layer that completely fills the groove; and forming the alignment mark by treating the first layer using oxygen plasma.

[0127] According to some embodiments, the first layer is one or more of silicon oxide, silicon nitride, or a polymer material. According to some embodiments, the first layer allows laser light to pass through.

[0128] The various embodiments described above can be combined to provide further embodiments.

[0129] In light of the above detailed description, these and other changes can be made to the embodiments. In general, in the appended claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and the full scope of equivalents to which these claims are entitled. Therefore, the claims are not limited by the present disclosure.

Claims

1. A method for making an alignment mark, characterized in that: The method includes: forming a groove in a first area of ​​a first surface of a wafer, the first area being designated for an alignment mark, and the groove extending downwardly through a first layer on a substrate of the wafer; forming a device structure in a second region of the first surface of the wafer, the device structure extending into the first layer; depositing a second layer on the first surface of the wafer, the second layer filling the recess and at least laterally adjacent to the device structure; Performing a first planarization process to remove a portion of the second layer adjacent to the recess to a first level on the first layer while retaining the device structure in the first layer; After the first planarization process, treating the second layer with oxygen plasma; as well as After treating the second layer with oxygen plasma, a second planarization process is performed to remove the device structure to a second level on the first layer.

2. The method according to claim 1, characterized in that The second level is the same level as the first level.

3. The method according to claim 1, characterized in that The second layer is treated with oxygen plasma to increase the surface hardness of a surface of the second layer in the groove.

4. The method according to claim 1, characterized in that: The method includes: after the first planarization process, treating a surface of the second layer adjacent to the groove using oxygen plasma.

5. The method according to claim 1, characterized in that The second layer is silicon oxide.

6. The method according to claim 1, characterized in that The second layer is silicon nitride.

7. The method according to claim 1, characterized in that The second layer is a polymer material.

8. The method according to claim 1, characterized in that The second layer allows a laser to pass through.

9. The method according to claim 1, characterized in that: The method includes: forming an isolation layer in the groove, wherein the second layer is formed on the isolation layer.

10. The method according to claim 9, characterized in that The isolation layer is a dielectric material different from that of the second layer.

11. A method for making an alignment mark, characterized in that: The method includes: forming a recess in a first area of ​​a first surface of a wafer, the first area being designated for an alignment mark, the recess extending downwardly through a first layer on a substrate of the wafer, wherein the device structure is at least partially located in the first layer, and the recess is laterally adjacent to the device structure; Depositing a second layer to fill the recess while at least partially retaining the device structure in the first layer; Performing a first planarization process to remove a portion of the second layer adjacent to the recess to a first level on the first layer while retaining the device structure in the first layer; forming the alignment mark by treating the second layer using oxygen plasma; as well as After treating the second layer using oxygen plasma, a second planarization process is performed to remove a portion of the device structure to a second level on the first layer while at least partially retaining the device structure in the first layer.

12. The method according to claim 11, characterized in that The second layer is one or more of silicon oxide, silicon nitride or a polymer material.

13. The method according to claim 11, characterized in that The second layer allows a laser to pass through.

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