Display panel, manufacturing method thereof, and display device

Abstract

The present invention provides a display panel, a manufacturing method thereof, and a display device. The display panel includes: a base substrate, the base substrate including a first display area and a second display area, the transmittance of the second display area being greater than the transmittance of the first display area, the second display area including a plurality of pixel areas and a light-transmitting area located between the plurality of pixel areas; a plurality of groups of sub-pixels of different colors located in the plurality of pixel areas, each group of sub-pixels including at least two sub-pixels of the same color, each group of sub-pixels including at least one pixel driving circuit and at least two anodes, the orthographic projection of the at least one pixel driving circuit on the base substrate being located within the orthographic projection of the at least two anodes on the base substrate. The present invention can solve the problem in the related art of display differences between the camera area and the normal display area, which affects the user's visual experience.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] OLED (Organic Light-Emitting Diode) screens, with their advantages such as self-luminescence, low power consumption, thinness, flexibility, brilliant colors, high contrast, and fast response time, have attracted widespread attention and are becoming the next generation of displays, gradually replacing LCD (Liquid Crystal Display) screens. Currently, full-screen displays are a popular design concept and a leading fashion trend. To further increase the screen-to-body ratio, major manufacturers are vying to develop new technologies that hide the camera under the screen. The biggest challenge in this technology is how to improve the screen's transmittance.

[0003] In related technologies, in order to improve the transmittance of the screen, the display PPI (Pixels Per Inch, pixel density) of the camera area is reduced, but this will cause a difference in display between the camera area and the normal display area, affecting the user's visual experience. Summary of the Invention

[0004] The purpose of the present invention is to provide a display panel, a manufacturing method thereof, and a display device, which can achieve high transmittance in the camera area while ensuring that the display PPI of the camera area remains unchanged, so as to solve the problem of display differences between the camera area and the normal display area, which affects the user's visual experience.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A first aspect of the present invention provides a display panel, comprising: a base substrate, the base substrate comprising a first display area and a second display area, the transmittance of the second display area being greater than the transmittance of the first display area, the second display area comprising a plurality of pixel areas and a translucent area located between the plurality of pixel areas; a plurality of groups of sub-pixels of different colors, located in the plurality of pixel areas, each group of sub-pixels comprising at least two sub-pixels of the same color, each group of sub-pixels comprising at least one pixel driving circuit and at least two anodes, the orthographic projection of the at least one pixel driving circuit on the base substrate being located within the orthographic projection of the at least two anodes on the base substrate.

[0007] Optionally, the number of the at least one pixel driving circuit is one, and the orthographic projection of the one pixel driving circuit on the base substrate is located within the orthographic projection of the at least two anodes on the base substrate.

[0008] Optionally, the one pixel driving circuit includes at least two sub-driving circuits, the at least two sub-driving circuits correspond one-to-one to the at least two sub-pixels of the same color, and the at least two sub-driving circuits correspond one-to-one to the at least two anodes, each sub-driving circuit is located between the corresponding anode and the base substrate of the display panel, the orthographic projection of each sub-driving circuit on the base substrate is located within the orthographic projection of the corresponding anode on the base substrate, the at least two sub-driving circuits are connected by a first transparent wiring, and the at least two anodes are connected by a second transparent wiring.

[0009] Optionally, the first transparent wiring and the second transparent wiring are arranged in the same layer or in different layers, and at least part of the first transparent wiring and at least part of the second transparent wiring are located in the light-transmitting area.

[0010] Optionally, the at least two sub-pixels of the same color are staggered by a predetermined distance in the first direction; or

[0011] The at least two sub-pixels of the same color are aligned in a first direction.

[0012] Optionally, the one pixel driving circuit includes:

[0013] a first storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;

[0014] Wherein, one end of the first storage capacitor is connected to the power line, and the other end of the storage capacitor is connected to the first node;

[0015] The control electrode of the first transistor is connected to the first gate signal line or the third gate signal line, the first electrode of the first transistor is connected to the first node, and the second electrode of the first transistor is connected to the initialization voltage level signal line;

[0016] The control electrode of the second transistor is connected to the second gate signal line or the fourth gate signal line, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the third node;

[0017] The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node;

[0018] The control electrode of the fourth transistor is connected to the second gate signal line or the fourth gate signal line, the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the data line;

[0019] The control electrode of the fifth transistor is connected to the first light-emitting control signal line or the second light-emitting control signal line, the first electrode of the fifth transistor is connected to the second node, and the second electrode of the fifth transistor is connected to the power line;

[0020] The control electrode of the sixth transistor is connected to the first light-emitting control signal line or the second light-emitting control signal line, the first electrode of the sixth transistor is connected to the fourth node, and the second electrode of the sixth transistor is connected to the third node;

[0021] The control electrode of the seventh transistor is connected to the second gate signal line or the fourth gate signal line, the first electrode of the seventh transistor is connected to the fourth node, and the second electrode of the seventh transistor is connected to the initialization voltage level signal line.

[0022] Optionally, the at least two sub-driving circuits include: a first sub-driving circuit and a second sub-driving circuit, the at least two anodes include a first anode and a second anode, the first sub-driving circuit corresponds to the first anode, and the second sub-driving circuit corresponds to the second anode;

[0023] The first sub-driving circuit includes the first storage capacitor, the third transistor, the fourth transistor, and the fifth transistor, and the second sub-driving circuit includes the first transistor, the second transistor, the sixth transistor, and the seventh transistor; or

[0024] The first sub-driving circuit includes the first storage capacitor, the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor, and the second sub-driving circuit includes the fifth transistor and the sixth transistor; or

[0025] The first sub-driving circuit includes the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, and the second sub-driving circuit includes the first storage capacitor and the third transistor; or

[0026] The first sub-driving circuit includes the first transistor, the second transistor, the fourth transistor, and the seventh transistor. The second sub-driving circuit includes the first storage capacitor, the third transistor, the fifth transistor, and the sixth transistor.

[0027] Optionally, the display panel further comprises: a first signal line and a second signal line, the first signal line comprises: a first light emitting control signal line and a second gate signal line, the second signal line comprises: a second light emitting control signal line and a fourth gate signal line;

[0028] In the second display area, the first light-emitting control signal is connected to the control electrode of the fifth transistor, the second gating signal is connected to the control electrode of the second transistor, the second light-emitting control signal line is located in the first display area and not in the second display area, and the fourth gating signal line is located in the first display area and not in the second display area; or

[0029] In the second display area, the second light-emitting control signal is connected to the control electrode of the fifth transistor, the fourth gate signal line is connected to the control electrode of the second transistor, the first light-emitting control signal line is located in the first display area and not in the second display area, and the second gate signal line is located in the first display area and not in the second display area.

[0030] Optionally, the display panel further includes: a data line and a power line, the data line is connected to the second electrode of the fourth transistor, and the power line is connected to the second electrode of the fifth transistor.

[0031] A second aspect of the present invention provides a method for manufacturing a display panel, wherein the display panel includes a base substrate, the base substrate including a first display area and a second display area, wherein the transmittance of the second display area is greater than the transmittance of the first display area, and the method includes:

[0032] A plurality of pixel areas and light-transmitting areas located between the plurality of pixel areas are formed in the second display area; wherein, a plurality of groups of sub-pixels of different colors are located in the plurality of pixel areas, each group of sub-pixels includes at least two sub-pixels of the same color, each group of sub-pixels includes at least one pixel driving circuit and at least two anodes, and the orthographic projection of the at least one pixel driving circuit on the substrate is located within the orthographic projection of the at least two anodes on the substrate.

[0033] A third aspect of the present invention provides a display device comprising the display panel described above.

[0034] The embodiments of the present invention have the following beneficial effects:

[0035] The embodiment of the present invention splits a pixel driving circuit into at least two sub-driving circuits, so that the pixel driving circuit in the camera area is reduced by at least half, thereby achieving high transmittance in the camera area while ensuring that the display PPI of the camera area remains unchanged. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A schematic diagram of the location of the camera area in the related art;

[0037] Figure 2 A schematic diagram of the display PPI of the camera area in the related art;

[0038] Figure 3 A schematic diagram of a driving circuit and anode of a camera area;

[0039] Figure 4 A schematic diagram of a driving circuit and anode of another camera area;

[0040] Figure 5 A schematic diagram of a driving circuit and anode of a camera area provided by an embodiment of the present invention;

[0041] Figure 6 A connection diagram of a first seed driving circuit provided by an embodiment of the present invention;

[0042] Figure 7 A connection diagram of a second seed driving circuit provided by an embodiment of the present invention;

[0043] Figure 8 A connection diagram of a third seed driving circuit provided by an embodiment of the present invention;

[0044] Figure 9 A connection diagram of a fourth seed driving circuit provided by an embodiment of the present invention;

[0045] Figure 10 A connection diagram of a fifth seed driving circuit provided by an embodiment of the present invention;

[0046] Figure 11 A schematic diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0047] Figure 12 For Figure 6 Schematic diagram of the connection between the corresponding light-emitting control signal and gate signal and the sub-driving circuit;

[0048] Figure 13 For Figure 6 Schematic diagram of the specific connection between the corresponding light-emitting control signal and gate signal and the sub-driving circuit;

[0049] Figure 14 For Figure 6 Schematic diagram of the corresponding cutting line;

[0050] Figure 15 A cross-sectional view of sub-pixels of the same color provided by an embodiment of the present invention;

[0051] Figure 16 Schematic diagram of the manufacturing process of a display panel according to an embodiment of the present invention;

[0052] Figure 17 A cross-sectional view of another sub-pixel of the same color provided by an embodiment of the present invention;

[0053] Figure 18 For Figure 7 Schematic diagram of the specific connection between the corresponding light-emitting control signal and gate signal and the sub-driving circuit;

[0054] Figure 19 For Figure 7 Schematic diagram of the corresponding cutting line;

[0055] Figure 20 A cross-sectional view of another sub-pixel of the same color provided by an embodiment of the present invention; DETAILED DESCRIPTION

[0056] In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, they will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] Hiding the camera module under the display area is a general trend, but in related technologies, the display PPI of the camera area is low, such as 200PPI, while the display PPI of the normal display area is usually between 400 and 600PPI. Figure 1 and Figure 2 As shown, Figure 1 Schematic diagram of the position of the camera area in the prior art. Figure 2 Schematic diagram of the display PPI of the camera area in the prior art.

[0058] Figure 3 Schematic diagram of a driving circuit and anode of a camera area. Figure 3 As shown, the display area of ​​the display screen includes a normal display area and a camera area. If a camera module is installed in the normal display area without adjusting the drive circuit and anode layout of the normal display area, the camera module can collect less external light because the drive circuit and anode are opaque, and the normal display area is non-transparent to the camera module. Figure 3 The camera area in the design consists of a transition zone and a transparent zone. The transparent zone contains only the anode. Since the driver circuit is not located in the transparent zone, the camera module can collect more external light, making the transparent zone transparent to the camera module. Because the driver circuit in the transparent zone is placed in the transition zone, the driver circuit and the anode are connected by transparent traces. When the transparent zone is large or the PPI is high, the number of traces can be very large, significantly impacting the design, process, and cost.

[0059] Figure 4 Schematic diagram of another driving circuit and anode of the camera area, such as Figure 4As shown, in the transmission area, the pixel driving circuit is not moved, but is placed under the anode for shielding. However, the existing mature driving circuit has high requirements for space, and the driving circuit cannot be completely shielded by the anode, resulting in unsatisfactory transmittance and diffraction effects.

[0060] In order to solve the problem in the related art that there is a display difference between the camera area and the normal display area, which affects the user's visual experience, the present invention provides a display panel, a manufacturing method thereof, and a display device.

[0061] An embodiment of the present invention provides a display panel, comprising: a base substrate, the base substrate comprising a first display area and a second display area, the second display area having a greater light transmittance than the first display area, the second display area comprising a plurality of pixel areas and a light-transmitting area located between the plurality of pixel areas;

[0062] Multiple groups of sub-pixels of different colors are located in the multiple pixel areas, each group of sub-pixels includes at least two sub-pixels of the same color, each group of sub-pixels includes at least one pixel driving circuit and at least two anodes, and the orthographic projection of the at least one pixel driving circuit on the substrate is located within the orthographic projection of the at least two anodes on the substrate.

[0063] Exemplarily, the number of the at least one pixel driving circuit is one, and the orthographic projection of the one pixel driving circuit on the substrate is located within the orthographic projection of the at least two anodes on the substrate.

[0064] Exemplarily, the one pixel driving circuit includes at least two sub-driving circuits, the at least two sub-driving circuits corresponding one-to-one to the at least two sub-pixels of the same color, and the at least two sub-driving circuits corresponding one-to-one to the at least two anodes, each sub-driving circuit is located between the corresponding anode and the base substrate of the display panel, the orthographic projection of each sub-driving circuit on the base substrate is located within the orthographic projection of the corresponding anode on the base substrate, the at least two sub-driving circuits are connected by a first transparent wiring, and the at least two anodes are connected by a second transparent wiring.

[0065] Exemplarily, the first transparent wiring and the second transparent wiring are arranged in the same layer or in different layers, and at least part of the first transparent wiring and at least part of the second transparent wiring are located in the light-transmitting area.

[0066] Exemplarily, the at least two sub-pixels of the same color are staggered by a predetermined distance in the first direction; or

[0067] The at least two sub-pixels of the same color are aligned in a first direction.

[0068] Exemplarily, the pixel driving circuit includes: a first storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

[0069] Wherein, one end of the first storage capacitor is connected to the power line, and the other end of the storage capacitor is connected to the first node;

[0070] The control electrode of the first transistor is connected to the first gate signal line or the third gate signal line, the first electrode of the first transistor is connected to the first node, and the second electrode of the first transistor is connected to the initialization voltage level signal line;

[0071] The control electrode of the second transistor is connected to the second gate signal line or the fourth gate signal line, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the third node;

[0072] The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node;

[0073] The control electrode of the fourth transistor is connected to the second gate signal line or the fourth gate signal line, the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the data line;

[0074] The control electrode of the fifth transistor is connected to the first light emitting control signal line, the first electrode of the fifth transistor is connected to the second node, and the second electrode of the fifth transistor is connected to the power line;

[0075] The control electrode of the sixth transistor is connected to the first light emitting control signal line, the first electrode of the sixth transistor is connected to the fourth node, and the second electrode of the sixth transistor is connected to the third node;

[0076] The control electrode of the seventh transistor is connected to the second gate signal line or the fourth gate signal line, the first electrode of the seventh transistor is connected to the fourth node, and the second electrode of the seventh transistor is connected to the initialization voltage level signal line.

[0077] Exemplarily, the at least two sub-driving circuits include: a first sub-driving circuit and a second sub-driving circuit; the at least two anodes include a first anode and a second anode; the first sub-driving circuit corresponds to the first anode, and the second sub-driving circuit corresponds to the second anode;

[0078] The first sub-driving circuit includes the first storage capacitor, the third transistor, the fourth transistor, and the fifth transistor, and the second sub-driving circuit includes the first transistor, the second transistor, the sixth transistor, and the seventh transistor; or

[0079] The first sub-driving circuit includes the first storage capacitor, the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor, and the second sub-driving circuit includes the fifth transistor and the sixth transistor; or

[0080] The first sub-driving circuit includes the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, and the second sub-driving circuit includes the first storage capacitor and the third transistor; or

[0081] The first sub-driving circuit includes the first transistor, the second transistor, the fourth transistor, and the seventh transistor. The second sub-driving circuit includes the first storage capacitor, the third transistor, the fifth transistor, and the sixth transistor.

[0082] Exemplarily, the display panel further includes: a first signal line and a second signal line, the first signal line includes: a first light-emitting control signal line and a second gate signal line, the second signal line includes: a second light-emitting control signal line and a fourth gate signal line; wherein,

[0083] In the second display area, the first light-emitting control signal is connected to the control electrode of the fifth transistor, the second gating signal is connected to the control electrode of the second transistor, the second light-emitting control signal line is located in the first display area and not in the second display area, and the fourth gating signal line is located in the first display area and not in the second display area; or

[0084] In the second display area, the second light-emitting control signal is connected to the control electrode of the fifth transistor, the fourth gate signal line is connected to the control electrode of the second transistor, the first light-emitting control signal line is located in the first display area and not in the second display area, and the second gate signal line is located in the first display area and not in the second display area.

[0085] Exemplarily, the display panel further includes a data line and a power line, the data line is connected to the second electrode of the fourth transistor, and the power line is connected to the second electrode of the fifth transistor.

[0086] Figure 5 A schematic diagram of a driving circuit and anode of a camera area provided by an embodiment of the present invention, such as Figure 5 As shown, the display panel includes a first display area and a second display area, wherein the transmittance of the second display area is greater than that of the first display area. The first display area is a normal display area, and the second display area is a camera area. The second display area is provided with multiple pixel areas, each pixel area including multiple groups of sub-pixels of different colors, each group of sub-pixels including at least two sub-pixels of the same color, and each group of sub-pixels includes a pixel driver circuit and at least two anodes. The pixel driver circuit in the camera area of ​​the present invention is not moved to another location. Instead, the original pixel driver circuit is split into two sub-driver circuits, and the two sub-driver circuits are associated with two sub-pixels of the same color in a one-to-one manner. The two sub-driver circuits are electrically connected via a first transparent trace. The two sub-driver circuits correspond one-to-one with the two anodes. Each sub-driver circuit is located between the corresponding anode and the base substrate of the display panel, with the orthographic projection of each sub-driver circuit on the base substrate located within the orthographic projection of the corresponding anode on the base substrate. The two anodes are electrically connected via a second transparent trace. The first transparent trace and the second transparent trace are disposed on the same layer or on different layers.

[0087] Figure 6 A connection diagram of a first seed driving circuit provided by an embodiment of the present invention, Figure 7 A connection diagram of a second seed driving circuit provided by an embodiment of the present invention, Figure 8 A connection diagram of a third seed driving circuit provided by an embodiment of the present invention, Figure 9 A connection diagram of a fourth seed driving circuit provided in an embodiment of the present invention is shown. Figure 10 This is a connection diagram of the fifth seed driving circuit provided by an embodiment of the present invention. Figures 6 to 10 , two sub-pixels of the same color are staggered by a predetermined distance in the first direction; or two sub-pixels of the same color are aligned in the first direction.

[0088] The connection method of the sub-driving circuits of the present invention is merely an exemplary connection method, but is not limited thereto.

[0089] Figure 11 A schematic diagram of a pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 11 As shown, the pixel driving circuit includes: a first storage capacitor Cst, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7.

[0090] One end of the first storage capacitor Cst is connected to the power line ELVDD, and the other end of the storage capacitor is connected to the first node N1;

[0091] The control electrode of the first transistor T1 is connected to the first gate signal line or the third gate signal line, the first electrode of the first transistor T1 is connected to the first node N1, and the second electrode of the first transistor T1 is connected to the initialization voltage level signal line Vinit, wherein,

[0092] The control electrode of the second transistor T2 is connected to the second gate signal line or the fourth gate signal line, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3;

[0093] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3;

[0094] A control electrode of the fourth transistor T4 is connected to the second gate signal line or the fourth gate signal line, a first electrode of the fourth transistor T4 is connected to the second node N2, and a second electrode of the fourth transistor T4 is connected to the data line Data.

[0095] The control electrode of the fifth transistor T5 is connected to the first light emitting control signal line EM, the first electrode of the fifth transistor T5 is connected to the second node N2, and the second electrode of the fifth transistor T5 is connected to the power line ELVDD;

[0096] The control electrode of the sixth transistor T6 is connected to the first light emitting control signal line EM, the first electrode of the sixth transistor T6 is connected to the fourth node N4, and the second electrode of the sixth transistor T6 is connected to the third node N3;

[0097] The control electrode of the seventh transistor T7 is connected to the second gate signal line or the fourth gate signal line, the first electrode of the seventh transistor T7 is connected to the fourth node N4, and the second electrode of the seventh transistor T7 is connected to the initialization voltage level signal line Vinit.

[0098] Among them, Figure 11 The pixel driving circuit shown is divided into a first sub-driving circuit and a second sub-driving circuit. The at least two anodes include a first anode and a second anode. The first sub-driving circuit corresponds to the first anode, and the second sub-driving circuit corresponds to the second anode.

[0099] The first sub-driver circuit includes a first storage capacitor Cst, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The second sub-driver circuit includes a first transistor T1, a second transistor T2, a sixth transistor T6, and a seventh transistor T7. T3, T4, T5, and Cst are shielded by the first anode, while T1, T2, T6, and T7 are shielded by the second anode. Using ITO to connect N1 to T1 and T2 reduces Ioff, which is beneficial for low frequencies while leaving data writing unaffected and maintaining high-frequency image quality.

[0100] Optionally, the first sub-driver circuit includes a first storage capacitor Cst, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a seventh transistor T7, and the second sub-driver circuit includes a fifth transistor T5 and a sixth transistor T6. T1, T2, T3, T4, T7, and Cst are shielded by the first anode, while T5 and T6 are shielded by the second anode. This reduces the number of horizontal traces while maintaining data writing and high-frequency image quality.

[0101] Optionally, the first sub-driver circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and the second sub-driver circuit includes a first storage capacitor Cst and the third transistor T3. T1, T2, T4, T5, T6, and T7 are shielded by anode 1, while T3 and Cst are shielded by anode 2. This reduces the number of lateral traces and reduces the Ioff of T1 and T2, which is beneficial for low frequencies.

[0102] Optionally, the first sub-driver circuit includes a first transistor T1, a second transistor T2, a fourth transistor T4, and a seventh transistor T7, and the second sub-driver circuit includes a first storage capacitor Cst, a third transistor T3, a fifth transistor T5, and a sixth transistor T6. T1, T2, T4, and T7 are shielded by the first anode, while T3, T5, T6, and Cst are shielded by the second anode. This reduces the number of lateral traces and reduces the Ioff of T1 and T2, which is beneficial for low frequencies.

[0103] Figure 12 For Figure 6 The corresponding light control signal and gate signal connection diagram with the sub-drive circuit, combined with Figure 6 、 Figure 11 and Figure 12 The display panel of the present invention further includes: a first signal line and a second signal line, the first signal line including: a first light-emitting control signal line EM1 and a second gate signal line Gate2, and the second signal line including: a second light-emitting control signal line EM2 and a fourth gate signal line Gate4.

[0104] refer to Figure 12 (a) In the second display area, the second light-emitting control signal EM2 is connected to the control electrode of the fifth transistor T5, the fourth gate signal line Gate4 is connected to the control electrode of the second transistor T2, the first light-emitting control signal line EM1 is located in the first display area and not in the second display area, and the second gate signal line Gate2 is located in the first display area and not in the second display area.

[0105] refer to Figure 12 (b) In the second display area, the first light-emitting control signal EM1 is connected to the control electrode of the fifth transistor T5, the second gate signal Gate2 is connected to the control electrode of the second transistor T2, the second light-emitting control signal line EM2 is located in the first display area and not in the second display area, and the fourth gate signal line Gate4 is located in the first display area and not in the second display area.

[0106] refer to Figure 12 (c) In the second display area, the first light-emitting control signal EM1 is connected to the control electrode of the fifth transistor T5, the second gate signal Gate2 is connected to the control electrode of the second transistor T2, the second light-emitting control signal line EM2 is disconnected, and the fourth gate signal line Gate4 is disconnected.

[0107] The display panel is characterized by further comprising: a data line and a power line, wherein the data line is connected to the second electrode of the fourth transistor, and the power line is connected to the second electrode of the fifth transistor.

[0108] Figure 13 For Figure 6 Schematic diagram of the specific connection between the corresponding light-emitting control signal and the gate signal and the sub-driving circuit; refer to Figure 6 、 Figure 11 and Figure 13 The first sub-drive circuit includes a first storage capacitor Cst, a third transistor T3, a fourth transistor T4, and a fifth transistor T5. The second sub-drive circuit includes a first transistor T1, a second transistor T2, a sixth transistor T6, and a seventh transistor T7. T3, T4, T5, and Cst are shielded by the first anode, while T1, T2, T6, and T7 are shielded by the second anode. Using ITO to connect N1 to T1 and T2 reduces Ioff, which is beneficial for low frequencies. Data writing is not affected, and high-frequency image quality is not affected.

[0109] The embodiment of the present invention splits a pixel driving circuit into at least two sub-driving circuits, so that the pixel driving circuit in the camera area is reduced by at least half, thereby achieving high transmittance in the camera area while ensuring that the display PPI of the camera area remains unchanged.

[0110] An embodiment of the present invention provides a method for manufacturing a display panel, wherein the display panel includes a base substrate, the base substrate including a first display area and a second display area, wherein the transmittance of the second display area is greater than the transmittance of the first display area, and the method includes:

[0111] A plurality of pixel areas and light-transmitting areas located between the plurality of pixel areas are formed in the second display area; wherein, a plurality of groups of sub-pixels of different colors are located in the plurality of pixel areas, each group of sub-pixels includes at least two sub-pixels of the same color, each group of sub-pixels includes at least one pixel driving circuit and at least two anodes, and the orthographic projection of the at least one pixel driving circuit on the substrate is located within the orthographic projection of the at least two anodes on the substrate.

[0112] Exemplarily, the number of the at least one pixel driving circuit is one, and the orthographic projection of the one pixel driving circuit on the substrate is located within the orthographic projection of the at least two anodes on the substrate.

[0113] Exemplarily, the one pixel driving circuit includes at least two sub-driving circuits, the at least two sub-driving circuits corresponding one-to-one to the at least two sub-pixels of the same color, and the at least two sub-driving circuits corresponding one-to-one to the at least two anodes, each sub-driving circuit is located between the corresponding anode and the base substrate of the display panel, the orthographic projection of each sub-driving circuit on the base substrate is located within the orthographic projection of the corresponding anode on the base substrate, the at least two sub-driving circuits are connected by a first transparent wiring, and the at least two anodes are connected by a second transparent wiring.

[0114] Exemplarily, the first transparent wiring and the second transparent wiring are formed through one patterning process.

[0115] Figure 14 For Figure 6 The corresponding cutting line diagram, Figure 15 A cross-sectional view of sub-pixels of the same color provided by an embodiment of the present invention, Figure 16 Schematic diagram of the manufacturing process of the display panel according to the embodiment of the present invention; Figure 14 、 Figure 15 、 Figure 16 .

[0116] The method for manufacturing a display panel provided by an embodiment of the present invention includes: manufacturing a semiconductor layer on a base substrate; and manufacturing a first insulating layer on the semiconductor layer. The base substrate may be a glass substrate or a quartz substrate.

[0117] Specifically, a layer of semiconductor material and an insulating material are sequentially deposited on a substrate, a layer of photoresist is coated on the insulating material, and the photoresist is exposed using a halftone or gray tone mask to form a photoresist unretained area, a photoresist partially retained area, and a photoresist completely retained area, wherein the photoresist completely retained area corresponds to an area where the pattern of the etch stop layer is located, and the photoresist unretained area corresponds to an area outside the pattern of the active layer; a development process is performed to completely remove the photoresist in the unretained area, while the thickness of the photoresist in the completely retained area remains unchanged, and part of the photoresist is retained in the partially retained area; the semiconductor material in the unretained area is completely etched away through an etching process to form a pattern of the active layer; the photoresist in the partially retained area is ashed, and the insulating material in the partially retained area is etched away through an etching process to form a pattern of the etch stop layer, and the remaining photoresist is stripped off.

[0118] A first gate layer is formed on the first insulating layer; specifically, a sputtering or thermal evaporation method can be used to deposit a thickness of about 100 nm on the completed substrate. The gate metal layer can be made of metals such as Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and alloys of these metals. The gate metal layer can be a single-layer structure or a multi-layer structure. The multi-layer structure can be Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. A layer of photoresist is coated on the gate metal layer, and the photoresist is exposed using a mask to form a photoresist-unretained area and a photoresist-retained area, wherein the photoresist-retained area corresponds to the area where the patterns of the gate lines and gate electrodes are located, and the photoresist-unretained area corresponds to the area outside the above-mentioned patterns; a development process is performed to completely remove the photoresist in the photoresist-unretained area, and the photoresist thickness in the photoresist-retained area remains unchanged; the gate metal film in the photoresist-unretained area is completely etched away through an etching process, and the remaining photoresist is stripped off to form the patterns of the gate lines and gate electrodes.

[0119] A second insulating layer is formed on the first gate layer; specifically, a plasma enhanced chemical vapor deposition (PECVD) method can be used to deposit a second insulating layer with a thickness of The gate insulating layer can be made of oxide, nitride or oxygen-nitrogen compound, and the corresponding reaction gas is SiH4, NH3, N2 or SiH2Cl2, NH3, N2.

[0120] forming a first transparent trace on the second insulating layer;

[0121] forming a third insulating layer, a second gate layer, and a fourth insulating layer on the second insulating layer;

[0122] opening via holes in the first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer;

[0123] A source and a drain are fabricated on the fourth insulating layer, and the source and the drain are connected to the semiconductor layer through the vias, wherein the sources of the two pixel driving sub-circuits for driving two sub-pixels of the same color are both connected to the first transparent wiring, or the drains of the two sub-pixels of the same color are both connected to the first transparent wiring.

[0124] Specifically, a layer with a thickness of about 100 nm can be deposited on the substrate after the fourth insulating layer is formed by magnetron sputtering, thermal evaporation or other film forming methods. The source-drain metal layer can be made of Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, and other metals, as well as alloys of these metals. The source-drain metal layer can be a single-layer structure or a multi-layer structure, and the multi-layer structure can be Cu\Mo, Ti\Cu\Ti, Mo\Al\Mo, etc. A layer of photoresist is coated on the source-drain metal layer, and the photoresist is exposed using a mask to form a photoresist-unretained area and a photoresist-retained area, wherein the photoresist-retained area corresponds to the area where the source electrode and drain electrode patterns are located, and the photoresist-unretained area corresponds to the area outside the above patterns; a development process is performed to completely remove the photoresist in the photoresist-unretained area, and the photoresist thickness in the photoresist-retained area remains unchanged; the source-drain metal layer in the photoresist-unretained area is completely etched away through an etching process, and the remaining photoresist is stripped off to form a drain electrode and a source electrode.

[0125] A fifth insulating layer is formed on the fourth insulating layer.

[0126] A third transparent wiring is manufactured on the fifth insulating layer, and the third transparent wiring is a data line or a power line.

[0127] Specifically, a layer with a thickness of about 100 nm can be deposited on the substrate after the fifth insulating layer is formed by magnetron sputtering, thermal evaporation or other film forming methods. A metal layer is formed, which may be made of Cu, Al, Ag, Mo, Cr, Nd, Ni, Mn, Ti, Ta, W, or other metals, as well as alloys thereof. A layer of photoresist is coated on the metal layer, and the photoresist is exposed using a mask to form a photoresist-unretained area and a photoresist-retained area, wherein the photoresist-retained area corresponds to the area where the data line pattern is located, and the photoresist-unretained area corresponds to the area outside the above-mentioned pattern. A development process is performed to completely remove the photoresist in the photoresist-unretained area, while the thickness of the photoresist in the photoresist-retained area remains unchanged. An etching process is then performed to completely etch away the source and drain metal layers in the photoresist-unretained area, and the remaining photoresist is stripped off to form a drain electrode data line.

[0128] A sixth insulating layer and an anode are formed on the fifth insulating layer.

[0129] Figure 17 A cross-sectional view of another sub-pixel of the same color provided by an embodiment of the present invention, Figure 17 and Figure 15 The difference is that only one layer of transparent traces is made.

[0130] Figure 18 For Figure 7 Schematic diagram of the specific connection between the corresponding light-emitting control signal and gate signal and the sub-driving circuit; Figure 19 For Figure 7 Schematic diagram of the corresponding cutting line. Figure 20 This is another cross-sectional view of sub-pixels of the same color provided by an embodiment of the present invention; both cross sections are B because the horizontal wiring partially passes through Gate 1 and partially passes through Gate 2.

[0131] A third aspect of the present invention provides a display device comprising the display panel described above.

[0132] The display device includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output unit, an input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. Those skilled in the art will appreciate that the structure of the above-mentioned display device does not limit the display device, and the display device may include more or fewer of the above-mentioned components, or a combination of certain components, or a different arrangement of components. In embodiments of the present invention, the display device includes, but is not limited to, a monitor, a mobile phone, a tablet computer, a television, a wearable electronic device, a navigation display device, and the like.

[0133] The display device can be any product or component with a display function, such as an LCD TV, an LCD monitor, a digital photo frame, a mobile phone, or a tablet computer. The display device further includes a flexible circuit board, a printed circuit board, and a backplane.

[0134] In the various method embodiments of the present invention, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present invention.

[0135] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, since the embodiments are generally similar to the product embodiments, the description is relatively simple. For relevant parts, refer to the partial description of the product embodiments.

[0136] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0137] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0138] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0139] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: include: a base substrate, the base substrate comprising a first display area and a second display area, the second display area having a light transmittance greater than that of the first display area, the second display area comprising a plurality of pixel areas and a light-transmitting area located between the plurality of pixel areas; A plurality of groups of sub-pixels of different colors are located in the plurality of pixel regions, each group of sub-pixels includes at least two sub-pixels of the same color, each group of sub-pixels includes at least one pixel driving circuit and at least two anodes, and an orthographic projection of the at least one pixel driving circuit on the substrate is located within an orthographic projection of the at least two anodes on the substrate; The number of the at least one pixel driving circuit is one, and the orthographic projection of the one pixel driving circuit on the substrate is located within the orthographic projection of the at least two anodes on the substrate; The pixel driving circuit includes at least two sub-driving circuits, the at least two sub-driving circuits corresponding one-to-one to the at least two sub-pixels of the same color, and the at least two sub-driving circuits corresponding one-to-one to the at least two anodes, each sub-driving circuit is located between the corresponding anode and the base substrate of the display panel, the orthographic projection of each sub-driving circuit on the base substrate is located within the orthographic projection of the corresponding anode on the base substrate, the at least two sub-driving circuits are connected by a first transparent trace, and the at least two anodes are connected by a second transparent trace; The pixel driving circuit comprises: a first storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; Wherein, one end of the first storage capacitor is connected to the power line, and the other end of the storage capacitor is connected to the first node; The control electrode of the first transistor is connected to the first gate signal line or the third gate signal line, the first electrode of the first transistor is connected to the first node, and the second electrode of the first transistor is connected to the initialization voltage level signal line; The control electrode of the second transistor is connected to the second gate signal line or the fourth gate signal line, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the third node; The control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the second electrode of the third transistor is connected to the third node; The control electrode of the fourth transistor is connected to the second gate signal line or the fourth gate signal line, the first electrode of the fourth transistor is connected to the second node, and the second electrode of the fourth transistor is connected to the data line; The control electrode of the fifth transistor is connected to the first light-emitting control signal line or the second light-emitting control signal line, the first electrode of the fifth transistor is connected to the second node, and the second electrode of the fifth transistor is connected to the power line; The control electrode of the sixth transistor is connected to the first light-emitting control signal line or the second light-emitting control signal line, the first electrode of the sixth transistor is connected to the fourth node, and the second electrode of the sixth transistor is connected to the third node; The control electrode of the seventh transistor is connected to the second gate signal line or the fourth gate signal line, the first electrode of the seventh transistor is connected to the fourth node, and the second electrode of the seventh transistor is connected to the initialization voltage level signal line; The at least two sub-driving circuits include: a first sub-driving circuit and a second sub-driving circuit; the at least two anodes include a first anode and a second anode; the first sub-driving circuit corresponds to the first anode; and the second sub-driving circuit corresponds to the second anode; The first sub-driving circuit includes the first storage capacitor, the third transistor, the fourth transistor, and the fifth transistor, and the second sub-driving circuit includes the first transistor, the second transistor, the sixth transistor, and the seventh transistor; or The first sub-driving circuit includes the first storage capacitor, the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor, and the second sub-driving circuit includes the fifth transistor and the sixth transistor; or The first sub-driving circuit includes the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, and the second sub-driving circuit includes the first storage capacitor and the third transistor; or The first sub-driving circuit includes the first transistor, the second transistor, the fourth transistor, and the seventh transistor. The second sub-driving circuit includes the first storage capacitor, the third transistor, the fifth transistor, and the sixth transistor.

2. The display panel according to claim 1, wherein: The first transparent wiring and the second transparent wiring are arranged in the same layer or in different layers, and at least part of the first transparent wiring and at least part of the second transparent wiring are located in the light-transmitting area.

3. The display panel according to claim 1, wherein: The at least two sub-pixels of the same color are staggered by a predetermined distance in the first direction; or The at least two sub-pixels of the same color are aligned in a first direction.

4. The display panel according to claim 1, further comprising: A first signal line and a second signal line, wherein the first signal line includes: a first light-emitting control signal line and a second gate signal line, and the second signal line includes: a second light-emitting control signal line and a fourth gate signal line; characterized in that: In the second display area, the first light-emitting control signal is connected to the control electrode of the fifth transistor, the second gating signal is connected to the control electrode of the second transistor, the second light-emitting control signal line is located in the first display area and not in the second display area, and the fourth gating signal line is located in the first display area and not in the second display area; or In the second display area, the second light-emitting control signal is connected to the control electrode of the fifth transistor, the fourth gate signal line is connected to the control electrode of the second transistor, the first light-emitting control signal line is located in the first display area and not in the second display area, and the second gate signal line is located in the first display area and not in the second display area.

5. The display panel according to claim 4, wherein: Also includes: A data line and a power line, wherein the data line is connected to the second electrode of the fourth transistor, and the power line is connected to the second electrode of the fifth transistor.

6. A method for manufacturing a display panel, the display panel comprising: A base substrate, wherein the base substrate includes a first display area and a second display area, wherein the transmittance of the second display area is greater than the transmittance of the first display area, wherein the method includes: A plurality of pixel regions and a light-transmitting region located between the plurality of pixel regions are formed in the second display area; wherein a plurality of groups of sub-pixels of different colors are located in the plurality of pixel regions, each group of sub-pixels includes at least two sub-pixels of the same color, each group of sub-pixels includes at least one pixel driving circuit and at least two anodes, and an orthographic projection of the at least one pixel driving circuit on the base substrate is located within an orthographic projection of the at least two anodes on the base substrate; The number of the at least one pixel driving circuit is one, and the orthographic projection of the one pixel driving circuit on the substrate is located within the orthographic projection of the at least two anodes on the substrate; the one pixel driving circuit includes at least two sub-driving circuits, the at least two sub-driving circuits correspond one-to-one to the at least two sub-pixels of the same color, and the at least two sub-driving circuits correspond one-to-one to the at least two anodes; The method further includes: arranging each sub-driving circuit between a corresponding anode and the base substrate of the display panel, arranging an orthographic projection of each sub-driving circuit on the base substrate within an orthographic projection of a corresponding anode on the base substrate, connecting the at least two sub-driving circuits via a first transparent trace, and connecting the at least two anodes via a second transparent trace; The method further includes: setting the pixel driving circuit to include: a first storage capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor; wherein one end of the first storage capacitor is connected to the power line, and the other end of the storage capacitor is connected to the first node; the control electrode of the first transistor is connected to the first gate signal line or the third gate signal line, the first electrode of the first transistor is connected to the first node, and the second electrode of the first transistor is connected to the initialization voltage level signal line; the control electrode of the second transistor is connected to the second gate signal line or the fourth gate signal line, the first electrode of the second transistor is connected to the first node, and the second electrode of the second transistor is connected to the third node; the control electrode of the third transistor is connected to the first node, the first electrode of the third transistor is connected to the second node, and the first electrode of the third transistor is connected to the initialization voltage level signal line. a second electrode connected to the third node; a control electrode of the fourth transistor connected to the second gating signal line or the fourth gating signal line, a first electrode of the fourth transistor connected to the second node, and a second electrode of the fourth transistor connected to the data line; a control electrode of the fifth transistor connected to the first light-emitting control signal line or the second light-emitting control signal line, a first electrode of the fifth transistor connected to the second node, and a second electrode of the fifth transistor connected to the power line; a control electrode of the sixth transistor connected to the first light-emitting control signal line or the second light-emitting control signal line, a first electrode of the sixth transistor connected to the fourth node, and a second electrode of the sixth transistor connected to the third node; a control electrode of the seventh transistor connected to the second gating signal line or the fourth gating signal line, a first electrode of the seventh transistor connected to the fourth node, and a second electrode of the seventh transistor connected to the initialization voltage level signal line; The method further includes: configuring the at least two sub-driving circuits to include a first sub-driving circuit and a second sub-driving circuit, configuring the at least two anodes to include a first anode and a second anode, wherein the first sub-driving circuit corresponds to the first anode, and the second sub-driving circuit corresponds to the second anode; The first sub-driving circuit includes the first storage capacitor, the third transistor, the fourth transistor, and the fifth transistor, and the second sub-driving circuit includes the first transistor, the second transistor, the sixth transistor, and the seventh transistor; or The first sub-driving circuit includes the first storage capacitor, the first transistor, the second transistor, the third transistor, the fourth transistor, and the seventh transistor, and the second sub-driving circuit includes the fifth transistor and the sixth transistor; or The first sub-driving circuit includes the first transistor, the second transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor, and the second sub-driving circuit includes the first storage capacitor and the third transistor; or The first sub-driving circuit includes the first transistor, the second transistor, the fourth transistor, and the seventh transistor. The second sub-driving circuit includes the first storage capacitor, the third transistor, the fifth transistor, and the sixth transistor.

7. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 5.

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