High-voltage semiconductor devices

Abstract

A high-voltage semiconductor device comprises a substrate, a buried layer, a drain region, a source region, a gate, and at least one concentration-modulated region. The substrate has a first conductivity type, the buried layer is disposed within the substrate and has a second conductivity type. The drain region and the source region are disposed within the substrate and above the buried layer, and the gate is disposed on the substrate and between the source region and the drain region. The at least one concentration-modulated region is disposed partially within the buried layer and below the drain region, wherein the at least one concentration-modulated region has the second conductivity type and a doping concentration less than that of the buried layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and in particular to a high-voltage semiconductor device. Background Art

[0002] With the advancement of semiconductor technology, the industry has been able to integrate control circuits, memory, low-voltage operating circuits, high-voltage operating circuits and related components onto a single chip to reduce costs and improve operating performance. Transistor devices, which are commonly used to amplify current or voltage signals in circuits, act as circuit oscillators, or act as switching elements to control circuit switching, have been used as high-power or high-voltage components with the advancement of semiconductor process technology. For example, transistor devices used as high-voltage components are placed between the chip's internal circuits and the input / output (I / O) pins to prevent a large amount of charge from entering the internal circuits through the I / O pins in a very short period of time and causing damage.

[0003] Current high-voltage transistors primarily increase their breakdown voltage by reducing lateral electric fields. These devices generally include double diffused drain metal oxide semiconductors (DDDMOS) and laterally diffused drain metal oxide semiconductors (LDMOS). However, further increasing the breakdown voltage of high-voltage semiconductor devices to meet practical requirements remains a challenge facing the industry. Summary of the Invention

[0004] The object of the present invention is to provide a high-voltage semiconductor device, which locally adds at least one concentration-modulated region within an insulating buried layer below a drain region. The at least one concentration-modulated region has the same conductivity type, the same dopant, and a lower doping concentration as the insulating buried layer, thereby reducing the electric field strength below the drain region and thereby increasing the breakdown voltage of the high-voltage semiconductor device.

[0005] To achieve the above-mentioned purpose, a preferred embodiment of the present invention provides a high-voltage semiconductor device, which includes a substrate, a buried layer, a drain region, a source region, a gate, and at least one concentration modulation region. The substrate has a first conductivity type, the buried layer is arranged in the substrate, and has a second conductivity type, and the second conductivity type is complementary to the first conductivity type. The drain region is arranged in the substrate and located above the buried layer, and the drain region has the first conductivity type. The source region is arranged in the substrate and located above the buried layer, and the source region has the first conductivity type. The gate is arranged on the substrate, located between the source region and the drain region. The at least one concentration modulation region is arranged in a local buried layer. The at least one concentration modulation region is located below the drain region and has the second conductivity type, and the doping concentration of the concentration modulation regions is less than the doping concentration of the buried layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 1 is a top view schematically showing a high-voltage semiconductor device according to a first embodiment of the present invention.

[0007] Figure 2 for Figure 1 Schematic cross-section along the tangent line AA'.

[0008] Figure 3 FIG. 1 is a schematic diagram illustrating simulation test results of a high-voltage semiconductor device according to a first embodiment of the present invention.

[0009] Figure 4 FIG. 1 is a schematic diagram illustrating a high-voltage semiconductor device according to a second embodiment of the present invention.

[0010] Figure 5 FIG. 1 is a schematic diagram illustrating a high-voltage semiconductor device according to a third embodiment of the present invention.

[0011] Figure 6 FIG. 1 is a schematic diagram illustrating a high-voltage semiconductor device according to a fourth embodiment of the present invention.

[0012] Figure 7 FIG. 1 is a schematic diagram illustrating a high-voltage semiconductor device according to a fifth embodiment of the present invention.

[0013] The description of the accompanying drawings is as follows:

[0014] 100, 300, 400, 500, 600: High-voltage semiconductor devices

[0015] 110: Base

[0016] 120, 320, 420, 520, 620: buried layer

[0017] 121: Concentration modulation area

[0018] 130: First Well Area

[0019] 140: Second Well Area

[0020] 150: Drain area

[0021] 160: Source region

[0022] 170: Matrix area

[0023] 190, 191, 193, 195: Insulation structure

[0024] 210: Gate

[0025] 211: Gate dielectric layer

[0026] 213: Gate electrode layer

[0027] 321: Concentration modulation area

[0028] 323: Square doped region

[0029] 421: Concentration modulation area

[0030] 521, 523: Concentration modulation area

[0031] 621, 623: Concentration modulation area

[0032] D1: First direction

[0033] D2: Second direction

[0034] E1, E2: Curve DETAILED DESCRIPTION

[0035] To help those skilled in the art further understand the present invention, several preferred embodiments of the present invention are listed below, along with accompanying drawings, to explain in detail the present invention's components and intended functions. Furthermore, those skilled in the art can, by referring to the following embodiments, replace, reorganize, or combine features from the various embodiments to create other embodiments without departing from the spirit of the present invention.

[0036] In the present invention, the statement "a first component is formed on or above a second component" may mean "the first component is in direct contact with the second component" or "another component is present between the first component and the second component," such that the first component and the second component are not in direct contact. Furthermore, various embodiments of the present invention may use repeated element numbers and / or textual notations. These repeated element numbers and textual notations are used to make the description more concise and clear, and are not used to indicate the relationship between different embodiments and / or configurations. Furthermore, for the purposes of the present invention, spatially relative terms such as "below," "above," "low," "high," "below," "above," "under," "above," "bottom," "top," and similar terms are used to describe the relative relationship of one component or feature to another (or multiple) components or features in the drawings for ease of description. In addition to the orientations shown in the drawings, these spatially relative terms are also used to describe possible orientations of the semiconductor device during fabrication, use, and operation. For example, when a semiconductor device is rotated 180 degrees, a component that was originally positioned "above" other components will now be positioned "below" the other components. Therefore, as the orientation of the semiconductor device changes (rotated 90 degrees or at other angles), spatially relative descriptions used to describe its orientation should be interpreted accordingly.

[0037] Although the present invention uses terms such as first, second, and third to describe various elements, components, regions, layers, and / or sections, it should be understood that these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, and / or section from another element, component, region, layer, and / or section, and do not represent any preceding ordinal number of the element, nor do they represent the order in which one element is arranged relative to another element, or the order in which one element is manufactured. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section.

[0038] The terms "about" or "substantially" mentioned herein generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the quantities provided in the specification are approximate quantities, that is, even if the word "about" or "substantially" is not specifically stated, the meaning of "about" or "substantially" may still be implied.

[0039] Please refer to Figure 1 and Figure 2, which illustrates a schematic diagram of a high-voltage semiconductor device 100 according to a first embodiment of the present invention, wherein: Figure 1 is a top view of the high-voltage semiconductor device 100. Figure 2 FIG1 is a cross-sectional view of a high-voltage semiconductor device 100. The high-voltage semiconductor device of the present invention refers to a semiconductor device having an operating voltage greater than approximately 90 volts (V), such as a laterally diffused metal oxide semiconductor transistor (LDMOS transistor), which may be a laterally diffused N-type LDMOS transistor or a laterally diffused P-type LDMOS transistor. In this embodiment, the high-voltage semiconductor device 100 is described using a laterally diffused P-type LDMOS transistor as an implementation, but the present invention is not limited thereto.

[0040] First, if Figure 1 and Figure 2 As shown, the high-voltage semiconductor device 100 includes a substrate 110, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, and at least one insulating structure 190 disposed on the substrate 110. In this embodiment, the insulating structure 190 is, for example, a field oxide (FOX) formed by a local oxidation of silicon (LOCOS) method. Figure 2 In another embodiment, the insulating structure may also be a shallow trench isolation (STI) formed by a deposition process or an insulating unit made by other suitable processes. It should be noted that in order to clearly show the relative relationship between certain specific doping regions in the high voltage semiconductor device 100, Figure 1 The insulating structure 190 is omitted, but a person skilled in the art should be able to Figure 2 It is easy to understand the location of the insulating structure 190. In addition, the specific location and quantity of the insulating structure 190 of the present invention will be described in the following paragraphs.

[0041] The substrate 110 has a first conductivity type (for example, P-type), and a first well region 130 and a second well region 140 are respectively provided therein. Specifically, the first well region 130 has the first conductivity type (such as P-type), and a drain region 150 is also formed in the first well region 130. The drain region 150 also has the first conductivity type (such as P-type), and its doping concentration is preferably greater than the doping concentration of the first well region 130. The second well region 140 is arranged in a ring outside the first well region 130 and has a second conductivity type (for example, N-type), and the second conductivity type (such as N-type) is complementary to the first conductivity type (such as P-type). In this embodiment, the depth of the second well region 140 in the substrate 110 is, for example, greater than the first well region 130, such as Figure 2 As shown, but not limited thereto, a source region 160 is formed in the second well region 140 , and the source region 160 has the first conductivity type (eg, P-type).

[0042] In addition, a body region 170 is formed in the second well region 140. The body region 170 has the second conductivity type (e.g., N-type) and its doping concentration is preferably greater than the doping concentration of the second well region 140. In one embodiment, the body region 170 is preferably not in direct contact with the drain region 150 disposed in the first well region 130. For example, an insulating structure 191 and an insulating structure 193 may be disposed on two opposite sides of the body region 170, respectively, while an insulating structure 193 and an insulating structure 195 may be disposed on two opposite sides of the drain region 150, respectively. In this way, the insulating structure 193 may be sandwiched between the drain region 150 and the body region 170, so that the drain region 150 and the body region 170 are electrically isolated from each other, as shown in FIG. Figure 2 Furthermore, in one embodiment, the base region 170 may be annular, for example, Figure 1 The rectangular frame shown in FIG. 1 may surround the drain region 150 and the source region 160. However, those skilled in the art will appreciate that in another embodiment, the base region may have other shapes, such as a square, annular, racetrack-shaped, or other suitable shapes, instead of the conventional rectangular frame. Figure 1The figures shown are limited. In addition, a gate 210 is also provided on the substrate 110. The gate 210 may include a gate dielectric layer 211 and a gate electrode layer 213 stacked in sequence on the substrate 110. The gate electrode layer 213 is, for example, a polysilicon gate layer or a metal gate layer, but is not limited thereto. The gate 210 is located between the source region 160 and the drain region 150. In this embodiment, one side of the gate 210 partially covers the second well region 140 in the substrate 110 and is adjacent to the source region 160, while the other side of the gate 210 partially covers the first well region 130 and the insulating structure 195 without directly contacting the drain region 150.

[0043] On the other hand, a buried layer 120 is further provided within the substrate 110, located below the first well region 130 and the second well region 140. The buried layer 120 may have the second conductivity type (e.g., N-type) and have a higher doping concentration than the first well region 130 and the second well region 140. In this embodiment, the buried layer 120 and the second well region 140 within the substrate 110 together serve as an isolation layer for the high-voltage semiconductor device 100, thereby preventing current from directly penetrating from the first well region 130 through the bottom or interior of the substrate 110 and affecting the device performance of the high-voltage semiconductor device 100. It should be noted that the high-voltage semiconductor device 100 of this embodiment further includes at least one concentration modulated region 121 partially opened within the buried layer 120. The number of concentration-modulated regions 121 can be single or multiple. The high-voltage semiconductor device 100 of this embodiment is described as having two separated concentration-modulated regions 121 within a local buried layer 120, but the present invention is not limited thereto. Those skilled in the art will readily appreciate that the number of concentration-modulated regions can be further adjusted based on actual device requirements, such as providing only a single concentration-modulated region within a local buried layer 120 or providing two or more concentration-modulated regions.

[0044] It should be noted that the concentration modulation region 121 is preferably disposed in a location with a stronger electric field in the high-voltage semiconductor device 100, such as adjacent to the PN junction between the first well region 130 and the second well region 140, or at the PN junction between the first well region 130 and the buried layer 120, but the present invention is not limited thereto. For example, the concentration modulation region 121 can be disposed in the buried layer 120 below the drain region 150 and the first well region 130, and extend between the top and bottom surfaces of the buried layer 120, and directly contact the first well region 130, such as Figure 2 As shown. Among them, each concentration modulation area 121 is as follows Figure 1The top view shown is, for example, a strip-shaped doped region, and the overall coverage area of ​​the concentration modulation region 121 is preferably smaller than the coverage area of ​​the first well region 130. Figure 1 and Figure 2 As shown. In a preferred embodiment, the projection of the concentration-modulated region 121 in a direction perpendicular to the substrate 110 (not shown) does not exceed the projection of the first well region 130 in the perpendicular direction. In one embodiment, the concentration-modulated region 121 is formed, for example, by providing a shield (not shown) during the ion implantation process of the buried layer 120. The shield blocks a local area of ​​the substrate 110, preventing dopants from being implanted in the ion implantation process. Instead, the local area receives only a small amount of dopants diffused from the buried layer 120 during the subsequent thermal drive-in process. Therefore, the concentration-modulated region 121 can have the same conductivity type (e.g., N-type) and dopant content as the buried layer 120, and a relatively low doping concentration. For example, the doping concentration of the concentration-modulated region 121 can be reduced by approximately 10% to 20%, preferably by approximately 15%, compared to the doping concentration of the buried layer 120, but this is not limited thereto. In another embodiment, the formation of the concentration modulation region 121 can also be selected to be performed before or after the formation of the buried layer 120. For example, another ion implantation process can be used to directly form a doping region with a relatively low doping concentration in the local substrate 110 as the concentration modulation region, and then the buried layer 120 is formed. Alternatively, when forming the buried layer 120 in the substrate 110, a local space is first reserved, and then another ion implantation process is used to directly form a doping region with a relatively low doping concentration in the reserved space as the concentration modulation region, but the present invention is not limited to this.

[0045] In other words, the concentration modulation region 121 is at least one opening (slot) in the buried layer 120 that is locally set (the portion below the drain region 150 and the first well region 130), and then a small amount of dopants diffused from the buried layer 120 are obtained through a thermal drive-in process, and can have a relatively low doping concentration. Therefore, the concentration modulation region 121 can reduce the electric field strength of the portion, thereby improving the problem of the high-voltage semiconductor device 100 having a low breakdown voltage in portions with stronger electric field strength (i.e., portions close to the PN junction or near the drain region 150). Under this setting, the breakdown voltage of the high-voltage semiconductor device 100 can be increased by, for example, about 5 volts, but is not limited to this. Please refer to Figure 3 As shown, the high-voltage semiconductor device 100 of this embodiment (as shown by curve E1) can indeed reduce the local electric field strength under simulation tests, thereby achieving a higher breakdown voltage than the conventional high-voltage semiconductor device (as shown by curve E2), but the present invention is not limited thereto. As a result, the high-voltage semiconductor device 100 of this embodiment can achieve better device performance.

[0046] Those skilled in the art should be able to easily understand that, in order to meet the actual product needs, the high-voltage semiconductor device of the present invention may also have other aspects, not limited to the aforementioned. For example, in the aforementioned embodiment, although the laterally diffused P-type metal oxide semiconductor transistor is used as the implementation aspect for description, and the first conductive type is P-type and the second conductive type is N-type, it is not limited to this. In another embodiment, the first conductive type can also be selected to be N-type and the second conductive type to be P-type to form high-voltage semiconductor devices of different types. Other embodiments or variations of the high-voltage semiconductor device will be further described below. And for the sake of simplicity, the following description will mainly detail the differences between the various embodiments, and will not repeat the similarities. In addition, the same elements in the various embodiments of the present invention are marked with the same reference numerals to facilitate comparison between the various embodiments.

[0047] According to another embodiment of the present invention, a high-voltage semiconductor device is provided, which can adjust the doping concentration of the buried layer locally to reduce the local electric field strength while preventing the doping concentration in the local area from being too low and affecting the effect of the buried layer as an insulating layer. Figure 4 FIG. 1 shows a schematic top view of a high-voltage semiconductor device 300 according to a second embodiment of the present invention. The structure of the high-voltage semiconductor device 300 in this embodiment is substantially the same as that of the high-voltage semiconductor device 100 described in the first embodiment, and similarly includes a substrate 110, a first well region 130, a second well region 140, a drain region 150, a source region 160, a body region 170, and an insulating structure 190. Details of the similarities are not repeated here. The primary difference between this embodiment and the aforementioned embodiment lies in the specific placement of the concentration-modulated region 321 within the buried layer 320, such as the placement area, pattern design, number, and size.

[0048] Specifically, a plurality of concentration modulation regions 321 are locally disposed within the buried layer 320 of this embodiment. The concentration modulation regions 321 are located below the drain region 150 and the first well region 130. Furthermore, the concentration modulation regions 321 may have the same conductivity type (e.g., N-type), the same dopant, and a lower doping concentration as the buried layer 320. It should be noted that the concentration modulation regions 321 of this embodiment are, for example, square doped regions, and each of the square doped regions is disposed in a manner similar to that of the first well region 130. Figure 4 In the top view shown, the layers are spaced apart and arranged in a staggered manner, and may present a checkerboard arrangement as a whole, but the present invention is not limited thereto. In other words, the local buried layer 320 of this embodiment (i.e., the portion of the buried layer 320 located below the first well region 130) may also form a plurality of square doped regions 323, and the square doped regions 323 and the concentration modulation region 321 are spaced apart and arranged in a staggered manner, such as Figure 4 shown.

[0049] As a result, the concentration-modulated region 321 of this embodiment can be more evenly distributed in areas of the high-voltage semiconductor device 300 where the electric field is relatively strong, allowing the doping concentration of the buried layer 320 below this area to be more evenly reduced. For example, the doping concentration of the buried layer 320 below this area can be reduced by approximately 10% to 20%, preferably by approximately 15%, compared to other areas. With this configuration, the high-voltage semiconductor device 300 of this embodiment can also improve the problem of low breakdown voltage in areas with relatively strong electric field strength (i.e., areas near the PN junction or near the drain region 150), effectively increasing the breakdown voltage in these areas by, for example, approximately 5 volts, thereby achieving better device performance.

[0050] Furthermore, those skilled in the art will readily appreciate that the number, pattern (e.g., square or strip), and size of the concentration-modulated regions 321 and 121 in the aforementioned embodiments are merely illustrative and not limiting. In other embodiments, the concentration-modulated regions may have other configurations based on actual device requirements, so as to more uniformly and locally reduce the doping concentration of the buried layer to achieve the effect of reducing the electric field strength. Furthermore, the overall area occupied by the concentration-modulated regions within the buried layer may also be adjusted based on actual device requirements, preferably to maximize the device breakdown voltage without affecting the buried layer's effectiveness as an insulating layer.

[0051] Please refer to Figures 5 to 7 , which respectively illustrate top views of high-voltage semiconductor devices 400 / 500 / 600 according to the third, fourth, and fifth embodiments of the present invention. The structures of the high-voltage semiconductor devices 400 / 500 / 600 are substantially the same as the high-voltage semiconductor device 300 described in the second embodiment, and are not further described. The primary difference between these embodiments and the second embodiment is that the concentration-modulated regions can have a variety of different configurations.

[0052] Specifically, in the third embodiment, the high voltage semiconductor device 400 includes a plurality of concentration modulation regions 421, and each concentration modulation region 421 is also a square doping region (with a lower doping concentration), and each of the square doping regions is as follows: Figure 5 In a top view, the high-voltage semiconductor device 500 is arranged in an in-line arrangement spaced apart from each other in the buried layer 420 below the first well region 130 or the drain region 150. In the fourth embodiment, the high-voltage semiconductor device 500 may include both a concentration-modulated region 521 and a concentration-modulated region 523. The concentration-modulated region 521 and the concentration-modulated region 523 are arranged in a manner similar to the following. Figure 6In a top view shown, each of the doped regions is a rectangular frame (with a lower doping concentration), wherein the concentration modulation region 523 and the concentration modulation region 521 are separated from each other and are located in the buried layer 520 below the first well region 130 or the drain region 150, and the concentration modulation region 523 surrounds the concentration modulation region 521. In addition, the geometric centers of the concentration modulation region 523 and the concentration modulation region 521 can overlap with each other, but are not limited to this. In the fifth embodiment, the high-voltage semiconductor device 600 can include a plurality of concentration modulation regions 621 and a plurality of concentration modulation regions 623 at the same time. The concentration modulation regions 621 are, for example, strip-shaped doped regions (with a lower doping concentration) that are parallel to each other and extend along a first direction D1, and the concentration modulation regions 623 are, for example, strip-shaped doped regions (with a lower doping concentration) that are parallel to each other and extend along a second direction D2, and the second direction D2 is different from the first direction D1. Thus, each concentration modulation region 623 is as follows. Figure 7 The top view shown may span the concentration modulation region 621 and present a grid-shaped structure in the buried layer 620 below the first well region 130 or the drain region 150, but is not limited thereto. In the fifth embodiment, the first direction D1 is, for example, perpendicular to the second direction D2. Figure 7 As shown, but not limited thereto, in another embodiment, the first direction and the second direction may be selected to intersect with each other but not be perpendicular to each other, and a concentration modulation region with a grid-like structure as a whole may still be formed.

[0053] Under the various configurations described above, the concentration modulation regions (including Figure 5 The concentration modulation region 421 is shown; Figure 6 The concentration modulation regions 521 and 523 are shown; and Figure 7 The concentration modulation regions 621, 623 shown in FIG. 4 can also be more evenly distributed in the portion of the high-voltage semiconductor device 400 / 500 / 600 where the electric field is stronger, so that the buried layer (including Figure 5 The buried layer 420 is shown; Figure 6 The buried layer 520 is shown; and Figure 7 The doping concentration of the buried layer 620 (shown) can be reduced more uniformly, for example, by approximately 10% to 20% compared to the doping concentration in other portions of the buried layer, preferably by approximately 15%, but not limited thereto. Under the aforementioned various configurations, the high-voltage semiconductor device 400 / 500 / 600 can also improve the problem of low breakdown voltage in portions of the device with stronger electric field strength (i.e., portions near the PN junction or near the drain region 150), thereby increasing the breakdown voltage in these portions by, for example, approximately 5 volts, thereby achieving better device performance.

[0054] Furthermore, it should be noted that, although the various embodiments of the present invention are described above with reference to the various concentration-modulated regions disposed within a buried layer, those skilled in the art will readily appreciate that the concentration-modulated regions described above may also be disposed within other electrically insulating layers of a high-voltage semiconductor device, such as within a deep well or a high-voltage well (HV well). Thus, the concentration-modulated regions can also be used to locally reduce the doping concentration of the electrically insulating layer, thereby locally reducing the electric field strength of the high-voltage semiconductor device.

[0055] The above descriptions are merely preferred embodiments of the present invention. Any equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the scope of protection of the present invention.

Claims

1. A high-voltage semiconductor device comprising: a substrate having a first conductivity type; a buried layer disposed in the substrate, the buried layer having a second conductivity type, and the second conductivity type is complementary to the first conductivity type; a drain region disposed in the substrate and above the buried layer, the drain region having the first conductivity type; a source region disposed in the substrate and above the buried layer, the source region having the first conductivity type; a gate disposed on the substrate and located between the source region and the drain region; and At least one concentration-modulated region is disposed in a portion of the buried layer, the at least one concentration-modulated region is located below the drain region and has the second conductivity type, and the doping concentration of the at least one concentration-modulated region is less than the doping concentration of the buried layer. The at least one concentration-modulated region is a plurality of concentration-modulated regions, and the plurality of concentration-modulated regions include a first concentration-modulated region extending along a first direction, and a second concentration-modulated region extending along a second direction. The second concentration-modulated region spans the first concentration-modulated region, and the first direction is different from the second direction.

2. The high-voltage semiconductor device according to claim 1, wherein The doping concentration of the at least one concentration-modulated region is reduced by 10% to 20% compared with the doping concentration of the buried layer.

3. The high-voltage semiconductor device according to claim 1 , further comprising: A first well region is disposed in the substrate, the first well region has the first conductivity type, and the drain region is disposed in the first well region.

4. The high-voltage semiconductor device according to claim 3, wherein: The coverage area of ​​the at least one concentration modulation region is smaller than the coverage area of ​​the first well region.

5. The high-voltage semiconductor device according to claim 3, wherein: The projection range of the at least one concentration modulation region does not exceed the projection range of the first well region.

6. The high-voltage semiconductor device according to claim 3, wherein: The at least one concentration-modulated region directly contacts the first well region.

7. The high-voltage semiconductor device according to claim 3, wherein: A PN junction is formed between the buried layer and the first well region.

8. The high-voltage semiconductor device according to claim 3, further comprising: a second well region disposed in the substrate, the second well region having the second conductivity type, wherein: The second well region surrounds the first well region, and the source region is disposed in the second well region. 9 . The high-voltage semiconductor device as claimed in claim 8 , wherein a doping concentration of the buried layer is greater than a doping concentration of the second well region.

10. The high-voltage semiconductor device according to claim 8, wherein One side of the gate partially covers the second well region, and the side of the gate is adjacent to the source region. 11 . The high-voltage semiconductor device according to claim 8 , further comprising a body region located in the second well region, wherein the body region has the second conductivity type. 12 . The high-voltage semiconductor device according to claim 11 , wherein the body region surrounds the drain region and the source region.

13. The high-voltage semiconductor device according to claim 11, further comprising: a first insulating structure disposed on the substrate and located between the base region and the drain region; as well as A second insulating structure is disposed on the substrate and located between the drain region and the gate, and the gate does not directly contact the drain region.

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