Integrated chip and preparation method thereof

Abstract

The present application provides an integrated chip and a preparation method thereof. The integrated chip includes a programmable gate array unit, which is integrated with a first bonding area and a programmable gate array connected to the first bonding area; the first dynamic storage array unit is integrated with a second bonding area and a first dynamic storage array connected to the second bonding area; the programmable gate array unit and the first dynamic storage array unit are stacked and bonded through the first bonding area and the second bonding area, and the programmable gate array is connected to the first dynamic storage array unit through the first bonding area and the second bonding area; the test module is integrated in the programmable gate array unit or the first dynamic storage array unit, and is connected to the programmable gate array or the first dynamic storage array, and is used to test and repair the first dynamic storage array. The integrated chip not only has the ability of logical programmability, but also effectively increases the number of interconnections; at the same time, it can provide high-bandwidth, high-energy-efficiency ratio, and low-latency large-capacity storage access for the logic part.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an integrated chip and a preparation method thereof. Background Art

[0002] With the rapid growth of application computing scale, the bandwidth and energy consumption overhead of storage access have become important factors limiting the development of scalable computing circuits. Summary of the invention

[0003] The present application provides an integrated chip and a method for preparing the same, wherein the integrated chip can achieve high-bandwidth, low-power, and low-latency large-capacity storage access.

[0004] In order to solve the above technical problems, a technical solution adopted by the present application is: to provide an integrated chip. The integrated chip includes a programmable gate array unit, a first dynamic storage array unit and a test module; wherein the programmable gate array unit integrates a first bonding area and a programmable gate array connected to the first bonding area; the first dynamic storage array unit integrates a second bonding area and a first dynamic storage array connected to the second bonding area; the programmable gate array unit and the first dynamic storage array unit are stacked and bonded through the first bonding area and the second bonding area, and the programmable gate array is connected to the first dynamic storage array unit through the first bonding area and the second bonding area; the test module is integrated in the programmable gate array unit or the first dynamic storage array unit, and the test module is connected to the programmable gate array or the first dynamic storage array, and is used to test and repair the first dynamic storage array.

[0005] The test module is integrated in the programmable gate array unit; the test module is connected to the first bonding area and further connected to the first dynamic storage array, and is used to test and repair the first dynamic storage array.

[0006] Among them, the programmable gate array unit includes: a first physical interface module and a test interface module; the first physical interface module is connected to the first bonding area, the test module is connected to the first physical interface module, the test interface module is connected to the test module and is used to connect to a test bus, and the test module tests and repairs the first dynamic storage array according to the test signal received by the test bus.

[0007] Wherein, the programmable gate array unit also includes: a multi-way selection module and a control module;

[0008] The multi-way selection module is connected to the first physical interface module, and the control module and the test module are connected to the multi-way selection module.

[0009] The test module is integrated in the first dynamic storage array unit; the test module is connected to the second bonding area and further connected to the first dynamic storage array, and is used to test and repair the first dynamic storage array.

[0010] Among them, the programmable gate array unit includes: a first physical interface module and a test interface module; the first physical interface module is connected to the first bonding area, the test module is connected to the second bonding area, the test interface module is connected to the first physical interface module and is used to connect to the test bus, and the test module tests and repairs the first dynamic storage array according to the test signal received by the test bus.

[0011] The first dynamic storage array unit includes a test interface module connected to the second bonding area and the test interface module, the test interface module is used to connect to a test bus, and the test module tests and repairs the first dynamic storage array according to a test signal received by the test bus.

[0012] Among them, the programmable gate array unit includes: a protection module and an interface module; the protection module is connected to the first bonding area and the interface module, the interface module is used to receive external signals and / or output signals of the first dynamic storage array, and the protection module is used to protect the programmable gate array unit to prevent external signals from damaging the programmable gate array unit.

[0013] Among them, the first dynamic storage array unit includes: a first driving module, a first level conversion module, a second level conversion module and a first buffer; the input end of the first driving module is connected to the first level conversion module, and the output end of the first driving module is connected to the second bonding area; the input end of the first buffer is connected to the second bonding area, and the output end of the first buffer is connected to the second level conversion module.

[0014] Among them, the programmable gate array unit includes: a second driving module, a second buffer, a third level conversion module and a fourth level conversion module; the input end of the second driving module is connected to the third level conversion module, and the output end of the second driving module is connected to the first bonding area; the input end of the second buffer is connected to the first bonding area, and the output end of the second buffer is connected to the fourth level conversion module.

[0015] The first dynamic storage array unit includes: a third driving module and a third buffer; the output end of the third driving module is connected to the second bonding area, and the input end of the third buffer is connected to the second bonding area.

[0016] The first dynamic storage array unit includes at least two layers, at least two layers of the first dynamic storage array unit are stacked and bonded on one side of the programmable gate array unit, and two adjacent first dynamic storage array units are stacked and bonded via their respective second bonding regions.

[0017] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a method for preparing an integrated chip. The method includes: preparing a programmable gate array unit and a first dynamic storage array unit, wherein a test unit is prepared on the programmable gate array unit or the first dynamic storage array unit; wherein the first surface of the programmable gate array unit includes a first protective layer, and the first surface of the first dynamic storage array unit includes a second protective layer; removing the first protective layer and the second protective layer; preparing a first bonding area on the first surface of the programmable gate array unit, and preparing a second bonding area on the first surface of the first dynamic storage array unit; bonding the first bonding area to the second bonding area, and then bonding the programmable gate array unit to the first dynamic storage array unit.

[0018] The steps of preparing a first bonding area on the first surface of the programmable gate array unit and preparing a second bonding area on the first surface of the first dynamic storage array unit include: preparing a first dielectric layer on the first surface of the programmable gate array unit and preparing a second dielectric layer on the first surface of the first dynamic storage array unit; preparing a first through hole on the first dielectric layer and preparing a second through hole on the second dielectric layer; and aligning the first through hole with the second through hole when bonding the first bonding area to the second bonding area.

[0019] The method further includes: preparing a second dynamic storage array unit; the first surface of the second dynamic storage array unit includes a third protective layer; removing the third protective layer; preparing a third bonding area on the first surface of the second dynamic storage array unit, and preparing a fourth bonding area on the second surface of the first dynamic storage array unit; bonding the third bonding area to the fourth bonding area, and then bonding the first dynamic storage array unit to the second dynamic storage array unit.

[0020] The steps of preparing a third bonding area on the first surface of the second dynamic memory array unit and preparing a fourth bonding area on the second surface of the first dynamic memory array unit include: preparing a third dielectric layer on the first surface of the second dynamic memory array unit and preparing a fourth dielectric layer on the second surface of the first dynamic memory array unit; preparing a third through hole on the third dielectric layer and preparing a fourth through hole on the fourth dielectric layer; and aligning the third through hole with the fourth through hole when bonding the third bonding area to the fourth bonding area.

[0021] The integrated chip and its preparation method provided by the present application are as follows: the integrated chip is provided with a programmable gate array unit so that the programmable gate array unit is integrated with a first bonding area and a programmable gate array connected to the first bonding area; at the same time, by providing a first dynamic storage array unit, the first dynamic storage array unit is integrated with a second bonding area and a first dynamic storage array connected to the second bonding area, and the programmable gate array unit and the first dynamic storage array unit are stacked and bonded through the first bonding area and the second bonding area, so that the programmable gate array of the programmable gate array unit can be connected to the first dynamic storage array unit through the first bonding area and the second bonding area; at the same time, a three-dimensional heterogeneous integrated structure is realized, so that the programmable gate array unit and the first dynamic storage array unit are integrated into a single chip, so that the integrated chip not only has the ability of logical programmability, but also effectively increases the number of interconnections; at the same time, it can provide high-bandwidth, high-energy-efficiency ratio, and low-latency large-capacity storage access for the logic part. In addition, by integrating a test module on the programmable gate array unit or the first dynamic storage array unit, the test module is connected to the programmable gate array or the first dynamic storage array, so that the first dynamic storage array can be tested and repaired through the test module. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A simplified three-dimensional structure diagram of an integrated chip provided in one embodiment of the present application;

[0023] Figure 2 A schematic plan view of an integrated chip provided in one embodiment of the present application;

[0024] Figure 3 An embodiment of the present application provides Figure 2 A simplified diagram of the three-dimensional structure of the corresponding integrated chip;

[0025] Figure 4 A schematic plan view of an integrated chip provided in another embodiment of the present application;

[0026] Figure 5 A schematic plan view of an integrated chip provided in yet another embodiment of the present application;

[0027] Figure 6 A schematic diagram of the structure of a bidirectional circuit from an interface module to a first dynamic storage array unit provided in an embodiment of the present application;

[0028] Figure 7 A schematic diagram of the physical structure of an integrated chip provided in one embodiment of the present application;

[0029] Figure 8 A schematic diagram of the structure of a bidirectional interface circuit in two adjacent units in an integrated chip provided in an embodiment of the present application;

[0030] Fig. 9A flow chart of a method for preparing an integrated chip provided in one embodiment of the present application;

[0031] Fig.10 A schematic diagram of the product structure of a programmable gate array unit, a first dynamic storage array unit or a second dynamic storage array unit provided in an embodiment of the present application;

[0032] Fig.11 for Fig. 9 Sub-flow chart of step S13;

[0033] Fig.12 A schematic diagram of a structure for forming a dielectric layer and a through hole on a programmable gate array unit, a first dynamic storage array unit or a second dynamic storage array unit provided in an embodiment of the present application;

[0034] Fig.13 A schematic diagram of the product structure after processing in step S14 provided in an embodiment of the present application;

[0035] Fig.14 A flow chart of a method for preparing an integrated chip provided in another embodiment of the present application;

[0036] Fig.15 for Fig.14 Sub-flow chart of step S17;

[0037] Fig.16 A schematic diagram of a structure in which a first dynamic memory array unit is thinned and a second conductive through hole is formed according to an embodiment of the present application;

[0038] Fig.17 A schematic diagram of the product structure after processing in step S17 provided in one embodiment of the present application;

[0039] Fig.18 A flow chart of a method for preparing an integrated chip provided in yet another embodiment of the present application;

[0040] Fig.19 A schematic diagram of the product structure after processing in step S19 provided in one embodiment of the present application.

[0041] Description of Reference Numerals

[0042] Integrated chip 10; programmable gate array unit 11; test module 11a; multi-way selection module 11b; control module 11c; first physical interface module 11d; test interface module 11e; random access memory 11f; display lookup table 11g; first substrate 111; first active layer 112; first metal layer 113; first dielectric layer 114; first through hole 115; first conductive through hole 116; conductive bump 117; first protection layer 118; first dynamic memory array unit 12; second substrate 121; second active layer 122; second metal layer 123; second dielectric layer 124; second through hole 125; fourth dielectric layer 126; fourth through hole 127; second conductive through hole 128; second protection layer 129; An input circuit 131; a first output circuit 132; a protection module 133; an interface module 134; a third input buffer 1321; a third level conversion module 1322; a fourth level conversion module 1331; a third driver module 1332; a bidirectional interface circuit 14; a first interface circuit 141; a third level conversion module 1411; a fourth level conversion module 1412; a second driver module 1413; a second buffer 1414; a third driver module 1415; a second input buffer 1416; a second interface circuit 142; a second dynamic storage array unit 15; a third substrate 151; a third active layer 152; a third metal layer 153; a third dielectric layer 154; a third through hole 155; and a third protection layer 156. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0045] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0046] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0047] See also Figure 1 , Figure 1 A three-dimensional structural diagram of an integrated chip provided in an embodiment of the present application; in this embodiment, an integrated chip 10 is provided. The integrated chip 10 includes a programmable gate array unit 11 and a first dynamic storage array unit 12. The programmable gate array unit 11 and the first dynamic storage array unit 12 can be semiconductor material wafers.

[0048] Among them, the programmable gate array unit 11 integrates a first bonding area and several programmable gate arrays connected to the first bonding area; the first dynamic storage array unit 12 integrates a second bonding area and several first dynamic storage arrays connected to the second bonding area; at least part of the programmable gate array unit 11 and the first dynamic storage array unit 12 are stacked and bonded together through the first bonding area and the second bonding area in a three-dimensional heterogeneous heterogeneous integration manner, so that the programmable gate array is connected to the first dynamic storage array unit 12 through the first bonding area and the second bonding area, and a three-dimensional heterogeneous integration structure is realized, thereby integrating the programmable gate array unit 11 and the first dynamic storage array unit 12 into a single chip, so that the integrated chip 10 not only has the ability of logical programmability, but also effectively increases the number of interconnections compared to the 2.5D packaging technology; at the same time, without the existence of a silicon interposer, the power consumption of reading and writing data is effectively reduced, thereby providing the logic part with high bandwidth, high energy efficiency ratio, and low latency large-capacity storage access.

[0049] Among them, see Figure 2 and Figure 3 ,in, Figure 2 A schematic plan view of an integrated chip provided in one embodiment of the present application; Figure 3 An embodiment of the present application provides Figure 2 The corresponding three-dimensional structure diagram of the integrated chip; the programmable gate array unit 11 or the first dynamic storage array unit 12 is integrated with a test module (Design For Test, DFT) 11a, the test module 11a is connected to the programmable gate array or the first dynamic storage array, and is used to test and repair the first dynamic storage array unit 12.

[0050] In one specific embodiment, see Figure 2 and Figure 3 , the test module 11a is integrated in the programmable gate array unit 11; the test module 11a is connected to the first bonding area, and then connected to the first dynamic storage array, for testing and repairing the first dynamic storage array. In this embodiment, the programmable gate array unit 11 also includes a multiplexer module 11b (multiplexer, MUX) connected to the first bonding area, a control module 11c (Memory Controller, MC), a first physical interface module 11d and a test interface module 11e.

[0051] Among them, the first physical interface module 11d is connected to the first bonding area, the test module 11a is connected to the first physical interface module 11d, the test interface module 11e is connected to the test module 11a, and the test interface module 11e is used to connect to the test bus. In a specific embodiment, the test bus is connected to the test interface module 11e, the test interface module 11e is connected to the test module 11a, the test interface module 11e is used to convert the signal received by the test bus into an internal test command, the test module 11a is further connected to the first physical interface module 11d, and the test module 11a is used to generate an internal test stimulus to test and repair the first dynamic storage array. The test module 11a and the control module 11c are connected to the multi-way selection module 11b, and the multi-way selection module 11b is connected to the first physical interface module 11d to selectively connect the test module 11a or the control module 11c to the first physical interface module 11d, and then connect to the first dynamic storage array unit 12. In a specific embodiment, the first dynamic storage array unit 12 is also integrated with a physical interface, and the first physical interface module 11d is connected to the physical interface on the first dynamic storage array unit 12 through the first bonding area and the second bonding area to realize the connection between the programmable gate array unit 11 and the first dynamic storage array unit 12.

[0052] In this embodiment, the programmable gate array unit 11 may also include a configuration bus, a random access memory 11f (Random Access Memory, RAM), and a display look-up table 11g (Look-Up-Table, LUT); wherein the configuration bus is connected to the display look-up table 11g (Look-Up-Table, LUT), and is connected to the control module 11c through the LUT; the RAM is connected to the configuration bus; in the specific implementation process, the multi-way selection module 11b selects the test module 11a, and tests the first dynamic storage array unit 12; then the first dynamic storage array unit 12 is repaired according to the test result; thereafter, EFUSE is burned to record whether the first dynamic storage array unit 12 is repaired to a good state; after the first dynamic storage array unit 12 is repaired to a good state, the multi-way selection module 11b switches to the control module 11c path, and the configuration bus starts the programmable gate array unit 11 to work, and the programmable gate array unit 11 can normally access the first dynamic storage array unit 12 through the control module 11c.

[0053] In another specific embodiment, see Figure 4 , Figure 4 A plan view schematic diagram of an integrated chip provided for another embodiment of the present application; a test module 11a is integrated in the first dynamic storage array unit 12; wherein the test module 11a is connected to the second bonding area and further connected to the first dynamic storage array for testing and repairing the first dynamic storage array.

[0054] In this embodiment, as one of the implementation methods, the programmable gate array unit 11 further includes: a first physical interface module 11d, a test interface module 11e and a test bus. That is, in this embodiment, the test interface module 11e is still integrated in the programmable gate array unit 11; in this implementation method; the first physical interface module 11d is connected to the first bonding area, the test module 11a is connected to the second bonding area, the test interface module 11e is connected to the first physical interface module 11d, and is used to connect to the test bus, and the test module 11a tests and repairs the first dynamic storage array according to the test signal received by the test bus.

[0055] As another embodiment, see Figure 5 , Figure 5 A schematic plan view of an integrated chip provided for another embodiment of the present application; the first dynamic storage array unit 12 includes: a test interface module 11e; the test module 11a is connected to the second bonding area and the test interface module 11e, the test interface module 11e is used to connect to the test bus, and the test module 11a tests and repairs the first dynamic storage array according to the test signal received by the test bus. That is, in this embodiment, the test module 11a and the test interface module 11e are both integrated into the first dynamic storage array unit 12 to complete the test and repair of the first dynamic storage array unit 12 during the preparation process of the first dynamic storage array unit 12; in this embodiment, the test interface module 11e and the test module 11a do not need to be led out to the outside of the chip through the programmable gate array unit 11.

[0056] It is understandable that in Figure 4 and Figure 5 In the corresponding embodiment, the programmable gate array may not include the multi-way selection module 11b to reduce the production cost.

[0057] For details, see Figure 6 and Figure 7 , Figure 6 A schematic diagram of the structure of an input / output circuit on a first dynamic storage array unit provided in an embodiment of the present application; Figure 7A schematic diagram of the physical structure of an integrated chip provided for an embodiment of the present application. The above-mentioned programmable gate array unit 11 may include a first substrate 111, a first active layer 112, a first metal layer 113 and a first dielectric layer 114 which are stacked in sequence; wherein the first active layer 112 is stacked on a side surface of the first substrate 111; the first metal layer 113 is stacked on a side surface of the first active layer 112 away from the first substrate 111; the first dielectric layer 114 is disposed on a side surface of the first metal layer 113 away from the first active layer 112; and in a specific embodiment, a first through hole 115 penetrating through the first surface and the second surface of the first dielectric layer 114 is provided to lead the first metal layer 113 out of the side surface of the first dielectric layer 114 away from the first metal layer 113 through the first through hole 115; in a specific embodiment, the number of layers of the first metal layer 113 may be multiple layers, and the multiple first metal layers 113 may be stacked and connected through dielectric layers. In a specific embodiment, the programmable gate array is specifically integrated into the first active layer 112 of the programmable gate array unit 11 .

[0058] The first dynamic storage array unit 12 may include a second substrate 121, a second active layer 122, a second metal layer 123, and a second dielectric layer 124 which are stacked in sequence; wherein the second active layer 122 is stacked on a side surface of the second substrate 121; the second metal layer 123 is stacked on a side surface of the second active layer 122 away from the second substrate 121; the second dielectric layer 124 is disposed on a side surface of the second metal layer 123 away from the second active layer 122; and in a specific embodiment, a second dielectric layer 124 is provided with a second surface extending through the second surface and the second surface thereof. The second through hole 125 is formed to lead the second metal layer 123 out of the second dielectric layer 124 away from the second metal layer 123 through the second through hole 125; wherein the second metal layer 123 may have multiple layers, and the multiple layers of second metal layers 123 may be stacked and connected through dielectric layers; in a specific embodiment, the first dielectric layer 114 of the programmable gate array unit 11 and the second dielectric layer 124 of the first dynamic storage array unit 12 are stacked and connected, and the first through hole 115 and the second through hole 125 are aligned to achieve the connection between the first metal layer 113 and the second metal layer 123. In a specific embodiment, the first dynamic storage array is specifically integrated in the second active layer 122 of the programmable gate array unit 11.

[0059] The first substrate 111 and the second substrate 121 are made of the same material, which can be a semiconductor substrate, such as a silicon substrate, a germanium substrate, etc. The first dielectric layer 114 and the first dielectric layer 114 can also be made of the same material, which can be silicon oxide. The first metal layer 113 and the second metal layer 123 can be back-end-of-line (BEOL) metallization layers. For example, the first metal layer 113 and the second metal layer 123 can be made of at least one of aluminum-copper alloy, aluminum, germanium, and copper, preferably copper. A conductive layer is provided in the first through hole 115 to connect the first metal layer 113 and the second metal layer 123; the conductive layer can be copper.

[0060] In one embodiment, see Figure 6 and Figure 7 ; The programmable gate array unit 11 also includes a protection module (electrostatic discharge, ESD) 133 and an interface module 134.

[0061] Among them, the protection module 133 is connected to the first bonding area and the interface module 134. In a specific embodiment, the protection module 134 can be specifically set on the programmable gate array unit 11, and is specifically located on the first active layer 112 on the programmable gate array unit 11. Compared with the solution of setting the protection module 133 on the first dynamic storage array unit 12, the protection module 133 is closer to the interface module 134, and the programmable gate array unit 11 can be effectively protected to prevent external signals from damaging the programmable gate array unit 11. The interface module 134 is used to receive external signals and / or output signals of the first dynamic storage array.

[0062] In this embodiment, the first dynamic storage array unit 12 further includes a first level conversion module 1331, a first driving module 1332, a first buffer 1321 and a second level conversion module 1322 arranged on the second active layer 122. The input end of the first driving module 1332 is connected to the first level conversion module 1331, the output end of the first driving module 1332 is connected to the second bonding area, the first driving module 1332 and the first level conversion module 1331 form a first output circuit 132 of the first dynamic storage array unit 12 to output the signal of the first dynamic storage array to the interface module 134 of the programmable gate array unit 11. The input end of the first buffer 1321 is connected to the second bonding area, the output end of the first buffer 1321 is connected to the second level conversion module 1322, the first buffer 1321 and the second level conversion module 1322 form a first input circuit 131 of the first dynamic storage array unit 12 to send the signal input from the interface module 134 of the programmable gate array unit 11 to the first dynamic storage array unit 12. In a specific embodiment, the programmable gate array and the first dynamic storage array are connected to the interface module 134 through their respective physical interfaces.

[0063] It is understood that in the specific embodiments, see Figure 7 The programmable gate array unit 11 is also provided with an input / output circuit to send the signal received from the interface module 134 to the programmable gate array unit 11, and output the signal of the programmable gate array unit 11 from the interface module 134; the input / output circuit on the programmable gate array unit 11 has the same or similar structure and function as the input / output circuit on the programmable gate array unit 11 in the prior art, and can achieve the same or similar technical effects. For details, please refer to the prior art and will not be repeated here.

[0064] See also Figure 7 and Figure 8 ,in, Figure 8 A schematic diagram of the circuit structure of two adjacent units in an integrated chip provided in an embodiment of the present application; in this embodiment, the integrated chip 10 also includes a bidirectional interface circuit 14; the bidirectional interface circuit 14 is arranged in the programmable gate array unit 11 and the first dynamic storage array unit 12, and is used for the programmable gate array unit 11 to send signals to the first dynamic storage array unit 12, and for the first dynamic storage array unit 12 to send signals to the programmable gate array unit 11.

[0065] For details, see Figure 8The bidirectional interface circuit 14 includes a first interface circuit 141 and a second interface circuit 142; the first interface circuit 141 is used for the programmable gate array unit 11 to send a signal to the first dynamic storage array unit 12; the second interface circuit 142 is used for the first dynamic storage array unit 12 to send a signal to the programmable gate array unit 11.

[0066] In this embodiment, the programmable gate array unit 11 further includes a third level conversion module 1411, a fourth level conversion module 1412, a second driving module 1413 and a second buffer 1414 arranged in the first active layer 112. Among them, the input end of the second driving module 1413 is connected to the third level conversion module 1411, and the output end of the second driving module 1413 is connected to the first bonding area. The input end of the second buffer 1414 is connected to the first bonding area, and the output end of the second buffer 1414 is connected to the fourth level conversion module 1412. The first dynamic storage array unit 12 further includes a third driving module 1415 and a third buffer 1416 arranged in the second active layer 122. The output end of the third driving module 1415 is connected to the second bonding area, and the input end of the third buffer 1416 is connected to the second bonding area.

[0067] In a specific embodiment, the third level conversion module 1411 and the second driving module 1413 are connected to the third buffer 1416 through the first bonding area and the second bonding area to form the first interface circuit 141. In a specific embodiment, the second driving module 1413 is specifically connected to the third buffer 1416 through the first through hole 115 and the second through hole 125. The third driving module 1415 is connected to the second buffer 1414 through the first bonding area and the second bonding area, and then connected to the fourth level conversion module 1412 to form the second interface circuit 142. In a specific embodiment, the third driving module 1415 is specifically connected to the second buffer 1414 through the first through hole 115 and the second through hole 125.

[0068] By respectively configuring the first interface circuit 141 and the second interface circuit 142 to include only one level conversion module, compared with a solution in which the first interface circuit 141 and the second interface circuit 142 include two level conversion modules respectively, not only the volume can be reduced, but also the core voltage can be used for signal transmission, which can effectively reduce energy consumption compared with using an external interface voltage for signal transmission.

[0069] In specific embodiments, see Figure 1 , Figure 2 or Figure 7, the number of layers of the first dynamic storage array unit 12 is at least two, at least two layers of the first dynamic storage array unit 12 are stacked and bonded on one side surface of the programmable gate array unit 11, and two adjacent first dynamic storage array units 12 are stacked and bonded through their respective second bonding areas. Among them, in the at least two layers of the first dynamic storage array unit 12, except for one layer of the first dynamic storage array unit 12 directly bonded to the programmable gate array unit 11, the protection module 133 of the input / output circuit on the other first dynamic storage array units 12 and the interface module 134 connected thereto are also arranged on the programmable gate array unit 11; the first input circuit 131 and the first output circuit 132 on the other first dynamic storage array units 12 are connected to the protection module 133 arranged on the programmable gate array unit 11 through one layer of the first dynamic storage array unit 12 directly bonded to the programmable gate array unit 11.

[0070] Furthermore, the other first dynamic storage array units 12 and the programmable gate array units 11 also form an interface circuit to input and output signals with the programmable gate array units 11; the specific structure and function of the input / output circuit and the interface circuit involved in this embodiment can be found in the above-mentioned related text description, and the same or similar technical effects can be achieved, which will not be repeated here.

[0071] The following takes the example that the number of layers of the first dynamic storage array unit 12 is two, and the other first dynamic storage array unit 12 except the first dynamic storage array unit 12 directly bonded to the programmable gate array unit 11 is referred to as the second dynamic storage array unit 15.

[0072] Among them, the second dynamic storage array unit 15 is stacked on a side surface of the first dynamic storage array unit 12 away from the programmable gate array unit 11; the specific structure and function of the second dynamic storage array unit 15 can refer to the structure and function of the first dynamic storage array unit 12, and can achieve the same or similar technical effects, which will not be repeated here.

[0073] The second dynamic storage array unit 15 includes a second input circuit (not shown) and a second output circuit (not shown). The second input circuit is provided in the second dynamic storage array unit 15 and connected to the interface module 134, and is used to send the signal input from the interface module 134 to the second dynamic storage array unit 15; specifically, the second input circuit can be connected to the interface module 134 through the first dynamic storage array unit 12; and the structure of the second input circuit can be the same as that of the first input circuit 131, and the details can be referred to the above related text description.

[0074] The second output circuit is disposed in the second dynamic storage array unit 15 and connected to the interface module 134, and is used to output the signal of the second dynamic storage array unit 15 from the interface module 134. Specifically, the second output circuit can be connected to the interface module 134 through the first dynamic storage array unit 12; and the structure of the second output circuit can be the same as that of the first output circuit 132, and the details can refer to the above related text description.

[0075] Furthermore, in this embodiment, the second dynamic storage array unit 15 may also include a third interface circuit and a fourth interface circuit (not shown); wherein the third interface circuit is arranged in the second dynamic storage array unit 15 and is connected to the bidirectional interface circuit 14 of the integrated chip 10, and is used for the programmable gate array unit 11 or the first dynamic storage array unit 12 to send a signal to the second dynamic storage array unit 15; the fourth interface circuit is arranged in the second dynamic storage array unit 15 and is connected to the bidirectional interface circuit 14 of the integrated chip 10, and is used for the second dynamic storage array unit 15 to send a signal to the programmable gate array unit 11 or the first dynamic storage array unit 12.

[0076] The integrated chip 10 provided in this embodiment, by setting a programmable gate array unit 11, the programmable gate array unit 11 includes a first bonding area and a programmable gate array connected to the first bonding area; at the same time, by setting a first dynamic storage array unit 12, the first dynamic storage array unit 12 includes a second bonding area and a first dynamic storage array connected to the second bonding area, and the programmable gate array unit 11 and the first dynamic storage array unit 12 are stacked and bonded through the first bonding area and the second bonding area, so that the programmable gate array of the programmable gate array unit 11 can access the first dynamic storage array unit 12 through the first bonding area and the second bonding area; at the same time, a three-dimensional heterogeneous integrated structure is realized, so that the programmable gate array unit 11 and the first dynamic storage array unit 12 are integrated into a single chip, so that the integrated chip 10 not only has the ability of logical programmability, but also effectively increases the number of interconnections; at the same time, it can provide high-bandwidth, high-energy-efficiency ratio, low-latency large-capacity storage access for the logic part. In addition, by integrating the test module 11a on the programmable gate array unit 11 or the first dynamic storage array unit 12, the test module 11a is connected to the programmable gate array or the first dynamic storage array, so as to test and repair the first dynamic storage array through the test module 11a.

[0077] In a specific embodiment, the integrated chip 10 can be manufactured by the following integrated chip manufacturing method.

[0078] See also Fig. 9 , Fig. 9A flowchart of a method for preparing an integrated chip provided in an embodiment of the present application; in this embodiment, a method for preparing an integrated chip is provided, the method comprising:

[0079] Step S11: preparing a programmable gate array unit and a first dynamic memory array unit.

[0080] A test unit 11 a is prepared on the programmable gate array unit 11 or the first dynamic storage array unit 12 ; the first surface of the programmable gate array unit 11 includes a first protection layer 118 , and the first surface of the first dynamic storage array unit 12 includes a second protection layer 129 .

[0081] Specifically, the specific structures of the programmable gate array unit 11 and the first dynamic storage array unit 12 are shown in Figure 7 and Fig.10 , Fig.10 A schematic diagram of the product structure of a programmable gate array unit, a first dynamic storage array unit or a second dynamic storage array unit provided in an embodiment of the present application; the programmable gate array unit 11 comprises a first substrate 111, a first active layer 112 and a first metal layer 113 stacked in sequence. The first protective layer 118 is disposed on a surface of the first metal layer 113 facing away from the first active layer 112. In a specific embodiment, the first active layer 112 may be provided with electronic components such as a protection module 133, a third level conversion module 1411, a second driving module 1413, a second buffer 1414 and a fourth level conversion module 1412, and these electronic components are electrically connected to the first metal layer 113.

[0082] The first dynamic storage array unit 12 includes a second substrate 121, a second active layer 122, and a second metal layer 123 stacked in sequence. The second protection layer 129 is disposed on a surface of the second metal layer 123 that is away from the second active layer 122. The second active layer 122 is provided with electronic components such as a second input buffer 1416 and a third driving module 1415.

[0083] Among them, the first protective layer 118 and the second protective layer 129 can be plastic films or inert materials such as silicon oxide arranged on the metal layer by electroplating or lamination; other specific structural descriptions of the programmable gate array unit 11 and the first dynamic storage array unit 12 can be found above.

[0084] Step S12: removing the first protective layer and the second protective layer.

[0085] Specifically, when the first protective layer 118 and the second protective layer 129 are plastic films, the protective layers can be directly torn off, and this application takes this as an example; when the first protective layer 118 and the second protective layer 129 are inert materials electroplated or laminated on a metal layer, the first protective layer 118 and the second protective layer 129 can be removed by mechanical polishing, grinding or etching.

[0086] Step S13: preparing a first bonding area on the first surface of the programmable gate array unit, and preparing a second bonding area on the first surface of the first dynamic memory array unit.

[0087] For details, see Fig.11 , Fig.11 for Fig. 9 Sub-flow chart of step S13 in FIG. Step S13 specifically includes:

[0088] Step S131: preparing a first dielectric layer on a first surface of a programmable gate array unit, and preparing a second dielectric layer on a first surface of a first dynamic memory array unit.

[0089] Specifically, the first dielectric layer 114 can be formed on the surface of the first metal layer 113 facing away from the first active layer 112, and the second dielectric layer 124 can be formed on the surface of the second metal layer 123 facing away from the second active layer 122 by lamination. The first dielectric layer 114 and / or the second dielectric layer 124 can be a prepreg.

[0090] Step S132: preparing a first through hole on the first dielectric layer, and preparing a second through hole on the second dielectric layer.

[0091] Specifically, a first through hole 115 may be formed in the first dielectric layer 114 by laser drilling or mechanical drilling, and the first through hole 115 extends to the first metal layer 113; then, a metal layer is electroplated in the first through hole 115 or a copper plating treatment is performed on the first through hole 115 to form a conductive through hole, and the conductive through hole is connected to the first metal layer 113. Similarly, a second through hole 125 may be formed in the second dielectric layer 124 by laser drilling or mechanical drilling, and the second through hole 125 extends to the second metal layer 123; then, a metal layer is electroplated in the second through hole 125 or a copper plating treatment is performed on the second through hole 125 to form a conductive through hole, and the conductive through hole is connected to the second metal layer 123. The metal layer may be a copper layer. Specifically, the structure of the programmable gate array unit 11 or the first dynamic storage array unit 12 after the processing of step S132 can be specifically referred to. Fig.12 ; Fig.12 A schematic diagram of a structure for forming a dielectric layer and a through hole on a programmable gate array unit, a first dynamic memory array unit or a second dynamic memory array unit provided in an embodiment of the present application.

[0092] Step S14: Bonding the first bonding region to the second bonding region, thereby bonding and connecting the programmable gate array unit to the first dynamic memory array unit.

[0093] The product structure after step S14 is shown in detail. Fig.13 , Fig.13 A schematic diagram of the product structure after step S14 is provided for an embodiment of the present application. Specifically, the first dielectric layer 114 and the second dielectric layer 124 are stacked and connected to realize the three-dimensional heterogeneous integration of the programmable gate array unit 11 and the first dynamic storage array unit 12. When the first bonding area is bonded to the second bonding area, the first through hole 115 is aligned with the second through hole 125 to realize the interconnection between the programmable gate array unit 11 and the first dynamic storage array unit 12. Among them, by stacking and bonding at least part of the programmable gate array unit 11 and the first dynamic storage array unit 12, so that the programmable gate array in the programmable gate array unit 11 is connected to the first dynamic storage array unit 12, and a three-dimensional heterogeneous integrated structure is realized, the programmable gate array unit 11 and the first dynamic storage array unit 12 are integrated into a single chip, so that the integrated chip 10 not only has the ability of logical programmability, but also effectively increases the number of interconnections; in addition, by setting the protection module 134 on the programmable gate array unit 11, compared with the solution of setting the protection module 133 on the first dynamic storage array unit 12, the protection module 133 is closer to the interface module 134, and the programmable gate array unit 11 can be effectively protected.

[0094] In one embodiment, see Fig.14 , Fig.14 A flowchart of a method for preparing an integrated chip provided in another embodiment of the present application; another method for preparing an integrated chip is provided, which is different from the method for preparing an integrated chip provided in the first embodiment in that the method further includes:

[0095] Step S15: preparing a second dynamic memory array unit.

[0096] The first surface of the second dynamic memory array unit 15 includes a third protection layer 156. Fig.10 The second dynamic storage array unit 15 includes a third substrate 151, a third active layer 152 and a third metal layer 153 stacked in sequence. The third protection layer 156 is specifically disposed on a surface of the third metal layer 153 that is away from the third active layer 152. In a specific embodiment, the specific structure and function of the second dynamic storage array unit 15 may be the same as or similar to the specific structure and function of the first dynamic storage array unit 12. For details, please refer to the above-mentioned text description of the first dynamic storage array unit 12, which will not be repeated here.

[0097] Step S16: removing the third protective layer.

[0098] The specific implementation process of step S16 can be the same or similar to the specific implementation process of removing the first protective layer 118 or the second protective layer 129 in step S12, and can achieve the same or similar technical effects, which will not be repeated here. In this embodiment, step S15 and step S16 can also be performed before step S13, and the order of step S11 and step S12 is not limited.

[0099] Step S17: preparing a third bonding region on the first surface of the second dynamic memory array unit, and preparing a fourth bonding region on the second surface of the first dynamic memory array unit.

[0100] For details, see Fig.15 , Fig.15 for Fig.14 Step S16 specifically includes:

[0101] Step S171: preparing a third dielectric layer on the first surface of the second dynamic memory array unit, and preparing a fourth dielectric layer on the second surface of the first dynamic memory array unit.

[0102] Among them, the specific implementation process of step S171 can refer to the specific implementation process of the above-mentioned step S131, and can achieve the same or similar technical effects, which will not be repeated here.

[0103] In the specific implementation process, before the step of forming the fourth dielectric layer 126 on the surface of the second substrate 121 away from the second active layer 122, the second substrate 121 is thinned. The specific structure of the first dynamic storage array unit 12 after this step can be seen in Fig.16 , Fig.16 A schematic diagram of the structure of thinning the first dynamic storage array unit and forming a second conductive through hole in one embodiment of the present application; then forming a second conductive through hole 128 on the second substrate 121 and the second active layer 122, the second conductive through hole 128 is connected to the second metal layer 123, and the second metal layer 123 is led out of the second substrate 121; in a specific embodiment, the fourth through hole 127 is electrically connected to the second metal layer 123 through the second conductive through hole 128.

[0104] Specifically, the second substrate 121 may be thinned by one or a combination of wet etching, grinding, chemical mechanical grinding, etc. The thickness of the second substrate 121 after thinning may be 0.5-300 microns, such as 0.5 microns, 10 microns, 50 microns, 200 microns, etc. Of course, the thickness of the second substrate 121 after thinning may also be less than 0.5 microns or greater than 300 microns, which may be selected according to the performance requirements of the integrated chip 10 to be produced and the product type.

[0105] The second conductive via 128 is filled with metal, such as copper; and the second conductive via 128 passes through the second substrate 121 and the second active layer 122 to be electrically connected to the second metal layer 123, and leads the second metal layer 123 out of the side surface of the second substrate 121 away from the second active layer 122; specifically, the specific manufacturing method of the second conductive via 128 can be made by referring to the TSV process in the prior art, and the same or similar technical effects can be achieved, which will not be repeated here.

[0106] Step S172: preparing a third through hole on the third dielectric layer, and preparing a fourth through hole on the fourth dielectric layer.

[0107] Specifically, the product structure after processing in step S172 can be found in Fig.12 The specific implementation process of step S172 can refer to the specific implementation process of step S132, and can achieve the same or similar technical effects, which will not be repeated here. The third through hole 155 is electrically connected to the third metal layer 153, and the fourth through hole 127 is electrically connected to the second metal layer 123.

[0108] Step S18: bonding the third bonding region to the fourth bonding region, thereby bonding and connecting the first dynamic memory array unit to the second dynamic memory array unit.

[0109] The product structure after step S18 can be found in Fig.17 , Fig.17 A schematic diagram of the product structure after step S17 is provided for an embodiment of the present application; in a specific embodiment, when the third bonding area is bonded to the fourth bonding area, the third through hole 155 is aligned with the fourth through hole 127.

[0110] Specifically, the third dielectric layer 154 and the fourth dielectric layer 126 are stacked and connected to achieve three-dimensional heterogeneous integration of the first dynamic storage array unit 12 and the second dynamic storage array unit 15. Specifically, after the first dynamic storage array unit 12 and the second dynamic storage array unit 15 are bonded, the third through hole 155 is correspondingly connected to the fourth through hole 127 to achieve connection of electronic components on the first dynamic storage array unit 12 and the second dynamic storage array unit 15.

[0111] For details, see Fig.18 , Fig.18 A flow chart of a method for preparing an integrated chip provided in another embodiment of the present application; the method for preparing the integrated chip further includes:

[0112] Step S19: forming a conductive bump on the first substrate that is connected to the first metal layer, so as to lead the first metal layer out of a surface of the first substrate that is away from the first active layer.

[0113] Specifically, the product structure after processing in step S19 can be found in Fig.19 , Fig.19 A schematic diagram of the product structure after step S19 is provided for an embodiment of the present application. In the specific implementation process, step S19 may specifically include: thinning the first substrate 111; then forming a first conductive via 116 that penetrates the first substrate 111 and the first active layer 112, the first conductive via 116 is connected to the first metal layer 113, so as to lead the first metal layer 113 out of the first substrate 111; then forming a conductive bump 117 on the surface of the first substrate 111 away from the first active layer 112, the conductive bump 117 is connected to the first conductive via 116, and then the first metal layer 113 is led out to the surface of the first substrate 111 through the conductive bump 117. Specifically, the specific process of thinning and opening the first conductive via 116 can refer to the relevant description in the above step S161, and the same or similar technical effects can be achieved, which will not be repeated here.

[0114] Of course, it can be understood that when the integrated chip 10 only includes the programmable gate array unit 11 and the first dynamic storage array unit 12, step S19 can be performed after step S13; when the integrated chip 10 includes multiple second dynamic storage array units 15, the multiple second dynamic storage array units 15 can be bonded in sequence on the side surface of the second dynamic storage array unit 15 away from the first dynamic storage array unit 12 in the manner of bonding the second dynamic storage array unit 15 to the first dynamic storage array unit 12, and step S19 can be performed after the bonding of the multiple second dynamic storage array units 15 is completed.

[0115] The preparation method of the integrated chip provided in this embodiment is as follows: a programmable gate array unit 11 and a first dynamic storage array unit 12 are prepared respectively; then the first protective layer 118 of the programmable gate array unit 11 and the second protective layer 129 of the first dynamic storage array unit 12 are removed; thereafter, the programmable gate array unit 11 and the first dynamic storage array unit 12 are bonded, so that the programmable gate array of the programmable gate array unit 11 can access the first dynamic storage array unit 12 through the first bonding area and the second bonding area; at the same time, a three-dimensional heterogeneous integrated structure is realized, so that the programmable gate array unit 11 and the first dynamic storage array unit 12 are integrated into a single chip, so that the prepared integrated chip 10 not only has the ability of logical programmability, but also effectively increases the number of interconnections; at the same time, it can provide high bandwidth, high energy efficiency ratio, low latency and large-capacity storage access for the logic part. In addition, by integrating a test module 11a on the programmable gate array unit 11 or the first dynamic storage array unit 12, the test module 11a is connected to the programmable gate array or the first dynamic storage array, so that the first dynamic storage array can be tested and repaired through the test module 11a.

[0116] It should be noted that the units involved in the present application may be crystal grains or wafers. In a specific embodiment, the programmable gate array unit may include multiple programmable gate arrays, each of which may include multiple programmable sub-units; the dynamic storage array unit may include multiple dynamic storage arrays, each of which may include multiple dynamic storage sub-units.

[0117] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0118] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0119] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An integrated chip, characterized in that: The integrated chip comprises: A programmable gate array unit, integrating a first bonding area and a programmable gate array connected to the first bonding area; A first dynamic storage array unit is integrated with a second bonding area and a first dynamic storage array connected to the second bonding area; the programmable gate array unit and the first dynamic storage array unit are stacked and bonded through the first bonding area and the second bonding area, and the programmable gate array is connected to the first dynamic storage array unit through the first bonding area and the second bonding area; the first dynamic storage array unit includes at least two layers, at least two layers of the first dynamic storage array units are stacked and bonded on one side of the programmable gate array unit, and two adjacent first dynamic storage array units are stacked and bonded through their respective second bonding areas; A test module, integrated in the programmable gate array unit or the first dynamic storage array unit, the test module is connected to the programmable gate array or the first dynamic storage array, and is used to test and repair the first dynamic storage array; The programmable gate array unit comprises: a protection module, an interface module, a second driving module, a second buffer, a third level conversion module and a fourth level conversion module; the protection module is connected to the first bonding area and the interface module, the interface module is used to receive external signals and / or output signals of the first dynamic storage array, and the protection module is used to protect the programmable gate array unit to prevent the external signal from damaging the programmable gate array unit; the input end of the second driving module is connected to the third level conversion module, and the output end of the second driving module is connected to the first bonding area; the input end of the second buffer is connected to the first bonding area, and the output end of the second buffer is connected to the fourth level conversion module; The integrated chip also includes a bidirectional interface circuit, which is arranged in the programmable gate array unit and the first dynamic storage array unit, and the bidirectional interface circuit includes a first interface circuit and a second interface circuit; the first interface circuit is used for the programmable gate array unit to send a signal to the first dynamic storage array unit; the second interface circuit is used for the first dynamic storage array unit to send a signal to the programmable gate array unit; wherein the first interface circuit includes one of the third level conversion modules, and the second interface circuit includes one of the fourth level conversion modules.

2. The integrated chip according to claim 1, characterized in that: The test module is integrated in the programmable gate array unit; the test module is connected to the first bonding area and further connected to the first dynamic storage array, and is used to test and repair the first dynamic storage array.

3. The integrated chip according to claim 2, characterized in that: The programmable gate array unit includes: a first physical interface module and a test interface module; The first physical interface module is connected to the first bonding area, and the test module is connected to the first physical interface module. The test interface module is connected to the test module and is used to connect to a test bus. The test module tests and repairs the first dynamic storage array according to a test signal received by the test bus.

4. The integrated chip according to claim 3, characterized in that: The programmable gate array unit also includes: a multi-way selection module and a control module; The multi-way selection module is connected to the first physical interface module, and the control module and the test module are connected to the multi-way selection module.

5. The integrated chip according to claim 1, characterized in that: The test module is integrated in the first dynamic storage array unit; the test module is connected to the second bonding area and further connected to the first dynamic storage array, and is used to test and repair the first dynamic storage array.

6. The integrated chip according to claim 5, characterized in that: The programmable gate array unit includes: a first physical interface module and a test interface module; The first physical interface module is connected to the first bonding area, the test module is connected to the second bonding area, the test interface module is connected to the first physical interface module and is used to connect to a test bus, and the test module tests and repairs the first dynamic storage array according to a test signal received by the test bus.

7. The integrated chip according to claim 5, characterized in that: The first dynamic storage array unit includes: a test interface module; The test module is connected to the second bonding area and the test interface module, the test interface module is used to connect to a test bus, and the test module tests and repairs the first dynamic storage array according to a test signal received by the test bus.

8. The integrated chip according to claim 1, characterized in that: The first dynamic storage array unit includes: a first driving module, a first level conversion module, a second level conversion module and a first buffer; An input end of the first driving module is connected to the first level conversion module, and an output end of the first driving module is connected to the second bonding area; An input end of the first buffer is connected to the second bonding area, and an output end of the first buffer is connected to the second level conversion module.

9. The integrated chip according to claim 1, characterized in that: The first dynamic storage array unit includes: a third driving module and a third buffer; An output end of the third driving module is connected to the second bonding area, and an input end of the third buffer is connected to the second bonding area.

10. A method for preparing an integrated chip, characterized in that: include: A programmable gate array unit and a first dynamic storage array unit are prepared, wherein a test unit is prepared on the programmable gate array unit or the first dynamic storage array unit; wherein the first surface of the programmable gate array unit includes a first protective layer, and the first surface of the first dynamic storage array unit includes a second protective layer; removing the first protective layer and the second protective layer; Preparing a first bonding area on the first surface of the programmable gate array unit, and preparing a second bonding area on the first surface of the first dynamic memory array unit; The first bonding area is bonded to the second bonding area, and then the programmable gate array unit is bonded to the first dynamic storage array unit; wherein the programmable gate array unit includes: a protection module, an interface module, a second driving module, a second buffer, a third level conversion module and a fourth level conversion module; the protection module is connected to the first bonding area and the interface module, the interface module is used to receive an external signal and / or output a signal of the first dynamic storage array, and the protection module is used to protect the programmable gate array unit to prevent the external signal from damaging the programmable gate array unit; the input end of the second driving module is connected to the third level conversion module, and the output end of the second driving module is connected to the first bonding area; the input end of the second buffer is connected to the first bonding area, and the output end of the second buffer is connected to the fourth level conversion module; The invention also includes: preparing a second dynamic memory array unit; the first surface of the second dynamic memory array unit includes a third protective layer; removing the third protective layer; Preparing a third bonding region on the first surface of the second dynamic memory array unit, and preparing a fourth bonding region on the second surface of the first dynamic memory array unit; Bonding the third bonding region to the fourth bonding region, thereby bonding and connecting the first dynamic memory array unit to the second dynamic memory array unit; It also includes setting a bidirectional interface circuit on the programmable gate array unit and the first dynamic storage array unit, the bidirectional interface circuit includes a first interface circuit and a second interface circuit; the first interface circuit is used for the programmable gate array unit to send a signal to the first dynamic storage array unit; the second interface circuit is used for the first dynamic storage array unit to send a signal to the programmable gate array unit; wherein the first interface circuit includes a third level conversion module, and the second interface circuit includes a fourth level conversion module.

11. The preparation method according to claim 10, characterized in that: The step of preparing a first bonding area on the first surface of the programmable gate array unit and preparing a second bonding area on the first surface of the first dynamic storage array unit comprises: Preparing a first dielectric layer on a first surface of the programmable gate array unit, and preparing a second dielectric layer on a first surface of the first dynamic memory array unit; preparing a first through hole on the first dielectric layer, and preparing a second through hole on the second dielectric layer; When the first bonding area is bonded to the second bonding area, the first through hole is aligned with the second through hole.

12. The method for preparing an integrated chip according to claim 10, characterized in that: The step of preparing a third bonding area on the first surface of the second dynamic memory array unit and preparing a fourth bonding area on the second surface of the first dynamic memory array unit comprises: Preparing a third dielectric layer on the first surface of the second dynamic memory array unit, and preparing a fourth dielectric layer on the second surface of the first dynamic memory array unit; preparing a third through hole on the third dielectric layer, and preparing a fourth through hole on the fourth dielectric layer; When the third bonding region is bonded to the fourth bonding region, the third through hole is aligned with the fourth through hole.

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