Method for implementing pre-stack three-dimensional reverse time migration based on FPGA using checkpoint technology

Abstract

The present invention relates to the technical field of oil and gas seismic exploration, and particularly to a method for implementing pre-stack three-dimensional reverse time migration based on FPGA using checkpoint technology. According to different-scale 3D-RTM calculation tasks and the amount of FPGA chip resources selected, the present invention sets checkpoint point parameters through software design on the CPU platform, making the calculation time of wavefield data and the required data transmission time dynamic, thereby achieving the effect of eliminating the I / O bottleneck. The utilization rate of FPGA resources is improved, and the calculation time of the entire calculation task is greatly shortened, thereby improving the efficiency of the entire heterogeneous computing acceleration. The present invention sets an optimal FPGA-CPU data interaction scheme according to the characteristics of different-scale data volumes, making the utilization rate of the entire computing resources optimal. At the same time, the present invention realizes the dynamic adjustment parameters through the software architecture on the CPU platform side, greatly enhancing the scalability of the present invention, and making the present invention have higher compatibility for improving the utilization rate of the computing resources of any FPGA for different-scale 3D-RTM calculation tasks.

Description

Technical Field

[0001] The present invention relates to the technical field of oil and gas exploration, and particularly to a method for implementing pre-stack three-dimensional reverse time migration based on FPGA using

[0002] the checkpoint technology. Background Art

[0003] In the oil and gas exploration industry, the potential for conventional oil and gas exploration remains huge. Unconventional oil and gas will be the main force for increasing reserves and production. However, the exploration and development targets will be more complex, and it will be more difficult to increase reserves on a large scale and maintain continuous production. The oil and gas target objects are becoming increasingly complex. The remaining resources of conventional oil and gas are distributed in areas such as complex nappe structures, sub-salt and inter-salt structures, complex geological bodies, and complex lithologies. The proportion of unconventional oil and gas is gradually increasing. Harsh surface conditions, complex underground structures, and complex reservoir storage spaces pose higher and higher requirements for geophysical exploration technologies. The focus of oil and gas exploration and development is constantly shifting towards deep - ultra-deep layers, shale oil and gas, and more complex areas with strong complex surfaces. Improving the development effectiveness of difficult-to-produce reserves and the recovery rate of old oil and gas fields also faces technical challenges.

[0004] In order to meet the needs of oil and gas exploration and development in the new situation, the oil and gas exploration industry has increased its scientific research efforts on key geophysical exploration bottleneck technologies in key areas of oil and gas exploration and development, and overcome the bottleneck technical problems urgently needed to be solved in production. The oil and gas industry has developed high-efficiency, low-cost, and high-precision geophysical exploration technologies, and focused on the research of deep and ultra-deep geophysical exploration. The migration method has been improved from integral pre-stack depth migration to pre-stack migration based on the wave equation. Among them, the reverse time migration technology based on the two-way wave equation has high precision and accurate phase, is not restricted in terms of dip angle and migration aperture, and can handle longitudinal and transverse variable velocity problems. It is considered to be the migration imaging technology with the highest imaging accuracy at present and is more suitable for complex structure imaging. However, the large amount of calculation and large storage capacity make the calculation cost of reverse time migration very high and it cannot be used for seismic imaging of large data volumes. For such a large amount of data, high-efficiency and high-quality calculations are required. For medium and small block data storage problems, storage strategies such as wave field reconstruction can be effectively solved. For the storage of large-scale three-dimensional data, issues such as the interaction between storage space CPU data and FPGA affecting calculation efficiency, I / O read and write speed (PCIe interface rate limit), and network bandwidth need to be considered. Wang Baoli et al. (2012) proposed an effective boundary storage strategy, drawing on the ideas of checkpoint and caching, which reduced the wave field storage and did not introduce calculation errors, but this method would increase additional calculation amounts.

[0005] The progress of geophysical technology necessarily implies a substantial increase in the amount of data, which is determined by its data foundation and premise. Moreover, its algorithmic foundation determines that it will definitely bring about a significant increase in the computational workload of data processing. Therefore, corresponding computing power support is required to ensure the success of the dimensionality-up revolution. Beyond the technical route of traditional CPUs evolving from single-core to multi-core (many-core), there are currently several active new technical routes, which may represent important directions for the future development of high-performance computing technology. An important direction is the reconfigurable computing technology based on FPGA (Field Programmable Gate Array). Whether internationally or domestically, petascale computer systems representing the current highest computing level all adopt this heterogeneous parallel computing system architecture. How to construct a multi-level parallel computing software development framework and programming tools on heterogeneous parallel computing systems to promote the development and transplantation of large-scale parallel computing application software is the key to achieving the large-scale popularization and application of heterogeneous parallel computing systems.

[0006] The development of heterogeneous cooperative parallel computing technology (FPGA) parallel computing technology can improve the overall level of geophysical data processing and create more economic benefits for society. At the same time, various technological advancements can also promote the reduction of computer hardware and software costs and introduce more computers for high-performance computing. In recent research, it was found that when implementing 3D-RTM on a heterogeneous platform through FPGA, for different FPGA model chips with different memory resources, when calculating data volumes of different scales, the data interaction time cannot be fully submerged in the calculation process, resulting in the FPGA resource utilization rate not reaching the maximum utilization, and there is a certain gap between the calculated acceleration ratio and the theoretical calculation. Summary of the Invention

[0007] In view of the above technical problems, the present invention provides a method for implementing pre-stack three-dimensional reverse time migration based on FPGA using the checkpoint technology. This invention patent can calculate different cache ratios according to the chip resources of different FPGA chips, enabling flexible switching on different model chips, increasing the bit multiplexing of FPGA, improving the computational efficiency of 3D-RTM calculation tasks of different scales, providing an FPGA heterogeneous computing acceleration solution for the industrial implementation of 3D-RTM, and making it possible to achieve industrialized computing for 3D-RTM.

[0008] The technical solution adopted by the present invention to solve the above technical problems is as follows:

[0009] A method for implementing pre-stack three-dimensional reverse time migration based on FPGA using the checkpoint technology, characterized in that the method includes:

[0010] Step S1: Determine whether the acquired seismic data can be stored according to the single-shot data volume of the calculation work area and the DDR size of the FPGA. If the single-shot data volume of the seismic data is greater than the DDR capacity of the FPGA, execute Step S2; otherwise, execute Step S3;

[0011] Step S2: Evaluate the transmission time of the stored seismic data and the calculation time of the FPGA. If the transmission time is greater than the calculation time of the FPGA, execute Step S3; if the transmission time is less than the calculation time of the FPGA, then determine whether the seismic data is greater than the DDR capacity of the CPU. If the seismic data is greater than the DDR capacity of the CPU, store the seismic data from the DDR of the CPU in the hard disk; otherwise, execute Step S3;

[0012] Step S3: Calculate the number of data points Nb that need to be cached for wavefield calculation according to the DDR resource volume of the FPGA, and obtain the corresponding checkpoint to be recorded as the initial wavefield value of the iteration; determine the number of wavefield time iteration times Nc = Nt / Nb included in a single checkpoint calculation, where Nt is the total number of sampling points of the wavefield duration; achieve dynamic balance between the wavefield calculation time and data transmission time of the FPGA by designing and calculating Nc and checkpoint parameters, and obtain these parameter values at the same time;

[0013] Step S4: Start the FPGA to perform wavefield value continuation according to the parameters set in S3, iterate Nb times in sequence according to the preset parameters, use the corresponding checkpoint as the wavefield initial value to input Nc time sampling points each time until Nb checkpoints are iterated, finally complete the iteration of the entire wavefield, and complete the cross-correlation imaging calculation of the forward wavefield and the reverse wavefield at each corresponding moment;

[0014] Step S5: Output the calculation result.

[0015] The above method for implementing prestack three-dimensional reverse time migration based on FPGA using the checkpoint technology is characterized in that the imaging calculation in Step S4 includes performing a cross-correlation operation on the forward wavefield and the reverse wavefield to obtain an imaging result;

[0016] The above method for implementing prestack three-dimensional reverse time migration based on FPGA using the checkpoint technology is characterized in that in Step S5, after outputting the calculation result, data stacking processing and low-frequency filtering processing are sequentially performed.

[0017] The above technical solution has the following advantages or beneficial effects:

[0018] The present invention realizes a pre-stack three-dimensional reverse time migration method based on FPGA using the checkpoint technology. The checkpoint technology is used to improve the boundary storage strategy. Considering the memory resources of different models of FPGA chips and the data volume of 3D-RTM calculations at different scales, the checkpoint point parameters are dynamically set and adjusted through a software architecture on the CPU platform, completely submerging the data preparation and transmission time in the FPGA calculation, achieving a dynamic balance between FPGA calculation and data transmission, improving the utilization rate of FPGA resources, and greatly shortening the algorithm calculation time. Thus, the effect of eliminating the I / O bottleneck is achieved. The present invention sets an optimal FPGA-CPU data interaction scheme according to the characteristics of data volumes at different scales, and the computing resources are maximally used to improve the computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By reading the detailed description of the non-restrictive embodiments with reference to the following drawings, the present invention and its features, shapes, and advantages will become more obvious. The same reference numerals indicate the same parts in all the drawings. The drawings are not drawn to scale, and the focus is on showing the gist of the present invention.

[0020] Figure 1 is a flowchart of a pre-stack three-dimensional reverse time migration method based on FPGA using the checkpoint technology;

[0021] Figure 2a and Figure 2b is a flowchart of FPGA computing 3D-RTM;

[0022] Figure 3 is a storage schematic diagram based on the checkpoint technology. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0024] The computational complexity and storage requirements of 3D-RTM make the computational cost of reverse time migration prohibitively high for industrial seismic imaging. The current deep and ultra-deep exploration data in oil and gas exploration, as well as the large volume of high-density seismic data, require efficient and high-quality computing. Storage strategies such as wavefield reconstruction can effectively solve the problem of storing data in medium and small blocks. For storing large-scale 3D data, issues such as the interaction between storage space, CPU data, and FPGA affecting computational efficiency, I / O read / write speed (PCIe interface rate limit), and network bandwidth need to be considered. By using a heterogeneous platform of CPU and FPGA for collaborative processing, such large computational requirements can be met. However, recent research has found that when implementing heterogeneous platform computing of 3D-RTM using FPGA, the memory resources of different FPGA models are different. In addition, for exploration in different work areas, the quality of exploration data and the depth of the exploration target layer are different, resulting in a large difference in the scale of calculation. When using the same set of FPGA implementation schemes for different data bodies, the FPGA design cannot fully submerge the cross-platform data interaction time in the calculation process, which poses a huge pressure and challenge to the FPGA design and cannot maximize the utilization rate of FPGA computing resources, resulting in a certain gap between the computational acceleration ratio and the theoretical calculation.

[0025] Therefore, the present invention provides a method for implementing pre-stack three-dimensional reverse time migration based on FPGA using the checkpoint technology, as Figures 1 - 3 shown, specifically including:

[0026] Step S1: Determine whether the collected seismic data can be stored according to the single-shot data volume of the calculation work area and the DDR size of the FPGA. If the single-shot data volume of the seismic data is greater than the DDR capacity of the FPGA, execute Step S2; otherwise, execute Step S3;

[0027] Step S2: Evaluate the transmission time of the stored seismic data and the calculation time of the FPGA. If the transmission time is greater than the calculation time of the FPGA, execute Step S3; if the transmission time is less than the calculation time of the FPGA, then determine whether the seismic data is greater than the DDR capacity of the CPU. If the seismic data is greater than the DDR capacity of the CPU, store the seismic data from the DDR of the CPU in the hard disk; otherwise, execute Step S3;

[0028] Step S3: Calculate the number of data points Nb that need to be cached for wave field calculation based on the DDR resources of the FPGA, and obtain the corresponding checkpoint to be recorded as the initial wave field value of the iteration; determine the number of wave field time iteration times Nc = Nt / Nb included in a single checkpoint calculation, where Nt is the total number of sampling points of the wave field duration; achieve dynamic balance between the wave field calculation time and data transmission time of the FPGA by designing and calculating Nc and checkpoint point parameters, and obtain these parameter values at the same time;

[0029] Step S4: Start the FPGA to perform wave field value continuation according to the parameters set in S3. Iterate Nb times in sequence according to the preset parameters, use the corresponding checkpoint as the initial wave field value for input, and iterate Nc time sampling points each time until Nb checkpoints are iterated to finally complete the iteration of the entire wave field and complete the cross-correlation imaging calculation of the forward wave field and the reverse wave field at each corresponding moment;

[0030] Step S5: Output the calculation result.

[0031] Among them, the imaging calculation in Step S4 includes performing a cross-correlation operation on the forward-propagating wave field and the reverse wave field to obtain an imaging result; in Step S5, after outputting the calculation result, data superposition processing and low-frequency filtering processing are sequentially performed.

[0032] In a specific embodiment of the present invention, for 3D-RTM seismic imaging, the collected seismic data is input as the boundary data of the two-way wave equation, and the forward wave field is obtained by solving the wave equation starting from the shot point. At the same time, the reverse wave field value is obtained by inverse-time propagation in time, and an imaging profile is obtained by performing a zero-delay cross-correlation (using the cross-correlation imaging condition) operation on the forward wave field and the reverse wave field at the corresponding moment. When performing heterogeneous computing, first consider the scale of the corresponding computing work area and the resources of the computing FPGA chip used, and determine the specific data storage scheme according to different computing tasks and chip resources. Consider whether to store the data in the DDR of the FPGA or transfer the data to the memory of the CPU through PCIE, or evaluate whether to store the data in the hard disk for ultra-large-scale computing tasks. After determining the scheme, next, evaluate the number of points of Nc of the specific Checkpoint and the Nb wave field storage points according to the computing task and the data clock cycle. After determining these parameters, through the software design on the CPU side to calculate the calculation method, start the FPGA to perform the specific algorithm implementation calculation, and the specific calculation process is shown in Figure 2a and Figure 2b .

[0033] Specific implementation process analysis:

[0034] 1) Determine the location where the calculation data can be cached based on the single-shot data volume of the calculation work area and the DDR size of the FPGA, whether in the DDR of the FPGA or it needs to be interacted out through the PCIE interface.

[0035] 2) If the cached data needs to interact with the CPU, evaluate the data transfer time and the FPGA calculation time.

[0036] 3) If the calculation data is interacted to the CPU side, evaluate the calculation time and the DDR capacity of the CPU, and determine whether it is necessary to cache the cached data from the DDR of the CPU in the hard disk.

[0037] 4) Complete the above evaluations and calculations to determine the number m of wavelength storage points and the number Nc of checkpoint points. During the imaging calculation process, use the wave field at the previous nearest moment in the checkpoint points to forward calculate the wave field value at this moment.

[0038] 5) After the above parameters are determined, pass the storage strategy parameters, single-shot record data, velocity model and other parameters into the FPGA through the (PCIE) interface, and start the FPGA to perform wave field numerical and imaging calculations.

[0039] 6) First, perform a forward modeling once, and store the wave field at the checkpoint points in the buffer area. As shown in the process of (Figure 2a), this process completes the wave field forward modeling calculation.

[0040] 7) After recording the wave field values at the checkpoint points, use the pre-stack shot gather data as the input for reverse wave field extrapolation.

[0041] 8) At the same time, use the checkpointing technology, use the previous nearest checkpoint point as the initial value, and forward calculate the wave field values between recording points 0 and m in sequence. When reaching the next checkpoint point, iteratively update the wave field values in the recording point buffer area. The specific process schematic diagram is shown in Figure 3 .

[0042] 9) Perform cross-correlation imaging on the wave field of the reverse extrapolation and the wave field values of the forward wave field at the recording points.

[0043] 10) Output the calculation results after cross-correlation, and perform subsequent stacking processing or processing to improve cost performance. Thus, complete the 3D-RTM calculation of CPU scheduling FPGA calculation through different storage strategies.

[0044] The core point of the present invention is to design the architecture of the entire heterogeneous computing platform driven by computing time and data capacity by comprehensively considering factors such as the memory capacities of the CPU and FPGA, the computing time-consuming of different computing tasks, and the data interaction time. Through this architecture, factors with greater flexibility and large variations are transferred to the CPU software side, compensating for the fixed defects of FPGA design, and the FPGA can be simply designed as a single logic circuit for completing specific computations. This architecture design takes into account different FPGA chip models and dynamically balances the computing and data interaction time according to the computing scale characteristics of different exploration work areas, thereby maximizing the utilization rate of FPGA computing resources. The adoption of this heterogeneous architecture can flexibly promote the popularization of FPGA for accelerating computations of dedicated computing tasks in the current oil and gas exploration field, providing basic technical support for overcoming bottleneck technical problems urgently needed in production, and thus providing a favorable solution for solving practical industrial problems in oil and gas exploration and development.

[0045] Those skilled in the art should understand that those skilled in the art can implement the said variation examples in combination with the prior art and the above embodiments, and details are not described herein. Such variation examples do not affect the essence of the present invention and are not described herein.

[0046] The preferred embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the above specific implementation manners, and the devices and structures not described in detail should be understood to be implemented in a common manner in the art; any person skilled in the art, without departing from the scope of the technical solution of the present invention, can make many possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above, or modify it into an equivalent embodiment with equivalent changes, which does not affect the essence of the present invention. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for implementing pre-stack three-dimensional reverse time migration based on FPGA using checkpoint technology, characterized in that, The method includes: Step S1: Determine whether the acquired seismic data can be stored according to the single-shot data volume of the calculation work area and the DDR size of the FPGA. If the single-shot data volume of the seismic data is greater than the DDR capacity of the FPGA, execute Step S2; otherwise, execute Step S3. Step S2: Evaluate the transmission time of the stored seismic data and the calculation time of the FPGA. If the transmission time is greater than the calculation time of the FPGA, execute Step S3; if the transmission time is less than the calculation time of the FPGA, determine whether the seismic data is greater than the DDR capacity of the CPU. If the seismic data is greater than the DDR capacity of the CPU, store the seismic data from the DDR of the CPU in the hard disk and then execute Step S3; if the seismic data is less than the DDR capacity of the CPU, directly execute Step S3. Step S3: Calculate the number of data points Nb that need to be cached for wavefield calculation according to the DDR resource volume of the FPGA, and find the corresponding checkpoint to be recorded as the initial wavefield value of the iteration; determine the number of wavefield time iteration times Nc = Nt / Nb included in a single checkpoint calculation, where Nt is the total number of sampling points of the wavefield duration; achieve dynamic balance between the wavefield calculation time and the data transmission time of the FPGA by designing the calculation of Nc and the checkpoint point parameters, and at the same time obtain the number m of wavelength storage points and the parameter values of the number Nc of checkpoint points. Step S4: Start the FPGA and perform wavefield value continuation according to the parameters set in Step S3, and iterate Nb times in sequence according to the preset parameters. Use the corresponding checkpoint as the initial wavefield value for input, and iterate Nc time sampling points each time until Nb checkpoints are iterated. Finally, complete the iteration of the entire wavefield, and perform cross-correlation imaging calculation of the forward wavefield and the reverse wavefield at each corresponding moment. Step S5: Finally, output the calculation result.

2. The method for implementing pre-stack three-dimensional reverse time migration based on FPGA using checkpoint technology according to claim 1, wherein The imaging calculation in Step S4 includes performing cross-correlation operation on the forward wavefield and the reverse wavefield to obtain the imaging result.

3. The method for implementing pre-stack three-dimensional reverse time migration based on FPGA using checkpoint technology according to claim 1, wherein In Step S5, after outputting the calculation result, data stacking processing and low-frequency filtering processing are sequentially performed.

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