System and method for hierarchical in-line interrupt scheme for efficient interrupt propagation and handling

Abstract

The present disclosure relates to systems and methods for a hierarchical in-line interrupt scheme for efficient interrupt propagation and handling. What is proposed is a new approach to a system and method of supporting a hierarchical interrupt propagation scheme for efficient interrupt propagation and handling. The hierarchical interrupt propagation scheme organizes functional blocks associated with multiple slave interrupt handling modules in a hierarchy in a chip. When an exception or error condition occurs in a functional block, a slave interrupt handling module associated with the functional block creates an interrupt packet as an interrupt notification and utilizes pre-existing input and output interfaces of registers that have been utilized to access the functional block to transmit the created interrupt packet through the hierarchy to a central interrupt handling module without requiring a dedicated interconnect to be laid out outside of the functional block. The central interrupt handling module then handles the interrupt notification and provides a response packet to the interrupt notification back to the slave interrupt handling module that created the interrupt packet to configure or adjust the functional block accordingly.

Description

[0001] Related Applications Cross Reference To

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 008,511, filed April 10, 2020, which is incorporated by reference herein in its entirety. BACKGROUND

[0003] As hardware-based application-specific integrated circuits (ASICs) become larger in size and more complex in architecture and functionality, the number of functional blocks (or simply blocks) in each of these ASIC chips is also rapidly growing. For example, it is typical for an ASIC chip to have a functional block count in the hundreds or even thousands. During operation, each of the functional blocks in the chip generates one or more interrupt notifications upon encountering various exception and error conditions. Currently, the interrupt notifications are sent out of each functional block to a central interrupt controller in the chip, where the interrupt notifications are combined and encoded. Only then are the interrupt notifications sent out of the chip to a host or interrupt handling module, which will execute an interrupt handling routine to process the interrupt notifications. Such an interrupt handling mechanism requires a number of interconnect lines (depending on the supported interrupt priority levels) to extend from the functional blocks to the central interrupt controller in the chip. When the number of functional blocks in the chip is large, the excessive interconnect lines can converge on the central interrupt controller. As a result, the chip designer will have to invest a significant amount of effort in the front-end resistive transistor level (RTL) development to implement the routing connectivity of these interconnect lines, which can be error-prone and can require a significant amount of front-end verification effort by the chip designer. Additionally, the excessive interconnect lines can cause congestion problems in the back-end flow of the chip layout, and can take a significant amount of back-end time and effort to meet the timing requirements of the top-level interconnect lines extending long traces across the chip.

[0004] The foregoing examples of the related art and the limitations related thereto are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon reading this description and studying the attached figures. BRIEF DESCRIPTION OF DRAWINGS

[0005] When read in conjunction with the attached Figure One Aspects of the disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, according to common practice, the various features are not necessarily drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for clarity. FIG. 1 illustrates an example of a hardware-based hierarchical interrupt propagation scheme for efficient interrupt propagation and handling, according to aspects of the present embodiments.

[0006] Figure 1 An example of a diagram depicting a hardware-based hierarchical interrupt propagation scheme for efficient interrupt propagation and handling, according to aspects of the present embodiments, is depicted.

[0007] FIG. 1 illustrates an example of a hardware-based hierarchical interrupt propagation scheme for efficient interrupt propagation and handling, according to aspects of the present embodiments.Figure 2 Examples of at least one input interface and output interface according to an aspect of this embodiment are depicted, which are associated with each of a central interrupt handling module, a plurality of address decoders, and a plurality of subordinate interrupt handling modules.

[0008] Figure 3 An example diagram illustrating a hardware-based hierarchical interrupt propagation scheme according to an aspect of this embodiment is provided, wherein a central interrupt handling module implements two interrupt registers corresponding to two different interrupt priorities.

[0009] Figure 4 A flowchart illustrating an example of a hardware-based hierarchical interrupt propagation process for efficient interrupt propagation and processing, according to aspects of this embodiment, is provided. Detailed Implementation

[0010] The following disclosure provides numerous different embodiments or examples for implementing various features of the subject matter. Specific examples of components and apparatus are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0011] Before describing the various embodiments in more detail, it should be understood that the embodiments are not limiting, as the elements in such embodiments may differ. It should also be understood that elements of the particular embodiments described and / or illustrated herein can be readily separated from those particular embodiments and may optionally be combined with or substituted for elements in any of the other embodiments described herein. It should also be understood that the terminology used herein is for the purpose of describing certain concepts and is not intended to be limiting. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood in the art to which the embodiments pertain.

[0012] A novel approach to a hierarchical interrupt propagation scheme for efficient interrupt propagation and handling is proposed. The hierarchical interrupt propagation scheme organizes multiple subordinate interrupt handlers associated with multiple functional blocks within a chip in a hierarchical structure or hierarchy. When an exception or error condition occurs in one of the functional blocks, the subordinate interrupt handler associated with the functional block creates an interrupt packet as an interrupt notification and transmits the created interrupt packet hierarchically to a central interrupt handler using pre-existing input and output interfaces and / or interconnects, without extending additional interconnects outside each functional block dedicated to interrupt notification. These pre-existing input and output interfaces and / or interconnects are already used to access the functional block's registers. The central interrupt handler then processes the interrupt notification received from the subordinate interrupt handlers and provides a response packet to the interrupt notification back to the subordinate interrupt handler that created the interrupt packet, allowing for appropriate configuration or adjustment of the functional block.

[0013] By reusing pre-existing register access interfaces and / or interconnects outside of functional blocks within the chip, the hierarchical interrupt propagation scheme proposed above eliminates the need for thousands of interrupt-based interconnects running from functional blocks to the central interrupt handling module. This hierarchical interrupt propagation scheme results in a significant reduction in the time and effort required for front-end design, verification, and back-end implementation of chips with a large number of functional blocks. Simultaneously, with appropriate design of the hierarchy of functional blocks within the chip, latency caused by the propagation delay of interrupt notifications through this hierarchy can be kept within certain constraints.

[0014] Figure 1 Examples of diagrams illustrating hardware-based hierarchical interrupt propagation schemes for efficient interrupt propagation and handling are provided. While these diagrams depict components as functionally separate, this depiction is for illustrative purposes only. It is evident that the components depicted in the diagrams can be arbitrarily combined or divided into separate software, firmware, and / or hardware components. Furthermore, it will be apparent that regardless of how such components are combined or divided, they can execute on the same host or multiple hosts, which may be connected by one or more networks.

[0015] exist Figure 1 In the example, architecture 100 includes at least one central / master interrupt handling module 102 and multiple address decoders 104 arranged in a multi-level hierarchy 106 (e.g., a tree structure). Figure 1The architecture 100 includes a plurality of slave interrupt handling modules 108 (e.g., 108_1 to 108_8), each slave interrupt handling module being attached to one of a plurality of address decoders 104, wherein each slave interrupt handling module 108 is a register module associated with or within a type of functional block (not shown) in the chip. The architecture 100 also includes a plurality of bidirectional links / interconnects 110 that connect the various components of the architecture 100 together to form the architecture 100. Each of these components in the architecture 100 is a dedicated hardware block / component that is programmable by a user at a host (not shown) via software instructions for various operations. When the software instructions are executed, each hardware component becomes a purpose-specific hardware component for implementing certain machine learning functions. In some embodiments, the architecture 100 is on a single chip, such as a system-on-a-chip (SoC).

[0016] exist Figure 1 In the example, each of the central interrupt handling module 102, the multiple address decoders 104, and the multiple subordinate interrupt handling modules 108 includes, for example: Figure 2 The example illustrates at least one input interface 202 and an output interface 204. In some embodiments, each of the input interface 202 and the output interface 204 is user-configurable and / or programmable. In some embodiments, each input interface 202 is configured to receive data, address, and control information / signals (e.g., valid signal qualifier (VLD) 206, frame status (SF) 208, and end-of-frame (EF) 210 from the transmitting interface) into interrupt handling modules 102 and 108 and / or address decoder 104, and to send flow control signals (e.g., fc 212) from interrupt handling modules 102 and 108 and / or address decoder 104 back to the interface that transmitted the VLD signal. Each output interface 204 is configured to send / transmit data, address, and control information / signals (e.g., vld 206, sf 208, and ef 210) to the interrupt handling modules 102 and 108 and / or the address decoder 104, and to receive flow control signals (e.g., fc 212) to the interrupt handling modules 102 and 108 and / or the address decoder 104. In some embodiments, the input interfaces 202 and output interfaces 204 pre-existing on each of the central interrupt handling module 102, the address decoder 104, and the slave interrupt handling module 108 serve as register access interfaces configured to access registers (not shown) in these components to write data and / or control information to or read data and / or control information from a register address in these components, respectively.

[0017] exist Figure 1In the example, each slave interrupt handling module 108 is a register module configured to implement a set of register functionalities associated with its functional block (not shown) within the chip. Here, the functional block associated with each of the slave interrupt handling modules 108_1 to 108_8 can be, but is not limited to, one of the following: a PCIe block for interface communication between an external host and the chip; an Ethernet memory block for processing and storing Ethernet communication with the chip; a bus block for transmitting address, data, and control information via a bus within the chip; and a local block for processing communication between the various functional blocks within the chip.

[0018] In some embodiments, each subordinate interrupt handling module 108 is configured to generate an interrupt transaction / notification and handle related operations for the interrupt notification, wherein such an interrupt notification is triggered when an exception or error condition occurs in a function block of the function block associated with the subordinate interrupt handling module 108. In some embodiments, the subordinate interrupt handling module 108 is configured to generate an interrupt notification when an interrupt bit in a specific interrupt register (not shown) of the subordinate interrupt handling module 108 is set by a function block. The subordinate interrupt handling module 108 is then configured to send the interrupt notification in the form of an interrupt packet to the central interrupt handling module 102 via a pre-existing register read interface (e.g., output interface 204), which is configured to transmit the interrupt packet beyond the transmission of the subordinate interrupt handling module 108. The following is a non-limiting example of the description of the various fields in the 32-bit interrupt packet. As shown in the example below, the interrupt group includes the interrupt bit (IntSet) discussed above; a one-bit priority field indicating the priority of the interrupt notification (e.g., high or low), which can be easily extended to a multi-bit priority by using more than one bit from the reserved field; a block type field (e.g., 16 bits) that uniquely identifies one of the different types (e.g., up to 64k) of functional blocks in the chip from which the interrupt notification is generated; and a block instance field (e.g., 8 bits) that uniquely identifies one of up to 256 instances of the type of functional block from which the interrupt notification is generated.

[0019]

[0020]

[0021] Once an interrupt packet is generated and sent outside of one of the subordinate interrupt handling modules 108 via its pre-existing register read / output interface 204, the interrupt packet is transmitted upwards to the central interrupt handling module 102 through one or more address decoders 104 in the multi-level hierarchy 106. For example... Figure 1As shown, each address decoder 104 acts as an intermediate node in the multi-level hierarchy 106 and is associated with one or more subordinate interrupt handling modules 108 and / or one or more other address decoders 104. In some embodiments, each address decoder 104 is configured to receive interrupt packets from one or more associated subordinate interrupt handling modules 108 and / or other address decoders 104, decode the destination address of the interrupt packets, and forward the interrupt packets to the central interrupt handling module 102 or the next address decoder 108 in the multi-level hierarchy 106 based on the decoded destination address. The central interrupt handling module 102 is then configured to receive and process the interrupt packets. Conversely, once the central interrupt handling module 102 has finished processing the interrupt packets and generated a response packet for the received interrupt packets, the address decoder 108 is configured to receive the response packet from the central interrupt handling module 102, decode the destination address of the response packet, and forward the response packet to the next address decoder 108 or the subordinate interrupt handling module 108 in the multi-level hierarchy 106 that sent the corresponding interrupt packets. Once the slave interrupt handling module 108 receives a response packet, the functional blocks associated with the slave interrupt handling module 108 can be configured or adjusted according to the received response packet.

[0022] exist Figure 1 In the example, the central interrupt handling module 102 is configured to accept and decode the various fields of an interrupt packet once it arrives at the central interrupt handling module 102. In some embodiments, the central interrupt handling module 102 includes two interrupt registers corresponding to two different (high and low) interrupt priorities—such as Figure 3The example illustrates interrupt high register (int_high) 302 and interrupt low register (int_low) 304. In some embodiments, when there are more than two interrupt priorities, more interrupt registers may be included in the central interrupt processing module 102. In some embodiments, both interrupt registers 302 and 304 have as many bits (width) as the number of functional blocks in the chip. In some embodiments, interrupt registers 302 and 304 are utilized by the central interrupt processing module 102 to combine interrupt notifications / packets received across functional blocks in the chip for processing. Specifically, in some embodiments, the central interrupt processing module 102 is configured to determine and select which of the interrupt high register 302 or interrupt low register 304 should be accessed and set for interrupt notification based on the “priority” field of the received interrupt packet. In some embodiments, the central interrupt processing module 102 is configured to utilize a combined {block type, block instance} field to index the received interrupt notification to select the corresponding interrupt bit among the interrupt registers selected based on the priority field. Once an interrupt bit in one of the interrupt registers is selected, the central interrupt handling module 102 is configured to set or clear the interrupt bit value based on the "IntSet" value. For example... Figure 3 As shown in the non-limiting example, interrupt notification 306_1 generated by the slave interrupt handling module associated with Se0 has high priority. In interrupt high register 302, the bit corresponding to {block type = 54, block instance = 0} is then set to 1. Interrupt notification 306_2 generated by the slave interrupt handling module associated with Se2 has low priority. In interrupt low register 304, the bit corresponding to {block type = 54, block instance = 2} is then set to 1. Interrupt notification 306_3 generated by the slave interrupt handling module associated with URW also has low priority, and in interrupt low register 304, based on IntSet = 0 in interrupt notification 306_3, the bit corresponding to {block type = 54, block instance = 2} is cleared to 0. The central interrupt handling module 102 is then configured to execute an interrupt handling routine to process the interrupt notifications / packets received in the interrupt register based on their priority or the order in which they were received in the interrupt register, in order to create multiple response packets corresponding to the interrupt packets. The central interrupt handling module 102 is then configured to send the generated response packets back to the subordinate interrupt handling module 108 that generated the interrupt notification via multiple address decoders 104 in the hierarchy 106 discussed above, for configuration or adjustment of the functional blocks associated with the subordinate interrupt handling module 108.

[0023] Figure 4A flowchart 400 illustrates an example of a hardware-based hierarchical interrupt propagation process for efficient interrupt propagation and handling. Although the functional steps are depicted in a specific order for illustrative purposes, these processes are not limited to any particular order or arrangement of steps. Those skilled in the art will understand that the various steps depicted in the diagram can be omitted, rearranged, combined, and / or adjusted in various ways.

[0024] exist Figure 4 In the example, flowchart 400 begins at block 402, where an interrupt notification is generated, and the associated operations for the interrupt notification are handled by a subordinate interrupt handling module associated with a function block within the chip. Such an interrupt notification is triggered when an exception or error condition occurs in the function block associated with the subordinate interrupt handling module. Flowchart 400 continues to block 404, where the interrupt notification is sent to the central interrupt handling module as an interrupt packet via a pre-existing output interface configured to transmit the interrupt packet outside the subordinate interrupt handling module. Flowchart 400 continues to block 406, where multiple fields of the interrupt packet are received and decoded by the central interrupt handling module. Flowchart 400 continues to block 408, where an interrupt handling routine is executed by the central interrupt handling module to process the received interrupt packet and create a response packet in response to the interrupt packet. Flowchart 400 continues to block 410, where the generated response packet is sent back to the subordinate interrupt handling module that generated the interrupt notification for configuration or adjustment of the function block associated with the subordinate interrupt handling module. Flowchart 400 ends at block 412, where response packets from the central interrupt handling module are received via a pre-existing input interface, and the function blocks associated with the subordinate interrupt handling modules are configured or adjusted accordingly.

[0025] The foregoing description of various embodiments of the claimed subject matter is provided for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the claimed subject matter to the precise forms disclosed. Many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to best illustrate the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the claimed subject matter and to conceive of various embodiments and modifications suitable for the intended particular use.

Claims

1. A hardware-based programmable hierarchical interrupt propagation architecture, comprising: Multiple slave interrupt handling modules, each associated with a function block within the chip, wherein each slave interrupt handling module communicates using at least one pre-existing input interface and at least one pre-existing output interface, wherein registers within the function block are accessed through the at least one pre-existing input interface and the at least one pre-existing output interface, and wherein each slave interrupt handling module is configured to: Generate the interrupt notification for the interrupt notification, wherein the interrupt notification is triggered when an exception or error condition occurs in the function block associated with the subordinate interrupt handling module; The interrupt notification is sent to the central interrupt handling module in the form of an interrupt packet via the pre-existing output interface, which is configured to transmit the interrupt packet outside the subordinate interrupt handling module; The system receives response packets from the central interrupt handling module via the pre-existing input interface and configures or adjusts the function blocks associated with the subordinate interrupt handling module accordingly.

2. The architecture according to claim 1 further includes: The central interrupt handling module is configured as follows: Accept and decode the individual fields of the interrupted packet; Execute the interrupt handling routine to process the received interrupt packet and create the response packet corresponding to the interrupt packet; The generated response packet is transmitted back to the subordinate interrupt handling module that generated the interrupt notification for configuration or adjustment of the functional block associated with the subordinate interrupt handling module.

3. The architecture according to claim 1, wherein: Each of the plurality of slave interrupt handling modules is a register module, which is configured to implement a set of register functionalities associated with the function block, which is associated with each slave interrupt handling module in the chip.

4. The architecture according to claim 2, wherein: The pre-existing input interface and the pre-existing output interface of each of the plurality of slave interrupt handling modules are register access interfaces. The register access interfaces have been used to access the register modules in the function block to write data and / or control information to the address of the register module, or to read data and / or control information from the address of the register module.

5. The architecture according to claim 1, further comprising: Multiple address decoders arranged in a multi-level hierarchy, wherein each of the multiple address decoders is associated with one or more slave interrupt handling modules among the multiple slave interrupt handling modules, and / or one or more other address decoders among the multiple address decoders, wherein each of the multiple address decoders is configured to: The interrupt packet is received from one or more subordinate interrupt handling modules associated with the plurality of subordinate interrupt handling modules, and / or one or more other address decoders; Decode the destination address of the interrupt packet; The interrupt packet is forwarded to the central interrupt handling module or the next address decoder in the multi-level hierarchy.

6. The architecture according to claim 5, wherein: Each of the plurality of address decoders is further configured to: Receive the response packet from the central interrupt handling module. Decode the destination address of the response packet. The response packet is forwarded to the next address decoder or the subordinate interrupt handling module that sent the corresponding interrupt packet in the multi-level hierarchy.

7. The architecture according to claim 1, wherein: Each of the plurality of slave interrupt handling modules is configured to generate the interrupt notification when the interrupt bit in the interrupt register of the slave interrupt handling module is set.

8. The architecture according to claim 7, wherein: The interrupt group includes one or more interrupt bits, a priority field indicating the priority of the interrupt notification, a block type field, and a block instance field, wherein the block type field uniquely identifies the type of the function block in which the interrupt notification is generated, and the block instance field uniquely identifies an instance of the type of the function block in which the interrupt notification is generated.

9. The architecture according to claim 2, wherein: According to the priority field of the interrupt group, the central interrupt processing module includes multiple interrupt registers corresponding to a set of interrupt priorities, wherein each of the multiple interrupt registers has the same number of bits as the number of functional blocks in the chip.

10. The architecture according to claim 9, wherein: The central interrupt handling module is configured to utilize the plurality of interrupt registers to combine interrupt notifications received from multiple functional blocks across the chip for processing.

11. The architecture according to claim 10, wherein: The central interrupt handling module is configured to select one of the plurality of interrupt registers to be accessed and set for interrupt notification based on the priority field of the interrupt group.

12. The architecture according to claim 8, wherein: The central interrupt handling module is configured to The combination of the block type field and the block instance field is used to index the received interrupt notification in order to select the corresponding interrupt bit in the interrupt register selected based on the priority field; Set or clear the value of the interrupt bit in the selected interrupt register.

13. The architecture according to claim 9, wherein: The central interrupt handling module is configured to execute an interrupt handling routine to process the received interrupt packets based on the priority of the received interrupt packets or the order in which the interrupt packets are received in the interrupt register, in order to create a response packet corresponding to the interrupt packet.

14. A method for a hierarchical interrupt propagation scheme for efficient interruption propagation and handling, comprising: The interrupt notification is generated by a subordinate interrupt handling module associated with a function block within the chip. Each of the plurality of subordinate interrupt handling modules communicates using at least one pre-existing input interface and at least one pre-existing output interface, wherein the registers within the function block are accessed through the at least one pre-existing input interface and the at least one pre-existing output interface. The interrupt notification is triggered when an abnormal or error condition occurs in a function block associated with the subordinate interrupt handling module. The interrupt notification is sent to the central interrupt handling module in the form of an interrupt packet via a pre-existing output interface, which is configured to transmit the interrupt packet outside the transmission of the subordinate interrupt handling module. The system receives response packets from the central interrupt handling module via the pre-existing input interface and configures or adjusts the function blocks associated with the subordinate interrupt handling module.

15. The method of claim 14, further comprising: The central interrupt processing module receives and decodes each field of the interrupt packet; Execute the interrupt handling routine to process the received interrupt packet and create the response packet corresponding to the interrupt packet; The generated response packet is transmitted back to the subordinate interrupt handling module that generated the interrupt notification for configuration or adjustment of the functional block associated with the subordinate interrupt handling module.

16. The method of claim 14, further comprising: The interrupt packets are received from one or more associated interrupt handling modules and / or one or more address decoders among the plurality of subordinate interrupt handling modules; Decode the destination address of the interrupt packet; The interrupt packet is forwarded to the central interrupt handling module or to the next address decoder in the multi-level hierarchy.

17. The method of claim 16, further comprising: Receive the response packet from the central interrupt handling module. Decode the destination address of the response packet. The response packet is forwarded to the next address decoder or the subordinate interrupt handling module that sent the corresponding interrupt packet in the multi-level hierarchy.

18. The method of claim 14, further comprising: The interrupt notification is generated when the interrupt bit in the interrupt register of the slave interrupt handling module is set.

19. The method of claim 18, wherein: The interrupt group includes one or more interrupt bits, a priority field indicating the priority of the interrupt notification, a block type field, and a block instance field, wherein the block type field uniquely identifies the type of the function block in which the interrupt notification is generated, and the block instance field uniquely identifies an instance of the type of the function block in which the interrupt notification is generated.

20. The method of claim 15, further comprising: Based on the priority field of the interrupt group, multiple interrupt registers corresponding to a set of interrupt priorities are implemented in the central interrupt processing module, wherein each of the multiple interrupt registers has the same number of bits as the number of functional blocks in the chip.

21. The method of claim 20, further comprising: The plurality of interrupt registers are used to combine interrupt notifications received from multiple functional blocks across the chip for processing.

22. The method of claim 21, further comprising: Based on the priority field of the interrupt group, one of the multiple interrupt registers to be accessed and set is selected for the interrupt notification.

23. The method of claim 19, further comprising: The combination of the block type field and the block instance field is used to index the received interrupt notification in order to select the corresponding interrupt bit in the interrupt register selected based on the priority field; Set or clear the value of the interrupt bit in the selected interrupt register.

24. The method of claim 20, further comprising: The interrupt handling routine is executed to process the received interrupt packets based on their priority or the order in which they were received in the interrupt register, in order to create a response packet corresponding to the interrupt packet.

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