A memory operation control method, device and storage medium

Abstract

The embodiment of the present invention provides a memory operation control method, device and storage medium. Because the memory block as a whole does not need to be locked when receiving a read operation thread and a write operation thread, the read operation thread and the write operation thread can be executed in parallel at the same time without blocking each other. At the same time, because the memory block is divided into at least two memory blocks, even if the read operation thread and the write operation thread are in parallel, the read operation thread operates on the current readable memory block of the memory block, and the write operation thread operates on other memory blocks except the readable memory block. Therefore, the two memory operation threads will not affect each other, and the correctness and effectiveness of data read and write operations can be guaranteed. Therefore, the solution provided by the embodiment of the present invention allows the read operation thread and the write operation thread to be executed in parallel on the basis of ensuring the correctness and effectiveness of memory operations, thereby improving the efficiency of memory read and write operations.

Description

Technical Field

[0001] The embodiments of the present invention relate to, but are not limited to, the field of storage technology, and specifically, relate to, but are not limited to, a memory operation control method, device, and storage medium. Background Art

[0002] In actual development, the write operation thread can query the memory address of the public data through the key value, and write new data according to the queried memory address; the read operation thread queries the memory address of the public data through the key value, and then reads and analyzes the data according to the queried memory address. In order to solve the thread synchronization problem, in the related art, a write lock is added to the memory when the write operation thread writes new data, and the write lock is released after the new data is written. During the period of adding the write lock to the memory, if a read operation thread is initiated, the data can only be read after the write operation thread ends. At the same time, the read operation thread will also add a read lock to the memory when reading data, and it will not be released until the read operation thread ends. During the period of adding the read lock to the memory, even if a write operation thread is initiated, the write operation thread cannot be responded immediately, but must wait until the read lock of the read operation thread is released before data can be read in the memory. It can be seen that in the related art, although the use of read locks and write locks can ensure the correctness of read and write operations, it will cause mutual blocking of the read operation thread and the write operation thread. In actual applications, a large number of concurrent read operation threads are prone to appear, so if the write operation thread takes a long time, a large number of read operation threads will be piled up in the system. Summary of the invention

[0003] The memory operation control method, device and storage medium provided by the embodiments of the present invention mainly solve the technical problem that: in related memory operation schemes, because read and write operations will lock the memory, it is easy to cause the read operation thread and the write operation thread for the same memory to block each other, affecting the efficiency of read and write operations.

[0004] In order to solve the above technical problems, an embodiment of the present invention provides a memory operation control method, comprising:

[0005] Divide K memory blocks from a memory block and determine the memory address of each memory block, where K is greater than or equal to 2;

[0006] After determining that a write operation thread for a memory block is initiated, a target memory block is allocated to the write operation thread, so that the write operation thread can perform a write operation according to the memory address of the target memory block;

[0007] If a read operation thread is initiated for a memory block within the read validity period of the target memory block, the target memory block is provided to the read operation thread as the current readable memory block of the memory block, so that the read operation thread can perform a read operation according to the memory address of the target memory block; the read validity period of the target memory block is from the completion of the write operation of the write operation thread to the target memory block to the completion of the next write operation thread;

[0008] If a new write operation thread is initiated for a memory block within the read validity period of the target memory block, a target memory block is allocated to the new write operation thread from other memory blocks other than the readable memory block for the write operation.

[0009] An embodiment of the present invention further provides a memory operation control device, the memory operation control device comprising a processor, a memory and a communication bus;

[0010] The communication bus is used to realize the connection and communication between the processor and the memory;

[0011] A memory operation control program is stored in the memory, and the memory includes at least one memory block, and the memory block includes K memory blocks, where K is greater than or equal to 2;

[0012] The processor is used to execute one or more programs stored in the memory to implement the steps of the above-mentioned memory operation control method.

[0013] An embodiment of the present invention further provides a storage medium storing a memory operation control program. The memory operation control program can be executed by one or more processors to implement the steps of the above-mentioned memory operation control method.

[0014] According to the memory operation control method, device and storage medium provided by the embodiment of the present invention, at least two memory blocks are divided from a memory block, and the memory address of each memory block is determined. Then, after determining that a write operation thread for the memory block is initiated, a target memory block is allocated to the write operation thread, so that the write operation thread can perform a write operation according to the memory address of the target memory block. The period from the end of the write operation thread to the completion of the next write operation thread belongs to the read validity period of the target memory block. If a read operation thread for the memory block is initiated during the read validity period, the target memory block is provided to the read operation thread as the current readable memory block of the memory block, so that the read operation thread can perform a read operation according to the memory address of the target memory block; if a new write operation thread for the memory block is initiated during the read validity period, the target memory block is allocated to the new write operation thread from other memory blocks other than the readable memory block for it to perform a write operation. According to the memory operation control scheme provided by the embodiment of the present invention, since the whole memory is lock-free, if a read operation request of the read operation thread is received within the read validity period of the target memory block, it can be responded immediately; if a write operation request of the write operation thread for the memory block is received within the read validity period of the target memory block, it can also be responded immediately, that is, the read operation thread and the write operation thread can be executed in parallel at the same time without blocking each other. At the same time, because the memory block is divided into at least two memory blocks, even if the read operation thread and the write operation thread are in parallel, the read operation thread operates on the current readable memory block of the memory block, and the write operation thread operates on other memory blocks except the readable memory block, so the two memory operation threads will not affect each other, and the correctness and effectiveness of data read and write operations can be guaranteed. Therefore, the scheme provided by the embodiment of the present invention allows the read operation thread and the write operation thread to execute in parallel on the basis of ensuring the correctness and effectiveness of memory operations, thereby improving the efficiency of memory read and write operations.

[0015] Other features and corresponding beneficial effects of the present invention are described in the latter part of the specification, and it should be understood that at least part of the beneficial effects become obvious from the description in the specification of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of a memory operation control method provided in Embodiment 1 of the present invention;

[0017] Figure 2 A schematic diagram of the structure of a memory block provided in Embodiment 1 of the present invention;

[0018] Figure 3 Another structural schematic diagram of the memory block provided in the first embodiment of the present invention;

[0019] Figure 4A flow chart of adding and allocating free memory blocks provided in the second embodiment of the present invention;

[0020] Figure 5 This is a schematic diagram of the first structure of the memory block provided in the second embodiment of the present invention;

[0021] Figure 6 A second structural diagram of a memory block provided in Embodiment 2 of the present invention;

[0022] Figure 7 A third structural schematic diagram of a memory block provided in Embodiment 2 of the present invention;

[0023] Figure 8 A fourth structural schematic diagram of a memory block provided in the second embodiment of the present invention;

[0024] Fig. 9 A flow chart of non-free memory block recovery provided in the second embodiment of the present invention;

[0025] Fig.10 A schematic diagram of the structure of a memory block provided in Embodiment 3 of the present invention;

[0026] Fig.11 A schematic diagram of the hardware structure of the memory operation control device provided in the fourth embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the following is a further detailed description of the embodiments of the present invention through specific implementation methods combined with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0028] Embodiment 1:

[0029] In order to solve the problem in the related art that the read operation thread and the write operation thread for a piece of memory will block each other, affecting the efficiency of the read and write operations, this embodiment provides a memory operation control method, which can be implemented by a memory operation control device. Figure 1 The flowchart of the memory operation control method is shown as follows:

[0030] S102: Divide a memory block into K memory blocks, and determine the memory address of each memory block.

[0031] The so-called "memory block" means that the read operation on the memory will not add a read lock, and the write operation on the memory will not add a write lock. In this way, when a write operation thread performs a write operation on the memory block, the write operation thread will not monopolize the memory block. In the process of accepting the data written by the write operation thread, the memory block can also synchronously accept operations from other operation threads, including read operation threads and other write operation threads. Similarly, when a read operation thread performs a data read operation on the memory block, it will not add a read lock to the memory block. Therefore, in the process of accepting the data read by the read operation thread, the memory block can also synchronously accept operations from other operation threads, including other read operation threads and write operation threads.

[0032] In this embodiment, K is greater than or equal to 2, that is, the memory operation control device can divide at least two memory blocks from a memory block. It is worth noting that the memory block is the specific operation object when the read operation thread and the write operation thread operate on the memory block, but the memory block provides services to the user as a whole, that is, for the user, it does not understand and does not need to understand the existence of each memory block in the memory block. The available size of the memory block when providing services to the user is equal to the size of the memory block. In some examples of this embodiment, the sizes of each memory block in the memory block are not exactly the same, but it can be understood that because the memory block is only shown as the size of a memory block to the outside, and for the user, the size of a memory block is fixed and will not change dynamically. Therefore, each memory block in the memory block can only provide the same memory read and write service to the outside according to the size of the smallest memory block. This easily leads to space waste in other larger memory blocks. Therefore, in order to avoid the problem of memory space waste, in other examples of this embodiment, the sizes of each memory block in the memory block are the same.

[0033] S104: After determining that a write operation thread for a memory block is initiated, a target memory block is allocated to the write operation thread.

[0034] After the memory operation control device completes the memory block division setting, it can receive the operation request of the operation thread for the memory block. After determining that a write operation thread has initiated a write operation to the memory block, the memory operation control device can allocate a memory block for the write operation thread to perform data write operation. The memory block allocated by the memory operation control device to the write operation thread is the target memory block of the write operation thread. It can be understood that each write operation thread has a corresponding target memory block. See Figure 2The memory block 20 shown includes a first memory block 21 and a second memory block 22. Assuming that a write operation thread is initiated after the memory operation control device completes the division setting of the memory block 20, the memory operation control device can select one from the first memory block 21 and the second memory block 22 to be assigned to the write operation thread as its target memory block. For example, in one example, the memory operation control device assigns the first memory block 21 to the write operation thread, then the first memory block 21 is the target memory block of the write operation thread, and the write operation thread will subsequently write data in the first memory block 21.

[0035] It should be understood that after a block of memory has been operated by a write operation thread, it will provide data reading operation services to the outside. Since each memory block in the memory block in this embodiment provides services to the outside as a memory block, after the memory block accepts the write operation of the first write operation thread until the memory block is completely released, there must be a memory block in the memory block that provides data reading services to the outside. Although the memory blocks that provide data reading services to the outside may be different at different times, there must be a memory block as the readable memory block of the memory block at any time during this period. Since the readable memory block needs to provide effective data reading services to the outside, when the memory operation control device allocates a target memory block for a write operation thread, the current readable memory block cannot be selected as the target memory block of the write operation thread, that is, the memory operation control device can only allocate target memory blocks to the write operation thread from other memory blocks other than the current readable memory block.

[0036] Under normal circumstances, when the memory operation control device allocates a target memory block for the currently initiated write operation thread, it selects from the current free memory blocks. The so-called free memory block refers to the memory block that has not yet been written to the data. The corresponding to the free memory block is the non-free memory block. Obviously, the non-free memory block is the memory block that currently stores data. There is no doubt that if the memory operation control device allocates a target memory block for a write operation thread from the free memory blocks, once the memory operation control device selects a free memory block, it can be directly allocated to the write operation thread for it to perform data writing operations. In some other examples of this embodiment, the memory operation control device can also allocate target memory blocks for the write operation thread from non-free memory blocks. In this case, after the memory operation control device selects a non-free memory block, the memory operation control device cannot directly allow the write operation thread to write data in the memory block, but needs to first clear the data in the non-free memory block, so that it changes from a non-free memory block to a free memory block before providing it to the write operation thread. Therefore, in essence, the target memory blocks allocated to the write operation thread by the memory operation control device are all free memory blocks, but the memory operation control device can select from different memory blocks during the allocation process.

[0037] S106: If a read operation thread is initiated for the memory block within the read validity period of the target memory block, the target memory block is provided to the read operation thread as the current readable memory block of the memory block; if a new write operation thread is initiated for the memory block, the target memory block is allocated to the new write operation thread from other memory blocks other than the readable memory block.

[0038] After the memory operation control device allocates a target memory block to the write operation thread, the write operation thread will write data in the target memory block. Because the memory block always provides the latest data currently stored to the outside, after the write operation of the write operation thread is completed, the target memory block will become the current readable memory block of the memory block. Here, the write operation thread is recorded as "a". Then, after the write operation thread a, if another write operation thread b also completes the write operation for its corresponding target memory block, then after the operation of the write operation thread b is completed, the target memory block of the write operation thread b will replace the target memory block of the write operation thread a and be called the new readable memory block of the memory block. Therefore, from the completion of the write operation of the write operation thread a to the target memory block, until the next write operation thread (for example, the write operation thread b) completes the write operation of another memory block, the readable memory block of the memory block to the outside is the target memory block of the write operation thread a. In other words, during this period, the target memory block of the write operation thread a is a valid readable memory block. In this embodiment, the period from when the write operation thread a completes the write operation on the target memory block to when the next write operation thread completes the write operation on another memory block is called the read validity period of the target memory block of the write operation thread a. For any write operation thread, the read validity period of its target memory block refers to the period from when the write operation thread completes the write operation on the target memory block to when the next write operation thread completes the write operation on another memory block.

[0039] It can be seen that the length of the read validity period of different target memory blocks is not fixed, but changes with the frequency of initiation of write operation threads, or with the frequency of termination of each write operation thread: if two write operation threads terminate one after another, but the termination times of the two are very close, then the read validity period of the target memory block of the write operation thread that terminates first will be very short.

[0040] For some examples of this embodiment, see Figure 3As shown, in addition to at least two memory blocks 31, the memory block 30 also includes a readable address recording space 32. The readable address recording space 32 is used to record the memory address of the readable memory block of the memory block 30: when a write operation thread completes the write operation on its target memory block, the memory operation control device can record the memory address of the target memory block in the readable address recording space 32. In some examples of this embodiment, when the memory operation control device records the memory address of the current readable memory block in the readable address recording space 32, it always records it in an overwrite manner, that is, the new memory address will replace the memory address originally recorded in the readable address recording space 32. In this case, there is at most one memory address in the readable address recording space 32, and the memory address is the memory address of the current readable memory block of the memory block 30. In some other examples of this embodiment, when the memory operation control device records the memory address of the current readable memory block in the readable address recording space 32, it will not overwrite the previous memory address, so the readable address recording space 32 may record multiple memory addresses at the same time, and the number of memory addresses recorded will increase as the write operation thread is continuously initiated. In this case, in order for the memory operation control device to know which memory address should be used to respond to the read operation request after receiving the read operation request of the read operation thread, the memory operation control device needs to record the write time of the corresponding memory address when writing the memory address to the readable address recording space 32. In this way, when a read operation thread is initiated, the memory operation control device can select the latest memory address according to the write time in the readable address recording space 32 to respond to the request of the read operation thread. Alternatively, when the memory operation control device writes the memory address to the readable address recording space 32, it can mark the latest written memory address, and determine the current latest memory address according to the mark in the subsequent process to respond to the request of the read operation thread.

[0041] In this embodiment, after a write operation of a write operation thread is completed, if the memory operation control device determines that a read operation thread for a memory block is initiated within the read validity period of the target memory block of the write operation thread, the memory operation control device will indicate the target memory block as the current readable memory block to the read operation thread, so that the read operation thread can read data from the readable memory block. Figure 3 The memory block 30 shown in FIG. 1 can be used to obtain the memory address of the current readable memory block from the readable address recording space 32, thereby responding to the read operation thread according to the memory address. If the memory operation control device determines that a new write operation thread is initiated for the memory block within the read validity period of the target memory block of the write operation thread, the memory operation control device will also allocate a target memory block for the new write operation thread from other memory blocks other than the current readable memory block.

[0042] It should be understood that, in some examples of the present embodiment, when the memory operation control device allocates a target memory block for a new write operation thread, it can select one from the free memory blocks as the target memory block for the new write operation thread. Since the current readable memory block must be the memory block to which data has been written, under this target memory block allocation method, the current readable memory block of the memory block will definitely not be used as a candidate memory block, that is, the memory operation control device must select a target memory block for the write operation thread from other memory blocks other than the readable memory block. In other examples of the present embodiment, the memory operation control device can also select one from the non-free memory blocks other than the current readable memory block, clear the data in the selected memory block, and then allocate the memory block as the target memory block for the new write operation thread to the new write operation thread.

[0043] In some examples of this embodiment, the memory operation control device can also receive a write request from a new write operation thread while a write operation thread is performing a data write operation on a memory block. However, in this case, when the memory operation control device allocates a target memory block for the new write operation thread, it must not only exclude the current readable memory block from the candidate memory blocks, but also exclude the memory block currently being operated by another write operation thread. For example, assuming that the memory operation control device determines that a first write operation thread is initiated at time t1, the memory operation control device can allocate a target memory block s1 for the first write operation thread. At time t2, the write operation of the first write operation thread is still continuing, but at the same time, a second write operation thread is initiated. Therefore, the memory operation control device needs to allocate a target memory block for the second write operation thread. When the memory operation control device selects a target memory block for the second write operation thread, it cannot select the current readable memory block, nor can it select the target memory block s1 of the first write operation thread.

[0044] In this embodiment, a memory operation control method is provided. When the read operation thread and the write operation thread operate on the memory, no read lock and write lock are added, so that the read operation thread and the write operation thread can be performed at the same time. At the same time, because the memory operation control device divides the memory block into at least two memory blocks, and excludes the current readable memory block when allocating the target memory block for the write operation thread to write data, the operation of the write operation thread will not affect the read operation thread. Even if the two operation threads operate on the memory block at the same time, because the memory blocks targeted by the operation are not the same, the correctness and effectiveness of data writing and data reading can be guaranteed without locking the memory block. That is, the memory operation control method in this embodiment ensures the same correctness and effectiveness as in the related art by setting at least two memory blocks, but in exchange for higher read and write efficiency, avoiding the situation where the read operation thread and the write operation thread are blocked by each other.

[0045] Furthermore, in this embodiment, because the memory operation control device avoids the target memory blocks of other write operation threads that have not yet ended when allocating target memory blocks for write operation threads, it can ensure that even if two or more write operation threads are carried out simultaneously, each write operation thread operates on a different memory block, thereby improving the efficiency of responding to concurrent write operation threads on the basis of dirty data generation, and can adapt to scenarios with a large number of concurrent write operations.

[0046] Embodiment 2:

[0047] This embodiment will continue to introduce the aforementioned memory operation control method and memory block based on the first embodiment. Figure 4 An implementation flow chart of allocating target memory blocks for write operation threads from memory blocks is shown:

[0048] S402: Allocate usage numbers for free memory blocks.

[0049] In this embodiment, when the memory operation control device allocates a target memory block for a write operation thread, it is always selected from the free memory blocks. Each free memory block is allocated, that is, it is used by the write operation thread in order, and the memory operation control device can manage each free memory block in a queue manner: the free memory block added to the free memory queue first will be allocated first, and the free memory block added to the free memory queue later will also be allocated later. In this case, each free memory block has a usage sequence number, which can represent the number of free memory blocks allocated cumulatively from the time when the memory block is divided into memory blocks until the free memory block is allocated (for ease of introduction, the number of free memory blocks allocated cumulatively from the time when the memory block is divided into memory blocks until the free memory block is allocated "is referred to as the cumulative allocation number below), in other words, it can reflect that the free memory block is the number of the free memory blocks allocated. However, it is worth noting that the usage sequence number of the free memory block can represent the cumulative allocation number, but this does not mean that the usage sequence number of the free memory block is equal to the corresponding cumulative allocation number. For example, if the usage sequence number is allocated starting from "0", then the usage sequence number of a free memory block is actually 1 less than the cumulative allocation number. Of course, if the usage sequence number is allocated starting from "1", then the usage sequence number of a free memory block is exactly equal to the corresponding cumulative allocation number.

[0050] It is understandable that after the memory operation control device divides the memory block, k free memory blocks can be obtained. Subsequently, the memory operation control device can allocate use numbers for these k free memory blocks. After the use numbers are allocated, these free memories are actually in the free memory queue. In some examples of this embodiment, each memory block will only be used for one round after applying for setting the memory block. When the free memory queue is empty, the memory operation device will release the memory block, and then re-apply for new memory space to set the memory block. But in some other examples of this embodiment, the memory operation control device will recycle these memory blocks, that is, it will recycle the non-free memory blocks, clear and release the data therein, and then continue to allocate use numbers for the obtained free memory and add it to the free memory queue. Therefore, in this example, although there are only k actual memory blocks in the memory block, the use number of the memory block can far exceed k. An actual memory block may become multiple logical memory blocks due to circular use. These logical memory blocks exist at different times and have different usage serial numbers. Therefore, an actual memory block may have multiple different usage serial numbers at different times.

[0051] Assume that a memory block in this embodiment contains 4 actual memory blocks, and their block identifiers are "0", "1", "2", and "3" respectively. Assume that in the initial stage, the memory operation control device allocates usage numbers "0", "1", "2", and "3" to these 4 free memory blocks respectively. If a write operation thread writes data to the free memory block with usage number "2", the memory operation control device recycles the memory block with usage number "0" and releases the data therein. Then this memory block will be reallocated with usage number "4" and added to the free memory queue.

[0052] In this embodiment, the memory block also includes a writable address recording space, which includes K recording partitions, each of which has a unique partition identifier. Therefore, the writable address recording space can just record the memory addresses of each actual memory block at the same time, and each memory address corresponds to a recording partition. Figure 5 The memory block 50 shown includes, in addition to at least two memory blocks 51, a writable address recording space 52. Figure 5 The case where k is equal to 3 is shown in Figure 5 There are 3 memory blocks and 3 record partitions in total. Figure 5 In the example, the three record partitions are set together and the three memory blocks are also adjacent, but in some other examples, the memory blocks can be set dispersedly, and the record partitions can also be set dispersedly. For example, in some examples, the memory blocks and the record partitions can be set alternately and cyclically.

[0053] In some examples of this embodiment, the memory block also includes a space for recording the total number of blocks, see Figure 6The memory block 60 shown in the figure includes, in addition to at least two memory blocks 61 and a writable address recording space 62, a total number of blocks recording space 63. The data L recorded in the total number of blocks recording space 63 can reflect the total number of free memory blocks currently added to the free memory queue. In this embodiment, when a new free memory block needs to be added to the free memory queue, the memory operation control device can allocate a usage sequence number for the free memory block according to the data L recorded in the total number of blocks recording space 63, and after the usage sequence number is allocated, modify the data L recorded in the total number of blocks recording space 63 according to the usage sequence number of the free memory block. For example, if the data currently recorded in the total number record space 62 is "167", it proves that 167 free memory blocks have been added to the free memory queue before. If the usage sequence number is allocated starting from "0", that is, the initial value of the usage sequence number is "0", then when there is a new free memory block that needs to be allocated with a usage sequence number, the memory operation control device will allocate the usage sequence number "167" to the new free memory block. If the usage sequence number is allocated starting from "1", the memory operation control device will allocate the usage sequence number "168" to the new free memory block. Whenever a new free memory block is added to the free memory queue, the value of L will increase by 1.

[0054] S404: Determine the partition identifier corresponding to the memory address of the free memory block in the writable address record space according to a preset rule and the usage sequence number of the free memory block.

[0055] In this embodiment, the record partition in which the memory address of a free memory block should be recorded can be determined according to the usage sequence number of the free memory block. In some examples of this embodiment, the memory operation control device determines the partition identifier corresponding to the memory address of the free memory block in the writable address record space according to the preset rule and the usage sequence number of the free memory block, that is, determines in which record partition of the writable address record space the memory address of the free memory block is located.

[0056] In an example of this embodiment, the memory operation control device can determine the remainder of the serial number pair K. For the sake of ease of introduction, the remainder is recorded as the "first remainder" here. After the memory operation control device obtains the first remainder, it can use the first remainder as the partition identifier corresponding to the memory address of the free memory block in the writable address recording space.

[0057] S406: Record the memory address of the free memory block into the record partition of the writable address record space according to the partition identifier corresponding to the free memory block.

[0058] After the memory operation control device determines the partition identifier corresponding to a free memory block memory address in the writable address recording space, it can record the memory address of the free memory block into the record partition of the writable address recording space according to the partition identifier.

[0059] S408: After determining that a write operation thread has been initiated for the memory block, determine the memory allocation sequence number corresponding to the write operation thread.

[0060] After determining that a write operation thread has been initiated for a memory block, the memory operation control device can determine a memory allocation sequence number for the write operation thread. In this embodiment, the memory allocation sequence number is determined for the write operation thread in order to ensure that the order in which the free memory blocks are allocated to each write operation thread conforms to the usage sequence number of the free memory block. The memory allocation sequence number of a write operation thread can represent the number of write operation threads that have accumulated since the memory block was divided into memory blocks until the write operation thread initiated it (for ease of introduction, the "number of write operation threads that have accumulated since the memory block was divided into memory blocks until the write operation thread initiated it" is referred to as the "cumulative number of threads" below). For example, a write operation thread is the 165th write operation thread initiated after the memory block is divided into memory blocks. Before this write operation thread, the memory operation control device has allocated target memory blocks to 164 write operation threads. According to the usage sequence numbers of the free memory blocks in the free memory queue, if the initial usage sequence number is "1", the write operation thread should be allocated to the free memory block with the usage sequence number "165"; if the initial usage sequence number is "0", the write operation thread should be allocated to the free memory block with the usage sequence number "164".

[0061] In some examples of this embodiment, the memory block also includes an allocation number record space, see Figure 7 In addition to at least two memory blocks 71 and a writable address recording space 72, the memory block 70 also includes an allocation number recording space 73. The data F recorded in the allocation number recording space 73 can reflect the total number of free memory blocks currently allocated. When a free memory block is allocated, the value of the data F will increase by 1. Therefore, when it is necessary to allocate a target memory block for a write operation thread, the memory operation control device can determine the memory allocation sequence number corresponding to the write operation thread according to the data F currently recorded in the allocation number recording space. After the memory allocation sequence number is allocated to the write operation thread, a free memory block will inevitably be allocated to it according to its memory allocation sequence number (although it has not yet been determined which free memory block it is). Therefore, after the memory allocation sequence number is allocated to the write operation thread, the data F in the allocation number recording space 73 can be modified to increase the value of F by 1.

[0062] S410: Determine the partition identifier corresponding to the memory address of the target memory block of the write operation thread in the writable address record space according to a preset rule and a memory allocation sequence number.

[0063] After the memory operation control device determines the memory allocation sequence number corresponding to a write operation thread, it can determine the partition identifier corresponding to the memory address of the target memory block of the write operation thread in the writable address record space according to the preset rule and the memory allocation sequence number. That is, it is determined in which record partition of the writable address record space the memory address of the target memory block corresponding to the write operation thread is recorded.

[0064] In an example of this embodiment, the memory operation control device can determine the remainder of the memory allocation sequence number with respect to K. For the sake of ease of introduction, the remainder is recorded as the "second remainder" here. After the memory operation control device obtains the second remainder, it can use the second remainder as the partition identifier corresponding to the memory address of the target memory block in the writable address record space.

[0065] S412: Query the writable address record space according to the partition identifier corresponding to the target memory block to determine the memory address of the target memory block.

[0066] After obtaining the partition identifier corresponding to the memory address of the target memory block in the writable address recording space, the memory operation control device can query the writable address recording space according to the partition identifier to determine the memory address of the target memory block.

[0067] S414: Provide the memory address of the target memory block to the write operation thread.

[0068] After determining the memory address of the target memory block, the memory operation control device may provide the memory address to the corresponding write operation thread, thereby completing the process of allocating the target memory block for the write operation thread.

[0069] It is understandable that the process of allocating target memory blocks for write operation threads in S408-S414 is not limited to the first write operation thread initiated after the memory block partitioning is set, but can also be applied to any other write operation thread, such as a new write operation thread after any write operation thread.

[0070] The following is an introduction to the mechanism by which the memory operation control device in this embodiment recycles non-free memory blocks:

[0071] For some examples of this embodiment, see Figure 8In addition to at least two memory blocks 81 and a writable address recording space 82, the memory block 80 also includes a counting recording space 83 corresponding to each memory block, that is, each memory block 81 uniquely corresponds to a counting recording space 83. Figure 8 Among them, the memory block 81 and the counting record space 83 are set alternately and cyclically, but in some other examples of this embodiment, the memory block 81 and its corresponding counting record free space 83 can also be set dispersedly. For example, in one example, each memory block 81 is set closely together, and each counting record free space is set closely together. The counting record space is used to record the number of read operation threads that currently perform read operations on the corresponding memory block. For example, if a memory block is currently operated by 3 read operation threads, the data recorded in its counting record space is "3". If a read operation thread is added to perform a read operation on it at this time, the data recorded in its counting record space will become "4". If these read operation threads gradually end, the data recorded in its counting record space will also become smaller and smaller until it returns to zero.

[0072] Therefore, in some examples of this embodiment, the memory operation control device can be based on Fig. 9 The flowchart shown is used to recycle non-free memory blocks:

[0073] S902: Monitor the data recorded in the counting recording space corresponding to the non-free memory block.

[0074] The non-free memory blocks include the current readable memory blocks and other ordinary non-free memory blocks. Considering that the readable memory blocks are still within their read validity period, even if there is no read operation thread currently performing a read operation on them, it cannot be guaranteed that there will be no read operation thread initiated within their remaining read validity period. Therefore, in some examples of this embodiment, even if the data recorded in the counting record space corresponding to the current readable memory block is 0, the memory operation control device will not release it temporarily. Therefore, the memory operation control device can only perform recovery monitoring on ordinary non-free memory blocks.

[0075] S904: Determine whether the data recorded in the corresponding counting record space is 0.

[0076] If the judgment result is yes, then go to S906, otherwise, continue to execute S902.

[0077] S906: Clear the data in the non-free memory block to obtain a free memory block.

[0078] It should be understood that after the memory operation control device clears the data in the non-free memory blocks and releases the free memory blocks, it can also Figure 4The description of S402-S406 in the above process puts the free memory block into the free memory queue. Please refer to the above description for the specific process, which will not be repeated here.

[0079] The memory operation control method provided in this embodiment realizes the infinite recycling of limited actual free memory blocks by recycling non-free memory blocks. And by recording the usage sequence number of the latest free memory block in the free memory queue and the number of allocated free memory blocks, combined with the recording of the memory address of each actual memory block in the writable address recording space, the orderly addition and allocation of free memory blocks can be realized.

[0080] Embodiment three:

[0081] In order to make the advantages and details of the memory operation control scheme in the embodiment of the present invention more clear to those skilled in the art, this embodiment will continue to explain the scheme with examples:

[0082] See also Fig.10 , Fig.10 The structure of a memory block is shown: the memory block 100 includes a readable address recording space R, an allocation number recording space F, a total block recording space L, a writable address recording space (including a first recording partition W1, a second recording partition W2 ... the kth recording partition Wk), at least two memory blocks (a first memory block mem1, a second memory block mem2 ... the kth memory block memk) and a counting recording space corresponding to each memory block (a first counting recording space c1, a second counting recording space c2 ... the kth counting recording space ck).

[0083] If a memory block, a memory block's count record space, and the record partition corresponding to the memory block are considered as a "segment", then the size S of the memory block as a whole is equal to k multiplied by the size k0 of the segment, plus the size Sr of the readable address record space R, the size Sf of the allocation number record space F, and the size Sl of the total number of blocks record space L, that is,

[0084] S= k* k0+Sr+Sf+ Sl;

[0085] In this embodiment, R, F, and L each occupy 8 bytes, and in a segment, a record partition and a count record space occupy 8 bytes and 4 bytes respectively. It is assumed that the size of a memory block is Ss.

[0086] In this embodiment, the data in the readable address recording space R, the allocation number recording space F, the total block recording space L, the writable address recording space, and the count recording space corresponding to each memory block are all modified with the volatile keyword (volatile is a characteristic modifier (type specifier). The role of volatile is to serve as an instruction keyword to ensure that this instruction will not be omitted due to compiler optimization and requires direct value reading each time) so that the memory operation control device can be notified immediately after the data changes.

[0087] The following describes the initialization of the memory block 100, the memory block 100 accepting the write operation of the write operation thread, the memory block 100 accepting the read operation of the read operation thread, and the recycling process of the memory blocks in the memory block 100 respectively:

[0088] (1) Initialization of memory block 100:

[0089] Set R=0, F=0, L=k-1, and each writable address recording space records the memory address of the immediately following memory block, but the memory address of the memory block 100 as a whole is P. The writable address recording space is a buffer for storing the memory address data of the memory block. F can represent the usage sequence number of the first free memory block in the free memory queue (0 in this embodiment, the usage sequence number of the free memory block is assigned starting from "0"), and L can represent the usage sequence number of the last free memory block in the free memory queue. When the memory operation control device takes out a free memory block from the queue, the value of F is increased by one, and when the memory operation control device puts a free memory block into the free memory queue, the value of L is increased by one. Obviously, when F is equal to L, it means that the free memory queue is empty; when L minus F is equal to the size of the free memory queue, it means that the free memory queue is full. F&(k-1) represents the partition identifier of the memory address of the free memory block at the head of the current free memory queue in the writable address recording space, and F&(k-1) is equivalent to F modulo k. L&(k-1) represents the partition identifier of the memory address of the free memory block at the end of the current free memory queue in the writable address record space. L&(k-1) is equivalent to L modulo k.

[0090] (2) The write operation thread performs a write operation on memory block 100:

[0091] After determining that a write operation thread has been initiated, determine that the current value of F is F1. The memory operation control device determines whether L is equal to F1. If so, it means that the free memory queue is empty and cannot be written temporarily, so the write operation thread temporarily gives up actively, and the corresponding CPU enters sleep and waits to be awakened; if the memory operation control device determines that L is greater than F1, CAS (F, F1, F1+1) is executed. This step represents an atomic operation to ensure that multiple write operation threads will not operate the same memory block at the same time. Here is a brief description of the CAS algorithm: CAS (F, F1, F1+1) means that if and only if F is equal to F1, the value of F is modified to F1+1. When the memory operation control device determines that L is greater than F1, the memory operation control device will take out the free memory block from the free memory queue and determine the partition identifier F1&(K-1) corresponding to the free memory block. Then the memory address P is offset by 24Byte + (F1&(K-1)) * (12Byte+Ss), and the first 8 bytes are read from the offset address to obtain the actual write address P1. After the write is completed, the memory address in R is updated to the actual write memory address P1.

[0092] (3) The read operation thread performs a read operation on memory block 100:

[0093] Assuming that a read operation thread is initiated, the memory operation control device reads the first 8 bytes of content from the memory address P of the memory block 100, which is the memory block address P1 of the readable memory block, and then reads the data according to the memory address. At the same time, the memory operation control device increases the value in the counting record space corresponding to the readable memory block by one. After the write operation thread writes the data, the memory operation control device will immediately update the R content, so the read operation thread can immediately obtain the memory address of the memory block where the latest data is located, and the subsequent write operation thread writes the memory address after the offset is calculated based on the F content, and will select a block in the free memory block for writing, avoiding read-write conflicts. After a read operation thread for the current readable memory block ends, the memory operation control device will control the value in the counting record space corresponding to the readable memory block to be reduced by one.

[0094] (4) Recycling of non-free memory blocks:

[0095] If a write operation thread is initiated and the memory operation control device finds that there are not enough free memory blocks in the free memory queue, it can traverse the counting record space of the free memory blocks (the partition identifier corresponds to the memory blocks from "0" to "F&(k-1)-1") to determine whether to clear and release the memory blocks: First, the memory operation control device records the current L value as L1, and then determines whether L1-F is equal to k-1. If so, it means that all free memory queues are full and do not need to be recycled; if L1-F is not equal to k-1, the memory operation control device executes CAS (L, L1, L1+1), which also represents an atomic operation to ensure that multiple threads cannot operate the same memory block at the same time. The recycled free memory block will be added to the tail of the free memory queue, and the memory operation control device will write the memory address of the recycled free memory block into the corresponding record partition for subsequent allocation.

[0096] In addition, the memory operation control device can also release the applied continuous memory P at one time, that is, completely release the memory block 100.

[0097] Embodiment 4:

[0098] The present embodiment provides a storage medium, which includes volatile or non-volatile, removable or non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, computer program modules or other data). Storage media include but are not limited to RAM (Random Access Memory), ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable read only memory), flash memory or other memory technology, CD-ROM (Compact Disc Read-Only Memory), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer.

[0099] The storage medium may store one or more computer programs that can be read, compiled and executed by one or more processors. In the present embodiment, the storage medium may store a memory operation control program, and the memory operation control program may be executed by one or more processors to implement the process of any one of the memory operation control methods described in the foregoing embodiments.

[0100] This embodiment also provides a computer program product, including a computer readable device, on which the computer program as shown above is stored. In this embodiment, the computer readable device may include the computer readable storage medium as shown above. For example, the computer program product includes a memory operation control device, such as Fig.11 As shown: the memory operation control device 11 includes a processor 111, a memory 112, and a communication bus 113 for connecting the processor 111 and the memory 112, wherein the memory 112 can be the storage medium storing the memory operation control program. The memory 112 includes at least one memory block, and the memory block includes K memory blocks, where K is greater than or equal to 2. The processor 111 can read the memory operation control program, compile and execute the process of implementing the memory operation control method described in the above embodiment:

[0101] The processor 111 divides K memory blocks from a memory block and determines the memory address of each memory block, where K is greater than or equal to 2. Subsequently, after determining that a write operation thread for the memory block is initiated, a target memory block is allocated to the write operation thread, so that the write operation thread can perform a write operation according to the memory address of the target memory block; if a read operation thread for the memory block is initiated within the read validity period of the target memory block, the processor 111 provides the target memory block as the current readable memory block of the memory block to the read operation thread, so that the read operation thread can perform a read operation according to the memory address of the target memory block; the read validity period of the target memory block is from the completion of the write operation of the write operation thread to the target memory block to the completion of the next write operation thread; if a new write operation thread for the memory block is initiated within the read validity period of the target memory block, the processor 111 allocates a target memory block to the new write operation thread from other memory blocks other than the readable memory block for the new write operation thread to perform a write operation.

[0102] After allocating a target memory block to the write operation thread, if a write operation request from a new write operation thread is received while the write operation thread is performing a write operation on the corresponding target memory block, the processor 111 can also allocate a target memory block to the new write operation thread from other memory blocks other than the current readable memory block and the target memory block of the write operation thread for its write operation.

[0103] In some examples of this embodiment, the memory block also includes a readable address recording space; when the processor 111 provides the target memory block as the current readable memory block of the memory block to the read operation thread for a read operation, after the write operation thread completes the write operation on the target memory block, the memory address of the target memory block can be first recorded in the readable address recording space; after receiving the read operation request from the read operation thread, the latest recorded memory address is extracted from the readable address recording space and provided to the read operation thread.

[0104] In some examples of this embodiment, when the processor 111 records the memory address of the target memory block into the readable address recording space, the memory address of the target memory block may be recorded into the readable address recording space in an overwritten manner.

[0105] In some examples of this embodiment, when the processor 111 allocates a target memory block to a new write operation thread from other memory blocks other than the readable memory block, one may be selected from the free memory blocks as the target memory block of the new write operation thread and allocated to the new write operation thread, where the free memory block is a memory block to which no data is currently written. In some other examples of this embodiment, the processor 111 may also select one from a non-free memory block other than the readable memory block, clear the data in the selected memory block, and then allocate the memory block as the target memory block of the new write operation thread to the new write operation thread.

[0106] In some examples of the present embodiment, the memory block also includes a writable address recording space, and the writable address recording space includes K record partitions, each of which has a unique partition identifier; after the processor 111 divides K memory blocks from a memory block, it can also assign a usage sequence number to the free memory block, and the usage sequence number of the free memory block can represent the number of free memory blocks that are cumulatively allocated from the memory block to the free memory block, and then determine the partition identifier corresponding to the memory address of the free memory block in the writable address recording space according to the preset rule and the usage sequence number of the free memory block. Subsequently, the processor 111 records the memory address of the free memory block in the record partition of the writable address recording space according to the partition identifier corresponding to the free memory block. When selecting a target memory block as a new write operation thread from the free memory blocks and assigning it to the new write operation thread, the processor 111 first determines the memory allocation sequence number corresponding to the new write operation thread, and the memory allocation sequence number of the write operation thread can represent the number of write operation threads that exist cumulatively from the memory block to the write operation thread initiating the memory block. Then, the processor 111 determines the partition identifier corresponding to the memory address of the target memory block of the new write operation thread in the writable address record space according to the preset rule and the memory allocation sequence number, and queries the writable address record space according to the partition identifier corresponding to the target memory block to determine the memory address of the target memory block. Subsequently, the processor 111 provides the memory address of the target memory block to the new write operation thread.

[0107] In some examples of this embodiment, the memory block also includes a block total number record space. When the processor 111 assigns usage numbers to free memory blocks, it can assign usage numbers to free memory blocks according to the data L recorded in the block total number record space, and modify the data L recorded in the block total number record space after assigning usage numbers to the free memory blocks.

[0108] In some examples of this embodiment, the memory block also includes an allocation number record space. When the processor 111 determines the memory allocation number corresponding to the new write operation thread, it can determine the memory allocation number corresponding to the new write operation thread based on the data F currently recorded in the allocation number record space, and modify the data F recorded in the allocation number record space after allocating the memory allocation number to the new write operation thread.

[0109] In some examples of this embodiment, when the processor 111 determines the partition identifier corresponding to the memory address of the free memory block in the writable address record space according to the preset rule and the usage sequence number of the free memory block, it can first determine the first remainder of the usage sequence number to K, and use the first remainder as the partition identifier corresponding to the memory address of the free memory block in the writable address record space;

[0110] When the processor 111 determines the partition identifier corresponding to the memory address of the target memory block of the new write operation thread in the writable address record space according to the preset rules and the memory allocation sequence number, the second remainder of the memory allocation sequence number to K can be determined, and the second remainder can be used as the partition identifier corresponding to the memory address of the target memory block in the writable address record space.

[0111] In some examples of the present embodiment, the memory block also includes a counting record space corresponding to each memory block, and the counting record space is used to record the number of read operation threads that currently perform read operations on the corresponding memory block; the processor 111 can also monitor the data recorded in the counting record space corresponding to the non-free memory block; if the data recorded in the counting record space is 0, the processor 111 clears the data in the non-free memory block to obtain the free memory block.

[0112] For details on how the processor 111 of the memory operation control device 11 executes the memory operation control program to implement the memory operation control method, please refer to the introduction in the aforementioned embodiment, which will not be repeated here.

[0113] In this embodiment, a memory operation control device is provided. When the read operation thread and the write operation thread operate on the memory, no read lock and write lock are added, so that the read operation thread and the write operation thread can be performed at the same time. At the same time, because the memory operation control device divides the memory block into at least two memory blocks, and excludes the current readable memory block when allocating the target memory block for the write operation thread to write data, the operation of the write operation thread will not affect the read operation thread. Even if the two operation threads operate on the memory block at the same time, because the memory blocks targeted by the operation are not the same, the correctness and effectiveness of data writing and data reading can be guaranteed without locking the memory block. That is, the memory operation control method in this embodiment ensures the same correctness and effectiveness as in the related art by setting at least two memory blocks, but in exchange for higher read and write efficiency, avoiding the situation where the read operation thread and the write operation thread are blocked with each other.

[0114] Furthermore, in this embodiment, because the memory operation control device avoids the target memory blocks of other write operation threads that have not yet ended when allocating target memory blocks for write operation threads, it can ensure that even if two or more write operation threads are carried out simultaneously, each write operation thread operates on a different memory block, thereby improving the efficiency of responding to concurrent write operation threads on the basis of dirty data generation, and can adapt to scenarios with a large number of concurrent write operations.

[0115] It can be seen that those skilled in the art should understand that all or some steps, systems, and functional modules / units in the above disclosed methods can be implemented as software (which can be implemented by computer program code executable by a computing device), firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be performed by several physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit.

[0116] In addition, it is well known to those skilled in the art that communication media generally contain computer readable instructions, data structures, computer program modules or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery media. Therefore, the present invention is not limited to any specific hardware and software combination.

[0117] The above contents are further detailed descriptions of the embodiments of the present invention in combination with specific implementation methods, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

Claims

1. A memory operation control method, comprising: Divide K memory blocks from a memory block, and determine the memory address of each memory block, where K is greater than or equal to 2; After determining that a write operation thread for the memory block is initiated, a target memory block is allocated to the write operation thread, so that the write operation thread can perform a write operation according to the memory address of the target memory block; If a read operation thread for the memory block is initiated within the read validity period of the target memory block, the target memory block is provided to the read operation thread as the current readable memory block of the memory block, so that the read operation thread performs a read operation according to the memory address of the target memory block; The read validity period of the target memory block is from the completion of the write operation of the write operation thread on the target memory block to the completion of the next write operation thread; If a new write operation thread is initiated for the target memory block within the read validity period of the target memory block, a target memory block is allocated to the new write operation thread from other memory blocks other than the readable memory block for the new write operation thread to perform write operations.

2. The memory operation control method according to claim 1, characterized in that: After allocating the target memory block to the write operation thread, the method further includes: If a write operation request from a new write operation thread is received while the write operation thread is performing a write operation on the corresponding target memory block, a target memory block is allocated to the new write operation thread from other memory blocks other than the current readable memory block and the target memory block of the write operation thread for its write operation.

3. The memory operation control method according to claim 1, wherein: The memory block also includes a readable address recording space; providing the target memory block as the current readable memory block of the memory block to the read operation thread for the read operation includes: After the write operation thread completes the write operation on the target memory block, recording the memory address of the target memory block into the readable address recording space; After receiving the read operation request of the read operation thread, the memory address of the latest record is extracted from the readable address record space and provided to the read operation thread.

4. The memory operation control method according to claim 3, characterized in that: The recording of the memory address of the target memory block into the readable address recording space comprises: The memory address of the target memory block is recorded in the readable address recording space in an overwriting manner.

5. The memory operation control method according to any one of claims 1 to 4, characterized in that: The allocating a target memory block for the new write operation thread from other memory blocks other than the readable memory block comprises: Select one from the free memory blocks as the target memory block of the new write operation thread and allocate it to the new write operation thread, wherein the free memory block is a memory block to which no data is currently written; or, Select one non-free memory block other than the readable memory block, clear the data in the selected memory block, and then allocate the memory block as the target memory block of the new write operation thread to the new write operation thread.

6. The memory operation control method according to claim 5, characterized in that: The memory block also includes a writable address recording space, the writable address recording space includes K recording partitions, and each of the recording partitions has a unique partition identifier; After dividing K memory blocks from a memory block, the method further includes: Assigning a usage sequence number to the free memory block, wherein the usage sequence number of the free memory block can represent the number of free memory blocks allocated cumulatively from the time when the memory block is divided into memory blocks until the free memory block is allocated; Determine the partition identifier corresponding to the memory address of the free memory block in the writable address recording space according to a preset rule and the usage sequence number of the free memory block; Recording the memory address of the free memory block into the record partition of the writable address record space according to the partition identifier corresponding to the free memory block; The step of selecting one of the free memory blocks as the target memory block of the new write operation thread and allocating it to the new write operation thread comprises: Determine a memory allocation sequence number corresponding to the new write operation thread, where the memory allocation sequence number of the write operation thread can represent the number of write operation threads that have accumulated since the memory block was divided into memory blocks until the write operation thread initiates the operation; Determine the partition identifier corresponding to the memory address of the target memory block of the new write operation thread in the writable address record space according to the preset rule and the memory allocation sequence number; Querying the writable address recording space according to the partition identifier corresponding to the target memory block to determine the memory address of the target memory block; The memory address of the target memory block is provided to the new write operation thread.

7. The memory operation control method according to claim 6, characterized in that: The memory block also includes a space for recording the total number of blocks, and the sequence numbers allocated for free memory blocks include: A usage sequence number is allocated to the free memory block according to the data L recorded in the block total number recording space, and the data L recorded in the block total number recording space is modified after the usage sequence number is allocated to the free memory block.

8. The memory operation control method according to claim 6, wherein: The memory block also includes an allocation number recording space, and the determining of the memory allocation sequence number corresponding to the new write operation thread includes: The memory allocation sequence number corresponding to the new write operation thread is determined according to the data F currently recorded in the allocation number record space, and the data F recorded in the allocation number record space is modified after the memory allocation sequence number is allocated to the new write operation thread.

9. The memory operation control method according to claim 6, wherein: The determining, according to a preset rule and the usage sequence number of the free memory block, a partition identifier corresponding to the memory address of the free memory block in the writable address recording space comprises: Determine a first remainder of the usage sequence number with respect to K, and use the first remainder as a partition identifier corresponding to the memory address of the free memory block in the writable address recording space; The determining, according to the preset rule and the memory allocation sequence number, of the partition identifier corresponding to the memory address of the target memory block of the new write operation thread in the writable address record space includes: Determine a second remainder of the memory allocation sequence number with respect to K, and use the second remainder as a partition identifier corresponding to the memory address of the target memory block in the writable address recording space.

10. The memory operation control method according to claim 6, wherein: The memory block also includes a counting recording space corresponding to each of the memory blocks, and the counting recording space is used to record the number of read operation threads currently performing a read operation on the corresponding memory block; The memory operation control method further includes: Monitor the data recorded in the counting record space corresponding to the non-free memory block; If the data recorded in the counting recording space is 0, the data in the non-free memory block is cleared to obtain the free memory block.

11. A memory operation control device, the memory operation control device comprising a processor, a memory and a communication bus; The communication bus is used to realize the connection and communication between the processor and the memory; The memory stores a memory operation control program, and the memory includes at least one memory block, the memory block includes K memory blocks, and K is greater than or equal to 2; The processor is used to execute one or more programs stored in the memory to implement the steps of the memory operation control method according to any one of claims 1 to 10.

12. A storage medium, characterized in that: The storage medium stores a memory operation control program, and the memory operation control program can be executed by one or more processors to implement the steps of the memory operation control method according to any one of claims 1 to 10.

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